WO2019137072A1 - 显示面板 - Google Patents

显示面板 Download PDF

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Publication number
WO2019137072A1
WO2019137072A1 PCT/CN2018/112639 CN2018112639W WO2019137072A1 WO 2019137072 A1 WO2019137072 A1 WO 2019137072A1 CN 2018112639 W CN2018112639 W CN 2018112639W WO 2019137072 A1 WO2019137072 A1 WO 2019137072A1
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WIPO (PCT)
Prior art keywords
layer
active layer
light
display panel
drain
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PCT/CN2018/112639
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English (en)
French (fr)
Inventor
唐国强
徐映嵩
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to JP2020535061A priority Critical patent/JP7121128B2/ja
Priority to US16/466,879 priority patent/US10998530B2/en
Priority to EP18882283.7A priority patent/EP3742509B1/en
Publication of WO2019137072A1 publication Critical patent/WO2019137072A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/30—Organic light-emitting transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment

Definitions

  • Embodiments of the present disclosure relate to the field of display technologies, and in particular, to a display panel.
  • the pixel structure in current OLED display panels includes an OLED light emitting layer and a driving thin film transistor (DTFT). Such a display panel still needs to be improved.
  • DTFT driving thin film transistor
  • an embodiment of the invention provides a display panel comprising:
  • a gate the gate being on a substrate
  • An active layer, the active layer and the gate being spaced apart by a gate insulating layer;
  • a source and a drain the source and the drain being configured such that a current can flow through the light emitting layer via the active layer.
  • an energy level transition layer is disposed between the active layer and the light emitting layer.
  • the active layer is made of an inorganic semiconductor material.
  • the inorganic semiconductor material includes at least one of polycrystalline silicon, single crystal silicon, and a metal oxide semiconductor.
  • the orthographic projection of the source and the drain on the active layer is two spaced concentric non-closed rings.
  • the source and the active layer are electrically connected, and the drain and the light emitting layer are electrically connected.
  • the source and the light emitting layer are electrically connected, and the drain and the light emitting layer are electrically connected.
  • the display panel further includes a connection electrode, and the light emitting layer and the drain are electrically connected through the connection electrode.
  • the orthographic projection of the connection electrode on the active layer overlaps with the orthographic projection of the luminescent layer on the active layer.
  • the drain and/or the connection electrode are transparent electrodes.
  • the active layer is a p-type active layer, and the highest occupied molecular orbital of the energy level transition layer matches the work function level of the p-type active layer.
  • the active layer is an n-type active layer, and a lowest unoccupied molecular orbital of the energy level transition layer matches a work function energy level of the n-type active layer.
  • a gate electrode, an active layer, a gate insulating layer, a light emitting layer, a source and a drain form an illuminating field effect transistor
  • the display panel includes a plurality of illuminating field effect transistors, and the plurality of The luminescence field effect transistor is arranged such that sources of two illuminating field effect transistors adjacent in the first direction are integrally formed as a first combination, and two illuminating field effects adjacent in the first direction
  • the drain of the transistor is integrally formed as a second combined body, and the first combined body and the second combined body are alternately disposed in the first direction.
  • the plurality of the light-emitting field effect transistors are arranged such that sources of the light-emitting field effect transistors adjacent in a second direction perpendicular to the first direction are integrally formed
  • the drains of the adjacent light-emitting field effect transistors adjacent in the second direction are integrally formed as the second combination body
  • the first combination is connected to a power line, and the second combination is connected to a ground line.
  • the display panel further includes a switching thin film transistor, a source of the switching thin film transistor is connected to a data line, a gate of the switching thin film transistor is connected to a gate line, and a drain of the switching thin film transistor The pole is electrically connected to the gate of the illuminating field effect transistor.
  • FIG. 1 is a schematic structural view of an illuminating field effect transistor in an embodiment of the present disclosure
  • FIG. 2 is a schematic diagram showing an equivalent circuit of an illuminating field effect transistor in an embodiment of the present disclosure
  • FIG. 3 is a schematic structural diagram of an illuminating field effect transistor in another embodiment of the present disclosure.
  • FIG. 4 is a schematic structural diagram of an illuminating field effect transistor in another embodiment of the present disclosure.
  • FIG. 5 is a schematic structural view of an orthographic projection of a source and a drain on an active layer in one embodiment of the present disclosure
  • FIG. 6 is a schematic structural view of an orthographic projection of a source and a drain on an active layer in another embodiment of the present disclosure
  • FIG. 7 is a schematic structural view of an orthographic projection of a source and a drain of a plurality of light-emitting field effect transistors on an active layer in an embodiment of the present disclosure
  • FIG. 8 is a schematic structural diagram of a source and a drain of a plurality of light-emitting field effect transistors in another embodiment of the present disclosure
  • FIG. 9 is a partial plan view showing a display panel in an embodiment of the present disclosure.
  • FIG. 10 is a partial plan view showing a display panel in another embodiment of the present disclosure.
  • FIG. 11 is a partial cross-sectional structural view of a display panel in another embodiment of the present disclosure.
  • FIG. 12 is a partial cross-sectional structural view of a display panel in another embodiment of the present disclosure.
  • FIG. 13 is a partial cross-sectional structural view of a display panel in another embodiment of the present disclosure.
  • FIG. 14 is a partial cross-sectional structural view of a display panel in another embodiment of the present disclosure.
  • 15 is a schematic flow chart of a method of preparing a display panel in an embodiment of the present disclosure.
  • 16 is a schematic flow chart of a method of preparing a display panel in another embodiment of the present disclosure.
  • 17 to 24 illustrate structures obtained at various stages of a method of manufacturing a display panel of an embodiment of the present disclosure
  • FIG. 25 is a schematic structural diagram of an illuminating field effect transistor in an embodiment of the present disclosure.
  • Embodiments of the present disclosure are described in detail below.
  • the embodiments described below are illustrative only and are not to be construed as limiting the disclosure.
  • the specific techniques or conditions not described in the examples are understood in accordance with the techniques or conditions described in the literature in the art.
  • the reagents or instruments used are not indicated by the manufacturer, and are conventional products that can be obtained commercially.
  • the pixel structure in the current OLED display panel includes an OLED light emitting layer and a driving thin film transistor (DTFT), wherein the light emitting region of the OLED light emitting layer is covered by the cathode, and is affected by factors such as surface plasmon (SPP) or transmittance.
  • SPP surface plasmon
  • the rate is low; and the existing pixel structure is relatively complicated, and the DTFT occupies a large area, which is not conducive to making a high PPI display panel.
  • the structure of the current display panel and the preparation process thereof are complicated, and the yield is low, which limits its application.
  • the current display panel includes an OLED light-emitting layer and a DTFT which are independently disposed.
  • the light-emitting area of the OLED light-emitting layer is affected by surface plasmons or transmittance due to the coverage of the cathode, so that the light-emitting rate is low, and the occupied area of the DTFT is large.
  • the researchers have proposed an organic light-emitting field effect transistor, which simplifies the OLED and the DTFT into one component, and the light-emitting field effect transistor itself has the driving function of the DTFT and the light-emitting function of the OLED.
  • the pixel structure is simpler.
  • the active layers in the current organic light-emitting field effect transistor are all organic materials, the mobility and conductivity are low, the film thickness is not uniform, the stability is poor, and electrical drift is prone to occur.
  • an object of embodiments of the present disclosure is to provide an illuminating field effect transistor having a simple structure, a high yield, a high light extraction rate, a low power consumption, or a good stability, and a light-emitting field effect transistor including the same Display panel.
  • the illuminating field effect transistor includes: a gate 100; an active layer 200, and the active layer 200 and the gate 100 are spaced apart by a gate insulating layer 300; a light emitting layer 400 stacked on a side of the active layer 200 away from the gate 100; and a source 510 and a drain 520 configured to cause a current
  • the light emitting layer 400 can be flowed through the active layer 200; wherein the active layer 200 is made of an inorganic semiconductor material, and an energy level transition is disposed between the active layer 200 and the light emitting layer 400.
  • Layer 600 is
  • the light-emitting field effect transistor having the above structure has a simple structure and is easy to implement, and the active layer is formed by using an inorganic semiconductor material, so that the mobility of the active layer is higher, the thickness is more uniform, the stability is better, and the process compatibility is better.
  • the conductivity is high, the driver can be driven with a smaller current, the power consumption is lower, the electrical drift is weaker, the picture uniformity can be effectively improved, the display quality is improved, and the energy level is set between the active layer and the light-emitting layer.
  • the transition layer can make the energy level of the light-emitting layer material and the energy level matching of the active layer material better, and improve the performance of the light-emitting field effect transistor.
  • an equivalent circuit diagram of each of the light-emitting field effect transistors may refer to FIG. 2, and an electrode in the entire light-emitting field effect transistor includes a source 510, a drain 520, and a gate 100, and the source
  • the pole 510 and the drain 520 serve as a cathode or an anode of the light-emitting layer, and the switch or current magnitude of the gate 100 can be controlled by the data signal a to control the current flowing through the source 510, the drain 520, and the light-emitting layer. Control whether the luminescent layer emits light or its illuminating intensity.
  • FIG. 1 the specific structure of the illuminating field effect transistor is exemplarily illustrated in FIG. 1 and is not to be construed as limiting the disclosure.
  • the equivalent circuit diagram can be as shown in FIG. 2, those skilled in the art can It is necessary to appropriately adjust the shape, setting position, and the like of each part.
  • the inorganic semiconductor material forming the active layer includes polycrystalline silicon, ⁇ -silicon, single crystal silicon or a metal oxide semiconductor such as indium gallium zinc oxide (IGZO), or the like.
  • IGZO indium gallium zinc oxide
  • the active layer mobility, the thickness uniformity, and the performance stability can be further improved, the process compatibility is better, and the driving can be realized with a smaller current, and the power consumption is small.
  • the active layer may be a p-type active layer or an n-type active layer.
  • the light-emitting field effect transistor of the embodiment of the present disclosure is provided with energy A graded transition layer that is matched to the active layer level such that charge can be smoothly conducted between the active layer, the level transition layer, and the luminescent layer at a suitable voltage.
  • the active layer is a p-type active layer (ie, a material forming the active layer is a p-type inorganic semiconductor material), and the highest occupied molecular orbital of the energy level transition layer is The work function energy levels of the p-type active layer are matched, that is, the highest occupied molecular orbital of the energy level transition layer overlaps with the electron orbit of the p-type active layer. Thereby, the energy level matching between the light-emitting layer and the active layer can be achieved through the energy level transition layer, thereby achieving a better light-emitting effect of the light-emitting layer.
  • the active layer is an n-type active layer (ie, the material forming the active layer is an n-type inorganic semiconductor material), and the lowest unoccupied molecular orbital of the energy level transition layer is The work function level of the n-type active layer is matched, that is, the lowest unoccupied molecular orbital of the energy level transition layer overlaps with the electron orbit of the n-type active layer.
  • the energy level matching between the light-emitting layer and the active layer can be achieved through the energy level transition layer, thereby achieving a better light-emitting effect of the light-emitting layer.
  • level matching in this paper means: taking the p-type active layer as an example for illustration, when the highest occupied molecular orbital of the energy level transition layer and the work function of the p-type active layer
  • level matching in the presence of a suitable voltage difference between the source and the drain, the charge can be conducted in the p-type active layer, the energy level transition layer, and the light-emitting layer; when the highest occupied molecule of the energy level transition layer
  • the power function level difference between the track and the p-type active layer exceeds a certain critical value, no matter how much voltage difference is applied between the source and the drain, the charge cannot be in the p-type active layer, the energy level transition layer, and the light-emitting layer.
  • the highest occupied molecular orbital of the energy level transition layer does not match the work function energy level of the p-type active layer. It can be understood that when the p-type active layer or the energy level transition layer selects different materials, the threshold value of the work function energy level difference between the highest occupied molecular orbit of the energy level transition layer and the p-type active layer is different. The technician can select an appropriate energy level matching transition layer and active layer according to actual needs.
  • the material forming the energy level transition layer is not particularly limited, and those skilled in the art can flexibly select according to actual needs as long as the requirements can be met.
  • the material of the energy level transition layer may be an organic material.
  • an organic hole conductive material or a hole injecting material that can match a polysilicon work function of 5.05 eV as an energy level transition layer material, which may include, but is not limited to, N,N'-diphenyl-N,N'-di-m-tolyl-1,1'biphenyl-4,4'-diamine (TPD) (ion potential energy (LUMO) 5.1 eV).
  • TPD N,N'-diphenyl-N,N'-di-m-tolyl-1,1'biphenyl-4,4'-diamine
  • LUMO on potential energy
  • n-type conductive IGZO For an active layer formed using n-type conductive IGZO, it can be matched with 1,3,5-tris(1-phenyl-1H-benzimidazol-2-yl)benzene (TPBi) (LUMO 2.7 eV). Therefore, the material source is wide, and the energy level of the light-emitting layer material and the energy level of the active layer material can be better matched, the display effect is improved, and the use performance is better.
  • TPBi 1,3,5-tris(1-phenyl-1H-benzimidazol-2-yl)benzene
  • FIG. 3 in order to better ensure that the current between the source 510 and the drain 520 can flow through the light emitting layer 400 via the active layer 200, so that the field effect transistor has both driving and light emitting functions, FIG. 3 can be employed.
  • the source 510 can be electrically connected to the light emitting layer 400, and the drain 520 and the light emitting layer 400 are electrically connected; the embodiment shown in FIG. 1 can also be used, and the source 510 can also be electrically connected to the active layer 200.
  • the drain 520 and the light emitting layer 400 are electrically connected. Thereby, it is possible to effectively enable a current flowing between the source and the drain to flow through the light-emitting layer via the active layer, and to function both as a driving function and as a light-emitting function.
  • the source may be directly connected to the light emitting layer or the active layer to achieve electrical connection (refer to FIGS. 1 and 3 ), and the source may be directly connected to the light emitting layer for detailed description below.
  • the source may be disposed on a surface of the light emitting layer away from the active layer, and an orthographic projection of the source on the active layer overlaps with an orthographic projection of the light emitting layer on the active layer (refer to FIG. 3), in order to improve the light emitting field
  • the light transmittance of the effect transistor the source may be a transparent electrode, whereby the light transmittance of the light-emitting field effect transistor can be improved.
  • the semiconductor material forming the active layer is an N-type semiconductor material
  • the source is optionally provided as a transparent electrode, while optionally the drain is provided as a non-transparent electrode;
  • the semiconductor material of the active layer is a p-type semiconductor material, optionally with the drain as a transparent electrode and optionally the source as a non-transparent electrode.
  • the drain 520 may be directly connected to the light emitting layer 400 to achieve electrical connection, and the orthographic projection of the drain on the active layer and the orthographic projection of the light emitting layer on the active layer Partially overlapping, and the drain can be a transparent electrode. Thereby, the light transmittance of the light-emitting field effect transistor can be effectively improved.
  • the drain 520 may also be indirectly electrically connected to the light emitting layer 400.
  • the light emitting field effect transistor further includes a connection electrode 700.
  • the light emitting layer 400 and the drain 520 are electrically connected through the connection electrode 700.
  • an orthographic projection of the connection electrode on the active layer overlaps with an orthographic projection of the light emitting layer on the active layer. Therefore, the structure is simple and easy to implement, and the connecting electrode does not completely cover the light emitting layer, and the light emitted from the light emitting layer does not need to be emitted through the connecting electrode, and the light utilization efficiency is higher.
  • the connection electrode may be a transparent electrode
  • the material for forming the connection electrode is not particularly limited, and those skilled in the art can flexibly select according to actual needs as long as the requirements can be met.
  • the material forming the connection electrode may include, but is not limited to, a transparent conductive oxide such as indium tin oxide, zinc tin oxide, etc., nano-scale metallic silver or Cs 2 CO 3 , etc., and there is no particular limitation on the method of forming the connection electrode, as long as Those skilled in the art can flexibly select according to actual needs.
  • the method of forming the connection electrode can be a mask thermal evaporation method or the like.
  • the drain and/or the connection electrode can be a transparent electrode.
  • the light-emitting area can be further increased, and the light utilization efficiency can be improved.
  • the material forming the source, the drain, or the gate is not particularly limited, and as long as it has an energy level suitable for electron injection, those skilled in the art can flexibly select according to actual needs.
  • the material forming the source, the drain or the gate may be a metal, an alloy, a conductive polymer, indium tin oxide or indium gallium zinc oxide or the like.
  • the shapes of the source and the drain may be designed to have a large aspect ratio.
  • the orthographic projection of the source 510 and the drain 520 on the active layer 200 is two spaced concentric rings, wherein the ring should be made
  • the ring may be a closed ring, such as the square ring shown in FIG. 5, a circular ring or other closed ring, or an unclosed ring, such as U-shaped or C-shaped. It is not limited here, and the C-type structure can be specifically referred to FIG. 6.
  • the channel width-to-length ratio can be increased, and the channel current can be increased, and the effect of surface light emission can be obtained, the uniformity of light can be improved, and the display effect can be improved.
  • the orthographic projection of the source and the drain on the active layer is two concentric rings arranged at intervals, the adjacent two sources or drains may be integrated by punching and routing. .
  • the orthographic projections of the source 510 and the drain 520 on the active layer 200 are comb-like, and the comb teeth are disposed to cross each other to form a bow groove. Road.
  • the orthographic projections of the source 510 and the drain 520 on the active layer 200 respectively have a tooth shape, including a plurality of protruding extensions and a recess between the extensions, and an extension of the source 510 The portion extends into the recess of the drain 520, and the extension of the drain 520 extends into the recess of the source 510.
  • the orthographic projections of the source 510 and the drain 520 on the active layer 200 respectively form a letter "F" shape.
  • the luminescent layer may be an organic electroluminescent layer, and the structure of the luminescent layer is not particularly limited, as long as the illuminating requirements can be met, those skilled in the art can flexibly select according to actual needs.
  • the light-emitting layer may include a hole transport layer (GHTL), a hole injection layer, a hole blocking layer (HBL), an electron transport layer (ETL), an electron injection layer, and an electron in addition to the basic organic electroluminescent layer. At least one of the barrier layers.
  • the material forming each layer of the light-emitting layer is a material of a conventional light-emitting layer, and details are not described herein again.
  • the material for forming the gate insulating layer is not particularly limited, and those skilled in the art can flexibly select according to actual needs as long as the requirements can be satisfied.
  • the material for forming the gate insulating layer may include, but is not limited to, silicon dioxide, silicon nitride or conjugated polyvinyl carbazole, etc., whereby the insulating effect is better and the use performance is better.
  • an embodiment of the present disclosure provides a display panel.
  • the display panel includes a plurality of the aforementioned light-emitting field effect transistors. The designer has found that the display panel has a simple structure, is easy to implement, has a better display effect, better use performance, and has all the features and advantages of the foregoing illuminating field effect transistor, which will not be described in detail herein.
  • the plurality of the light-emitting field effect transistors are arranged such that sources of two adjacent light-emitting field effect transistors adjacent in the first direction are integrally formed as a first combined body,
  • the drains of the two adjacent light-emitting field effect transistors in the first direction are integrally formed as a second combined body, and the first combined body and the second combined body are alternately disposed in the first direction.
  • the structure of the source and the drain in the illuminating field effect transistor will be described below by taking five illuminating field effect transistors as an example. For details, refer to FIG. 8, which are respectively labeled 1, 2, 3, 4, and 5 on the five illuminating field effect transistors.
  • the illuminating field effect transistors 1 and 2 are adjacent in the first direction, and the sources 510 of the two illuminating field effect transistors are integrated to form the first combining body 511, which will illuminate the field
  • the drain 520 of the effect transistor 2 is integrated with the drain 520 of the adjacent light-emitting field effect transistor 3 to form a second combined body 521, and then the source 510 of the light-emitting field effect transistor 3 is in the first direction and
  • the source 510 of the adjacent illuminating field effect transistor 4 is integrated to form the first combined body 511, and so on, the drains 520 of the adjacent illuminating field effect transistors 4 and 5 in the first direction are integrated to form a second The body 521 is combined.
  • the pixel circuit can be simplified, and the line width can be increased to reduce the resistance.
  • the above examples are merely exemplary and are only used to illustrate the present application, and are not to be construed as limiting the present application.
  • Those skilled in the art may select an appropriate number of light-emitting field effect transistors according to the needs of different display panels and The structure and connection of the source and drain of the luminescence field effect transistor are adaptively set. According to a specific example of the present disclosure, referring to FIG.
  • a plurality of light-emitting field effect transistors are spaced apart and arrayed, and a plurality of light-emitting field effect transistors are arranged such that adjacent in a second direction perpendicular to the first direction
  • the source 510 of all the illuminating field effect transistors is integrally formed as the first combined body 511, and the drains 520 of all the illuminating field effect transistors adjacent in the second direction are integrally formed into the second combination
  • the body 521 is connected to the power line, and the second unit 522 is connected to the ground line.
  • the source 510 of all the illuminating field effect transistors adjacent in the second direction perpendicular to the first direction is integrally formed as described above.
  • a first combined body 511, the drains 520 of all the light-emitting field effect transistors adjacent in the second direction are integrally formed as the second combined body 521, and the first combined body 511 is connected to a power line.
  • the second combination 522 is connected to the ground line.
  • the integration of the source and the drain described above should be understood in a broad sense, and the integration may be to form two sources or drains adjacent in the first direction or the second direction during the preparation process.
  • An integral body (such as a wire forming a first direction or two sources or drains adjacent in the second direction) is integrated, or may form an independent source and drain first, and then will be in the first direction or
  • the two adjacent sources or drains in the second direction are electrically connected by punching and routing (for example, the first source or the two sources adjacent in the second direction are separately provided by the wires or
  • the drain electrical connection is integrated, whereby the structure is simple, easy to implement, and the pixel circuit can be simplified.
  • the display panel in order to realize the display function of the display device, referring to FIG. 11 and FIG. 13, the display panel includes a switching thin film transistor, the source 540 of the switching thin film transistor is connected to the data line, and the gate 550 and the gate are connected. The wires are connected, and the drain 530 is electrically connected to the gate 100 of the light-emitting field effect transistor. Therefore, the structure is simple, easy to implement, and cost-effective, and the thin film transistor can be effectively used for controlling the switch of the light-emitting field effect transistor to realize the display function of the display device.
  • the display panel may be classified into a bottom source-drain type display panel or a top source-drain type display panel according to different source and drain positions.
  • the bottom-drain-type display panel includes, in addition to the foregoing light-emitting field effect transistor and switching thin film transistor, a substrate 710 disposed on one surface of the substrate 710.
  • the buffer layer 720 is disposed on the surface of the gate insulating layer 300 away from the substrate 710 and covers the active layer 200 and the interlayer dielectric layer 500 of the active layer 560 of the switching thin film transistor.
  • the interlayer dielectric layer 500 is disposed away from the substrate 710.
  • the switching thin film transistor is disposed on the surface of the buffer layer 720 away from the substrate 710
  • the source 510 in the light emitting field effect transistor is electrically connected to the active layer 200
  • the drain 520 and the light emitting layer 400 are connected to the electrode 700.
  • the connection electrode 700 and the drain 520 are connected via vias to form an actual drain in the bottom-drain-type display panel.
  • the principle of illumination of the panel is that holes are directly injected from the source 510 into the active layer 200 and flow through the energy level transition layer 600 and the electroluminescent layer in the light emitting layer 400 to the drain 520, and electrons are injected from the drain 520 to In the electroluminescent layer, electron holes converge in the electroluminescent layer to quench the luminescence.
  • the injected holes and electrons flow obliquely toward the opposite pole in the channel, increasing the probability of exciton formation, thereby improving the performance of the display panel.
  • the drains 520 of two adjacent light-emitting field effect transistors may be integrated by wires, and one of the two adjacent light-emitting field effect transistors
  • the two source 510s of the third illuminating field effect transistor adjacent thereto can also be integrated by wires, thereby simplifying the structure, realizing the simplification of the circuit, saving cost, and the structure of the source and the connecting electrode and the drain. It is asymmetrically up and down, which is beneficial to increase the probability of recombination of electrons and holes, and increase the photoelectric conversion efficiency of the light-emitting field effect transistor.
  • the source can serve as an anode of the light-emitting layer
  • the drain can serve as a cathode of the light-emitting layer
  • the anodes of two adjacent light-emitting field effect transistors can share a single trace, one of the two adjacent light-emitting field effect transistors and
  • the two cathodes of the adjacent third illuminating field effect transistor can also share a single trace, thereby increasing the trace area, reducing the trace resistance, and reducing the tolerance of the etch process.
  • the top-source-drain-type display panel is different from the structure of the bottom-drain-type display panel in that a source 510 is away from the light-emitting layer 400.
  • a portion of the surface of the active layer 200 is in contact to electrically connect the source 510 to the light emitting layer 400.
  • the connection electrode 700 and the drain 520 are connected via via holes to become the actual drain of the top-source-drain-type display panel.
  • the principle of the light is: after the hole is injected from the source 510, the light flows through the light emitting layer 400 to the active layer 200, then flows along the active layer 200 to the side of the connecting electrode 700, and flows again through the electrophoretic layer 400.
  • the light-emitting layer flows to the drain 520, and electrons are injected from the drain 520 to the electroluminescent layer, and the electron holes converge at the light-emitting layer to quench the light.
  • 14 is a cross-sectional view of a display panel including a top-source-drain-type structure, the drains 520 of two adjacent light-emitting field effect transistors may be integrated by wires, and in the two adjacent light-emitting field effect transistors
  • the two source 510s of a third illuminating field effect transistor adjacent thereto can also be integrated by wires, thereby simplifying the structure, simplifying the pixel circuit, saving cost, and facilitating the simplification of the manufacturing process (eg,
  • the source and the connection electrode may be formed by one process.
  • the source may serve as an anode of the light-emitting layer
  • the drain may serve as a cathode of the light-emitting layer
  • the anodes of two adjacent light-emitting field effect transistors may share a single trace.
  • One of the two adjacent illuminating field effect transistors and the two cathodes of the third illuminating field effect transistor adjacent thereto can also share a single trace, thereby increasing the trace area and reducing the trace resistance. And reduce the tolerance of the etching process.
  • the gates are time-divisionally driven to meet the display requirements of the display device.
  • the light emitting layer 400 further includes: a hole transport layer 410, an electroluminescent layer 420 disposed on the surface of the hole transport layer 410 away from the substrate 710, and being disposed in the electroluminescence
  • the layer 420 is away from the hole blocking layer 430 on the surface of the substrate 710 and the electron transport layer 440 disposed on the surface of the hole blocking layer 430 away from the substrate 710, whereby the structure is simple and easy to implement, and electroluminescence and luminous efficiency can be effectively realized. Higher.
  • the hole transport layer, the electroluminescent layer, the hole blocking layer, and the electron transport layer are identical to a conventional hole transport layer, an electroluminescence layer, a hole blocking layer, and an electron transport layer, I won't go into too much detail here.
  • an embodiment of the present disclosure provides a display device.
  • the display device includes the display panel described above.
  • the display device has found that the display panel has a higher PPI, higher display quality, better use performance, and the display device has all the features and advantages of the display panel described above, and will not be described again.
  • the above display panel is consistent with the foregoing description, and details are not described herein again.
  • the display device includes a structure that the conventional display device should have in addition to the display panel described above, such as a protective cover, a polarizer, a touch substrate, a flat layer, or a package structure. No more details here.
  • embodiments of the present disclosure provide a method of preparing a display panel. According to an embodiment of the present disclosure, the method includes forming a plurality of light-emitting field effect transistors distributed in an array on a first surface of a substrate.
  • FIG. 11 and FIG. 13 are schematic cross-sectional structures of one light-emitting field effect transistor and one light-emitting transistor in the display panel
  • FIG. 12 And shown in FIG. 14 is a schematic cross-sectional structural view of three sub-pixels in the display panel.
  • the steps of forming the light-emitting field effect transistor include:
  • the gate, the active layer, the source, the drain, the light emitting layer, and the energy level transition layer are consistent with the foregoing description, and no further details are provided herein.
  • the manner of forming the gate may be etching or deposition; the active layer may be formed by excimer laser annealing or excimer laser annealing or wet etching.
  • the way of forming the source and the drain may be a thermal evaporation method or a sputtering etching method, etc., and the method of forming the energy level transition layer is deposited by thermal evaporation, thereby making the operation simple and convenient, and easy. Realized, the product yield is high.
  • the step of forming the light emitting layer further includes the steps of forming a hole transporting layer, an electroluminescent layer, a hole blocking layer, and an electron transporting layer, forming the hole transporting layer, the electroluminescent layer, and the hole
  • the method of the barrier layer and the electron transport layer may be a thermal evaporation method, whereby the structure or the process is simple, and the formed light-emitting layer has better applicability.
  • the foregoing method may further include:
  • connection electrode 700 forming the connection electrode 700, and the structure diagram can be seen in FIG. 4.
  • connection electrode is identical to the previous description, and will not be further described herein.
  • manner of forming the connection electrode may be a method such as thermal evaporation.
  • the source and the connection electrode are formed by one patterning process, thereby making the preparation process simple, convenient, and cost-effective. And the yield is high.
  • the patterning process may be a mask thermal evaporation process or the like.
  • forming the above-described switching thin film transistor further includes the step of forming a gate, a source, a drain, and an active layer of the switching thin film transistor.
  • the manner of forming the gate of the switching thin film transistor may be etching or deposition, and the manner of forming the source and the drain of the switching thin film transistor may be thermal evaporation or sputtering etching; Therefore, the preparation process is simple, convenient, and cost-saving, and the switch thin film transistor can be effectively used for controlling the switch of the sub-pixel to realize the display function of the display device.
  • the structure of the prepared display surface is greatly simplified, the yield is improved, and the light extraction rate is high, which is suitable for preparing high PPI products.
  • the substrate 710 is cleaned, and a buffer layer 720 is formed on the surface of the substrate 710. See FIG. 17 for a schematic structural view;
  • the buffer layer 720 is away from the surface of the substrate 710 to form the gate 100 and the gate 550 of the switching thin film transistor, a schematic structural diagram with reference to Figure 18;
  • a buffer insulating layer 300 is formed on the surface of the buffer layer 720 away from the substrate 710 and covers the gate 100 and the gate 550 of the switching thin film transistor, and the structure is shown in FIG. 19;
  • an initial active layer 740 is formed on the surface of the gate insulating layer 300 away from the substrate 710, a schematic structural view is shown in FIG. 20;
  • the initial active layer 740 is patterned to form the active layer 200 and the active layer 560 of the switching thin film transistor, the structure diagram is shown in Figure 21;
  • An interlayer dielectric layer 500 is formed on the surface of the gate insulating layer 300 away from the substrate 710 and covers the active layer 200 and the active layer 560 of the switching thin film transistor, in the interlayer dielectric layer 500. Punching and depositing a source 510, a drain 520, a drain 530 of the switching thin film transistor, and a source 540 of the switching thin film transistor, a schematic structural view is shown in FIG. 22;
  • the energy level transition layer 600 and the light emitting layer 400 are formed by an evaporation method, wherein the light emitting layer 400 is on the surface of the energy level transition layer 600 away from the substrate 710, and the structure is shown in FIG. 24;
  • connection electrode 700 ie, the cathode
  • the connection electrode 700 is formed by a mask evaporation method, and the structure is shown in FIG.
  • the OLED and the DTFT are independently disposed, and the OLED light-emitting layer has a low light-emitting efficiency due to the coverage of the cathode, and the DTFT is disadvantageous for the high PPI due to the large occupied space.
  • the preparation of the display panel thus limits its application.
  • an illuminating field effect transistor is used instead of the OLED luminescent layer and the DTFT, which itself has the driving function of the DTFT and the illuminating function of the OLED luminescent layer, so that the display panel structure is simpler and the prepared display is obtained.
  • the screen is thinner, the process flow is reduced, the product yield is higher, and the inorganic active layer is used to drive the light-emitting layer to emit light, which can be driven with a smaller current, consume less energy, and has high mobility, high conductivity, and electricity.
  • the property drift is weak, the stability is better, the process compatibility is better, and a transition layer is disposed between the inorganic active layer and the light-emitting layer to make the energy level of the light-emitting layer material and the energy level of the active layer material match better. , improve the display.
  • the light-emitting region of the light-emitting field effect transistor is outside the coverage of the cathode, and is not affected by factors such as surface plasmons or transmittance, and the light-emitting efficiency is high, and more importantly, the light-emitting field effect transistor itself
  • the light-emitting area is smaller than the OLED light-emitting layer, and is suitable for producing a high PPI display panel.
  • the energy level transition layer is disposed to compensate for a large difference between the energy level of the active layer formed using the inorganic semiconductor material and the energy level of the light emitting layer, in the active layer and the light emitting layer.
  • the energy level transition layer is disposed between the energy level of the light emitting layer material and the energy level of the active layer material to improve the performance of the light emitting field effect transistor.
  • an energy level transition layer is not necessary, especially when the energy level difference between the active layer and the light-emitting layer is not significant.
  • 25 is an illuminating field effect transistor of one embodiment of the present disclosure, which differs from the embodiment illustrated in FIG. 1 in that no energy level transition layer is disposed between the active layer 200 and the luminescent layer 400.
  • the light-emitting field effect transistor includes: a gate electrode 100; an active layer 200, the active layer 200 and the gate electrode 100 are separated by a gate insulating layer 300; a light-emitting layer 400, the light-emitting layer 400 is stacked on a side of the active layer 200 away from the gate 100; and a source 510 and a drain 520 configured to enable current to pass through the active layer 200 Flowing through the light emitting layer 400; wherein the active layer 200 is made of an inorganic semiconductor material.
  • the light-emitting field effect transistor having the above structure can be configured as a display panel for display application, has a simple structure, is easy to implement, and forms an active layer using an inorganic semiconductor material to make the active layer have higher mobility, uniform thickness, and stability.
  • the performance is better, the process compatibility is better, the conductivity is higher, the driving can be realized with a smaller current, the power consumption is lower, the electrical drift is weaker, the picture uniformity can be effectively improved, and the display quality is improved.

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Abstract

一种显示面板，包括：衬底基板；栅极，所述栅极位于衬底基板上；有源层，所述有源层与所述栅极之间通过栅绝缘层间隔开；发光层，所述发光层层叠在所述有源层的远离所述栅极一侧；以及源极和漏极，所述源极和漏极被配置成使得电流能够经由所述有源层流过所述发光层。图1

Description

显示面板
相关申请的交叉引用
本申请要求于2018年1月15日递交的中国专利申请CN201810036170.3的权益，其全部内容通过参考并入本文中。
技术领域
本公开的实施例涉及显示技术领域，具体地，涉及一种显示面板。
背景技术
目前的OLED显示面板中的像素结构包括OLED发光层和驱动薄膜晶体管(DTFT)。这样的显示面板仍有待改进。
公开内容
在本发明的一个方面，本发明的实施例提供了一种显示面板，包括：
衬底基板；
栅极，所述栅极位于衬底基板上；
有源层，所述有源层与所述栅极之间通过栅绝缘层间隔开；
发光层，所述发光层层叠在所述有源层的远离所述栅极一侧；以及
源极和漏极，所述源极和漏极被配置成使得电流能够经由所述有源层流过所述发光层。
根据本发明的实施例，所述有源层与所述发光层之间设置有能级过渡层。
根据本发明的实施例，所述有源层由无机半导体材料制成。
根据本发明的实施例，所述无机半导体材料包括多晶硅、单晶硅和金属氧化物半导体中的至少一种。
根据本发明的实施例，所述源极和所述漏极在所述有源层上的正投影为两个间隔设置的同心非闭合环形。
根据本发明的实施例，所述源极和所述有源层电连接，并且所述漏极和所述发光层电连接。
根据本发明的实施例，所述源极和所述发光层电连接，并且所述漏极和所述发光层电连接。
根据本发明的实施例，所述显示面板还包括连接电极，所述发光层和所述漏极通过所 述连接电极电连接。
根据本发明的实施例，所述连接电极在所述有源层上的正投影与所述发光层在所述有源层上的正投影部分重叠。
根据本发明的实施例，所述漏极和/或所述连接电极为透明电极。
根据本发明的实施例，所述有源层为p型有源层，所述能级过渡层的最高被占据分子轨道与所述p型有源层的功函数能级匹配。
根据本发明的实施例，所述有源层为n型有源层，所述能级过渡层的最低未占分子轨道与所述n型有源层的功函数能级匹配。
根据本发明的实施例，栅极、有源层、栅绝缘层、发光层、源极和漏极形成发光场效应晶体管，所述显示面板包括多个发光场效应晶体管，所述多个所述发光场效应晶体管被布置成：使得在第一方向上相邻的两个发光场效应晶体管的源极一体化形成为第一结合体，在所述第一方向上相邻的两个发光场效应晶体管的漏极一体化形成为第二结合体，并且所述第一结合体和所述第二结合体在所述第一方向上交替设置。
根据本发明的实施例，所述多个所述发光场效应晶体管被布置成：使得在与所述第一方向垂直的第二方向上相邻的所述发光场效应晶体管的源极一体化形成为所述第一结合体，在所述第二方向上相邻的所述发光场效应晶体管的漏极一体化形成为所述第二结合体，
所述第一结合体连接至电源线，所述第二结合体连接至接地线。
根据本发明的实施例，所述显示面板还包括开关薄膜晶体管，所述开关薄膜晶体管的源极与数据线连接，所述开关薄膜晶体管的栅极与栅线连接，所述开关薄膜晶体管的漏极与所述发光场效应晶体管的栅极电连接。
附图说明
图1是本公开一个实施例中的发光场效应晶体管的结构示意图；
图2是本公开一个实施例中的发光场效应晶体管的等效电路示意图；
图3是本公开另一个实施例中的发光场效应晶体管的结构示意图；
图4是本公开另一个实施例中的发光场效应晶体管的结构示意图；
图5是本公开一个实施例中源极和漏极在有源层上的正投影的结构示意图；
图6是本公开另一个实施例中源极和漏极在有源层上的正投影的结构示意图；
图7是本公开一个实施例中的多个发光场效应晶体管的源极和漏极在有源层上的正投影的结构示意图；
图8是本公开另一个实施例中的多个发光场效应晶体管的源极和漏极的结构示意图；
图9是本公开一个实施例中的显示面板的部分平面结构示意图；
图10是本公开另一个实施例中的显示面板的部分平面结构示意图；
图11是本公开另一个实施例中的显示面板的部分剖面结构示意图；
图12是本公开另一个实施例中的显示面板的部分剖面结构示意图；
图13是本公开另一个实施例中的显示面板的部分剖面结构示意图；
图14是本公开另一个实施例中的显示面板的部分剖面结构示意图；
图15是本公开一个实施例中制备显示面板的方法的流程示意图；
图16是本公开另一个实施例中制备显示面板的方法的流程示意图；
图17-图24示出了在本公开的实施例的制备显示面板的方法的各个阶段所获得的结构；以及
图25是本公开一个实施例中的发光场效应晶体管的结构示意图。
具体实施方式
下面详细描述本公开的实施例。下面描述的实施例是示例性的，仅用于解释本公开，而不能理解为对本公开的限制。实施例中未注明具体技术或条件按照本领域内的文献所描述的技术或条件理解。所用试剂或仪器未注明生产厂商者，均为可以通过市购获得的常规产品。
目前的OLED显示面板中的像素结构包括OLED发光层和驱动薄膜晶体管(DTFT)，其中，OLED发光层的发光区域被阴极覆盖，受到表面等离子激元(SPP)或透射率等因素的影响，出光率较低；并且现有的像素结构比较复杂，且DTFT占用面积较大，不利于制作高PPI显示面板。目前的显示面板的结构及其制备工艺流程复杂，良率低，限制了其应用。
本公开的实施例是基于设计人的以下认识和发现而完成的：
目前的显示面板中含有独立设置的OLED发光层和DTFT，OLED发光层的发光区域由于阴极的覆盖会受到表面等离子激元或者透射率的影响使得其出光率较低，DTFT的占用面积较大以至于不利于制备高PPI的显示面板，因此研究人员提出了有机发光场效应晶体管，将OLED和DTFT简化为一个元件，发光场效应晶体管本身兼备了DTFT的驱动作用和OLED的发光功能，二者结合起来使得像素结构更简单，目前的有机发光场效应晶体管中的有源层均为有机材料，迁移率和导电率较低，膜厚不均匀，稳定性较差，易发生电性漂移。针对上述问题，设计人研究后发现，有源层选用无机材料制备，可以提高迁移率和导电率，可以利用较小的电流实现驱动，功耗较低，电性漂 移较弱，稳定性较佳，可以提高显示画面的均匀性。
有鉴于此，本公开的实施例旨在至少在一定程度上解决相关技术中的技术问题之一。为此，本公开的实施例的一个目的在于提出一种结构简单、良率较高、出光率较高、功耗较小或者稳定性较佳的发光场效应晶体管，以及包括该发光场效应晶体管的显示面板。
在本公开的一个方面，本公开的实施例提供了一种发光场效应晶体管。根据本公开的实施例，参照图1，所述发光场效应晶体管包括：栅极100；有源层200，所述有源层200与所述栅极100之间通过栅绝缘层300间隔开；发光层400，所述发光层400层叠在所述有源层200的远离所述栅极100一侧；以及源极510和漏极520，所述源极510和漏极520被配置成使得电流能够经由所述有源层200流过所述发光层400；其中，所述有源层200由无机半导体材料制成，所述有源层200与所述发光层400之间设置有能级过渡层600。设计人发现，具有上述结构的发光场效应晶体管结构简单，易于实现，并且采用无机半导体材料形成有源层使得有源层的迁移率较高，厚度较均匀，稳定性较佳，工艺兼容性较好，导电率较高，可以利用更小的电流实现驱动，功耗较低，电性漂移较弱，可有效改善画面均匀性，提高显示质量，在有源层与发光层之间设置能级过渡层可以使得发光层材料的能级和有源层材料的能级匹配性更好，提高发光场效应晶体管的使用性能。
根据本公开的实施例，每个所述发光场效应晶体管的等效电路图可参照图2，整个发光场效应晶体管中的电极中包括源极510、漏极520以及栅极100，且所述源极510以及所述漏极520作为发光层的阴极或者阳极，可以通过数据信号a来控制栅极100的开关或者电流大小以控制流经源极510、漏极520以及发光层的电流大小，进而控制发光层是否发光或者其发光强度。
需要说明的是，图1中仅是示例性说明发光场效应晶体管的具体结构，并不能理解为是对本公开的限制，只要其等效电路图可以如图2所示，本领域技术人员可以根据实际需要对其中的各部分的形状、设置位置等进行适当调整。
根据本公开的实施例，形成有源层的无机半导体材料包括多晶硅，α-硅，单晶硅或金属氧化物半导体(如铟镓锌氧化物(IGZO))等。由此，可以进一步提高有源层迁移率、厚度均匀性和性能稳定性，工艺兼容性更佳，并能利用较小的电流实现驱动，功耗较小。根据本公开的实施例，有源层可以为p型有源层，也可以为n型有源层。
根据本公开的实施例，由于无机半导体材料形成的有源层的能级与发光层的能级相差较大，为了有效实现电荷的传导，本公开的实施例的发光场效应晶体管中设置有能级过渡层，该能级过渡层与有源层能级匹配，以使得在合适的电压下电荷可以在有源层、能级过渡层和发光层之间顺利传导。具体的，在本公开的一些实施例中，所述有源层为p型有源 层(即形成有源层的材料为p型无机半导体材料)，能级过渡层的最高被占据分子轨道与所述p型有源层的功函数能级匹配，也就是说所述能级过渡层的最高被占据分子轨道与所述p型有源层的电子轨道存在交叠。由此，可以通过能级过渡层实现发光层和有源层的能级匹配，进而实现发光层较佳的发光效果。在本公开的另一些实施例中，所述有源层为n型有源层(即形成有源层的材料为n型无机半导体材料)，能级过渡层的最低未占分子轨道与所述n型有源层的功函数能级匹配，也就是说所述能级过渡层的最低未占分子轨道与所述n型有源层的电子轨道存在交叠。由此，可以通过能级过渡层实现发光层和有源层的能级匹配，进而实现发光层较佳的发光效果。需要说明的是，本文中的术语“能级匹配”的含义是：以p型有源层为例进行说明，当能级过渡层的最高被占据分子轨道与p型有源层的功函数能级匹配时，在源极和漏极之间存在合适的电压差的情况下，电荷可以在p型有源层、能级过渡层和发光层中传导；当能级过渡层的最高被占据分子轨道与p型有源层的功函数能级差超过某个临界值时，无论源极和漏极之间施加多大的电压差，电荷都无法在p型有源层、能级过渡层和发光层中传导，此时，能级过渡层的最高被占据分子轨道与p型有源层的功函数能级不匹配。可以理解的是，当p型有源层或者能级过渡层选择不同的材料时，能级过渡层的最高被占据分子轨道与p型有源层的功函数能级差的临界值不同，本领域技术人员可以根据实际需要选择合适的能级匹配的能级过渡层与有源层。
根据本公开的实施例，对形成所述能级过渡层的材料没有特别限制，只要能够满足要求，本领域技术人员可以根据实际需要灵活选择。在本公开的一些实施例中，能级过渡层的材料可以为有机材料。例如，对于利用p型导电多晶硅形成的有源层来说，需要找到一种可以匹配多晶硅功函数5.05eV的有机空穴导电材料或空穴注入材料作为能级过渡层材料，可以包括但不限于N，N’-二苯基-N，N’-二间甲苯基-1，1’联苯-4，4’-二胺(TPD)(离子势能(LUMO)5.1eV)。对于利用n型导电IGZO形成的有源层来说，可以用1，3，5-三(1-苯基-1H-苯并咪唑-2-基)苯(TPBi)(LUMO 2.7eV)来匹配，由此，材料来源广泛，且能够使得发光层材料的能级与有源层材料的能级匹配性更好，提高显示效果，使用性能较佳。
根据本公开的实施例，为了更好的保证源极510和漏极520之间的电流能够经由有源层200流过发光层400，使得场效应晶体管兼具驱动和发光功能，可以采用图3所示的实施方式，源极510可以和发光层400电连接，漏极520和发光层400电连接；也可以采用图1所示的实施方式，源极510也可以和有源层200电连接，漏极520和发光层400电连接。由此，能够有效使得流经源极和漏极之间的电流能够经由所述有源层流过所述发光层，既能起到驱动作用，又可以发挥发光功能。
根据本公开的一些实施例，源极可以与发光层或者有源层直接相连以实现电连接(参 照图1和图3)，下面以源极可以与发光层直接相连进行较详细的说明，具体的，源极可以设置在发光层远离有源层的表面，且源极在有源层上的正投影与发光层在有源层上的正投影部分重叠(参照图3)，为了提高发光场效应晶体管的透光率，源极可以为透明电极，由此，可以提高发光场效应晶体管的透光率。
根据本公开的一些具体实施例，如果形成有源层的半导体材料为N型半导体材料，则可选地将源极设置为透明电极，同时可选地将漏极设置为非透明电极；如果形成有源层的半导体材料为p型半导体材料，则可选地将漏极设置为透明电极，同时可选地将源极设置为非透明电极。由此，有利于提高注入效率，提高光电转化效率。
根据本公开的实施例，参照图1或者3，漏极520可以与发光层400直接相连以实现电连接，且漏极在有源层上的正投影与发光层在有源层上的正投影部分重叠，且漏极可以为透明电极。由此，可以有效提高发光场效应晶体管的透光率。
根据本公开的实施例，参照图4，漏极520也可以间接与发光层400电连接，为了实现漏极520与发光层400的电连接，所述发光场效应晶体管还包括连接电极700，所述发光层400和所述漏极520通过所述连接电极700电连接。由此，利于简化制备工艺，并且能够使得漏极与发光层电连接效果较佳。根据本公开的实施例，所述连接电极在所述有源层上的正投影与所述发光层在所述有源层上的正投影部分重叠。由此，结构简单，易于实现，并且连接电极不完全覆盖发光层，发光层发出的光不需要经过连接电极出射，光利用率更高。
根据本公开的实施例，连接电极可以为透明电极，且对形成连接电极的材料没有特别限制，只要能够满足要求，本领域技术人员可以根据实际需要灵活选择。例如形成连接电极的材料可以包括但不限于透明导电氧化物如氧化铟锡、氧化锌锡等、纳米级别的金属银或者Cs 2CO 3等，对形成连接电极的方法也没有特别限制，只要能够满足要求，本领域技术人员可以根据实际需要灵活选择，例如形成连接电极的方法可以为掩膜版热蒸镀法等。
可见，所述漏极和/或所述连接电极可以为透明电极。由此，可以进一步增大发光面积，提高光利用率。
根据本公开的实施例，对形成源极、漏极或者栅极的材料没有特别限制，只要具有适合电子注入的能级，本领域技术人员可以根据实际需要灵活选择。例如形成源极、漏极或者栅极的材料可以为金属、合金、导电聚合物、氧化铟锡或者铟镓锌氧化物等。
根据本公开的实施例，为了获得较大的沟道电流，可以对源极与漏极的形状进行设计，使其具有较大的宽长比。在本公开的一些实施例中，参照图5，所述源极510和所述漏极520在所述有源层200上的正投影为两个间隔设置的同心环形，其中，上述环形应当做广 义的理解，所述环形可以为封闭的环形，例如图5中示出的方形环，也可以为圆形环或其他封闭的环形，也可以为不封闭的环形，例如U型或者C型等，在此不做限定，其中C型结构具体可参照图6。由此，可以提高沟道宽长比，进而增大沟道电流，同时可以获得面发光的效果，提高光的均匀性，进而提高显示效果。需要说明的是，当源极和漏极在有源层上的正投影为两个间隔设置的同心环形时，可以通过打孔和走线的方式将相邻两个源极或者漏极一体化。在本公开的另一些实施例中，参照图7，所述源极510和所述漏极520在有源层200上的正投影为梳状，且梳齿彼此交叉设置，以形成弓型沟道。具体地，所述源极510和所述漏极520在有源层200上的正投影分别具有齿形，包括多个伸出的延伸部和位于延伸部之间的凹部，源极510的延伸部伸入漏极520的凹部内，漏极520的延伸部伸入源极510的凹部内。在图7中，所述源极510和所述漏极520在有源层200上的正投影分别形成字母“F”形。由此，可以提高沟道宽长比(W/L)，进而增大沟道电流，并且由于像素较小，使得线型发光实际上看起来是面发光，可以提高光的均匀性，提高显示装置的显示质量。
根据本公开的实施例，发光层可以为有机电致发光层，且对发光层的结构没有特别限制，只要能够满足发光要求，本领域技术人员可以根据实际需要灵活选择。例如发光层除了基本的有机电致发光层之外，还可以包括空穴传输层(GHTL)、空穴注入层、空穴阻挡层(HBL)、电子传输层(ETL)、电子注入层和电子阻挡层中的至少一种。由此，结构简单，易于实现，发光效果较佳。根据本公开的实施例，形成发光层各层的材料为常规发光层的材料，在此不再过多赘述。
根据本公开的实施例，对形成栅绝缘层的材料没有特别限制，只要能够满足要求，本领域技术人员可以根据实际需要灵活选择。例如形成栅绝缘层的材料可以包括但不限于二氧化硅、氮化硅或者偶联聚乙烯咔唑等，由此，绝缘效果较佳，使用性能较佳。
在本公开的另一方面，本公开的实施例提供了一种显示面板。根据本公开的实施例，所述显示面板包括多个前面所述的发光场效应晶体管。设计人发现，该显示面板结构简单，易于实现，显示效果较佳，使用性能较佳，且具有前面所述的发光场效应晶体管的所有特征和优点，在此不再过多赘述。
根据本公开的实施例，所述多个所述发光场效应晶体管被布置成：使得在第一方向上相邻的两个发光场效应晶体管的源极一体化形成为第一结合体，在所述第一方向上相邻的两个发光场效应晶体管的漏极一体化形成为第二结合体，并且所述第一结合体和所述第二结合体在所述第一方向上交替设置。下面以五个发光场效应晶体管为例进行说明发光场效应晶体管中源极和漏极的结构，具体情况参照图8，在五个发光场效应晶体管上分别标号1、 2、3、4、5，代表发光场效应晶体管1～5，发光场效应晶体管1和2在第一方向上相邻，将该两个发光场效应晶体管的源极510一体化，形成第一结合体511，将发光场效应晶体管2的漏极520和与其相邻的发光场效应晶体管3的漏极520一体化，形成第二结合体521，然后将发光场效应晶体管3的源极510与在第一方向上和其相邻的发光场效应晶体管4的源极510一体化，形成第一结合体511，以此类推，在第一方向上相邻的发光场效应晶体管4和5的漏极520一体化形成第二结合体521。由此，可以简化像素电路，且可以增加线宽，减小电阻。需要说明的是，以上举例仅仅是示例性的，仅用于说明本申请，而不能理解为对本申请的限制，本领域技术人员可以根据不同显示面板的需要选择合适数量的发光场效应晶体管并对发光场效应晶体管的源极和漏极的结构和连接方式进行适应性的设置。根据本公开的一个具体示例，参照图9，多个发光场效应晶体管间隔、且阵列分布，多个发光场效应晶体管被布置成：使得在与所述第一方向垂直的第二方向上相邻的所有发光场效应晶体管的源极510一体化形成为所述第一结合体511，在所述第二方向上相邻的所有发光场效应晶体管的漏极520一体化形成为所述第二结合体521，所述第一结合体511连接至电源线，所述第二结合体522连接至接地线。由此，可以进一步简化像素电路，增加线宽，减小电阻。根据本公开的另一个具体示例，当源极510和所述漏极520在所述有源层200上的正投影为两个间隔设置的同心环形时，多个间隔、且阵列分布的发光场效应晶体管中的源极510和漏极520的结构示意图可参照图10，在与所述第一方向垂直的第二方向上相邻的所有发光场效应晶体管的源极510一体化形成为所述第一结合体511，在所述第二方向上相邻的所有发光场效应晶体管的漏极520一体化形成为所述第二结合体521，所述第一结合体511连接至电源线，所述第二结合体522连接至接地线。由此，可以进一步简化像素电路，增加线宽，减小电阻。需要说明的是，上述源极和漏极的一体化应该做广义的理解，所述一体化可以为在制备过程中将第一方向或者第二方向上相邻的两个源极或者漏极形成一个整体(如一根导线构成第一方向或者第二方向上相邻的两个源极或者漏极)实现一体化，也可以为先形成独立的源极和漏极，然后将在第一方向或者第二方向上相邻的两个源极或者漏极通过打孔和走线使其电连接的方式(如通过导线将单独设置的第一方向或者第二方向上相邻的两个源极或者漏极电连接)实现一体化，由此，结构简单，易于实现，且能够简化像素电路。
根据本公开的实施例，为了实现显示装置的显示功能，参照图11、图13，所述显示面板包括开关薄膜晶体管，所述开关薄膜晶体管的源极540与数据线连接，栅极550与栅线连接，漏极530与所述发光场效应晶体管的栅极100电连接。由此，结构简单，易于实现，节省成本，且该薄膜晶体管可以有效用于控制发光场效应晶体管的开关，实现显示装置的 显示功能。
根据本公开的实施例，所述显示面板根据源极和漏极位置的不同可以分为底源-顶漏型显示面板或者顶源-顶漏型显示面板。
根据本公开的实施例，参照图11，底源-顶漏型显示面板中除了包括前面所述的发光场效应晶体管和开关薄膜晶体管，还包括：衬底710，设置在衬底710一个表面上的缓冲层720，设置在栅绝缘层300远离衬底710的表面并覆盖有源层200和开关薄膜晶体管的有源层560的层间介质层500，设置在层间介质层500远离衬底710的表面并覆盖源极510、漏极520、开关薄膜晶体管的漏极530、开关薄膜晶体管的源极540的像素界定层730，其中，发光场效应晶体管设置在缓冲层720远离所述衬底710的表面上，开关薄膜晶体管设置在缓冲层720远离所述衬底710的表面上，发光场效应晶体管中的源极510与有源层200电连接、漏极520与发光层400通过连接电极700电连接，连接电极700与漏极520经过过孔连接，成为底源-顶漏型显示面板中的实际漏极。该面板的发光原理为：空穴从源极510直接注入到有源层200并经过能级过渡层600以及发光层400中的电致发光层向漏极520流动，电子从漏极520注入到电致发光层，电子空穴在电致发光层汇聚、湮灭发光。在底源-顶漏型显示面板中，注入的空穴和电子在沟道中斜着流向对极，增大了激子形成的概率，进而提高显示面板的使用性能。图12为含有底源-顶漏型显示面板的剖面图，两个相邻的发光场效应晶体管的漏极520可以通过导线一体化，且上述两个相邻的发光场效应晶体管中的一个和与其相邻的第三个发光场效应晶体管的两个源极510也可以通过导线一体化，由此，结构简单，实现了电路的简化，节约成本，且源极与连接电极和漏极的结构是上下不对称的，有利于提高电子与空穴的复合几率，增加发光场效应晶体管的光电转换效率。源极可以作为发光层的阳极，漏极可以作为发光层的阴极，相邻两个发光场效应晶体管的阳极可以共用一根走线，上述两个相邻的发光场效应晶体管中的一个和与其相邻的第三个发光场效应晶体管的两个阴极也可以共用一根走线，由此，可以增大走线面积，降低走线电阻，并且降低刻蚀工艺的公差。
根据本公开的实施例，参照图13，所述顶源-顶漏型显示面板与所述底源-顶漏型显示面板的结构的不同之处在于：源极510与所述发光层400远离所述有源层200的表面的一部分相接触，以使所述源极510与所述发光层400电连接。其中，连接电极700与漏极520经过过孔连接，成为顶源-顶漏型显示面板的实际漏极。其发光原理为：空穴从源极510注入后，先经过发光层400流向有源层200，然后沿着有源层200流向连接电极700一侧，并再次流经发光层400中的电致发光层流向漏极520，电子从漏极520注入到电致发光层，电子空穴在发光层汇聚、湮灭发光。图14为含有顶源-顶漏型结构的显示面板的剖面图， 两个相邻的发光场效应晶体管的漏极520可以通过导线一体化，且上述两个相邻的发光场效应晶体管中的一个和与其相邻的第三个发光场效应晶体管的两个源极510也可以通过导线一体化，由此，结构简单，实现了像素电路的简化，节约成本，且有利于简化制备工艺(如源极和连接电极可以通过一次工艺形成)，另外，源极可以作为发光层的阳极，漏极可以作为发光层的阴极，相邻两个发光场效应晶体管的阳极可以共用一根走线，上述两个相邻的发光场效应晶体管中的一个和与其相邻的第三个发光场效应晶体管的两个阴极也可以共用一根走线，由此，可以增大走线面积，降低走线电阻，并且降低刻蚀工艺的公差。
需要说明的是，当相邻两个发光场效应晶体管的源极或者漏极通过导线连接起来时，栅极分时驱动，以满足显示装置的显示需求。
根据本公开的实施例，参照图12和图14，发光层400还包括：空穴传输层410、设置在空穴传输层410远离衬底710表面的电致发光层420、设置在电致发光层420远离衬底710表面的空穴阻挡层430和设置在空穴阻挡层430远离衬底710表面的电子传输层440，由此，结构简单易于实现，并且能够有效实现电致发光且发光效率较高。根据本公开的实施例，所述空穴传输层、电致发光层、空穴阻挡层以及电子传输层与常规的空穴传输层、电致发光层、空穴阻挡层以及电子传输层一致，在此不再过多赘述。
在本公开的另一方面，本公开的实施例提供了一种显示装置。根据本公开的实施例，所述显示装置包括前面所述的显示面板。设计人发现，该显示装置的显示面板PPI较高，显示质量较高，使用性能较佳，且该显示装置具备前面所述的显示面板的所有特征和优点，在此不再过多赘述。
根据本公开的实施例，上述显示面板与前面的描述一致，在此不再过多赘述。根据本公开的实施例，所述显示装置除了具备前面所述的显示面板之外，还包括常规显示装置应该具备的结构，例如保护盖板、偏光片、触控基板、平坦层或者封装结构等，在此不再过多赘述。
在本公开的另一方面，本公开的实施例提供了一种制备显示面板的方法。根据本公开的实施例，所述方法包括：在衬底的第一表面上形成阵列分布的多个发光场效应晶体管。
需要说明的是，上述第一表面是指在使用时靠近用户的表面，另外，图11和图13中示出的是显示面板中一个发光场效应晶体管和一个开光晶体管的剖面结构示意图，图12和图14中示出的是显示面板中三个子像素的剖面结构示意图。
根据本公开的实施例，参照图15，形成所述发光场效应晶体管的步骤包括：
S100：形成栅极100、有源层200、源极510、漏极520、发光层400和能级过渡层600，结构示意图可参照图1、图3或图4。
S300：形成开关薄膜晶体管。
根据本公开的实施例，所述栅极、有源层、源极、漏极、发光层和能级过渡层与前面的描述一致，在此不再过多赘述。
根据本公开的实施例，形成栅极的方式可以为刻蚀或者沉积等方式；形成有源层的方式可以为先刻蚀后准分子激光退火或者先准分子激光退火后刻蚀或者湿法刻蚀等方式，形成源极、漏极的方式可以为热蒸镀法或者溅射刻蚀法等等方式，形成能级过渡层的方式一股为热蒸镀沉积，由此，操作简单方便，易于实现，产品良率较高。
根据本公开的实施例，形成发光层的步骤还包括形成空穴传输层、电致发光层、空穴阻挡层和电子传输层的步骤，形成上述空穴传输层、电致发光层、空穴阻挡层和电子传输层的方法可以为热蒸镀法，由此，结构或者工艺较简单，形成的发光层适用性能较佳。
在本公开的一些实施例中，参照图16，上述方法还可以包括：
S200：形成连接电极700，结构示意图可参见图4。
根据本公开的实施例，所述连接电极与前面的描述一致，在此不再过多赘述。根据本公开的实施例，形成连接电极的方式可以为热蒸镀等方式。
根据本公开的实施例，在底源-顶漏型显示面板或者顶源-顶漏型显示面板中，源极与连接电极通过一次构图工艺形成，由此，制备工艺简单、方便，节省成本，且良率较高。根据本公开的实施例，所述构图工艺可以为掩模热蒸镀工艺等。
根据本公开的实施例，上述开关薄膜晶体管与前面的描述一致，在此不再过多赘述。根据本公开的实施例，形成上述开关薄膜晶体管还包括形成开关薄膜晶体管的栅极、源极、漏极和有源层的步骤。根据本公开的实施例，形成开关薄膜晶体管的栅极的方式可以为刻蚀或者沉积等方式，形成开关薄膜晶体管的源极、漏极的方式可以为热蒸镀或者溅射刻蚀等方式；由此，制备工艺简单、方便，节省成本，且该开关薄膜晶体管可以有效用于控制子像素的开关，实现显示装置的显示功能。
设计人发现，上述方法工艺流程简单易于实现，成本较低，制备得到的显示面的结构得到很大程度的简化，良率得到提高，出光率较高，适于制备高PPI产品。
下面以制备底源-顶漏型显示面板的具体流程为例来具体阐述本公开的实施例的制备显示面板的方法，参照图17-图24和图11，需要说明的是，下面描述的实施例是示例性的，仅用于解释本公开，而不能理解为对本公开的限制。
1、清洗衬底710，并在衬底710表面形成一层缓冲层720，结构示意图可参见图17；
2、在缓冲层720远离衬底710的表面形成栅极100和开关薄膜晶体管的栅极550，结构示意图参照图18；
3、在缓冲层720远离衬底710的表面形成一层栅绝缘层300并覆盖所述栅极100以及开关薄膜晶体管的栅极550，结构示意图参照图19；
4、在所述栅绝缘层300远离衬底710的表面形成一层初始有源层740，结构示意图参照图20；
5、对初始有源层740进行图形化处理，形成有源层200和开关薄膜晶体管的有源层560，结构示意图参照图21；
6、在所述栅绝缘层300远离衬底710的表面形成一层层间介质层500并覆盖所述有源层200和开关薄膜晶体管的有源层560，在所述层间介质层500中打孔并沉积源极510、漏极520、开关薄膜晶体管的漏极530和开关薄膜晶体管的源极540，结构示意图参照图22；
7、在所述层间介质层500远离衬底710的表面形成一层像素界定层730，并覆盖所述源极510、漏极520、开关薄膜晶体管的漏极530和开关薄膜晶体管的源极540，之后对像素界定层730和层间介质层500进行图形化处理，限定出能级过渡层、发光层和连接电极的位置，结构示意图参照图23；
8、利用蒸镀法形成能级过渡层600和发光层400，其中发光层400在能级过渡层600远离衬底710的表面上，结构示意图参照图24；
9、利用掩膜版蒸镀法形成连接电极700(即阴极)，结构示意图参照图11。
根据本公开的实施例，在一股的显示面板中，其OLED与DTFT是独立设置的，OLED发光层由于阴极的覆盖导致出光效率较低，而DTFT由于所占空间较大不利于高PPI的显示面板的制备，因而限制了其应用。而在本公开的实施例中，用一个发光场效应晶体管来代替OLED发光层与DTFT，其本身兼具DTFT的驱动作用和OLED发光层的发光功能，使得显示面板结构更加简单，制备得到的显示屏更薄，工艺流程减少，产品良率较高，并且采用无机有源层进行驱动发光层发光，可以利用更小的电流进行驱动，能耗较小，并且迁移率高，导电率高，电性漂移较弱，稳定性较佳，工艺兼容性较佳，并在无机有源层与发光层之间设置过渡层以使得发光层材料的能级和有源层材料的能级匹配性更好，提高显示效果。并且，发光场效应晶体管的发光区域的至少一部分在阴极覆盖范围之外，不会受到表面等离子激元或者透射率等因素的影响，出光效率较高，更重要的是，发光场效应晶体管的自身发光区域比OLED发光层更小，适合制作高PPI的显示面板。
在本公开的实施例中，能级过渡层的设置是为了弥补采用无机半导体材料形成的有源层的能级与发光层的能级之间存在的较大差异，在有源层与发光层之间设置能级过渡层可以使得发光层材料的能级和有源层材料的能级匹配性更好，提高发光场效应晶体管的使用性能。然而，需要说明的是，能级过渡层并不是必须的，特别是在有源层与发光层之间的 能级差不明显时。图25是本公开的一个实施例的发光场效应晶体管，其与图1所示的实施例的区别在于：在有源层200与发光层400之间没有设置能级过渡层。具体地，所述发光场效应晶体管包括：栅极100；有源层200，所述有源层200与所述栅极100之间通过栅绝缘层300间隔开；发光层400，所述发光层400层叠在所述有源层200的远离所述栅极100一侧；以及源极510和漏极520，所述源极510和漏极520被配置成使得电流能够经由所述有源层200流过所述发光层400；其中，所述有源层200由无机半导体材料制成。具有上述结构的发光场效应晶体管能够被构造为显示面板，用于显示应用，结构简单，易于实现，并且采用无机半导体材料形成有源层使得有源层的迁移率较高，厚度较均匀，稳定性较佳，工艺兼容性较好，导电率较高，可以利用更小的电流实现驱动，功耗较低，电性漂移较弱，可有效改善画面均匀性，提高显示质量。
尽管上面已经示出和描述了本公开的实施例，可以理解的是，上述实施例是示例性的，不能理解为对本公开的限制，本领域的普通技术人员在本公开的范围内可以对上述实施例进行变化、修改、替换和变型。

Claims (15)

  1. 一种显示面板，包括：
    衬底基板；
    栅极，所述栅极位于衬底基板上；
    有源层，所述有源层与所述栅极之间通过栅绝缘层间隔开；
    发光层，所述发光层层叠在所述有源层的远离所述栅极一侧；以及
    源极和漏极，所述源极和漏极被配置成使得电流能够经由所述有源层流过所述发光层。
  2. 根据权利要求1所述的显示面板，其中，所述有源层与所述发光层之间设置有能级过渡层。
  3. 根据权利要求1所述的显示面板，其中，所述有源层由无机半导体材料制成。
  4. 根据权利要求3所述的显示面板，其中，所述无机半导体材料包括多晶硅、单晶硅和金属氧化物半导体中的至少一种。
  5. 根据权利要求1所述的显示面板，其中，所述源极和所述漏极在所述有源层上的正投影为两个间隔设置的同心非闭合环形。
  6. 根据权利要求1所述的显示面板，其中，所述源极和所述有源层电连接，并且所述漏极和所述发光层电连接。
  7. 根据权利要求1所述的显示面板，其中，所述源极和所述发光层电连接，并且所述漏极和所述发光层电连接。
  8. 根据权利要求6或7所述的显示面板，还包括连接电极，所述发光层和所述漏极通过所述连接电极电连接。
  9. 根据权利要求8所述的显示面板，其中，所述连接电极在所述有源层上的正投影与所述发光层在所述有源层上的正投影部分重叠。
  10. 根据权利要求9所述的显示面板，其中，所述漏极和/或所述连接电极为透明电极。
  11. 根据权利要求2所述的显示面板，其中，所述有源层为p型有源层，所述能级过渡层的最高被占据分子轨道与所述p型有源层的功函数能级匹配。
  12. 根据权利要求2所述的显示面板，其中，所述有源层为n型有源层，所述能级过渡层的最低未占分子轨道与所述n型有源层的功函数能级匹配。
  13. 根据权利要求1所述的显示面板，其中，栅极、有源层、栅绝缘层、发光层、源极和漏极形成发光场效应晶体管，所述显示面板包括多个发光场效应晶体管，所述多个所述发光场效应晶体管被布置成：使得在第一方向上相邻的两个发光场效应晶体管的源极一 体化形成为第一结合体，在所述第一方向上相邻的两个发光场效应晶体管的漏极一体化形成为第二结合体，并且所述第一结合体和所述第二结合体在所述第一方向上交替设置。
  14. 根据权利要求13所述的显示面板，其中，
    所述多个所述发光场效应晶体管被布置成：使得在与所述第一方向垂直的第二方向上相邻的所述发光场效应晶体管的源极一体化形成为所述第一结合体，在所述第二方向上相邻的所述发光场效应晶体管的漏极一体化形成为所述第二结合体，
    所述第一结合体连接至电源线，所述第二结合体连接至接地线。
  15. 根据权利要求13-14中任一项所述的显示面板，还包括开关薄膜晶体管，所述开关薄膜晶体管的源极与数据线连接，所述开关薄膜晶体管的栅极与栅线连接，所述开关薄膜晶体管的漏极与所述发光场效应晶体管的栅极电连接。
PCT/CN2018/112639 2018-01-15 2018-10-30 显示面板 WO2019137072A1 (zh)

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CN112467002B (zh) * 2020-11-25 2022-05-10 华南理工大学 一种氧化物发光场效应晶体管
CN116096126A (zh) * 2021-11-02 2023-05-09 中国科学院化学研究所 一种面光源出射的平面构型发光晶体管及其制备方法和应用

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CN110048010A (zh) 2019-07-23
US10998530B2 (en) 2021-05-04
JP7121128B2 (ja) 2022-08-17
EP3742509A1 (en) 2020-11-25
JP2021508942A (ja) 2021-03-11
US20200274107A1 (en) 2020-08-27
EP3742509B1 (en) 2024-05-22

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