WO2019100609A1 - 掩膜版及薄膜封装方法 - Google Patents

掩膜版及薄膜封装方法 Download PDF

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Publication number
WO2019100609A1
WO2019100609A1 PCT/CN2018/076343 CN2018076343W WO2019100609A1 WO 2019100609 A1 WO2019100609 A1 WO 2019100609A1 CN 2018076343 W CN2018076343 W CN 2018076343W WO 2019100609 A1 WO2019100609 A1 WO 2019100609A1
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Prior art keywords
area
mask
opening
sub
pixel
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PCT/CN2018/076343
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English (en)
French (fr)
Inventor
杜骁
陈永胜
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Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Priority to US16/084,869 priority Critical patent/US10873052B2/en
Publication of WO2019100609A1 publication Critical patent/WO2019100609A1/zh
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    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/04—Coating on selected surface areas, e.g. using masks
    • C23C16/042—Coating on selected surface areas, e.g. using masks using masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H10K50/844—Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/70—Testing, e.g. accelerated lifetime tests
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/873—Encapsulations

Definitions

  • the present application belongs to the field of display technologies, and in particular, to a mask and a film packaging method.
  • the glass packaging technology used in the conventional display panel is difficult to achieve flexibility.
  • the flexible packaging method developed at this stage generally has a thickness of the package layer of a dozen micrometers. Compared with the conventional glass package, the thickness of the package layer is greatly reduced. It is called Thin Film Ecapsulation (TFE).
  • TFE Thin Film Ecapsulation
  • Barix packaging technology inorganic-organic multi-film packaging
  • ALD technology atomic layer deposition packaging
  • a metal mask is used to confine the package region to the film formation region (as shown in the number 10 in FIG. 1), and the portion of the display panel is separated from the vapor deposition protective film. Preventing panel bonding from being covered by the TFE film layer causes subsequent module process and detection failure.
  • the purpose of the present application is to provide a mask to solve the problem that the existing circuit is susceptible to damage and disconnection, resulting in low lighting yield.
  • a mask in a first aspect, includes a shielding area and an opening area, the shielding area is disposed around the opening area, and the shape and position of the opening area correspond to a film forming area and a partial binding area of the sub-pixel, The thin film encapsulation material passing through the open area covers the film formation area and the partial bonding area of the sub-pixel, and exposes the FPC and the test interface.
  • the shielding area includes an outer frame and a stopper protruding from a middle portion of the bottom edge of the outer frame toward an inner portion of the opening region, so that the opening region is in the A first opening and a second opening are respectively formed on both sides of the stopper, and the stopper is used to block the FPC area on the sub-pixel.
  • the block is rectangular, and the left and right sides, the top edge, and the bottom of the shielding area An extension of the upper edge of the side of the block collectively encloses a rectangular area forming the open area, the first opening and the second opening being rectangular and having the same width.
  • the left and right sides and the top edge of the shielding area correspond to a film forming area of the sub-pixel The corresponding position is offset outward by 100-500 ⁇ m, and the inner bottom edge of the shielding area is 100-500 ⁇ m from the upper edge of the binding area.
  • the block has a distance of 100-500 ⁇ m along the lower edge of the binding region.
  • the mask has a thickness of 0.01 to 0.3 mm.
  • the open area is two or more, and the plurality of open areas are spaced apart.
  • the open areas are arranged in an array on the mask.
  • the present application also provides a thin film encapsulation method, which adopts the following technical solutions:
  • a method of packaging a film comprising the steps of:
  • the mask plate comprising a shielding area and an opening area, the shielding area is disposed around the opening area, the shape and position of the opening area corresponding to a film forming area and a partial binding area of the sub-pixel,
  • the thin film encapsulation material passing through the open area covers the film formation area and the partial binding area of the sub-pixel, and exposes the FPC and the test interface, and enters the next process site;
  • a thin film encapsulation inputting a thin film encapsulating material and forming a protective film on the glass substrate through an open area of the mask;
  • the mask plate and the glass substrate are separated, and the state of the film formed on the glass substrate is inspected.
  • the mask is first plated with a corrosion resistant protective film and then moved to the next process site.
  • a mask provided by the present application by providing a masking area and an opening area, the shape and position of the opening area corresponding to a film forming area and a partial binding area of the sub-pixel, so that the film encapsulating material passing through the opening area Covering the film formation area and the partial binding area of the sub-pixel, and exposing the FPC and the test interface, so that the line of the binding area on the sub-pixel can be covered by the film and protected, and does not affect the need for subsequent processes.
  • FPC and test interface by providing a masking area and an opening area, the shape and position of the opening area corresponding to a film forming area and a partial binding area of the sub-pixel, so that the film encapsulating material passing through the opening area Covering the film formation area and the partial binding area of the sub-pixel, and exposing the FPC and the test interface, so that the line of the binding area on the sub-pixel can be covered by the film and protected, and does not affect the need for subsequent processes.
  • FPC and test interface by providing
  • FIG. 1 is a schematic structural view of a sub-pixel in the prior art
  • FIG. 2 is a schematic structural view of a mask corresponding to the sub-pixel of FIG. 1;
  • FIG. 3 is a schematic structural view of a mask plate according to an embodiment of the present application.
  • FIG. 4 is a schematic diagram of a sub-pixel structure made by the mask of FIG. 3;
  • FIG. 5 is a schematic structural view of a mask of an embodiment of FIG. 3; FIG.
  • Figure 6 is a schematic view showing the state of use of the mask in Figure 5.
  • a pixel of an OLED display device includes three sub-pixels of color R (red), G (green), and B (blue), and FIG. 1 is a schematic structural diagram of any one of the sub-pixels.
  • a film is deposited in the film-forming region 10 for encapsulation, and the traces of the bonding region 20 are exposed for the next process.
  • the routing inside the bonding region is complicated, and at least the FPC and the FPC are included.
  • the test interface is likely to cause damage or disconnection of the line in the bonded area during the production process of the flexible substrate, so that the subsequent lighting yield is reduced.
  • FIG. 2 is a schematic structural diagram of a mask used in the production process of the sub-pixel of FIG. 1 , which includes a shielding area 01 and an opening area 02 .
  • the shielding area 01 surrounds the rectangular opening area 02 and the opening area 02
  • the shape and position correspond to the film formation region 10 of the sub-pixel, and the thin film encapsulation material forms a package protection film on the flexible substrate through the opening region 02.
  • an embodiment of the present application provides a mask, including a shielding area 100 and an opening area 200 , the shielding area 100 is disposed around the opening area 200 , and the opening area 200
  • the shape and position correspond to the film formation region 10 and the partial bonding region 20 of the sub-pixel, so that the film encapsulation material passing through the opening region 200 covers the film formation region 10 and the partial bonding region 20 of the sub-pixel, and exposes the FPC 21 And test interface 22.
  • the film encapsulated in the TFE process covers the film formation region 10 and the partial bonding region 20, and The FPC 21 and the test interface 22, which need to be used in subsequent processes, are exposed, so that most of the traces in the binding area are covered and protected by the film, and the line is not easily damaged or broken, which can improve the lighting yield.
  • the mask provided in this embodiment can not only form a sub-pixel package film on the substrate, but also provide protection for the line of the bonding area on the sub-pixel, which can be completed in a TFE process, On the basis of additional process steps, the process can be significantly optimized, which can greatly improve the yield of subsequent process processes.
  • the mask is a metal mask, and the preferred material is stainless steel or Invar.
  • the mask surface is plated with a corrosion-resistant protective film, preferably Al 2 O 3 or PTFE coating, and the coating thickness is 0.1-20 ⁇ m to prevent mask damage in the TFE process.
  • the occlusion area 100 includes an outer frame and a stopper 101 protruding from the middle of the bottom edge of the outer frame toward the inner portion of the opening area 200, so that the opening area 200 is at the stop block 101.
  • the side forms a first opening 201 and a second opening 202, respectively, for blocking the FPC area 21 on the sub-pixel.
  • the FPC area is blocked, and the formed film layer on the sub-pixel covers the partial binding area 20 and exposes the FPC area, which does not affect the subsequent process, and better protects the FPC area. 21 line safety.
  • the bottom edge of the outer frame of the shielding area 100 and the first opening 201 and the second opening 202 respectively block the position of the test interface 22 of the binding area 20, so that the sub-pixel test interface 22 is exposed, so that the binding area is protected. At the same time, it does not affect the subsequent use of the test interface for lighting test and other operations.
  • the block 101 is rectangular, and the extensions 114 of the upper edge of the block 101 on the left and right sides 112/113, the top side 110 and the bottom side 111 of the shielding area 100 are collectively enclosed to form the A rectangular area of the open area 200, the first opening 201 and the second opening 202 are rectangular and have the same width.
  • the open area 200 is composed of a large rectangular area and a rectangular first opening 201 and a second opening 202, forming a shape in which a rectangle formed by four sides inside the shielding area 100 is concave inward at the position of the stopper 101, corresponding thereto, shielding
  • the four sides inside the area form a shape convex by the position of the stopper
  • the corresponding positions of the left and right sides 112/113 and the top side 110 of the masking area 100 corresponding to the film forming area 10 of the sub-pixel are outwardly shifted by 100-500 ⁇ m, preferably 200-300 ⁇ m, so that The film covers the entire film-forming region 10; the inner bottom edge 111 of the occlusion region 100 is 100-500 ⁇ m, preferably 200-300 ⁇ m, from the upper side of the binding region 20, so that the occlusion region 100 can block the test interface 22 while covering other The binding area of the area is routed.
  • the upper edge of the binding block 101 is 100-500 ⁇ m, preferably 200-300 ⁇ m, so that the block can completely block the FPC area 21.
  • the mask has a thickness of 0.01 to 0.3 mm. Studies have shown that the width of the sub-pixel is limited by the thickness of the mask. The thinner the thickness of the mask, the smaller the width of the sub-pixel, the larger the PPI. After testing, the thickness range of the mask of the present embodiment is obtained.
  • a preferred mask has a thickness in the range of 0.1 to 0.2 mm.
  • the open area 200 is two or more, and the plurality of open areas 200 are spaced apart.
  • the mask is mounted on the bracket 300.
  • the mask may be fixed on the bracket 300 by using a laser welding process; the open areas 200 are arranged in an array on the mask, for example, In the rectangular array mode, corresponding to the position of the sub-pixel, M rows and N columns of open areas 200 are arranged, and M ⁇ N sub-pixels can be packaged in one TFE process, wherein the packaged film covers the film formation area of each sub-pixel. 10 and part of the binding area 20, and expose the FPC 21 and the test interface 22, so that the line of the binding area of each sub-pixel can be protected.
  • an embodiment of the present application provides a thin film encapsulation method, the method comprising the following steps:
  • a mask 100 is provided.
  • the mask 100 includes a masking area 100 and an opening area 200.
  • the masking area 100 is disposed around the opening area 200.
  • the shape and position of the opening area 200 correspond to a film forming area of a sub-pixel. 10 and a portion of the bonding region 20, such that the thin film encapsulation material passing through the open region 200 covers the film formation region 10 and the partial bonding region 20 of the sub-pixel, and exposes the FPC 21 and the test interface 22, and proceeds to the next Process site
  • a thin film encapsulation inputting a thin film encapsulating material and forming a protective film on the glass substrate 400 through the open region 200 of the mask 100;
  • the mask 100 and the glass substrate 400 are separated, and the state of the film formed on the glass substrate 400 is inspected.
  • the mask plate is mounted on the bracket 300, and the CCD or the thimble is further mounted on the substrate carrying platform 500.
  • the CCD or the ejector pin is used to move the glass substrate 400 to complete the alignment.
  • the glass substrate 400 is located at a vertical projection position of the mask 100.
  • the glass substrate 400 is supported by the carrier platform 500.
  • the reticle 100 and the glass substrate 400 which are aligned and adhered are in the TFE process, and the open area 200 of the reticle 100 corresponds to the film formation area 10 of the sub-pixel formed on the glass substrate 400 and partially bound.
  • Zone 20 the film formed in the TFE process covers the area and exposes the FPC 21 and test interface 22 locations to protect the line without affecting subsequent processes.
  • the mask 100 is first plated with a corrosion resistant protective film (not shown) and then moved to the next process site.
  • the corrosion-resistant protective film is preferably an Al 2 O 3 or PTFE coating having a coating thickness ranging from 0.1 to 20 ⁇ m.

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Abstract

提供一种掩膜版，包括遮蔽区（100）和开口区（200），所述遮蔽区（100）围绕所述开口区（200）设置，所述开口区（200）的形状和位置对应亚像素的成膜区（10）和部分绑定区（20），以使通过所述开口区（200）的薄膜封装材料覆盖所述亚像素的成膜区（10）和部分绑定区（20），并露出FPC（21）和测试接口（22）。通过所述开口区（200）的薄膜封装材料覆盖所述亚像素的成膜区（10）和部分绑定区（20），并露出FPC（21）和测试接口（22），使亚像素上的绑定区（20）的线路可以得到薄膜的覆盖而得到保护，解决了现有技术所存在线路易损伤和断开而造成点灯良率低的问题。还提供了一种薄膜封装方法。

Description

掩膜版及薄膜封装方法
本申请要求于2017年11月27日提交中国专利局、申请号为201711208519.9、申请名称为“掩膜版及薄膜封装方法”的中国专利申请的优先权，上述在先申请的内容以引入的方式并入本文本中。
技术领域
本申请属于显示技术领域，尤其涉及一种掩膜版及薄膜封装方法。
背景技术
在柔性基板上构筑OLED器件以此制备柔性显示设备是现阶段显示技术发展的热点方向，前期研究和相应制程经验表明环境中的水氧浓度对OLED寿命会产生非常大的影响，因此对OLED进行有效封装,使器件的各功能层与大气中的水汽、氧气等成分隔开，即可大大延长器件寿命。
传统显示面板采用的玻璃封装技术难以实现柔性需求，现阶段开发的柔性封装方法，由于其封装层厚度一般为十几微米，相比于传统的玻璃封装，其封装层厚度大大降低，所以也可称为薄膜封装技术(Thin Film Ecapsulation，简称TFE)。目前比较热门、最有希望应用于量产的TFE为Barix封装技术(无机-有机多膜层封装)和ALD技术(原子层沉积封装)，其原理均为在基板表面通过气相化学反应沉积一层薄膜完成对基板的封装。
应用此类技术对基板进行封装时需使用金属掩膜版将封装区域限定在成膜区(如图1中序号10所示区域)，将显示面板(panel)区域部分与气相沉积保护膜隔离，防止绑定区(panel bonding)被TFE膜层覆盖导致后续模组制程和检测失效。
然而由于panel bonding区分布电路较细和脆弱，在柔性基板生产过程中极有可能因为刮擦、基板形变、静电或环境颗粒(particle)等原因导致线路损伤或断开，导致后续点灯良率降低。
发明内容
本申请的目的是提供一种掩膜版，以解决现有技术所存在线路易损伤和断开而造成点灯良率低的问题。
为实现本申请的目的，本申请提供了如下的技术方案：
第一方面，一种掩膜版，包括遮蔽区和开口区，所述遮蔽区围绕所述开口区设置，所述开口区的形状和位置对应亚像素的成膜区和部分绑定区，以使通过所述开口区的薄膜封装材料覆盖所述亚像素的成膜区和部分绑定区，并露出FPC和测试接口。
在第一方面的第一种可能的实现方式中，所述遮蔽区包括外框和从所述外框底边中部向所述开口区内部突出的挡块，以使所述开口区在所述挡块两侧分别形成第一开口和第二开口，所述挡块用于遮挡亚像素上的FPC区域。
结合第一方面及第一方面的第一种可能的实现方式，在第一方面的第二种可能的实现方式中，所述挡块为矩形，所述遮蔽区内部左右两边、顶边和底边的所述挡块上沿的延伸共同围合形成所述开口区的矩形区域，所述第一开口和所述第二开口为矩形且宽度相同。
结合第一方面及第一方面的第二种可能的实现方式，在第一方面的第三种可能的实现方式中，所述遮蔽区内部左右两边和顶边对应所述亚像素的成膜区的对应位置向外偏移100～500μm，所述遮蔽区内部底边距离所述绑定区上沿100～500μm。
结合第一方面及第一方面的第二种可能的实现方式，在第一方面的第四种可能的实现方式中，所述挡块上沿距离所述绑定区下沿100～500μm。
在第一方面的第五种可能的实现方式中，所述掩膜版的厚度为0.01～0.3mm。
在第一方面的第六种可能的实现方式中，所述开口区为两个以上，多个所述开口区间隔设置。
结合第一方面及第一方面的第六种可能的实现方式，在第一方面的第七种可能的实现方式中，所述开口区在所述掩膜版上阵列排列。
本申请还提供了一种薄膜封装方法，采用如下的技术方案：
第二方面，一种薄膜封装方法，所述方法包括如下步骤：
提供掩膜版，所述掩膜版包括遮蔽区和开口区，所述遮蔽区围绕所述开口区设置，所述开口区的形状和位置对应亚像素的成膜区和部分绑定区，以使通过所述开口区的薄膜封装材料覆盖所述亚像素的成膜区和部分绑定区，并露出FPC和测试接口，并进入下一制程站点；
将所述掩膜版与玻璃基板对位并紧贴；
薄膜封装，输入薄膜封装材料并通过所述掩膜版的开口区在所述玻璃基板上形成封装保护膜；
将所述掩膜版和所述玻璃基板分离，检查所述玻璃基板上形成的薄膜状况。
在第二方面的第一种可能的实现方式中，所述掩膜版先镀制耐腐蚀保护膜再进入下一制程站点。
本申请的有益效果：
本申请提供的一种掩膜版，通过设置遮蔽区和开口区，所述开口区的形状和位置对应亚像素的成膜区和部分绑定区，以使通过所述开口区的薄膜封装材料覆盖所述亚像素的成膜区和部分绑定区，并露出FPC和测试接口，使亚像素上的绑定区的线路可以得到薄膜的覆盖而得到保护，同时不影响后续制程所需要使用的FPC和测试接口。
附图说明
为了更清楚地说明本申请实施方式或现有技术中的技术方案，下面将对实施方式或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施方式，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是现有技术中的亚像素的结构示意图；
图2是图1中的亚像素对应的掩膜版结构示意图；
图3是本申请一种实施方式的掩膜版结构示意图；
图4是图3的掩膜版所制成的亚像素结构示意图；
图5是图3中的一种实施方式的掩膜版的结构示意图；
图6是图5中的掩膜版使用状态示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
请参阅图1，OLED显示器件的一个像素包括三个颜色分别为R(红)、G(绿)、B(蓝)的亚像素，图1为其中任意一种亚像素的结构示意图，在制作亚像素的过程中，需要在成膜区10沉积薄膜进行封装，并露出绑定区20的走线，以用于下一步制程，绑定区内部的走线较为复杂，其至少包含了FPC和测试接口，在柔性基板生产过程中易造成绑定区内的线路损伤或断开，使得后续点灯良率降低。
请参阅图2，是图1的亚像素的生产过程中所使用的掩膜版结构示意图，其包括遮蔽区01和开口区02，遮蔽区01围绕在矩形的开口区02外侧，开口区02的形状和位置对应亚像素的成膜区10，薄膜封装材料通过开口区02在柔性基板上形成封装保护膜。
请参阅图3和图4，本申请一种实施方式提供了一种掩膜版，包括遮蔽区100和开口区200，所述遮蔽区100围绕所述开口区200设置，所述开口区200的形状和位置对应亚像素的成膜区10和部分绑定区20，以使通过所述开口区200的薄膜封装材料覆盖所述亚像素的成膜区10和部分绑定区20，并露出FPC21和测试接口22。
本实施方式中，通过设置开口区200的形状和位置对应亚像素的成膜区10和部分绑定区20，使得在TFE制程中封装的薄膜覆盖成膜区10和部分绑定区20，并露出需要在后续制程使用的FPC 21和测试接口22，使绑定区的大部分走线被薄膜覆盖和保护，线路不易损伤或断开，可提高点灯良率。
本实施方式给出的掩膜版，既能在基板上形成亚像素的封装薄膜，同时又能提供对亚像素上的绑定区的线路的保护，在一次TFE制程中即可完成，在不需要另外的制程步骤的基础上，可对制程带来明显优化，可极大提升后续制程工艺上的良率。
本实施方式中，所述掩膜版为金属掩膜版，优选的材质为不锈钢或因瓦合金(Invar)。所述掩膜版表面镀有耐腐蚀保护膜，优选Al 2O 3或PTFE涂层，涂层厚度为0.1～20μm，以防止TFE制程中造成掩膜版损伤。
一种实施方式中，所述遮挡区100包括外框和从所述外框底边中部向所述开口区200内部突出的挡块101，以使所述开口区200在所述挡块101两侧分别形成第一开口201和第二开口202，所述挡块101用于遮挡亚像素上的FPC区域21。
通过设置挡块并向开口区内部突出，使FPC区域被遮挡，亚像素上的形成的膜层覆盖部分绑定区20并露出FPC区域，既不影响后续制程，又较好的保护了FPC区域21的线路安全。
本实施方式中，遮蔽区100外框底边与第一开口201和第二开口202对应位置遮挡绑定区20的测试接口22位置，使得亚像素的测试接口22露出，使绑定区获得保护的同时，不影响后续使用测试接口进行点灯测试等操作。
一种实施方式中，所述挡块101为矩形，所述遮蔽区100内部左右两边112/113、顶边110和底边111的所述挡块101上沿的延伸114共同围合形成所述开口区200的矩形区域，所述第一开口201和所述第二开口202为矩形且宽度相同。开口区200由大的矩形区域和矩形的第一开口201及第二开口202组成，形成由遮蔽区100内部四条边形成的矩形在挡块101位置向内凹的形状，与之对应的，遮蔽区内部四条边形成由挡块位置外凸的形状
一种实施方式中，所述遮蔽区100内部左右两边112/113和顶边110对应所述亚像素的成膜区10的对应位置向外偏移100～500μm，优选为200～300μm，以使薄膜覆盖完全成膜区10；所述遮挡区100内部底边111距离所述绑定区20上沿100～500μm，优选为200～300μm，以使遮挡区100可遮挡测试接口22同时可覆盖其他区域的绑定区走线；一种实施方式中，所述挡块101上沿距离所述绑定区20下沿100～500μm，优选为200～300μm，使得挡块可完全遮挡FPC区域21。
一种实施方式中，所述掩膜版的厚度为0.01～0.3mm。研究表明，亚像素的宽度受到掩膜版厚度的限制，掩膜版厚度越薄，亚像素的宽度越小，PPI就越大，经试验，得到本实施方式的掩膜版厚度范围，进一步的优选的掩膜版的 厚度范围为0.1～0.2mm。
一种实施方式中，请参考图5，所述开口区200为两个以上，多个所述开口区200间隔设置。
本实施方式中，掩膜版安装于支架300上，具体的，可使用激光焊接工艺将掩膜版固定于支架300上；所述开口区200在所述掩膜版上阵列排列，例如，采用矩形阵列方式，对应亚像素的位置，设置M行N列个开口区200，可在一次TFE制程中对M×N个亚像素进行封装，其中，封装的薄膜覆盖每个亚像素的成膜区10和部分绑定区20，并露出FPC 21和测试接口22，使每个亚像素的绑定区的线路都可以得到保护。
请参考图3至图6，本申请一种实施方式提供了一种薄膜封装方法，所述方法包括如下步骤：
提供掩膜版100，所述掩膜版100包括遮蔽区100和开口区200，所述遮蔽区100围绕所述开口区200设置，所述开口区200的形状和位置对应亚像素的成膜区10和部分绑定区20，以使通过所述开口区200的薄膜封装材料覆盖所述亚像素的成膜区10和部分绑定区20，并露出FPC 21和测试接口22，并进入下一制程站点；
将所述掩膜版100与玻璃基板400对位并紧贴；
薄膜封装，输入薄膜封装材料并通过所述掩膜版100的开口区200在所述玻璃基板400上形成封装保护膜；
将所述掩膜版100和所述玻璃基板400分离，检查所述玻璃基板400上形成的薄膜状况。
本实施方式中，掩膜版安装在支架300上，基板承载平台500上还安装有CCD或顶针，对位时采用CCD或顶针移动玻璃基板400以完成对位，其中，对位完成的标志为玻璃基板400位于掩膜版100的垂直投影位置。玻璃基板400由承载平台500支撑。
本实施方式中，对位完成并紧贴的掩膜版100和玻璃基板400进入TFE制程，掩膜版100的开口区200对应玻璃基板400上形成的亚像素的成膜区10和部分绑定区20，TFE制程中形成的膜覆盖上述区域，并露出FPC 21和测试接口22位置，以对线路进行保护并不影响后续制程。
一种实施方式中，所述掩膜版100先镀制耐腐蚀保护膜(未图示)再进入下一制程站点。该耐腐蚀保护膜优选为Al 2O 3或PTFE涂层，涂层厚度范围为0.1～20μm。
以上所揭露的仅为本申请一种较佳实施方式而已，当然不能以此来限定本申请之权利范围，本领域普通技术人员可以理解实现上述实施方式的全部或部分流程，并依本申请权利要求所作的等同变化，仍属于申请所涵盖的范围。

Claims (10)

  1. 一种掩膜版，其中，包括遮蔽区和开口区，所述遮蔽区围绕所述开口区设置，所述开口区的形状和位置对应亚像素的成膜区和部分绑定区，以使通过所述开口区的薄膜封装材料覆盖所述亚像素的成膜区和部分绑定区，并露出FPC和测试接口。
  2. 如权利要求1所述的掩膜版，其中，所述遮蔽区包括外框和从所述外框底边中部向所述开口区内部突出的挡块，以使所述开口区在所述挡块两侧分别形成第一开口和第二开口，所述挡块用于遮挡亚像素上的FPC区域。
  3. 如权利要求2所述的掩膜版，其中，所述挡块为矩形，所述遮蔽区内部左右两边、顶边和底边的所述挡块上沿的延伸共同围合形成所述开口区的矩形区域，所述第一开口和所述第二开口为矩形且宽度相同。
  4. 如权利要求3所述的掩膜版，其中，所述遮蔽区内部左右两边和顶边对应所述亚像素的成膜区的对应位置向外偏移100～500μm，所述遮蔽区内部底边距离所述绑定区上沿100～500μm。
  5. 如权利要求3所述的掩膜版，其中，所述挡块上沿距离所述绑定区下沿100～500μm。
  6. 如权利要求1所述的掩膜版，其中，所述掩膜版的厚度为0.01～0.3mm。
  7. 如权利要求1所述的掩膜版，其中，所述开口区为两个以上，多个所述开口区间隔设置。
  8. 如权利要求7所述的掩膜版，其中，所述开口区在所述掩膜版上阵列排列。
  9. 一种薄膜封装方法，其中，所述方法包括如下步骤：
    提供掩膜版，所述掩膜版包括遮蔽区和开口区，所述遮蔽区围绕所述开口区设置，所述开口区的形状和位置对应亚像素的成膜区和部分绑定区，以使通过所述开口区的薄膜封装材料覆盖所述亚像素的成膜区和部分绑定区，并露出FPC和测试接口，并进入下一制程站点；
    将所述掩膜版与玻璃基板对位并紧贴；
    薄膜封装，输入薄膜封装材料并通过所述掩膜版的开口区在所述玻璃基板 上形成封装保护膜；
    将所述掩膜版和所述玻璃基板分离，检查所述玻璃基板上形成的薄膜状况。
  10. 如权利要求9所述的薄膜封装方法，其中，所述掩膜版先镀制耐腐蚀保护膜再进入下一制程站点。
PCT/CN2018/076343 2017-11-27 2018-02-11 掩膜版及薄膜封装方法 Ceased WO2019100609A1 (zh)

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