WO2019090526A1 - 一种高性能热电器件及其超快速制备方法 - Google Patents

一种高性能热电器件及其超快速制备方法 Download PDF

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WO2019090526A1
WO2019090526A1 PCT/CN2017/109980 CN2017109980W WO2019090526A1 WO 2019090526 A1 WO2019090526 A1 WO 2019090526A1 CN 2017109980 W CN2017109980 W CN 2017109980W WO 2019090526 A1 WO2019090526 A1 WO 2019090526A1
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layer
barrier layer
type
thermoelectric
buffer
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PCT/CN2017/109980
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English (en)
French (fr)
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何佳清
周毅
付良威
陈跃星
冯丹
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南方科技大学
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Priority to PCT/CN2017/109980 priority Critical patent/WO2019090526A1/zh
Publication of WO2019090526A1 publication Critical patent/WO2019090526A1/zh
Priority to US16/657,080 priority patent/US11101420B2/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N10/00—Thermoelectric devices comprising a junction of dissimilar materials, i.e. devices exhibiting Seebeck or Peltier effects
    • H10N10/80—Constructional details
    • H10N10/81—Structural details of the junction
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N10/00—Thermoelectric devices comprising a junction of dissimilar materials, i.e. devices exhibiting Seebeck or Peltier effects
    • H10N10/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N10/00—Thermoelectric devices comprising a junction of dissimilar materials, i.e. devices exhibiting Seebeck or Peltier effects
    • H10N10/10—Thermoelectric devices comprising a junction of dissimilar materials, i.e. devices exhibiting Seebeck or Peltier effects operating with only the Peltier or Seebeck effects
    • H10N10/17—Thermoelectric devices comprising a junction of dissimilar materials, i.e. devices exhibiting Seebeck or Peltier effects operating with only the Peltier or Seebeck effects characterised by the structure or configuration of the cell or thermocouple forming the device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N10/00—Thermoelectric devices comprising a junction of dissimilar materials, i.e. devices exhibiting Seebeck or Peltier effects
    • H10N10/80—Constructional details
    • H10N10/85—Thermoelectric active materials

Definitions

  • the invention relates to the field of thermoelectric devices and clean energy, in particular to a high performance thermoelectric device and an ultra-fast preparation method thereof.
  • thermoelectric devices are environmentally friendly clean energy devices that use the Seebeck effect or the Peltier effect to directly convert thermal energy from electrical energy. Because thermoelectric devices have the advantages of strong environmental adaptability, good working stability, long service life, no maintenance, no noise, and miniaturization, they are currently in military defense, deep space deep sea, polar exploration, biomedical, electronics industry, artificial intelligence. Other important areas are widely used.
  • thermoelectric materials In recent years, the raw material cost, material properties, and manufacturing processes of thermoelectric devices have received extensive attention from academia and industry.
  • the traditional Bi 2 Te 3 based material has low abundance of crustal elements, and currently uses low cost, high abundance of CoSb 3 based materials, SnSe based materials, Cu 2 Se based materials, Mg 2 Si based materials.
  • thermoelectric conversion efficiency ZT cold surface temperature T C and hot surface temperature T H can be used to express thermoelectric conversion efficiency as
  • ⁇ TE (ZT, T C , T H ) can be optimized from the merit value ZT of the thermoelectric material, the temperature difference ⁇ T between the cold surface and the hot surface.
  • the high merit of the thermoelectric material have been reported, in which a conventional PbTe at 915K ZT has reached 2.2; SnSe at 923K ZT reached 2.6; Cu 2 Se at 850K ZT reached 2.6.
  • the conventional Bi 2 Te 3 has a zT of 1.4 at 450 K and a thermoelectric conversion of only 6% at a temperature difference of 217 K.
  • thermoelectric device the maximum temperature difference between the hot end and the cold end of the thermoelectric device is effectively utilized; the energy conversion efficiency of the Bi 2 Te 3 /CoSb 3 segmented device experimental module has reached 12%; using the guided heat flow or carriers in the thermoelectric
  • the moving direction of the device increases the internal thermal resistance of the thermoelectric device, increases the contact area between the thermoelectric device and the electrode to reduce the contact resistance to increase the temperature difference, thereby enhancing the electrical output performance of the thermoelectric device.
  • thermoelectric film is prepared by metal organic chemical vapor deposition (MOCVD); the volume ratio power and heat matching are improved by adjusting the internal structure volume ratio of the thermoelectric device; and the discharge plasma sintering (SPS) process is adopted.
  • MOCVD metal organic chemical vapor deposition
  • SPS discharge plasma sintering
  • Thermoelectric material elementary powder is rapidly sintered to obtain thermoelectric block; target thermoelectric leg is deposited by hollowing mask and ball positioning direction; nanowire thermoelectric device is fabricated by semiconductor integration and micro-nano processing technology; self-propagating combustion
  • the firing and thermal explosion reactions, and the rapid preparation of millimeter-scale thin film thermoelectric devices by inkjet printing, selective laser melting 3D printing and additive manufacturing techniques are disclosed.
  • thermoelectric material elements in order to avoid sublimation of thermoelectric material elements at high temperatures, the performance of periodic thermal cycling devices is degraded, and an alloy layer and a diffusion barrier layer are added between the thermoelectric material layer and the electrode layer; and an organic inorganic ceramic coating/porous glass surface layer is used for the thermoelectric device. Coating the surface, using (connecting the transition layer/barrier layer) n (n ⁇ 1) to coat the high temperature end of the thermoelectric material and reacting at the contact interface to form a diffusion layer has a significant effect.
  • thermoelectric devices have improved the performance of thermoelectric devices to some extent and improved the preparation method of thermoelectric devices
  • main problems that need to be solved in the case of large-scale industrial thermoelectric devices are: 1 Insulation of thermoelectric materials in direct contact with the external environment To prevent material from sublimation and from inside to outside oxidation; 2 to improve the thermal stability of the thermoelectric legs, reduce or even eliminate the contact thermal expansion and crack generation; 3 to maintain excellent electrical output performance and working stability for a long time.
  • the high-performance thermoelectric device proposed by the invention can break through the technical bottlenecks such as low energy conversion efficiency, small specific power, poor thermal stability, poor impact resistance and complicated preparation process, and has high energy conversion efficiency and good working stability. , ultra-fast preparation and other characteristics.
  • Embodiments of the present invention provide an ultra-fast preparation method for a high performance thermoelectric device and a high performance thermoelectric device.
  • thermoelectric device (1) comprising a thermoelectric module (20) stacked in turn by a thermoelectric unit (10) and an insulating interlayer (113) Forming;
  • the thermoelectric unit (10) includes a p-type thermoelectric leg (10p) and an n-type thermoelectric leg (10n);
  • the p-type thermoelectric leg (10p) includes a p-type high temperature thermoelectric leg (101p) arranged in order from top to bottom ), a first barrier layer (102p), a first buffer stress layer (103p), a second barrier layer (104p), a p-type intermediate temperature thermoelectric leg (105p), a third barrier layer (106p), a second buffer stress Layer (107p), fourth barrier layer (108p), p-type low temperature thermoelectric leg (109p);
  • said n-type thermoelectric leg (10n) includes n-type high temperature thermoelectric leg (101n) and fifth set in order from top to bottom a barrier layer (102n), a third buffer stress layer
  • the high performance thermoelectric device (1) is a square structure.
  • thermoelectric devices (1) a plurality of the high performance thermoelectric devices (1) can be combined in series, in parallel, or in series and parallel.
  • the material of the p-type high temperature thermoelectric leg (101p) comprises a p-type SiGe-based material, a p-type CoSb 3 -based material, a p-type SnSe-based material, a p-type PbSe-based material, and a p-type Cu 2 Se Base material, p-type BiCuSeO-based material, p-type Half-Heusler material, p-type Cu(In,Ga)Te 2 material, p-type FeSi 2 -based material, CrSi 2 , MnSi 1.73 , CoSi, p-type Cu 1.8 S-based material Or p-type oxide material;
  • the material of the p-type medium temperature thermoelectric leg (105p) comprises a p-type PbTe-based material, a p-type CoSb 3 -based material, a p-type Half-Heusler material, a p-type Cu 1.8 S-based material or a p-type AgSbTe 2 -based material;
  • the material of the p-type low temperature thermoelectric leg (109p) includes a p-type Bi 2 Te 3 based material, a p-type Sb 2 Se 3 based material, or a p-type Sb 2 Te 3 based material.
  • the material of the n-type high temperature thermoelectric leg (101n) comprises an n-type SiGe-based material, an n-type CoSb 3 -based material, an n-type SnSe-based material, an n-type SnTe-based material, and an n-type Cu 2 Se a base material, an n-type Half-Heusler material or an n-type oxide material;
  • the material of the n-type medium temperature thermoelectric leg (105n) includes an n-type PbTe-based material, an n-type PbS-based material, an n-type CoSb 3 -based material, an n-type Mg 2 Si-based material, and an n-type Zn 4 Sb 3 -based material. , an n-type InSb-based material, an n-type Half-Heusler material, an n-type oxide material or an n-type AgSbTe 2 -based material;
  • the material of the n-type low temperature thermoelectric leg (109n) includes an n-type Bi 2 Te 3 based material, an n-type BiSb-based material, an n-type Zn 4 Sb 3 -based material, an n-type Mg 3 Sb 2 -based material, and an n-type Bi 2 . Se 3 based material or n type Sb 2 Se 3 based material.
  • the thicknesses of the ten barrier layer (112a), the eleventh barrier layer (110b), and the twelfth barrier layer (112b) are all in the range of [0.01 mm, 0.1 mm].
  • the first barrier layer (102p), the second barrier layer (104p), the third barrier layer (106p), the fourth barrier layer (108p), the first a fifth barrier layer (102n), the sixth barrier layer (104n), the seventh barrier layer (106n), the eighth barrier layer (108n), the ninth barrier layer (110a), the first The ten barrier layer (112a), the eleventh barrier layer (110b), and the twelfth barrier layer (112b) are all present in the form of a powder, a film or a foil.
  • the materials of the eleventh barrier layer (110b) and the twelfth barrier layer (112b) all include gold (Au), silver (Ag), tantalum (Ta), copper (Cu), titanium (Ti), and nitrogen.
  • the first barrier layer (102p) is the same material as the ninth barrier layer (110a); the second barrier layer (104p) is the same material as the third barrier layer (106p);
  • the barrier layer (108p) is the same material as the twelfth barrier layer (112b);
  • the fifth barrier layer (102n) is the same material as the tenth barrier layer (112a);
  • the sixth barrier layer ( 104n) is the same material as the seventh barrier layer (106n);
  • the eighth barrier layer (108n) is the same material as the eleventh barrier layer (110b).
  • the first buffer stress layer (103p), the second buffer stress layer (107p), the third buffer stress layer (103n), and the fourth buffer stress layer (107n) The thickness of the fifth buffer stress layer (111a) and the sixth buffer stress layer (111b) ranges from [0.01 mm, 0.1 mm].
  • the first buffer stress layer (103p), the second buffer stress layer (107p), the third buffer stress layer (103n), and the fourth buffer stress layer (107n) are both in the form of a powder, a film or a foil.
  • the first buffer stress layer (103p), the second buffer stress layer (107p), the fifth buffer stress layer (111a), and the sixth buffer stress layer (111b) Each of the materials includes one or more of copper (Cu), platinum (Pt), nickel (Ni), and copper-molybdenum (Cu-Mo) alloys, the first buffer stress layer (103p), the second The buffer stress layer (107p), the fifth buffer stress layer (111a), and the sixth buffer stress layer (111b) are made of the same material;
  • the materials of the third buffer stress layer (103n) and the fourth buffer stress layer (107n) each include molybdenum oxide (MoO x ), copper (Cu), platinum (Pt), nickel (Ni), copper molybdenum ( One or more of the Cu-Mo) alloys, the third buffer stress layer (103n) and the fourth buffer stress layer (107n) are made of the same material.
  • the materials of the first electrical output electrode (114p) and the second electrical output electrode (114n) comprise gold (Au), palladium (Pd), platinum (Pt), aluminum (Al). Or one or more of copper (Cu), nickel (Ni), and titanium (Ti), the first electrical output electrode (114p) being the same material as the second electrical output electrode (114n);
  • the materials of the first electrical output lead (115p) and the second electrical output lead (115n) are both polyvinyl chloride insulated copper core wires.
  • the insulating interlayer (113) includes a phonon scattering layer (113a) and a negative thermal expansion buffer layer (113b), the phonon scattering layer (113a) and the negative thermal expansion buffer layer (113b)
  • the insulating interlayers (113) are inlaid and fixed between the adjacent p-type thermoelectric legs (10p) and the n-type thermoelectric legs (10n).
  • the high performance thermoelectric device (1) further includes a package structure including two layers, an inner package (201) and an outer package (202), respectively, the thermoelectric module (20)
  • the outer surface is provided with the inner package (201)
  • the outer surface of the inner package (201) is provided with the outer package (202);
  • the first electrical output wire (115p) passes through the outer surface
  • the package (202) and the inner package (201) are connected to the first electrical output electrode (114p)
  • the second electrical output wire (115n) passes through the outer package (202) and the inner package ( 201) accessing the second electrical output electrode (114n); or
  • the package structure includes a single-layer encapsulation layer disposed on an outer surface of the thermoelectric module (20), and the first electrical output lead (115p) passes through the single-layer encapsulation layer access station The first electrical output electrode (114p) is inserted through the single-layer encapsulation layer to the second electrical output electrode (114n).
  • the insulating interlayer (113) includes a phonon scattering layer (113a) and a negative thermal expansion buffer layer (113b), the phonon scattering layer (113a) and the negative thermal expansion buffer layer (113b) Arbitrarily stacked, the insulating interlayer (113) is disposed opposite to the left and right between the thermoelectric module (20) and the inner package (201); or
  • the insulating interlayer (113) is disposed opposite to each other and between the thermoelectric module (20) and the single-layer encapsulation layer.
  • the phonon scattering layer (113a) is a nano-insulating particle layer, and the thickness of the phonon scattering layer (113a) ranges from [1 nm, 100 nm], the phonon scattering layer The number of layers of (113a) ranges from [10, 10000], and the material of the phonon scattering layer (113a) includes SiO 2 , Al 2 O 3 , AlN, MgO, TiO 2 , Si 3 N 4 or SiC.
  • the material of the phonon scattering layer (113a) includes SiO 2 , Al 2 O 3 , AlN, MgO, TiO 2 , Si 3 N 4 or SiC.
  • the thickness of the negative thermal expansion buffer layer (113b) ranges from [1 nm, 100 nm], and the number of layers of the negative thermal expansion buffer layer (113b) ranges from [10, 10000], and the negative thermal expansion buffer
  • the material of the layer (113b) includes one or more of BaTiO 3 , PbTiO 3 , LaCrO 3 , ZrW 2 O 8 , ZrV 2 O 7 or HfW 2 O 8 .
  • the material of the inner package (201) comprises a carbon fiber or graphite-epoxy thermally conductive composite material
  • the outer package (202) comprises FeNi alloy
  • the ultra-fast preparation method of the high performance thermoelectric device (1) of the embodiment of the present invention includes:
  • thermoelectric leg (101p), p-type medium temperature thermoelectric leg (105p), p-type low temperature thermoelectric leg (109p), n-type high temperature thermoelectric leg (101n), n-type medium temperature thermoelectric leg (105n) The elemental stoichiometric ratio of each element in the n-type low-temperature thermoelectric leg (109n) is used to weigh the elemental powder to obtain the thermoelectric material powder, and the first barrier layer (102p), the second barrier layer (104p), and the third barrier layer are respectively weighed.
  • barrier layer powder respectively weigh the first buffer stress layer (103p), the second buffer stress layer (107p), and the third buffer stress layer (103n) a fourth buffer stress layer (107n) and a fifth buffer stress layer (111a) each layer of material powder to obtain a buffer stress layer powder;
  • thermoelectric material powder, the barrier layer powder, and the buffer stress layer powder are sequentially laid on the mold (302) and the upper pressing head (301) in the order of the thermoelectric material layer, the barrier layer, and the buffer stress layer.
  • a space surrounded by the lower pressing head (306), and the p-type thermoelectric leg (10p) in the thermoelectric material powder is used by the first partition (303), the intermediate partition (305), and the second partition (304).
  • the material powder of each layer is separated from the powder of each layer of the n-type thermoelectric leg (10n), and is subjected to discharge plasma sintering to form a thermoelectric block;
  • thermoelectric unit (10) Cutting the thermoelectric block to form a thermoelectric unit (10);
  • the phonon scattering layer (113a) and the negative thermal expansion buffer layer (113b) are alternately prepared by chemical vapor deposition to form an insulating interlayer (113), and the thermoelectric unit (10) is inlaid by the insulating interlayer (113). fixed;
  • thermoelectric module (20) Electing an eleventh barrier layer between a convex section of the n-type low temperature thermoelectric leg (109n) adjacent to the thermoelectric unit (10) and a convex section of the p-type low temperature thermoelectric leg (109p) 110b), a sixth buffer stress layer (111b) and a twelfth barrier layer (112b), alternately stacking the thermoelectric unit (10) to obtain a thermoelectric module (20);
  • thermoelectric module (20) Preparing a first electrical output electrode (114p) and a second electrical output electrode (114n) of the thermoelectric module (20), respectively, and respectively connecting the first electrical output lead (115p) and the second electrical output lead (115n) .
  • the ultra-fast preparation method of the high performance thermoelectric device (1) further comprises:
  • An outer package (202) material FeNi kovar is fixed on the outer surface of the inner package (201), and the interface of the outer package (202) material is fixed with a sealant to form an outer package (202).
  • the upper pressing head (301) and the lower pressing head (306) are made of graphite;
  • the material of the mold (302) includes one or more of graphite, an alloy, an Al 2 O 3 based ceramic, an AlN based ceramic, a Si 3 N 4 based ceramic or a SiC based ceramic;
  • the materials of the first separator (303), the intermediate separator (305), and the second separator (304) each include graphite or ceramic, and the first separator (303) and the middle partition
  • the plates (305) and the second separator (304) are made of the same material.
  • thermoelectric device under the temperature difference, the thermoelectric device generates migration of holes and electrons inside the p-type thermoelectric leg (10p) and the n-type thermoelectric leg (10n), and adopts high temperature, medium temperature and low temperature segmented thermoelectric materials to maximize Using the temperature difference between the hot and cold faces of the device, combined with the mean free path difference between phonons and electrons (the electron mean free path is on the order of 1 nm, the phonon mean free path is on the order of 100 nm), the nanostructure phonon scattering layer is designed ( 113a) and the negative thermal expansion buffer layer (113b) composite material, while increasing the phonon scattering of the thermoelectric material, reducing or even eliminating the material contact thermal expansion, and using the inner package (201) and the outer package (202) to improve the working stability of the thermoelectric device .
  • the high performance thermoelectric device (1) provided by the invention effectively breaks through the energy of the conventional thermoelectric device by adopting the segment structure, the nanophonon scattering structure, the negative thermal expansion material, the inner package (201) and the outer package (202) material.
  • Technical bottlenecks such as low conversion efficiency, low specific power, poor thermal stability, poor impact resistance, complicated preparation process, high energy conversion efficiency, high output power, strong environmental applicability, good work stability, long service life, easy implementation, etc.
  • It can work stably for a long time in important fields such as military defense, deep space deep sea, polar exploration, biomedical, electronics industry, artificial intelligence, etc., further satisfying the environmental protection, high efficiency, portability and universality of energy conversion.
  • the main benefits are as follows:
  • the present invention employs a segmented structure, a barrier layer, a buffer stress layer, a nanoparticle phonon scattering material, and a negative thermal expansion.
  • the insulating interlayer (113) formed by the expanding material and the package structure design thermoelectric device break through the traditional thermoelectric device limited to contact thermal expansion, element migration diffusion, thermal energy material sublimation and oxidation, low energy utilization, small volume ratio power, work Technical defects such as poor stability and impact resistance greatly improve the electrical output performance and working stability of thermoelectric devices.
  • the invention adopts a hot pressing process combined with a mold (302) and a separator to prepare a thermoelectric unit (10), and realizes direct sintering of a pyroelectric material, a medium temperature section thermoelectric material, a low temperature section thermoelectric material, a barrier layer and a buffer stress layer. , the mutual diffusion between elements is reduced, the bonding strength and thermal matching between the layers of the segmented thermoelectric device are enhanced, and the contact resistance is reduced.
  • thermoelectric leg (10p) and n-type thermoelectric leg (10n) Directly connecting p-type thermoelectric leg (10p) and n-type thermoelectric leg (10n), the insulating interlayer (113) formed by using nano-particle phonon scattering material and negative thermal expansion material occupies the existing thermoelectric leg between the adjacent thermoelectric device.
  • the air gap is inlaid and supported by adjacent p-type thermoelectric legs (10p) and n-type thermoelectric legs (10n), which increases the internal thermal resistance of the device, reduces the contact resistance, increases the specific power per unit volume, enhances the phonon scattering, and reduces Small contact thermal expansion, avoiding current reflow, greatly improving the energy conversion efficiency of the thermoelectric device, meeting the requirements of energy conversion, low carbon environmental protection, integrated high efficiency, and economic universality.
  • the invention uses the inner package (201) and the outer package (202) to fix the structure of the thermoelectric module (20), which helps to buffer the mechanical extrusion and thermal stress existing in the internal structure of the thermoelectric device, and buffers the thermoelectric device from the external environment.
  • the mechanical impact between the thermoelectric devices makes the thermoelectric device have a certain self-repairing function and work better in various harsh environments.
  • thermoelectric device 1 is a schematic view showing the structure of a high performance thermoelectric device according to some embodiments of the present invention.
  • thermoelectric device 2 is a front elevational view of a high performance thermoelectric device in accordance with some embodiments of the present invention.
  • thermoelectric device 3 is a front elevational view of a high performance thermoelectric device in accordance with some embodiments of the present invention.
  • thermoelectric device 4 is a front elevational view of a high profile thermoelectric device of some embodiments of the present invention.
  • FIG. 5 is a schematic diagram of a high performance thermoelectric device to be packaged according to some embodiments of the present invention.
  • Figure 6 is a schematic diagram of the operation of a thermoelectric device based on the Seebeck effect.
  • Figure 7 is a schematic view showing the structure of a conventional segmented thermoelectric device.
  • thermoelectric device 8 is a flow diagram of an ultra-fast preparation method of a high performance thermoelectric device in accordance with some embodiments of the present invention.
  • thermoelectric device 9 through 20 are flow diagrams showing the fabrication process of a high performance thermoelectric device in accordance with some embodiments of the present invention.
  • thermoelectric device 1 High performance thermoelectric device 1, thermoelectric unit 10, thermoelectric module 20, p-type thermoelectric leg 10p, n-type thermoelectric leg 10n, p-type high temperature thermoelectric leg 101p, first barrier layer 102p, first buffer stress layer 103p, second barrier layer 104p, p-type intermediate temperature thermoelectric leg 105p, third barrier layer 106p, second buffer stress layer 107p, fourth barrier layer 108p, p-type low temperature thermoelectric leg 109p, n-type high temperature thermoelectric leg 101n, fifth barrier layer 102n, The third buffer stress layer 103n, the sixth barrier layer 104n, the n-type intermediate temperature thermoelectric leg 105n, the seventh barrier layer 106n, the fourth buffer stress layer 107n, the eighth barrier layer 108n, the n-type low temperature thermoelectric leg 109n, and the ninth The barrier layer 110a, the fifth buffer stress layer 111a, the tenth barrier layer 112a, the eleventh barrier layer 110b, the sixth buffer stress layer 111b,
  • first and second are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated.
  • features defining “first” or “second” may include one or more of the described features either explicitly or implicitly.
  • the meaning of "a plurality" is two or more unless specifically and specifically defined otherwise.
  • connection In the description of the present invention, it should be noted that the terms “installation”, “connected”, and “connected” are to be understood broadly, and may be fixed or detachable, for example, unless otherwise explicitly defined and defined. Connected, or integrally connected; may be mechanically connected, or may be electrically connected or may communicate with each other; may be directly connected or indirectly connected through an intermediate medium, may be internal communication of two elements or interaction of two elements relationship. For those skilled in the art, the specific meanings of the above terms in the present invention can be understood on a case-by-case basis.
  • the high performance thermoelectric device 1 of the embodiment of the present invention includes a thermoelectric module 20 (shown in FIG. 16) and a package structure.
  • the thermoelectric module 20 is formed by sequentially stacking the thermoelectric unit 10 (shown in FIG. 10) and the insulating interlayer 113. 10 and 16, the thermoelectric unit 10 includes a p-type thermoelectric leg 10p and an n-type thermoelectric leg 10n.
  • the p-type thermoelectric leg 10p includes a p-type high temperature thermoelectric leg 101p disposed in order from top to bottom, a first barrier layer 102p, a first buffer stress layer 103p, a second barrier layer 104p, a p-type intermediate temperature thermoelectric leg 105p, and a third The barrier layer 106p, the second buffer stress layer 107p, the fourth barrier layer 108p, and the p-type low temperature thermoelectric leg 109p.
  • the n-type thermoelectric leg 10n includes an n-type high temperature thermoelectric leg 101n, a fifth barrier layer 102n, a third buffer stress layer 103n, a sixth barrier layer 104n, an n-type intermediate temperature thermoelectric leg 105n, and a seventh, which are disposed in this order from top to bottom.
  • the p-type high temperature thermoelectric leg 101p and the n-type high temperature thermoelectric leg 101n are connected through the ninth barrier layer 110a, the fifth buffer stress layer 111a, and the tenth barrier layer 112a to form the thermoelectric unit 10.
  • thermoelectric leg 109n of the adjacent thermoelectric unit 10 and the p-type low-temperature thermoelectric leg 109p are fixedly connected by the eleventh barrier layer 110b, the sixth buffer stress layer 111b, and the twelfth barrier layer 112b, and are inlaid by the insulating interlayer 113. Stacked to form the thermoelectric module 20.
  • thermoelectric module 20 The outer surface of the thermoelectric module 20 is provided with an inner package 201, and the outer surface of the inner package 201 is provided with an outer package 202.
  • the p-type low temperature thermoelectric leg 109p on both sides of the bottom end of the thermoelectric module 20 is provided with a first electrical output electrode 114p
  • the n-type low temperature thermoelectric leg 109n is provided with a second electrical output electrode 114n.
  • the first electrical output lead 115p sequentially passes through the inner package 201 and the outer package 202 to the first electrical output electrode 114p.
  • the second electrical output lead 115n sequentially passes through the inner package 201 and the outer package 202 to the second electrical output electrode 114n.
  • the insulating interlayer 113 is a composite material in which the phonon scattering layer 113a and the negative thermal expansion buffer layer 113b are sequentially laminated.
  • the phonon scattering layer 113a is a nano-insulating particle, and the particles do not contact each other.
  • the insulating interlayer 113 is inlaid and fixed between the adjacent p-type thermoelectric leg 10p and the n-type thermoelectric leg 10n (shown in FIGS. 12, 14, and 15).
  • an insulating interlayer 113 is further disposed between the outer surface of the thermoelectric module 20 and the inner package 201. Among them, the insulating interlayer 113 is provided only on the left and right sides of the outer surface of the thermoelectric module 20 (shown in FIGS. 18, 19, and 20).
  • thermoelectric device 1 of the embodiment of the present invention under the action of temperature difference, internal holes and electrons of the p-type thermoelectric leg 10p and the n-type thermoelectric leg 10n are transferred, thereby converting thermal energy into electrical energy.
  • the high-performance thermoelectric device 1 of the embodiment of the present invention adopts a high-temperature, medium-temperature, and low-temperature segmented thermoelectric material to maximize the utilization of the temperature difference between the hot surface and the cold surface of the high-performance thermoelectric device 1 to improve energy conversion efficiency;
  • the buffer stress layer, the phonon scattering layer 113a, the negative thermal expansion buffer layer 113b, and the segment structure of the package structure are designed to Breaking the traditional thermoelectric device (shown in Figure 7) is limited to contact thermal expansion, element migration and diffusion, sublimation and oxidation of thermoelectric materials, low energy utilization, small volumetric power, poor stability and low impact resistance.
  • the electrical output performance and operational stability of the high performance thermoelectric device 1 are improved.
  • the barrier layer of the high performance thermoelectric device 1 of the embodiment of the present invention can prevent the thermoelectric material (ie, the material of the p-type thermoelectric leg 10p and the n-type thermoelectric leg 10n) during the high-temperature sintering process when manufacturing the high-performance thermoelectric device 1 on the one hand.
  • the interdiffusion of elements between the buffer stress layer and on the other hand can enhance the bonding strength between the buffer stress layer and the thermoelectric material, form a good ohmic contact, and reduce the contact resistance.
  • the material of the buffer stress layer of the high performance thermoelectric device 1 of the embodiment of the present invention has good composition, structure and heat matching with the thermoelectric material, and forms a compound with the powder of the thermoelectric material and the powder of the barrier layer during the densification sintering process.
  • the interface forms a chimeric structure, which increases the bonding strength, reduces cracks, blocks the migration of contact interface elements, reduces contact resistance, and increases carrier extraction capability.
  • the high performance thermoelectric device 1 of the embodiment of the present invention directly connects the p-type thermoelectric leg 10p and the n-type thermoelectric leg 10n, and combines the mean free path difference of phonons and electrons (the electron mean free path is on the order of 1 nm, and the phonon average The free path is on the order of 100 nm.
  • the composite material of the nanostructured phonon scattering layer 113a and the negative thermal expansion buffer layer 113b is designed and used to occupy the air gap existing between the adjacent thermoelectric legs of the conventional thermoelectric device and to support the adjacent p-type.
  • thermoelectric leg 10p and the n-type thermoelectric leg 10n increase the internal thermal resistance of the high-performance thermoelectric device 1, reduce the contact resistance, increase the specific power per unit volume, enhance the phonon scattering of the thermoelectric material, and reduce or even eliminate the thermal contact expansion.
  • the current recirculation is avoided, the energy conversion efficiency of the high-performance thermoelectric device 1 is greatly improved, and the requirements of energy conversion, low carbon environmental protection, integration efficiency, and economic versatility are met.
  • the high-performance thermoelectric device 1 of the embodiment of the present invention fixes the structure of the thermoelectric module 20 by using the inner package 201 and the outer package 202, and helps to buffer the mechanical backlog and thermal stress existing in the internal structure of the high-performance thermoelectric device 1.
  • the mechanical impact between the performance thermoelectric device 1 and the external environment makes the high-performance thermoelectric device 1 have a certain self-repairing function and can work better in various harsh environments.
  • the high performance thermoelectric device 1 of the embodiment of the present invention may have a square structure.
  • a plurality of high-performance thermoelectric devices 1 may be combined in series, in parallel, or in series and parallel.
  • the high performance thermoelectric device 1 can be optionally configured with a DC/DC boost module to manage the electrical output of the high performance thermoelectric device 1.
  • the output end of a high-performance thermoelectric device 1 can be assembled with a DC/DC boosting module, and the output terminals of the plurality of high-performance thermoelectric devices 1 combined in series, parallel or series-parallel can be combined with DC/DC boosting.
  • the module is assembled. In this way, the output voltage of the high performance thermoelectric device 1 can be increased.
  • the p-type high temperature thermoelectric leg 101p may be made of a p-type SiGe-based material, a p-type CoSb 3 -based material, a p-type SnSe-based material, a p-type PbSe-based material, and a p-type.
  • the p-type medium temperature thermoelectric leg 105p may be made of a p-type PbTe-based material, a p-type CoSb 3 -based material, a p-type Half-Heusler material, a p-type Cu 1.8 S-based material, or a p-type AgSbTe 2 -based material.
  • the material of the p-type low temperature thermoelectric leg 109p may be a p-type Bi 2 Te 3 based material, a p-type Sb 2 Se 3 based material, or a p-type Sb 2 Te 3 based material.
  • the n-type high temperature thermoelectric leg 101n may be made of an n-type SiGe-based material, an n-type CoSb 3 -based material, an n-type SnSe-based material, an n-type SnTe-based material, an n-type Cu 2 Se-based material, an n-type Half-Heusler material, or N-type oxide material.
  • the material of the n-type medium temperature thermoelectric leg 105n may be an n-type PbTe-based material, an n-type PbS-based material, an n-type CoSb 3 -based material, an n-type Mg 2 Si-based material, an n-type Zn 4 Sb 3 -based material, and an n-type.
  • the material of the n-type low-temperature thermoelectric leg 109n may be an n-type Bi 2 Te 3 -based material, an n-type BiSb-based material, an n-type Zn 4 Sb 3 -based material, an n-type Mg 3 Sb 2 -based material, and an n-type Bi 2 Se 3 -based material. Material or n-type Sb 2 Se 3 based material.
  • the thickness of the first barrier layer 102p ranges from [0.01 mm, 0.1 mm].
  • the thickness of the first barrier layer 102p may be 0.01 mm, 0.02 mm. 0.025 mm, 0.031 mm, 0.05 mm, 0.06 mm, 0.07 mm, 0.08 mm, 0.09 mm or 0.1 mm, and the like.
  • the first barrier layer 102p may be in the form of a powder, a film or a foil.
  • the material of the first barrier layer 102p may be metal gold (Au), silver (Ag), tantalum (Ta), copper (Cu), titanium (Ti), titanium nitride (TiN), titanium tungsten (TiW), nickel.
  • One or more of (Ni) or molybdenum (Mo) for example, the material of the first barrier layer 102p may be Au, Cu, Ti or TiW, etc., and the material of the first barrier layer 102p may also be composed of Au and Ag. Alloy, an alloy composed of Cu, Ti, Ni, an alloy composed of Au, Ta, Cu, Ni, and Mo.
  • the thickness of the ninth barrier layer 110a ranges from [0.01 mm, 0.1 mm].
  • the thickness of the ninth barrier layer 110a may be 0.01 mm, 0.02 mm, 0.025 mm, 0.031 mm, 0.05 mm, 0.06 mm, 0.07 mm. , 0.08mm, 0.09mm or 0.1mm, etc.
  • the ninth barrier layer 110a may be in the form of a powder, a film or a foil.
  • the material of the ninth barrier layer 110a may be one or more of metal Au, Ag, Ta, Cu, Ti, TiN, TiW, Ni or Mo.
  • the material of the ninth barrier layer 110a may be Au, Cu.
  • the material of the ninth barrier layer 110a may be an alloy composed of Au or Ag, an alloy composed of Cu, Ti, and Ni, an alloy composed of Au, Ta, Cu, Ni, and Mo, or the like.
  • the materials used by the first barrier layer 102p and the ninth barrier layer 110a in the same thermoelectric unit 10 are the same. It can be understood that, as shown in FIG. 1, the first barrier layer 102p in the same thermoelectric unit 10 is adjacent to the position where the ninth barrier layer 110a is located in the thermoelectric unit 10, and the first barrier layer 102p is in contact with the ninth barrier layer 110a. The same p-type high-temperature thermoelectric leg 101p is used.
  • the first barrier layer 102p and the ninth barrier layer 110a are formed of the same material, on the one hand, the element diffusion between different materials can be reduced, and on the other hand, the thermoelectric unit 10 can be formed.
  • the stress is matched to enhance the stability of the structure of the thermoelectric unit 10.
  • the thickness of the second barrier layer 104p ranges from [0.01 mm, 0.1 mm].
  • the thickness of the second barrier layer 104p may be 0.01 mm, 0.02 mm. 0.025mm, 0.031mm, 0.05 mm, 0.06 mm, 0.07 mm, 0.08 mm, 0.09 mm or 0.1 mm, and the like.
  • the second barrier layer 104p may be in the form of a powder, a film or a foil.
  • the material of the second barrier layer 104p may be one or more of metals Au, Ag, Ta, Cu, Ti, TiN, TiW, Ni or Mo.
  • the material of the second barrier layer 104p may be Au, Cu, Ti or TiW, etc.
  • the material of the second barrier layer 104p may be an alloy composed of Au or Ag, an alloy composed of Cu, Ti, and Ni, an alloy composed of Au, Ta, Cu, Ni, and Mo.
  • the thickness of the third barrier layer 106p ranges from [0.01 mm, 0.1 mm].
  • the thickness of the third barrier layer 106p may be 0.01 mm, 0.02 mm, 0.025 mm, 0.031 mm, 0.05 mm, 0.06 mm, 0.07 mm. , 0.08mm, 0.09mm or 0.1mm, etc.
  • the third barrier layer 106p may be in the form of a powder, a film or a foil.
  • the material of the third barrier layer 106p may be one or more of metals Au, Ag, Ta, Cu, Ti, TiN, TiW, Ni or Mo.
  • the material of the third barrier layer 106p may be Au, Cu, Ti or TiW, etc.
  • the material of the third barrier layer 106p may be an alloy composed of Au or Ag, an alloy composed of Cu, Ti, and Ni, an alloy composed of Au, Ta, Cu, Ni, and Mo.
  • the material used by the second barrier layer 104p and the third barrier layer 106p in the same thermoelectric unit 10 is the same. It can be understood that, as shown in FIG.
  • the second barrier layer 104p in the same thermoelectric unit 10 is in contact with the third barrier layer 106p by the same p-type intermediate temperature thermoelectric leg 105p. Therefore, the second barrier layer 104p is made of the same material.
  • the third barrier layer 106p can facilitate the selection of materials.
  • the thickness of the fourth barrier layer 108p ranges from [0.01 mm, 0.1 mm].
  • the thickness of the fourth barrier layer 108p may be 0.01 mm, 0.02 mm. 0.025 mm, 0.031 mm, 0.05 mm, 0.06 mm, 0.07 mm, 0.08 mm, 0.09 mm or 0.1 mm, and the like.
  • the fourth barrier layer 108p may be in the form of a powder, a film or a foil.
  • the material of the fourth barrier layer 108p may be one or more of metals Au, Ag, Ta, Cu, Ti, TiN, TiW, Ni or Mo.
  • the material of the fourth barrier layer 108p may be Au, Cu, Ti or TiW, etc.
  • the material of the fourth barrier layer 108p may be an alloy composed of Au or Ag, an alloy composed of Cu, Ti, and Ni, an alloy composed of Au, Ta, Cu, Ni, and Mo.
  • the thickness of the twelfth barrier layer 112b ranges from [0.01 mm, 0.1 mm].
  • the thickness of the twelfth barrier layer 112b may be 0.01 mm, 0.02 mm, 0.025 mm, 0.031 mm, 0.05 mm, 0.06 mm, 0.07mm, 0.08mm, 0.09mm or 0.1mm, etc.
  • the twelfth barrier layer 112b may be in the form of a powder, a film or a foil.
  • the material of the twelfth barrier layer 112b may be one or more of metals Au, Ag, Ta, Cu, Ti, TiN, TiW, Ni or Mo.
  • the material of the twelfth barrier layer 112b may be Au, Cu, Ti or TiW, etc.
  • the material of the twelfth barrier layer 112b may be an alloy composed of Au or Ag, an alloy composed of Cu, Ti, and Ni, an alloy composed of Au, Ta, Cu, Ni, and Mo.
  • the first barrier layer 102p and the ninth barrier layer 110a of the adjacent two thermoelectric units 10 are made of the same material.
  • the fourth barrier layer 108p of the adjacent two thermoelectric units 10 is adjacent to the position where the twelfth barrier layer 112b is located, and the fourth barrier layer 108p and the twelfth barrier layer 112b The same p-type low temperature thermoelectric leg 109p is contacted. Therefore, the fourth barrier layer 108p and the twelfth barrier layer 112b are made of the same material, which is convenient for material selection. Stress matching can be formed when manufacturing the thermoelectric module 20, enhancing the stability of the structure of the thermoelectric module 20 (shown in Figure 16).
  • the thickness of the fifth barrier layer 102n ranges from [0.01 mm, 0.1 mm].
  • the thickness of the fifth barrier layer 102n may be 0.01 mm, 0.02 mm. 0.025 mm, 0.031 mm, 0.05 mm, 0.06 mm, 0.07 mm, 0.08 mm, 0.09 mm or 0.1 mm, and the like.
  • the fifth barrier layer 102n may be in the form of a powder, a film or a foil.
  • the material of the fifth barrier layer 102n may be one or more of metals Au, Ag, Ta, Cu, Ti, TiN, TiW, Ni or Mo.
  • the material of the fifth barrier layer 102n may be Au, Cu, Ti or TiW or the like, the material of the fifth barrier layer 102n may be an alloy composed of Au or Ag, an alloy composed of Cu, Ti, and Ni, an alloy composed of Au, Ta, Cu, Ni, and Mo.
  • the thickness of the tenth barrier layer 112a ranges from [0.01 mm, 0.1 mm].
  • the thickness of the tenth barrier layer 112a may be 0.01 mm, 0.02 mm, 0.025 mm, 0.031 mm, 0.05 mm, 0.06 mm, 0.07 mm. , 0.08mm, 0.09mm or 0.1mm, etc.
  • the tenth barrier layer 112a may be in the form of a powder, a film or a foil.
  • the material of the tenth barrier layer 112a may be one or more of metals Au, Ag, Ta, Cu, Ti, TiN, TiW, Ni or Mo.
  • the material of the tenth barrier layer 112a may be Au, Cu
  • the material of the tenth barrier layer 112a such as Ti or TiW may be an alloy composed of Au or Ag, an alloy composed of Cu, Ti, and Ni, an alloy composed of Au, Ta, Cu, Ni, and Mo.
  • the materials used by the fifth barrier layer 102n and the tenth barrier layer 112a in the same thermoelectric unit 10 are the same.
  • the fifth barrier layer 102n and the tenth barrier layer 112a in the same thermoelectric unit 10 are adjacent to each other in the thermoelectric unit 10, and the fifth barrier layer 102n is in contact with the tenth barrier layer 112a.
  • the same n-type high-temperature thermoelectric leg 101n is used. Therefore, the fifth barrier layer 102n and the tenth barrier layer 112a are made of the same material to facilitate material selection, and on the other hand, stress matching can be formed when the thermoelectric unit 10 is manufactured. The stability of the structure of the thermoelectric unit 10 is enhanced.
  • the thickness of the sixth barrier layer 104n ranges from [0.01 mm, 0.1 mm].
  • the thickness of the sixth barrier layer 104n may be 0.01 mm, 0.02 mm. 0.025 mm, 0.031 mm, 0.05 mm, 0.06 mm, 0.07 mm, 0.08 mm, 0.09 mm or 0.1 mm, and the like.
  • the sixth barrier layer 104n may be in the form of a powder, a film or a foil.
  • the material of the sixth barrier layer 104n may be one or more of metals Au, Ag, Ta, Cu, Ti, TiN, TiW, Ni or Mo.
  • the material of the sixth barrier layer 104n may be Au, Cu, Ti or TiW, etc.
  • the material of the sixth barrier layer 104n may be an alloy composed of Au or Ag, an alloy composed of Cu, Ti, and Ni, an alloy composed of Au, Ta, Cu, Ni, and Mo.
  • the thickness of the seventh barrier layer 106n ranges from [0.01 mm, 0.1 mm].
  • the thickness of the seventh barrier layer 106n may be 0.01 mm, 0.02 mm, 0.025 mm, 0.031 mm, 0.05 mm, 0.06 mm, 0.07 mm. , 0.08mm, 0.09mm or 0.1mm, etc.
  • the seventh barrier layer 106n may be in the form of a powder, a film or a foil.
  • the material of the seventh barrier layer 106n may be one or more of metals Au, Ag, Ta, Cu, Ti, TiN, TiW, Ni or Mo.
  • the material of the seventh barrier layer 106n may be Au, Cu, Ti or TiW, etc.
  • the material of the seventh barrier layer 106n may also be an alloy composed of Au and Ag, an alloy composed of Cu, Ti, and Ni, Au, Ta, Cu, Ni. An alloy composed of Mo and the like.
  • the materials used by the sixth barrier layer 104n and the seventh barrier layer 106n in the same thermoelectric unit 10 are the same. It can be understood that, as shown in FIG.
  • the sixth barrier layer 104n and the seventh barrier layer 106n in the same thermoelectric unit 10 are in contact with the same n-type intermediate temperature thermoelectric leg 105n. Therefore, the sixth barrier layer 104n is made of the same material.
  • the seventh barrier layer 106n can facilitate the selection of materials.
  • the thickness of the eighth barrier layer 108n ranges from [0.01 mm, 0.1 mm].
  • the thickness of the eighth barrier layer 108n may be 0.01 mm, 0.02 mm. 0.025 mm, 0.031 mm, 0.05 mm, 0.06 mm, 0.07 mm, 0.08 mm, 0.09 mm or 0.1 mm, and the like.
  • the eighth barrier layer 108n may be in the form of a powder, a film or a foil.
  • the material of the eighth barrier layer 108n may be one or more of metals Au, Ag, Ta, Cu, Ti, TiN, TiW, Ni or Mo.
  • the material of the eighth barrier layer 108n may be Au, Cu, Ti or TiW, etc.
  • the material of the eighth barrier layer 108n may be an alloy composed of Au or Ag, an alloy composed of Cu, Ti, and Ni, an alloy composed of Au, Ta, Cu, Ni, and Mo.
  • the thickness of the eleventh barrier layer 110b ranges from [0.01 mm, 0.1 mm].
  • the thickness of the eleventh barrier layer 110b may be 0.01 mm, 0.02 mm, 0.025 mm, 0.031 mm, 0.05 mm, 0.06 mm, 0.07mm, 0.08mm, 0.09mm or 0.1mm, etc.
  • the eleventh barrier layer 110b may be in the form of a powder, a film or a foil.
  • the material of the eleventh barrier layer 110b may be one or more of metals Au, Ag, Ta, Cu, Ti, TiN, TiW, Ni or Mo.
  • the material of the eleventh barrier layer 110b may be Au, Cu, Ti or TiW, etc.
  • the material of the eleventh barrier layer 110b may be an alloy composed of Au or Ag, an alloy composed of Cu, Ti, and Ni, an alloy composed of Au, Ta, Cu, Ni, and Mo.
  • the material of the eighth barrier layer 108n and the eleventh barrier layer 110b of the adjacent two thermoelectric units 10 are the same. It can be understood that, as shown in FIG.
  • the eighth barrier layer 108n of the adjacent two thermoelectric units 10 is adjacent to the position where the eleventh barrier layer 110b is located, and the eighth barrier layer 108n and the eleventh barrier layer 110b The same n-type low-temperature thermoelectric leg 109n is contacted. Therefore, the eighth barrier layer 108n and the eleventh barrier layer 110b are made of the same material to facilitate material selection on the one hand, and stress can be formed when manufacturing the thermoelectric module 20 on the other hand. Matching enhances the stability of the structure of the thermoelectric module 20 (shown in Figure 16).
  • the first barrier layer 102p, the second barrier layer 104p, the third barrier layer 106p, the fourth barrier layer 108p, the fifth barrier layer 102n, and the sixth barrier layer 104n The materials of the seven barrier layer 106n, the eighth barrier layer 108n, the ninth barrier layer 110a, the tenth barrier layer 112a, the eleventh barrier layer 110b, and the twelfth barrier layer 112b may all be the same, thereby facilitating the selection of the barrier material. Further, the manufacture of the high-performance thermoelectric device 1 can be simplified.
  • the thickness of the first barrier layer 102p can be adjusted according to the actual working environment of the high performance thermoelectric device 1.
  • the thickness of the second barrier layer 104p can be adjusted according to the actual working environment of the high performance thermoelectric device 1.
  • the thickness of the third barrier layer 106p can be adjusted according to the actual working environment of the high performance thermoelectric device 1.
  • the thickness of the fourth barrier layer 108p can be adjusted according to the actual working environment of the high performance thermoelectric device 1.
  • the thickness of the fifth barrier layer 102n can be adjusted according to the actual working environment of the high performance thermoelectric device 1.
  • the thickness of the sixth barrier layer 104n can be adjusted according to the actual working environment of the high performance thermoelectric device 1.
  • the thickness of the seventh barrier layer 106n can be adjusted according to the actual working environment of the high performance thermoelectric device 1.
  • the thickness of the eighth barrier layer 108n can be adjusted according to the actual working environment of the high performance thermoelectric device 1.
  • the thickness of the ninth barrier layer 110a can be adjusted according to the actual working environment of the high performance thermoelectric device 1.
  • the thickness of the tenth barrier layer 112a can be adjusted according to the actual working environment of the high performance thermoelectric device 1.
  • the thickness of the eleventh barrier layer 110b can be adjusted according to the actual working environment of the high performance thermoelectric device 1.
  • the thickness of the twelfth barrier layer 112b can be adjusted according to the actual working environment of the high performance thermoelectric device 1.
  • the thickness of the first buffer stress layer 103p ranges from [0.01 mm, 0.1 mm].
  • the thickness of the first buffer stress layer 103p may be 0.01 mm, 0.02. Mm, 0.025 mm, 0.031 mm, 0.05 mm, 0.06 mm, 0.07 mm, 0.08 mm, 0.09 mm or 0.1 mm, and the like.
  • the first buffer stress layer 103p may be present in the form of a powder, a film or a foil.
  • the material of the first buffer stress layer 103p may be one or more of metal Cu, Pt, Ni or Cu-Mo alloy.
  • the material of the first buffer stress layer 103p may be Cu, Pt, Ni, etc.
  • the first buffer The material of the stress layer 103p may be an alloy composed of Cu or pt, an alloy composed of Cu and Ni, an alloy composed of Cu, Pt, and Ni, and a Cu-Mo alloy.
  • the thickness of the second buffer stress layer 107p ranges from [0.01 mm, 0.1 mm].
  • the thickness of the second buffer stress layer 107p may be 0.01 mm, 0.02 mm, 0.025 mm, 0.031 mm, 0.05 mm, 0.06 mm. , 0.07mm, 0.08mm, 0.09mm or 0.1mm, etc.
  • the second buffer stress layer 107p may be present in the form of a powder, a film or a foil.
  • the material of the second buffer stress layer 107p may be one or more of metal Cu, Pt, Ni or Cu-Mo alloy.
  • the material of the second buffer stress layer 107p may be Cu, Pt, Ni, etc.
  • the second buffer The material of the stress layer 107p may be an alloy composed of Cu or pt, an alloy composed of Cu or Ni, an alloy composed of Cu, Pt, and Ni, and a Cu-Mo alloy.
  • the thickness of the fifth buffer stress layer 111a ranges from [0.01 mm, 0.1 mm].
  • the thickness of the fifth buffer stress layer 111a may be 0.01 mm, 0.02 mm, 0.025 mm, 0.031 mm, 0.05 mm, 0.06 mm. , 0.07mm, 0.08mm, 0.09mm or 0.1mm, etc.
  • the fifth buffer stress layer 111a may be present in the form of a powder, a film or a foil.
  • the material of the fifth buffer stress layer 111a may be one or more of metal Cu, Pt, Ni or Cu-Mo alloy.
  • the material of the fifth buffer stress layer 111a may be Cu, Pt, Ni, etc., the fifth buffer.
  • the material of the stress layer 111a may be an alloy composed of Cu or pt, an alloy composed of Cu or Ni, an alloy composed of Cu, Pt, and Ni, and a Cu-Mo alloy.
  • the thickness of the sixth buffer stress layer 111b ranges from [0.01 mm, 0.1 mm].
  • the thickness of the sixth buffer stress layer 111b may be 0.01 mm, 0.02 mm, 0.025 mm, 0.031 mm, 0.05 mm, 0.06 mm. , 0.07mm, 0.08mm, 0.09mm or 0.1mm, etc.
  • the sixth buffer stress layer 111b may be present in the form of a powder, a film or a foil.
  • the material of the sixth buffer stress layer 111b may be one or more of metal Cu, Pt, Ni or Cu-Mo alloy.
  • the material of the sixth buffer stress layer 111b may be Cu, Pt, Ni or the like
  • the material of the sixth buffer stress layer 111b may be an alloy composed of Cu or pt, an alloy composed of Cu and Ni, an alloy composed of Cu, Pt, and Ni, and a Cu-Mo alloy.
  • the materials used for the first buffer stress layer 103p, the second buffer stress layer 107p, the fifth buffer stress layer 111a, and the sixth buffer stress layer 111b are the same.
  • the first buffer stress layer 103p in the same thermoelectric unit 10 is adjacent to the position of the fifth buffer stress layer 111a. Therefore, the first buffer stress layer 103p and the fifth buffer are made of the same material.
  • the stress layer 111a can facilitate the selection of materials, and on the other hand, stress matching can be formed when the thermoelectric unit 10 is manufactured, and the stability of the structure of the thermoelectric unit 10 is enhanced.
  • the second buffer stress layer 107p and the sixth buffer stress layer 111b of the adjacent two thermoelectric modules 20 are adjacent to each other, and therefore, the second buffer stress layer 107p and the sixth buffer stress layer are formed of the same material.
  • 111b can facilitate the selection of materials, and on the other hand, stress matching can be formed when manufacturing the thermoelectric module 20, and the stability of the structure of the thermoelectric module 20 (shown in FIG. 16) is enhanced.
  • the first buffer stress layer 103p and the second buffer stress layer 107p are components of the p-type thermoelectric leg 10p in the same thermoelectric unit 10, and it is convenient to use the same material to form the first buffer stress layer 103p and the second buffer stress layer 107p. The choice of materials simplifies the manufacture of high performance thermoelectric devices 1.
  • the fifth buffer stress layer 111a may be connected to the p-type high temperature thermoelectric leg 101p and the n-type high temperature thermoelectric leg 101n in the same thermoelectric unit 10
  • the sixth buffer stress layer 111b may be connected to the p-type low temperature thermoelectric leg 109p in the adjacent thermoelectric unit 10 and
  • the n-type low-temperature thermoelectric leg 109n, the fifth buffer stress layer 111a functions similarly to the sixth buffer stress layer 111b
  • the fifth buffer stress layer 111a and the sixth buffer stress layer 111b are also made of the same material, and the material selection is also convenient.
  • the manufacture of the high performance thermoelectric device 1 is simplified.
  • the thickness of the third buffer stress layer 103n ranges from [0.01 mm, 0.1 mm].
  • the thickness of the third buffer stress layer 103n may be 0.01 mm, 0.02. Mm, 0.025 mm, 0.031 mm, 0.05 mm, 0.06 mm, 0.07 mm, 0.08 mm, 0.09 mm or 0.1 mm, and the like.
  • the third buffer stress layer 103n may be present in the form of a powder, a film or a foil.
  • the material of the third buffer stress layer 103n may be one or more of metal Cu, Pt, molybdenum oxide MoO x , and Cu-Mo alloy.
  • the material of the third buffer stress layer 103n may be Cu, Pt, Ni, or the like.
  • the material of the first buffer stress layer 103p may be an alloy composed of Cu or pt, an alloy composed of Cu or Ni, an alloy composed of Cu, Pt, and Ni, a molybdenum oxide MoO x , a Cu-Mo alloy, or the like.
  • the thickness of the fourth buffer stress layer 107n ranges from [0.01 mm, 0.1 mm].
  • the thickness of the fourth buffer stress layer 107n may be 0.01 mm, 0.02 mm, 0.025 mm, 0.031 mm, 0.05 mm, 0.06 mm. , 0.07mm, 0.08mm, 0.09mm or 0.1mm, etc.
  • the fourth buffer stress layer 107n may be present in the form of a powder, a film or a foil.
  • the material of the fourth buffer stress layer 107n may be one or more of metal Cu, Pt, Ni or Cu-Mo alloy.
  • the material of the fourth buffer stress layer 107n may be Cu, Pt, Ni, etc.
  • the second buffer The material of the stress layer 107p may be an alloy composed of Cu or pt, an alloy composed of Cu and Ni, an alloy composed of Cu, Pt, and Ni, a molybdenum oxide MoO x , a Cu-Mo alloy, or the like.
  • the third buffer stress layer 103n and the fourth buffer stress layer 107n are components of the n-type thermoelectric leg 10n in the same thermoelectric unit 10, and the third buffer stress layer 103n and the fourth buffer stress layer 107n are made of the same material. It facilitates the selection of materials and simplifies the manufacture of high-performance thermoelectric devices 1.
  • the buffer stress layer 111b can be made of the same material, so that the selection of the buffer stress layer material can be facilitated, and the manufacture of the high-performance thermoelectric device 1 can be further simplified.
  • the thickness of the first buffer stress layer 103p can be adjusted according to the actual working environment of the high performance thermoelectric device 1.
  • the thickness of the second buffer stress layer 107p can be adjusted according to the actual working environment of the high performance thermoelectric device 1.
  • the thickness of the third buffer stress layer 103n can be adjusted according to the actual working environment of the high performance thermoelectric device 1.
  • the thickness of the fourth buffer stress layer 107n can be adjusted according to the actual working environment of the high performance thermoelectric device 1.
  • the thickness of the fifth buffer stress layer 111a can be adjusted according to the actual working environment of the high performance thermoelectric device 1.
  • the thickness of the sixth buffer stress layer 111b can be adjusted according to the actual working environment of the high performance thermoelectric device 1.
  • the inner package 201 may be made of carbon fiber or Graphite Epoxy Composite (GEC).
  • the material of the outer package 202 may be FeNi Kovar.
  • the package structure may also be a single-layer package layer structure.
  • a single layer encapsulation layer is disposed on the outer surface of the thermoelectric module 20.
  • the first electrical output lead 115p is passed through the single-layer encapsulation layer to the first electrical output electrode 114p
  • the second electrical output lead 115n is passed through the single-layer encapsulation layer to the second electrical output electrode 114n.
  • An insulating interlayer 113 is disposed between the outer surface of the thermoelectric module 20 and the single-layer encapsulation layer.
  • the insulating interlayer 113 is disposed only on the left and right sides of the outer surface of the thermoelectric module 20 (shown in FIG. 1).
  • the single-layer encapsulation layer may be the inner package 201.
  • the material of the single-layer encapsulation layer may be carbon fiber or graphite-epoxy thermal conductive composite material, and the first electrical output wire 115p passes through the inner package 201 to access the first electrical circuit.
  • the output electrode 114p and the second electrical output lead 115n are connected to the second electrical output electrode 114n through the inner package 201.
  • An insulating interlayer 113 is disposed between the outer surface of the thermoelectric module 20 and the inner package 201.
  • the single-layer encapsulation layer may also be the outer package 202.
  • the material of the single-layer encapsulation layer may be FeNi Kovar, and the first electrical output wire 115p passes through the outer package 202 to the first electrical output electrode 114p.
  • the output lead 115n passes through the outer package 202 to the second electrical output electrode 114n.
  • An insulating interlayer 113 is disposed between the outer surface of the thermoelectric module 20 and the outer package 202.
  • the thickness of the inner package 201 can be adjusted according to the actual working environment of the high performance thermoelectric device 1.
  • the thickness of the outer package 202 can also be based on high performance thermoelectricity.
  • the actual working environment of device 1 is adjusted.
  • the thickness of the single-layer package layer can also be based on high performance.
  • the actual working environment of the thermoelectric device 1 is adjusted.
  • the thickness of the phonon scattering layer 113a (shown in FIG. 11) in the insulating interlayer 113 ranges from [1 nm, 100 nm], for example, the phonon scattering layer 113a.
  • the thickness may be 1 nm, 15 nm, 30 nm, 41.3 nm, 57 nm, 66 nm, 70 nm, 85 nm, 93 nm, 98 nm or 100 nm, or the like.
  • the number of layers of the phonon scattering layer 113a ranges from [10, 10000].
  • the number of layers of the phonon scattering layer 113a may be 10 layers, 68 layers, 100 layers, 827 layers, 1000 layers, 2500 layers, and 4000 layers. 5100 layers, 6015 layers, 7777 layers, 8000 layers, 9000 layers or 10000 layers, and the like.
  • the material of the phonon scattering layer 113a may be one or more of SiO 2 , Al 2 O 3 , AlN, MgO, TiO 2 , Si 3 N 4 or SiC.
  • the material of the phonon scattering layer 113a may be SiO.
  • the material of the phonon scattering layer 113a may also be a mixture of SiO 2 , Al 2 O 3 , a mixture of AlN, MgO, Si 3 N 4 and SiC, SiO 2 , a mixture of Al 2 O 3 , AlN, MgO, TiO 2 , Si 3 N 4 and SiC, and the like.
  • the number of layers of the phonon scattering layer 113a may be a plurality of layers, in a specific embodiment of the present invention, when the material of the phonon scattering layer 113a of the first layer is determined, the material of the remaining number of layers of the phonon scattering layer 113a shall be The material of the phonon scattering layer 113a of the first layer is the same, so that the material of the phonon scattering layer 113a is selected, and the insulating interlayer 113 is manufactured.
  • the thickness of the negative thermal expansion buffer layer 113b (shown in FIG. 11) in the insulating interlayer 113 ranges from [1 nm, 100 nm], for example, the negative thermal expansion buffer layer 113b.
  • the thickness may be 1 nm, 15 nm, 30 nm, 41.3 nm, 57 nm, 66 nm, 70 nm, 85 nm, 93 nm, 98 nm or 100 nm, or the like.
  • the number of layers of the negative thermal expansion buffer layer 113b ranges from [10, 10000].
  • the number of layers of the negative thermal expansion buffer layer 113b may be 10 layers, 68 layers, 100 layers, 827 layers, 1000 layers, 2500 layers, and 4000 layers. 5100 layers, 6015 layers, 7777 layers, 8000 layers, 9000 layers or 10000 layers, and the like.
  • the material of the negative thermal expansion buffer layer 113b may be one or more of SiO 2 , Al 2 O 3 , AlN, MgO, TiO 2 , Si 3 N 4 or SiC.
  • the material of the negative thermal expansion buffer layer 113b may be SiO.
  • the material of the negative thermal expansion buffer layer 113b may also be a mixture of SiO 2 , Al 2 O 3 , a mixture of AlN, MgO, Si 3 N 4 and SiC, SiO 2 , a mixture of Al 2 O 3 , AlN, MgO, TiO 2 , Si 3 N 4 and SiC, and the like.
  • the material of the negative thermal expansion buffer layer 113b of the first layer when the material of the negative thermal expansion buffer layer 113b of the first layer is determined, the material of the remaining number of negative thermal expansion buffer layers 113b shall be The material of the negative thermal expansion buffer layer 113b of the first layer is the same, so as to select the material of the negative thermal expansion buffer layer 113b and the manufacture of the insulating interlayer 113.
  • the material of the first electrical output electrode 114p may be metal Cu, Au, Ag, Mo, W, Fe, Pd, Pt, Al, Ni or Ti.
  • the material of the second electrical output electrode 114n may be metal Cu, Au, Ag, Mo, W, Fe, Pd, Pt, Al, Ni or Ti.
  • the material of the first electrical output electrode 114p and the material of the second electrical output electrode 114n are the same, thus facilitating the selection of the material of the output electrode and the manufacture of the high-performance thermoelectric device 1.
  • the first electrical output lead 115p is made of the same material as the second electrical output lead 115n, and is a polyvinyl chloride insulated copper core lead.
  • the present invention also provides an ultra-fast preparation method of a high performance thermoelectric device 1.
  • the ultra-fast preparation method of the high performance thermoelectric device 1 of the embodiment of the present invention includes:
  • thermoelectric leg 101p according to p-type high temperature thermoelectric leg 101p, p-type medium temperature thermoelectric leg 105p, p-type low temperature thermoelectric leg 109p, n-type high temperature thermoelectric leg 101n, n-type medium temperature thermoelectric leg 105n, n-type low temperature thermoelectric leg 109n
  • Each element is stoichiometrically weighed into an elemental powder to obtain a thermoelectric material powder.
  • the material of each layer of the ninth barrier layer 110a and the tenth barrier layer 112a is used to obtain a barrier layer powder.
  • the material powders of the first buffer stress layer 103p, the second buffer stress layer 107p, the third buffer stress layer 103n, the fourth buffer stress layer 107n, and the fifth buffer stress layer 111a are respectively weighed to obtain a buffer stress layer powder.
  • the p-type CoSb 3 -based material is a p-type high-temperature thermoelectric leg 101p material
  • the p-type PbTe-based material is a p-type medium-temperature thermoelectric leg 105p material
  • the p-type Bi 2 Te 3 -based material is a p-type low temperature.
  • thermoelectric leg 109p material the n-type CoSb 3 -based material is an n-type high-temperature thermoelectric leg 101n material
  • the n-type PbTe-based material is an n-type medium-temperature thermoelectric leg 105n material
  • the n-type Bi 2 Te 3 -based material is an n-type low-temperature thermoelectric leg
  • each of the above materials is weighed into an elemental powder in an elemental stoichiometric ratio to obtain a thermoelectric material powder.
  • the metal Mo is used as the first barrier layer 102p material
  • the metal Cu is used as the first buffer stress layer 103p material
  • the metal Mo is used as the second barrier layer 104p material
  • the metal Mo is used as the third barrier layer 106p material
  • the metal Cu is used as the first Two buffer stress layer 107p material
  • TiN as the fourth barrier layer 108p material
  • metal Mo as the fifth barrier layer 102n material
  • MoO x as the third buffer stress layer 103n material
  • metal Mo as the sixth barrier layer 104n material the seventh metallic Mo as a barrier material 106n, 107n as the material of the fourth MoO x stress buffer layer, a TiN barrier layer 108n material of the eighth, the ninth metallic Mo as a barrier material layer 110a, a metal as the Cu
  • the material of the fifth buffer stress layer 111a and the material of the metal layer Mo as the tenth barrier layer 112a are respectively weighed to the material powder of each of the barrier layer and the buffer stress layer to obtain a barrier
  • thermoelectric material powder, the barrier layer powder, and the buffer stress layer powder are sequentially laid in the space surrounded by the mold 302, the upper pressing head 301, and the lower pressing head 306 in the order of the thermoelectric material layer, the barrier layer, and the buffer stress layer. Separating the material powder of each layer of the p-type thermoelectric leg 10p in the thermoelectric material powder from the material powder of each layer of the n-type thermoelectric leg 10n by using the first separator 303, the intermediate partition 305, and the second separator 304, and The discharge plasma sintering is performed to form a thermoelectric block (shown in FIGS. 9 and 10).
  • the material of the upper pressing head 301 and the lower pressing head 306 are all graphite.
  • the material of the mold 302 includes one or more of graphite, an alloy, an Al 2 O 3 -based ceramic, an AlN-based ceramic, a Si 3 N 4 -based ceramic, or a SiC-based ceramic.
  • the material of the mold 302 may be graphite, Al 2 O 3 -based ceramics, SiC-based ceramics, etc., and the material of the mold 302 may also be graphite, a mixture of alloys, Al 2 O 3 based ceramics, AlN based ceramics, Si 3 N 4 a mixture of base ceramics, and the like.
  • the material of the first separator 303, the intermediate separator 305, and the second separator 304 may be graphite or ceramic.
  • the first separator 303, the intermediate partition 305, and the second separator 304 are made of the same material.
  • thermoelectric material powder, the barrier layer powder, and the buffer stress layer powder are sequentially laid in a space surrounded by the mold 302, the upper pressing head 301 and the lower pressing head 306, and the first partition plate 303 and the intermediate partition plate 305 are used.
  • the second separator 304 separates the material powder of each layer of the p-type thermoelectric leg 10p in the thermoelectric material powder from the material powder of each layer of the n-type thermoelectric leg 10n, and performs discharge plasma sintering to form a thermoelectric block.
  • thermoelectric block cutting the thermoelectric block to form the thermoelectric unit 10, and alternately preparing the phonon scattering layer 113a and the negative thermal expansion buffer layer 113b layer by layer by chemical vapor deposition to form an insulating interlayer 113, and the thermoelectric unit 10 is inlaid by the insulating interlayer 113.
  • Fixed shown in Figures 11 and 12).
  • SiO 2 is used as the material of the phonon scattering layer 113a
  • ZrW 2 O 8 is used as the material of the negative thermal expansion buffer layer 113b
  • the phonon scattering layer 113a of the SiO 2 material is alternately prepared by chemical vapor deposition.
  • the negative thermal expansion buffer layer 113b of the ZrW 2 O 8 material forms the insulating interlayer 113; and the insulating interlayer 113 is mounted and fixed to the thermoelectric unit 10 to complete the preparation of the thermoelectric unit 10.
  • thermoelectric module 20 Electrode deposition of the eleventh barrier layer 110b, the sixth buffer stress layer 111b, and the tenth between the convex section of the n-type low temperature thermoelectric leg 109n of the adjacent thermoelectric unit 10 and the convex section of the p-type low temperature thermoelectric leg 109p
  • thermoelectric unit 10 is used as the material of the eleventh barrier layer 110b
  • metal Cu is used as the material of the sixth buffer stress layer 111b
  • TiN is used as the material of the twelfth barrier layer 112b
  • the n-type low-temperature thermoelectric leg 109n convex section and the p-type low-temperature thermoelectric leg 109p convex section are plated with TiN as the eleventh barrier layer 110b, the metal Cu as the sixth buffer stress layer 111b, and TiN as the twelfth barrier layer 112b.
  • the thermoelectric unit 10 is alternately stacked to obtain the thermoelectric module 20.
  • thermoelectric module 20 The first electrical output electrode 114p and the second electrical output electrode 114n of the thermoelectric module 20 are separately electroplated and respectively connected to the first electrical output lead 115p and the second electrical output lead 115n (shown in FIGS. 17 and 18).
  • metal Cu is used as the material of the first electrical output electrode 114p and the second electrical output electrode 114n
  • the polyvinyl chloride insulated copper core wire is used as the first electrical output lead 115p and the second electrical output lead 115n.
  • Metal Cu is electroplated on one of the two thermoelectric units 10 to be assembled to form a first electrical output electrode 114p, and is soldered to the first electrical output lead 115p.
  • One of the n-type low temperature thermoelectric legs 109n is plated with metal Cu to form a second electrical output electrode 114n, and is soldered to the second electrical output lead 115n to complete the assembly of the thermoelectric module 20.
  • first electrical output electrode 114p and the second electrical output electrode 114n may also be prepared by plasma spraying, evaporation or sputtering.
  • the carbon fiber is coated on the outer surface of the thermoelectric module 20 with a high temperature sealant to form the inner package 201; the outer surface of the inner package 201 is fixed to cover the outer package 202 material FeNi kovar alloy, and the outer package 202 material is used at the interface of the outer package 202 The sealant is secured to form outer package 202 (shown in Figures 19 and 20).
  • the package structure is a single-layer package layer
  • only the high-temperature sealant is required to cover the outer surface of the thermoelectric module 20 to form a single-layer encapsulation layer, or only need to be fixed on the outer surface of the thermoelectric module 20.
  • the coating material FeNi Kovar alloy, the interface of the FeNi Kovar alloy is fixed with a sealant to form a single encapsulation layer.
  • the ultra-fast preparation method of the high-performance thermoelectric device 1 of the embodiment of the present invention adopts a hot pressing process in combination with the mold 302 and the separator to prepare the thermoelectric unit 10 in one time, thereby realizing a high-temperature section thermoelectric material, a medium-temperature thermoelectric material, and a low-temperature section thermoelectric material with a barrier layer.
  • the direct sintering with the buffer stress layer reduces inter-diffusion between elements, enhances the bonding strength and thermal matching between the layers of the segmented thermoelectric device, and reduces the contact resistance.

Abstract

一种高性能热电器件(1)及其超快速制备方法。高性能热电器件(1)采用分段结构进行热电材料与温差环境最优匹配、采用阻挡层(102p,104p,106p,108p, 102n,104n,106n,108n)与缓冲应力层(103p,107p,103n,107n)减小界面元素迁移与纵向接触热膨胀应力并增大结合强度、采用声子散射层(113a)与负热膨胀缓冲层(113b)嵌套固定热电腿(10p,10n)增大高性能热电器件(1)内部热阻与横向热匹配性能、采用内封装(201)与外封装(202)避免热电材料升华氧化并增强热电器件(1)外部抗撞击能力，有效突破了传统热电器件存在能量转换效率低、比功率小、热稳定性差、抗撞击性差、制备工艺复杂等技术瓶颈，同时较大程度地提升了高性能热电器件(1)的热学稳定性与机械结构性能，保障了长时间优异的电学输出性能，扩大了工作环境。

Description

一种高性能热电器件及其超快速制备方法 技术领域
本发明涉及热电器件与清洁能源领域，特别涉及一种高性能热电器件及其超快速制备方法。
背景技术
热电器件是利用赛贝克(Seebeck)效应或帕尔贴(Peltier)效应实现热能与电能直接转换的一种环境友好型清洁能源器件。由于热电器件具有环境适应性强、工作稳定性好、服役寿命长、无需维护、无噪声、小型化等优点，目前已在军事国防、深空深海、极地探测、生物医疗、电子工业、人工智能等重要领域被广泛应用。
近年来，热电器件的原料成本、材料性能、制造工艺等方面得到了学术界与工业界的广泛关注。在热电材料原料方面，传统的Bi2Te3基材料地壳元素丰度低，目前采用低成本、元素丰度高的CoSb3基材料、SnSe基材料、Cu2Se基材料、Mg2Si基材料、氧化物材料、石墨烯、拓扑绝缘体制造无机热电器件；以及导电聚合物、电荷转移复合物、金属有机配位聚合物制造有机热电器件得到了一定尝试。
在热电材料性能方面，可用热电材料优值ZT、冷面温度TC与热面温度TH将热电转换效率表示为
Figure PCTCN2017109980-appb-000001
ηTE(ZT,TC,TH)可从热电材料优值ZT、冷面与热面之间温差ΔT等方面来进行优化。目前，高优值热电材料相继被报道，其中传统的PbTe在915K时ZT已达到2.2；SnSe在923K时ZT达到了2.6；Cu2Se在850K时ZT也达到了2.6。但就热电器件而言，传统的Bi2Te3在450K时优值zT为1.4，217K温差下热电转换仅为6％。此外，通过设计分段结构，有效利用热电器件热端与冷端的最大温差；Bi2Te3/CoSb3分段器件实验模块能量转换效率已经达到了12％；采用引导热流或载流子在热电器件中运动方向增加热电器件内部热阻，增大热电器件同电极间接触面积以减小接触电阻来提高温差，进而增强热电器件电学输出性能。
在制造工艺方面，采用金属有机化学气相沉积法(MOCVD)制备纳米超晶格热电薄膜；通过调整热电器件内部结构容积比来提高体积比功率与热匹配；采用放电等离子体烧结(SPS)工艺从热电材料单质粉体快速烧结得到热电块体；采用镂空掩模板与滚珠定位方向沉积目标热电腿；采用半导体集成与微纳加工技术制造纳米线热电器件；通过自蔓延燃 烧、热爆反应，采用喷墨打印、选择性激光熔融3D打印与增材制造技术快速制备毫米级薄膜热电器件等技术被公开。
此外，为避免高温下热电材料元素升华，周期性热循环器件性能下降，在热电材料层与电极层之间增加合金层与扩散阻挡层；采用有机无机陶瓷涂层/多孔玻璃面层对热电器件表面进行涂覆，采用(连接过渡层/阻挡层)n(n≥1)包覆热电材料高温端并在接触界面反应形成扩散层具有明显作用。
然而，尽管上述工作一定程度上提升了热电器件的性能，改进了热电器件的制备方法，但就大规模工业化热电器件而言，迫切需要解决的主要问题在于：①隔绝热电材料同外部环境直接接触，防止材料自内向外升华与自外向内氧化；②提高热电腿的热稳定性，减小甚至消除接触热膨胀与裂缝产生；③保持长时间优异的电学输出性能与工作稳定性。
本发明提出的一种高性能热电器件能够突破传统热电器件存在能量转换效率低、比功率小、热稳定性差、抗撞击性差、制备工艺复杂等技术瓶颈，具有能量转换效率高、工作稳定性好、超快速制备等特点。
发明内容
本发明的实施例提供了一种高性能热电器件及高性能热电器件的超快速制备方法。
本发明实施方式的高性能热电器件(1)，所述高性能热电器件(1)包括热电模块(20)，所述热电模块(20)由热电单元(10)和绝缘夹层(113)依次堆叠形成；所述热电单元(10)包括p型热电腿(10p)和n型热电腿(10n)；所述p型热电腿(10p)包括自上而下依次设置的p型高温热电腿(101p)、第一阻挡层(102p)、第一缓冲应力层(103p)、第二阻挡层(104p)、p型中温热电腿(105p)、第三阻挡层(106p)、第二缓冲应力层(107p)、第四阻挡层(108p)、p型低温热电腿(109p)；所述n型热电腿(10n)包括自上而下依次设置的n型高温热电腿(101n)、第五阻挡层(102n)、第三缓冲应力层(103n)、第六阻挡层(104n)、n型中温热电腿(105n)、第七阻挡层(106n)、第四缓冲应力层(107n)、第八阻挡层(108n)、n型低温热电腿(109n)；所述p型高温热电腿(101p)与所述n型高温热电腿(101n)通过第九阻挡层(110a)、第五缓冲应力层(111a)、第十阻挡层(112a)相连以形成所述热电单元(10)，相邻所述热电单元(10)的所述n型低温热电腿(109n)与所述p型低温热电腿(109p)通过第十一阻挡层(110b)、第六缓冲应力层(111b)、第十二阻挡层(112b)固定连接并采用所述绝缘夹层(113)镶嵌形成所述热电模块(20)；所述热电模块(20)底端两侧的所述p型低温热电腿(109p)、所述n型低温热电腿(109n)分别设有第一电学输出电极(114p)和第二电学输出电极(114n)，所述第一电学输出电极(114p)连接第一 电学输出导线(115p)，所述第二电学输出电极(114n)连接第二电学输出导线(115n)。
在某些实施方式中，所述高性能热电器件(1)为方形结构。
在某些实施方式中，多个所述高性能热电器件(1)可通过串联方式、并联方式或串并联方式结合。
在某些实施方式中，所述p型高温热电腿(101p)的材质包括p型SiGe基材料、p型CoSb3基材料、p型SnSe基材料、p型PbSe基材料、p型Cu2Se基材料、p型BiCuSeO基材料、p型Half-Heusler材料、p型Cu(In,Ga)Te2材料、p型FeSi2基材料、CrSi2、MnSi1.73、CoSi、p型Cu1.8S基材料或p型氧化物材料；
所述p型中温热电腿(105p)的材质包括p型PbTe基材料、p型CoSb3基材料、p型Half-Heusler材料、p型Cu1.8S基材料或p型AgSbTe2基材料；
所述p型低温热电腿(109p)的材质包括p型Bi2Te3基材料、p型Sb2Se3基材料或p型Sb2Te3基材料。
在某些实施方式中，所述n型高温热电腿(101n)的材质包括n型SiGe基材料、n型CoSb3基材料、n型SnSe基材料、n型SnTe基材料、n型Cu2Se基材料、n型Half-Heusler材料或n型氧化物材料；
所述n型中温热电腿(105n)的材质包括n型PbTe基材料、n型PbS基材料、n型CoSb3基材料、n型Mg2Si基材料、n型Zn4Sb3基材料、n型InSb基材料、n型Half-Heusler材料、n型氧化物材料或n型AgSbTe2基材料；
所述n型低温热电腿(109n)的材质包括n型Bi2Te3基材料、n型BiSb基材料、n型Zn4Sb3基材料、n型Mg3Sb2基材料、n型Bi2Se3基材料或n型Sb2Se3基材料。
在某些实施方式中，所述第一阻挡层(102p)、所述第二阻挡层(104p)、所述第三阻挡层(106p)、所述第四阻挡层(108p)、所述第五阻挡层(102n)、所述第六阻挡层(104n)、所述第七阻挡层(106n)、所述第八阻挡层(108n)、所述第九阻挡层(110a)、所述第十阻挡层(112a)、所述第十一阻挡层(110b)、所述第十二阻挡层(112b)的厚度的取值范围均为[0.01mm,0.1mm]。
在某些实施方式中，所述第一阻挡层(102p)、所述第二阻挡层(104p)、所述第三阻挡层(106p)、所述第四阻挡层(108p)、所述第五阻挡层(102n)、所述第六阻挡层(104n)、所述第七阻挡层(106n)、所述第八阻挡层(108n)、所述第九阻挡层(110a)、所述第十阻挡层(112a)、所述第十一阻挡层(110b)、所述第十二阻挡层(112b)均以粉末、薄膜或箔片的形式存在。
在某些实施方式中，所述第一阻挡层(102p)、所述第二阻挡层(104p)、所述第三阻挡层(106p)、所述第四阻挡层(108p)、所述第五阻挡层(102n)、所述第六阻挡层(104n)、所述第七阻挡层(106n)、所述第八阻挡层(108n)、所述第九阻挡层(110a)、所述第十阻挡层(112a)、所 述第十一阻挡层(110b)、所述第十二阻挡层(112b)的材质均包括金(Au)、银(Ag)、钽(Ta)、铜(Cu)、钛(Ti)、氮化钛(TiN)、钛钨(TiW)、镍(Ni)或钼(Mo)中的一种或多种；
所述第一阻挡层(102p)与所述第九阻挡层(110a)的材质相同；所述第二阻挡层(104p)与所述第三阻挡层(106p)的材质相同；所述第四阻挡层(108p)与所述第十二阻挡层(112b)的材质相同；所述第五阻挡层(102n)与所述第十阻挡层(112a)的材质相同；所述第六阻挡层(104n)与所述第七阻挡层(106n)的材质相同；所述第八阻挡层(108n)与所述第十一阻挡层(110b)的材质相同。
在某些实施方式中，所述第一缓冲应力层(103p)、所述第二缓冲应力层(107p)、所述第三缓冲应力层(103n)、所述第四缓冲应力层(107n)、所述第五缓冲应力层(111a)和所述第六缓冲应力层(111b)的厚度的取值范围均为[0.01mm,0.1mm]。
在某些实施方式中，所述第一缓冲应力层(103p)、所述第二缓冲应力层(107p)、所述第三缓冲应力层(103n)、所述第四缓冲应力层(107n)、所述第五缓冲应力层(111a)和所述第六缓冲应力层(111b)均以粉末、薄膜或箔片的形式存在。
在某些实施方式中，所述第一缓冲应力层(103p)、所述第二缓冲应力层(107p)、所述第五缓冲应力层(111a)和所述第六缓冲应力层(111b)的材质均包括铜(Cu)、铂(Pt)、镍(Ni)、铜钼(Cu-Mo)合金中的一种或多种，所述第一缓冲应力层(103p)、所述第二缓冲应力层(107p)、所述第五缓冲应力层(111a)和所述第六缓冲应力层(111b)的材质相同；
所述第三缓冲应力层(103n)和所述第四缓冲应力层(107n)的材料均包括氧化钼(MoOx)、铜(Cu)、铂(Pt)、镍(Ni)、铜钼(Cu-Mo)合金中的一种或多种，所述第三缓冲应力层(103n)和所述第四缓冲应力层(107n)的材质相同。
在某些实施方式中，所述第一电学输出电极(114p)与所述第二电学输出电极(114n)的材质均包括金(Au)、钯(Pd)、铂(Pt)、铝(Al)、铜(Cu)、镍(Ni)、钛(Ti)中的一种或多种，所述第一电学输出电极(114p)与所述第二电学输出电极(114n)的材质相同；
所述第一电学输出导线(115p)与所述第二电学输出导线(115n)的材质均为聚氯乙烯绝缘铜芯导线。
在某些实施方式中，所述绝缘夹层(113)包括声子散射层(113a)和负热膨胀缓冲层(113b)，所述声子散射层(113a)与所述负热膨胀缓冲层(113b)依次层叠设置，所述绝缘夹层(113)镶嵌固定于相邻的所述p型热电腿(10p)与所述n型热电腿(10n)之间。
在某些实施方式中，所述高性能热电器件(1)还包括封装结构，所述封装结构包括两层，分别为内封装(201)和外封装(202)，所述热电模块(20)的外表面设置有所述内封装(201)，所述内封装(201)的外表面设置有所述外封装(202)；所述第一电学输出导线(115p)穿过所述外 封装(202)与所述内封装(201)接入所述第一电学输出电极(114p)，所述第二电学输出导线(115n)穿过所述外封装(202)与所述内封装(201)接入所述第二电学输出电极(114n)；或
所述封装结构包括单层封装层，所述单层封装层设置在所述热电模块(20)的外表面，所述第一电学输出导线(115p)穿过所述单层封装层接入所述第一电学输出电极(114p)，所述第二电学输出导线(115n)穿过所述单层封装层接入所述第二电学输出电极(114n)。
在某些实施方式中，所述绝缘夹层(113)包括声子散射层(113a)和负热膨胀缓冲层(113b)，所述声子散射层(113a)与所述负热膨胀缓冲层(113b)依次层叠设置，所述绝缘夹层(113)左右相对设置且位于所述热电模块(20)与所述内封装(201)之间；或
所述绝缘夹层(113)左右相对设置且位于所述热电模块(20)与所述单层封装层之间。
在某些实施方式中，所述声子散射层(113a)为纳米绝缘颗粒层，所述声子散射层(113a)的厚度的取值范围为[1nm,100nm]，所述声子散射层(113a)的层数的取值范围为[10,10000]，所述声子散射层(113a)的材料包括SiO2、Al2O3、AlN、MgO、TiO2、Si3N4或SiC中的一种或多种；
所述负热膨胀缓冲层(113b)的厚度的取值范围为[1nm,100nm]，所述负热膨胀缓冲层(113b)的层数的取值范围为[10,10000]，所述负热膨胀缓冲层(113b)的材料包括BaTiO3、PbTiO3、LaCrO3、ZrW2O8、ZrV2O7或HfW2O8中的一种或多种。
在某些实施方式中，所述封装结构包括两层时，所述内封装(201)的材质包括碳纤维或石墨-环氧树脂导热复合材料，所述外封装(202)的材质包括FeNi可伐合金。
本发明实施方式的高性能热电器件(1)的超快速制备方法包括：
分别按照p型高温热电腿(101p)、p型中温热电腿(105p)、p型低温热电腿(109p)、n型高温热电腿(101n)、n型中温热电腿(105n)、n型低温热电腿(109n)中各元素化学计量比称量单质粉体以得到热电材料粉体，分别称量第一阻挡层(102p)、第二阻挡层(104p)、第三阻挡层(106p)、第四阻挡层(108p)、第五阻挡层(102n)、第六阻挡层(104n)、第七阻挡层(106n)、第八阻挡层(108n)、第九阻挡层(110a)、第十阻挡层(112a)各层材料粉体以得到阻挡层粉体；分别称量第一缓冲应力层(103p)、第二缓冲应力层(107p)、第三缓冲应力层(103n)、第四缓冲应力层(107n)、第五缓冲应力层(111a)各层材料粉体以得到缓冲应力层粉体；
按照热电材料层、阻挡层、缓冲应力层的顺序将所述热电材料粉体、所述阻挡层粉体、所述缓冲应力层粉体依次铺设于模具(302)、上压头(301)与下压头(306)围成的空间中，并用第一隔板(303)、中间隔板(305)、第二隔板(304)将所述热电材料粉体中的p型热电腿(10p)各层材料粉体与n型热电腿(10n)各层材料粉体分离，并进行放电等离子体烧结形成热电块体；
切割所述热电块体形成热电单元(10)；
采用化学气相沉积法逐层交替制备声子散射层(113a)和负热膨胀缓冲层(113b)以形成绝缘夹层(113)，利用所述绝缘夹层(113)对所述热电单元(10)进行镶嵌固定；
在相邻所述热电单元(10)的所述n型低温热电腿(109n)的凸起截面与所述p型低温热电腿(109p)的凸起截面之间电镀沉积第十一阻挡层(110b)、第六缓冲应力层(111b)和第十二阻挡层(112b)，交替堆叠热电单元(10)以得到热电模块(20)；
分别电镀制备所述热电模块(20)的第一电学输出电极(114p)和第二电学输出电极(114n)，并分别接入第一电学输出导线(115p)和第二电学输出导线(115n)。
在某些实施方式中，所述高性能热电器件(1)的超快速制备方法还包括：
采用高温密封胶将碳纤维包覆于所述热电模块(20)的外表面以形成内封装(201)；
在所述内封装(201)的外表面固定包覆外封装(202)材料FeNi可伐合金，所述外封装(202)材料的接口处用密封胶固定以形成外封装(202)。
在某些实施方式中，所述上压头(301)和所述下压头(306)的材质均为石墨；
所述模具(302)的材质包括石墨、合金、Al2O3基陶瓷、AlN基陶瓷、Si3N4基陶瓷或SiC基陶瓷中的一种或多种；
所述第一隔板(303)、所述中间隔板(305)、所述第二隔板(304)的材料均包括石墨或陶瓷，所述第一隔板(303)、所述中间隔板(305)、所述第二隔板(304)的材质相同。
本发明所依据的原理是：热电器件在温差作用下，p型热电腿(10p)与n型热电腿(10n)内部空穴与电子产生迁移，采用高温、中温、低温分段热电材料最大限度利用器件热面与冷面之间温差，结合声子与电子的平均自由程差异(电子平均自由程为1nm量级，声子平均自由程为100nm量级)，设计纳米结构声子散射层(113a)与负热膨胀缓冲层(113b)复合材料，在增大热电材料声子散射的同时减小甚至消除材料接触热膨胀，并采用内封装(201)与外封装(202)提高热电器件工作稳定性。
本发明提供的高性能热电器件(1)，通过采用分段结构、纳米声子散射结构、负热膨胀材料、内封装(201)与外封装(202)材料，有效突破了传统热电器件存在的能量转换效率低、比功率小、热稳定性差、抗撞击性差、制备工艺复杂等技术瓶颈，具有能量转换效率高、输出功率大、环境适用性强、工作稳定性好、使用寿命长、易于实施等特点，可长时间稳定工作于军事国防、深空深海、极地探测、生物医疗、电子工业、人工智能等重要领域，进一步满足了能量转换的环保、高效、便携、普适。与现有技术相比，主要有益效果如下：
1、本发明采用分段结构、阻挡层、缓冲应力层、纳米颗粒声子散射材料与负热膨 胀材料形成的绝缘夹层(113)、封装结构设计热电器件，突破了传统热电器件局限于接触热膨胀、元素迁移扩散、热电材料升华与氧化所带来的能量利用率低、体积比功率小、工作稳定性和抗撞击性差等技术缺陷，大幅提高了热电器件的电学输出性能与工作稳定性。
2、本发明采用热压工艺结合模具(302)与隔板一次成型制备热电单元(10)，实现高温段热电材料、中温段热电材料、低温段热电材料同阻挡层与缓冲应力层的直接烧结，减小了元素间相互扩散，增强了分段热电器件层间结合强度与热匹配度，降低接触电阻。
3、直接连接p型热电腿(10p)与n型热电腿(10n)，采用纳米颗粒声子散射材料与负热膨胀材料形成的绝缘夹层(113)占据传统热电器件相邻热电腿之间存在的空气间隙并镶嵌支撑相邻p型热电腿(10p)与n型热电腿(10n)，增大了器件内部热阻，降低了接触电阻、提高了单位容积比功率、增强了声子散射、减小了接触热膨胀、避免了电流回流，较大程度地提高了热电器件的能量转化效率，满足能量转换低碳环保、集成高效、经济普适的要求。
4、本发明采用内封装(201)与外封装(202)对热电模块(20)结构进行固定，有助于缓冲热电器件内部结构存在的机械挤压与热应力，缓冲热电器件同外部环境之间的机械撞击，使得热电器件具备一定的自修复功能，并且更好的工作于各种恶劣环境。
本发明的附加方面和优点将在下面的描述中部分给出，部分将从下面的描述中变得明显，或通过本发明的实践了解到。
附图说明
本发明上述的和/或附加的方面和优点从下面结合附图对实施例的描述中将变得明显和容易理解，其中：
图1是本发明某些实施方式的高性能热电器件的结构示意图。
图2是本发明某些实施方式的高性能热电器件的正视图。
图3是本发明某些实施方式的高性能热电器件的冷面正视图。
图4是本发明某些实施方式的高性能热电器件的热面正视图。
图5是本发明某些实施方式的高性能热电器件待封装结构示意图。
图6是基于Seebeck效应的热电器件工作原理图。
图7是传统分段热电器件结构示意图。
图8是本发明某些实施方式的高性能热电器件的超快速制备方法的流程示意图。
图9至图20是本发明某些实施方式的高性能热电器件的制作工艺流程图。
主要元件及符号说明：
高性能热电器件1、热电单元10、热电模块20、p型热电腿10p、n型热电腿10n、p型高温热电腿101p、第一阻挡层102p、第一缓冲应力层103p、第二阻挡层104p、p型中温热电腿105p、第三阻挡层106p、第二缓冲应力层107p、第四阻挡层108p、p型低温热电腿109p、n型高温热电腿101n、第五阻挡层102n、第三缓冲应力层103n、第六阻挡层104n、n型中温热电腿105n、第七阻挡层106n、第四缓冲应力层107n、第八阻挡层108n、n型低温热电腿109n、第九阻挡层110a、第五缓冲应力层111a、第十阻挡层112a、第十一阻挡层110b、第六缓冲应力层111b、第十二阻挡层112b、绝缘夹层113、声子散射层113a、负热膨胀缓冲层113b、第一电学输出电极114p、第一电学输出导线115p、第二电学输出电极114n、第二电学输出导线115n；
内封装201、外封装202；
上压头301、模具302、第一隔板303、第二隔板304、中间隔板305、下压头306。
具体实施方式
下面详细描述本发明的实施例，所述实施例的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施例是示例性的，旨在用于解释本发明，而不能理解为对本发明的限制。
在本发明的描述中，需要理解的是，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本发明的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
在本发明的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接或可以相互通信；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本发明中的具体含义。
下文的公开提供了许多不同的实施方式或例子用来实现本发明的不同结构。为了简化本发明的公开，下文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本发明。此外，本发明可以在不同例子中重复参考数字和/或参考字母，这 种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施方式和/或设置之间的关系。此外，本发明提供了的各种特定的工艺和材料的例子，但是本领域普通技术人员可以意识到其他工艺的应用和/或其他材料的使用。
请一并参阅图1至图7，本发明实施方式的高性能热电器件1包括热电模块20(图16所示)和封装结构。
其中，热电模块20由热电单元10(图10所示)和绝缘夹层113依次堆叠形成。请结合图10及图16，热电单元10包括p型热电腿10p和n型热电腿10n。p型热电腿10p包括自上而下依次设置的p型高温热电腿101p、第一阻挡层102p、第一缓冲应力层103p、第二阻挡层104p、p型中温热电腿105p、第三阻挡层106p、第二缓冲应力层107p、第四阻挡层108p和p型低温热电腿109p。n型热电腿10n包括自上而下依次设置的n型高温热电腿101n、第五阻挡层102n、第三缓冲应力层103n、第六阻挡层104n、n型中温热电腿105n、第七阻挡层106n、第四缓冲应力层107n、第八阻挡层108n、n型低温热电腿109n。p型高温热电腿101p与所述n型高温热电腿101n通过第九阻挡层110a、第五缓冲应力层111a、第十阻挡层112a相连以形成热电单元10。相邻的热电单元10的n型低温热电腿109n与p型低温热电腿109p通过第十一阻挡层110b、第六缓冲应力层111b、第十二阻挡层112b固定连接并采用绝缘夹层113镶嵌依次堆叠以形成热电模块20。
热电模块20的外表面设置有内封装201，内封装201的外表面设置有外封装202。
热电模块20底端两侧的p型低温热电腿109p设有第一电学输出电极114p，n型低温热电腿109n设有第二电学输出电极114n。第一电学输出导线115p依次穿过内封装201与外封装202接入第一电学输出电极114p。第二电学输出导线115n依次穿过内封装201与外封装202接入第二电学输出电极114n。
请结合图11，绝缘夹层113为声子散射层113a与负热膨胀缓冲层113b依次层叠设置而成的复合材料。声子散射层113a为纳米绝缘颗粒，颗粒间互不接触。绝缘夹层113镶嵌固定于相邻的p型热电腿10p与n型热电腿10n之间(图12、图14和图15所示)。此外，热电模块20的外表面与内封装201之间还设有绝缘夹层113。其中，绝缘夹层113仅设置在热电模块20的外表面的左右两侧(图18、图19和图20所示)。
请结合图6，本发明实施方式的高性能热电器件1在温差作用下，p型热电腿10p与n型热电腿10n的内部空穴与电子会产生迁移，从而将热能转换为电能。
本发明实施方式的高性能热电器件1采用高温、中温、低温分段的热电材料可以最大限度地利用高性能热电器件1热面与冷面之间的温差，提升能量转换效率；采用阻挡层、缓冲应力层、声子散射层113a、负热膨胀缓冲层113b、封装结构的分段结构进行设计，突 破了传统热电器件(图7所示)局限于接触热膨胀、元素迁移扩散、热电材料升华与氧化所带来的能量利用率低、体积比功率小、工作稳定性和抗撞击性差等缺陷，大幅提高了高性能热电器件1的电学输出性能与工作稳定性。
再者，本发明实施方式的高性能热电器件1的阻挡层一方面可以防止在制作高性能热电器件1时，高温烧结过程中热电材料(即p型热电腿10p及n型热电腿10n的材料)与缓冲应力层之间的元素相互扩散，另一方面可以增强缓冲应力层与热电材料之间的结合强度，形成良好的欧姆接触，减小接触电阻。本发明实施方式的高性能热电器件1缓冲应力层的材料与热电材料具有良好的成分、结构与热匹配，在致密化烧结过程中与热电材料的粉体、阻挡层的粉体形成化合物，使界面形成嵌合结构，增大结合强度，减小裂缝，阻挡接触界面元素迁移，降低接触电阻，增大载流子萃取能力。
另外，本发明实施方式的高性能热电器件1直接连接p型热电腿10p与n型热电腿10n，且结合声子与电子的平均自由程差异(电子平均自由程为1nm量级，声子平均自由程为100nm量级)，设计并采用纳米结构声子散射层113a和负热膨胀缓冲层113b的复合材料以占据传统热电器件相邻热电腿之间存在的空气间隙并镶嵌支撑相邻的p型热电腿10p与n型热电腿10n，增大了高性能热电器件1的内部热阻，降低了接触电阻，提高了单位容积比功率，增强了热电材料声子散射，减小甚至消除热接触膨胀，避免了电流回流，较大程度地提高了高性能热电器件1的能量转换效率，满足能量转换低碳环保、集成高效、经济普适的要求。
此外，本发明实施方式的高性能热电器件1采用内封装201与外封装202对热电模块20的结构进行固定，有助于缓冲高性能热电器件1内部结构存在的机械积压与热应力，缓冲高性能热电器件1同外部环境之间的机械撞击，使得高性能热电器件1具备一定的自修复功能，且能更好地工作于各种恶劣环境。
请再参阅图1，在某些实施方式中，本发明实施方式的高性能热电器件1的结构可为方形结构。多个高性能热电器件1可通过串联的方式结合，也可通过并联的方式结合，还可通过串并联的方式结合。高性能热电器件1在应用时，可选择装配DC/DC升压模块对高性能热电器件1的电学输出进行管理。具体地，一个高性能热电器件1的输出端可与DC/DC升压模块进行装配，多个高性能热电器件1经过串联、并联或串并联方式结合后的输出端可与DC/DC升压模块进行装配。如此，可对高性能热电器件1的输出电压进行提升。
请再参阅图1，在某些实施方式中，p型高温热电腿101p的材质可以是p型SiGe基材料、p型CoSb3基材料、p型SnSe基材料、p型PbSe基材料、p型Cu2Se基材料、p型BiCuSeO基材料、p型Half-Heusler材料、p型Cu(In,Ga)Te2材料、p型FeSi2基材料、CrSi2、MnSi1.73、 CoSi、p型Cu1.8S基材料或p型氧化物材料。p型中温热电腿105p的材质可以是p型PbTe基材料、p型CoSb3基材料、p型Half-Heusler材料、p型Cu1.8S基材料或p型AgSbTe2基材料。p型低温热电腿109p的材质可以是p型Bi2Te3基材料、p型Sb2Se3基材料或p型Sb2Te3基材料。n型高温热电腿101n的材质可以是n型SiGe基材料、n型CoSb3基材料、n型SnSe基材料、n型SnTe基材料、n型Cu2Se基材料、n型Half-Heusler材料或n型氧化物材料。n型中温热电腿105n的材质可以是n型PbTe基材料、n型PbS基材料、n型CoSb3基材料、n型Mg2Si基材料、n型Zn4Sb3基材料、n型InSb基材料、n型Half-Heusler材料、n型氧化物材料或n型AgSbTe2基材料。n型低温热电腿109n的材质可以是n型Bi2Te3基材料、n型BiSb基材料、n型Zn4Sb3基材料、n型Mg3Sb2基材料、n型Bi2Se3基材料或n型Sb2Se3基材料。
请再参阅图1，在某些实施方式中，第一阻挡层102p的厚度的取值范围为[0.01mm,0.1mm]，例如，第一阻挡层102p的厚度可为0.01mm、0.02mm、0.025mm、0.031mm、0.05mm、0.06mm、0.07mm、0.08mm、0.09mm或0.1mm等。第一阻挡层102p可以以粉末、薄膜或箔片的形式存在。第一阻挡层102p的材质可以是金属的金(Au)、银(Ag)、钽(Ta)、铜(Cu)、钛(Ti)、氮化钛(TiN)、钛钨(TiW)、镍(Ni)或钼(Mo)中的一种或多种，例如，第一阻挡层102p的材料可以是Au、Cu、Ti或TiW等，第一阻挡层102p的材料还可以是Au、Ag组成的合金，Cu、Ti、Ni组成的合金，Au、Ta、Cu、Ni及Mo组成的合金等。第九阻挡层110a厚度的取值范围为[0.01mm,0.1mm]，例如，第九阻挡层110a的厚度可为0.01mm、0.02mm、0.025mm、0.031mm、0.05mm、0.06mm、0.07mm、0.08mm、0.09mm或0.1mm等。第九阻挡层110a可以以粉末、薄膜或箔片的形式存在。第九阻挡层110a的材质可以是金属的Au、Ag、Ta、Cu、Ti、TiN、TiW、Ni或Mo中的一种或多种，例如，第九阻挡层110a的材料可以是Au、Cu、Ti或TiW等，第九阻挡层110a的材料还可以是Au、Ag组成的合金，Cu、Ti、Ni组成的合金，Au、Ta、Cu、Ni及Mo组成的合金等。在本发明的具体实施例中，同一热电单元10中的第一阻挡层102p与第九阻挡层110a使用的材质是相同的。可以理解，图1所示，同一热电单元10中的第一阻挡层102p与第九阻挡层110a在热电单元10中所处的位置相邻，且第一阻挡层102p与第九阻挡层110a接触的是同一p型高温热电腿101p，因此，采用相同的材质制作第一阻挡层102p与第九阻挡层110a一方面可以减小不同材料间元素扩散，另一方面在制造热电单元10时可以形成应力匹配，增强热电单元10的结构的稳定性。
请再参阅图1，在某些实施方式中，第二阻挡层104p的厚度的取值范围为[0.01mm,0.1mm]，例如，第二阻挡层104p的厚度可为0.01mm、0.02mm、0.025mm、0.031mm、 0.05mm、0.06mm、0.07mm、0.08mm、0.09mm或0.1mm等。第二阻挡层104p可以以粉末、薄膜或箔片的形式存在。第二阻挡层104p的材质可以是金属Au、Ag、Ta、Cu、Ti、TiN、TiW、Ni或Mo中的一种或多种，例如，第二阻挡层104p的材料可以是Au、Cu、Ti或TiW等，第二阻挡层104p的材料还可以是Au、Ag组成的合金，Cu、Ti、Ni组成的合金，Au、Ta、Cu、Ni及Mo组成的合金等。第三阻挡层106p厚度的取值范围为[0.01mm,0.1mm]，例如，第三阻挡层106p的厚度可为0.01mm、0.02mm、0.025mm、0.031mm、0.05mm、0.06mm、0.07mm、0.08mm、0.09mm或0.1mm等。第三阻挡层106p可以以粉末、薄膜或箔片的形式存在。第三阻挡层106p的材质可以是金属Au、Ag、Ta、Cu、Ti、TiN、TiW、Ni或Mo中的一种或多种，例如，第三阻挡层106p的材料可以是Au、Cu、Ti或TiW等，第三阻挡层106p的材料还可以是Au、Ag组成的合金，Cu、Ti、Ni组成的合金，Au、Ta、Cu、Ni及Mo组成的合金等。在本发明的具体实施例中，同一热电单元10中的第二阻挡层104p与第三阻挡层106p使用的材质是相同的。可以理解，图1所示，同一热电单元10中的第二阻挡层104p与第三阻挡层106p接触的是同一p型中温热电腿105p，因此，采用相同的材质制作第二阻挡层104p与第三阻挡层106p可以方便材质的选择。
请再参阅图1，在某些实施方式中，第四阻挡层108p的厚度的取值范围为[0.01mm,0.1mm]，例如，第四阻挡层108p的厚度可为0.01mm、0.02mm、0.025mm、0.031mm、0.05mm、0.06mm、0.07mm、0.08mm、0.09mm或0.1mm等。第四阻挡层108p可以以粉末、薄膜或箔片的形式存在。第四阻挡层108p的材质可以是金属Au、Ag、Ta、Cu、Ti、TiN、TiW、Ni或Mo中的一种或多种，例如，第四阻挡层108p的材料可以是Au、Cu、Ti或TiW等，第四阻挡层108p的材料还可以是Au、Ag组成的合金，Cu、Ti、Ni组成的合金，Au、Ta、Cu、Ni及Mo组成的合金等。第十二阻挡层112b厚度的取值范围为[0.01mm,0.1mm]，例如，第十二阻挡层112b的厚度可为0.01mm、0.02mm、0.025mm、0.031mm、0.05mm、0.06mm、0.07mm、0.08mm、0.09mm或0.1mm等。第十二阻挡层112b可以以粉末、薄膜或箔片的形式存在。第十二阻挡层112b的材质可以是金属Au、Ag、Ta、Cu、Ti、TiN、TiW、Ni或Mo中的一种或多种，例如，第十二阻挡层112b的材料可以是Au、Cu、Ti或TiW等，第十二阻挡层112b的材料还可以是Au、Ag组成的合金，Cu、Ti、Ni组成的合金，Au、Ta、Cu、Ni及Mo组成的合金等。在本发明的具体实施例中，相邻的两个热电单元10中的第一阻挡层102p与第九阻挡层110a使用的材质是相同的。可以理解，图1所示，相邻的两个热电单元10中的第四阻挡层108p与第十二阻挡层112b所处的位置相邻，且第四阻挡层108p与第十二阻挡层112b接触的是同一p型低温热电腿109p，因此，采用相同的材质制作第四阻挡层108p与第十二阻挡层112b一方面可以方便材质的选择，另一方面 在制造热电模块20时可以形成应力匹配，增强热电模块20(图16所示)的结构的稳定性。
请再参阅图1，在某些实施方式中，第五阻挡层102n的厚度的取值范围为[0.01mm,0.1mm]，例如，第五阻挡层102n的厚度可为0.01mm、0.02mm、0.025mm、0.031mm、0.05mm、0.06mm、0.07mm、0.08mm、0.09mm或0.1mm等。第五阻挡层102n可以以粉末、薄膜或箔片的形式存在。第五阻挡层102n的材质可以是金属Au、Ag、Ta、Cu、Ti、TiN、TiW、Ni或Mo中的一种或多种，例如，第五阻挡层102n的材料可以是Au、Cu、Ti或TiW等，第五阻挡层102n的材料还可以是Au、Ag组成的合金，Cu、Ti、Ni组成的合金，Au、Ta、Cu、Ni及Mo组成的合金等。第十阻挡层112a厚度的取值范围为[0.01mm,0.1mm]，例如，第十阻挡层112a的厚度可为0.01mm、0.02mm、0.025mm、0.031mm、0.05mm、0.06mm、0.07mm、0.08mm、0.09mm或0.1mm等。第十阻挡层112a可以以粉末、薄膜或箔片的形式存在。第十阻挡层112a的材质可以是金属Au、Ag、Ta、Cu、Ti、TiN、TiW、Ni或Mo中的一种或多种，例如，第十阻挡层112a的材料可以是Au、Cu、Ti或TiW等，第十阻挡层112a的材料还可以是Au、Ag组成的合金，Cu、Ti、Ni组成的合金，Au、Ta、Cu、Ni及Mo组成的合金等。在本发明的具体实施例中，同一热电单元10中的第五阻挡层102n与第十阻挡层112a使用的材质是相同的。可以理解，图1所示，同一热电单元10中的第五阻挡层102n与第十阻挡层112a在热电单元10中所处的位置相邻，且第五阻挡层102n与第十阻挡层112a接触的是同一n型高温热电腿101n，因此，采用相同的材质制作第五阻挡层102n与第十阻挡层112a一方面可以方便材质的选择，另一方面在制造热电单元10时可以形成应力匹配，增强热电单元10的结构的稳定性。
请再参阅图1，在某些实施方式中，第六阻挡层104n的厚度的取值范围为[0.01mm,0.1mm]，例如，第六阻挡层104n的厚度可为0.01mm、0.02mm、0.025mm、0.031mm、0.05mm、0.06mm、0.07mm、0.08mm、0.09mm或0.1mm等。第六阻挡层104n可以以粉末、薄膜或箔片的形式存在。第六阻挡层104n的材质可以是金属Au、Ag、Ta、Cu、Ti、TiN、TiW、Ni或Mo中的一种或多种，例如，第六阻挡层104n的材料可以是Au、Cu、Ti或TiW等，第六阻挡层104n的材料还可以是Au、Ag组成的合金，Cu、Ti、Ni组成的合金，Au、Ta、Cu、Ni及Mo组成的合金等。第七阻挡层106n厚度的取值范围为[0.01mm,0.1mm]，例如，第七阻挡层106n的厚度可为0.01mm、0.02mm、0.025mm、0.031mm、0.05mm、0.06mm、0.07mm、0.08mm、0.09mm或0.1mm等。第七阻挡层106n可以以粉末、薄膜或箔片的形式存在。第七阻挡层106n的材质可以是金属Au、Ag、Ta、Cu、Ti、TiN、TiW、Ni或Mo中的一种或多种，例如，第七阻挡层106n的材料可以是Au、Cu、Ti或TiW等，第七阻挡层106n的材料还可以是Au、Ag组成的合金，Cu、Ti、Ni组成的合金，Au、Ta、Cu、Ni 及Mo组成的合金等。在本发明的具体实施例中，同一热电单元10中的第六阻挡层104n与第七阻挡层106n使用的材质是相同的。可以理解，图1所示，同一热电单元10中的第六阻挡层104n与第七阻挡层106n接触的是同一n型中温热电腿105n，因此，采用相同的材质制作第六阻挡层104n与第七阻挡层106n可以方便材质的选择。
请再参阅图1，在某些实施方式中，第八阻挡层108n的厚度的取值范围为[0.01mm,0.1mm]，例如，第八阻挡层108n的厚度可为0.01mm、0.02mm、0.025mm、0.031mm、0.05mm、0.06mm、0.07mm、0.08mm、0.09mm或0.1mm等。第八阻挡层108n可以以粉末、薄膜或箔片的形式存在。第八阻挡层108n的材质可以是金属Au、Ag、Ta、Cu、Ti、TiN、TiW、Ni或Mo中的一种或多种，例如，第八阻挡层108n的材料可以是Au、Cu、Ti或TiW等，第八阻挡层108n的材料还可以是Au、Ag组成的合金，Cu、Ti、Ni组成的合金，Au、Ta、Cu、Ni及Mo组成的合金等。第十一阻挡层110b厚度的取值范围为[0.01mm,0.1mm]，例如，第十一阻挡层110b的厚度可为0.01mm、0.02mm、0.025mm、0.031mm、0.05mm、0.06mm、0.07mm、0.08mm、0.09mm或0.1mm等。第十一阻挡层110b可以以粉末、薄膜或箔片的形式存在。第十一阻挡层110b的材质可以是金属Au、Ag、Ta、Cu、Ti、TiN、TiW、Ni或Mo中的一种或多种，例如，第十一阻挡层110b的材料可以是Au、Cu、Ti或TiW等，第十一阻挡层110b的材料还可以是Au、Ag组成的合金，Cu、Ti、Ni组成的合金，Au、Ta、Cu、Ni及Mo组成的合金等。在本发明的具体实施例中，相邻的两个热电单元10中的第八阻挡层108n与第十一阻挡层110b使用的材质是相同的。可以理解，图1所示，相邻的两个热电单元10中的第八阻挡层108n与第十一阻挡层110b所处的位置相邻，且第八阻挡层108n与第十一阻挡层110b接触的是同一n型低温热电腿109n，因此，采用相同的材质制作第八阻挡层108n与第十一阻挡层110b一方面可以方便材质的选择，另一方面在制造热电模块20时可以形成应力匹配，增强热电模块20(图16所示)的结构的稳定性。
请再参阅图1，在某些实施方式中，第一阻挡层102p、第二阻挡层104p、第三阻挡层106p、第四阻挡层108p、第五阻挡层102n、第六阻挡层104n、第七阻挡层106n、第八阻挡层108n、第九阻挡层110a、第十阻挡层112a、第十一阻挡层110b和第十二阻挡层112b使用的材质可以均相同，从而方便阻挡层材质的选择，进一步可简化高性能热电器件1的制造。
请再参阅图1，在某些实施方式中，第一阻挡层102p的厚度可根据高性能热电器件1的实际工作环境进行调节。第二阻挡层104p的厚度可根据高性能热电器件1的实际工作环境进行调节。第三阻挡层106p的厚度可根据高性能热电器件1的实际工作环境进行调节。 第四阻挡层108p的厚度可根据高性能热电器件1的实际工作环境进行调节。第五阻挡层102n的厚度可根据高性能热电器件1的实际工作环境进行调节。第六阻挡层104n的厚度可根据高性能热电器件1的实际工作环境进行调节。第七阻挡层106n的厚度可根据高性能热电器件1的实际工作环境进行调节。第八阻挡层108n的厚度可根据高性能热电器件1的实际工作环境进行调节。第九阻挡层110a的厚度可根据高性能热电器件1的实际工作环境进行调节。第十阻挡层112a的厚度可根据高性能热电器件1的实际工作环境进行调节。第十一阻挡层110b的厚度可根据高性能热电器件1的实际工作环境进行调节。第十二阻挡层112b的厚度可根据高性能热电器件1的实际工作环境进行调节。
请再参阅图1，在某些实施方式中，第一缓冲应力层103p的厚度的取值范围为[0.01mm,0.1mm]，例如，第一缓冲应力层103p的厚度可为0.01mm、0.02mm、0.025mm、0.031mm、0.05mm、0.06mm、0.07mm、0.08mm、0.09mm或0.1mm等。第一缓冲应力层103p可以以粉末、薄膜或箔片的形式存在。第一缓冲应力层103p的材质可以是金属Cu、Pt、Ni或Cu-Mo合金的一种或多种，例如，第一缓冲应力层103p的材质可以是Cu、Pt、Ni等，第一缓冲应力层103p的材质还可以是Cu、pt组成的合金，Cu、Ni组成的合金，Cu、Pt、Ni组成的合金以及Cu-Mo合金等。第二缓冲应力层107p的厚度的取值范围为[0.01mm,0.1mm]，例如，第二缓冲应力层107p的厚度可为0.01mm、0.02mm、0.025mm、0.031mm、0.05mm、0.06mm、0.07mm、0.08mm、0.09mm或0.1mm等。第二缓冲应力层107p可以以粉末、薄膜或箔片的形式存在。第二缓冲应力层107p的材质可以是金属Cu、Pt、Ni或Cu-Mo合金的一种或多种，例如，第二缓冲应力层107p的材质可以是Cu、Pt、Ni等，第二缓冲应力层107p的材质还可以是Cu、pt组成的合金，Cu、Ni组成的合金，Cu、Pt、Ni组成的合金以及Cu-Mo合金等。第五缓冲应力层111a的厚度的取值范围为[0.01mm,0.1mm]，例如，第五缓冲应力层111a的厚度可为0.01mm、0.02mm、0.025mm、0.031mm、0.05mm、0.06mm、0.07mm、0.08mm、0.09mm或0.1mm等。第五缓冲应力层111a可以以粉末、薄膜或箔片的形式存在。第五缓冲应力层111a的材质可以是金属Cu、Pt、Ni或Cu-Mo合金的一种或多种，例如，第五缓冲应力层111a的材质可以是Cu、Pt、Ni等，第五缓冲应力层111a的材质还可以是Cu、pt组成的合金，Cu、Ni组成的合金，Cu、Pt、Ni组成的合金以及Cu-Mo合金等。第六缓冲应力层111b的厚度的取值范围为[0.01mm,0.1mm]，例如，第六缓冲应力层111b的厚度可为0.01mm、0.02mm、0.025mm、0.031mm、0.05mm、0.06mm、0.07mm、0.08mm、0.09mm或0.1mm等。第六缓冲应力层111b可以以粉末、薄膜或箔片的形式存在。第六缓冲应力层111b的材质可以是金属Cu、Pt、Ni或Cu-Mo合金的一种或多种，例如，第六缓冲应力层111b的材质可以是Cu、Pt、 Ni等，第六缓冲应力层111b的材质还可以是Cu、pt组成的合金，Cu、Ni组成的合金，Cu、Pt、Ni组成的合金以及Cu-Mo合金等。在本发明的具体实施例中，第一缓冲应力层103p、第二缓冲应力层107p、第五缓冲应力层111a和第六缓冲应力层111b使用的材质是相同的。
可以理解，图1所示，同一热电单元10中的第一缓冲应力层103p与第五缓冲应力层111a所处位置相邻，因此，采用相同的材质制作第一缓冲应力层103p与第五缓冲应力层111a一方面可以方便材质的选择，另一方面在制造热电单元10时可以形成应力匹配，增强热电单元10的结构的稳定性。同样地，相邻两个热电模块20中的第二缓冲应力层107p和第六缓冲应力层111b所处位置相邻，因此，采用相同的材质制作第二缓冲应力层107p和第六缓冲应力层111b一方面可以方便材质的选择，另一方面在制造热电模块20时可以形成应力匹配，增强热电模块20(图16所示)的结构的稳定性。而第一缓冲应力层103p与第二缓冲应力层107p为同一热电单元10中的p型热电腿10p的组成部分，采用相同的材质制作第一缓冲应力层103p与第二缓冲应力层107p可方便材质的选择，简化高性能热电器件1的制造。第五缓冲应力层111a可连接同一热电单元10中的p型高温热电腿101p和n型高温热电腿101n，第六缓冲应力层111b可连接相邻热电单元10中的p型低温热电腿109p和n型低温热电腿109n，第五缓冲应力层111a与第六缓冲应力层111b所起作用类似，采用相同的材质制作第五缓冲应力层111a与第六缓冲应力层111b也可方便材质的选择，简化高性能热电器件1的制造。
请再参阅图1，在某些实施方式中，第三缓冲应力层103n的厚度的取值范围为[0.01mm,0.1mm]，例如，第三缓冲应力层103n的厚度可为0.01mm、0.02mm、0.025mm、0.031mm、0.05mm、0.06mm、0.07mm、0.08mm、0.09mm或0.1mm等。第三缓冲应力层103n可以以粉末、薄膜或箔片的形式存在。第三缓冲应力层103n的材质可以是金属Cu、Pt、氧化钼MoOx、Cu-Mo合金的一种或多种，例如，第三缓冲应力层103n的材质可以是Cu、Pt、Ni等，第一缓冲应力层103p的材质还可以是Cu、pt组成的合金，Cu、Ni组成的合金，Cu、Pt、Ni组成的合金、氧化钼MoOx、Cu-Mo合金等。第四缓冲应力层107n的厚度的取值范围为[0.01mm,0.1mm]，例如，第四缓冲应力层107n的厚度可为0.01mm、0.02mm、0.025mm、0.031mm、0.05mm、0.06mm、0.07mm、0.08mm、0.09mm或0.1mm等。第四缓冲应力层107n可以以粉末、薄膜或箔片的形式存在。第四缓冲应力层107n的材质可以是金属Cu、Pt、Ni或Cu-Mo合金的一种或多种，例如，第四缓冲应力层107n的材质可以是Cu、Pt、Ni等，第二缓冲应力层107p的材质还可以是Cu、pt组成的合金，Cu、Ni组成的合金，Cu、Pt、Ni组成的合金、氧化钼MoOx、Cu-Mo合金等。可以理解，第三缓冲应力 层103n和第四缓冲应力层107n为同一热电单元10中的n型热电腿10n的组成部分，采用相同的材质制作第三缓冲应力层103n和第四缓冲应力层107n可方便材质的选择，简化高性能热电器件1的制造。
请再参阅图1，在某些实施方式中，第一缓冲应力层103p、第二缓冲应力层107p、第三缓冲应力层103n、第四缓冲应力层107n、第五缓冲应力层111a和第六缓冲应力层111b均可采用相同的材质制造，如此，可方便缓冲应力层材质的选择，进一步可简化高性能热电器件1的制造。
请再参阅图1，在某些实施方式中，第一缓冲应力层103p的厚度可根据高性能热电器件1的实际工作环境进行调节。第二缓冲应力层107p的厚度可根据高性能热电器件1的实际工作环境进行调节。第三缓冲应力层103n的厚度可根据高性能热电器件1的实际工作环境进行调节。第四缓冲应力层107n的厚度可根据高性能热电器件1的实际工作环境进行调节。第五缓冲应力层111a的厚度可根据高性能热电器件1的实际工作环境进行调节。第六缓冲应力层111b的厚度可根据高性能热电器件1的实际工作环境进行调节。
请再参阅图1，在某些实施方式中，内封装201的材质可以是碳纤维或石墨-环氧树脂导热复合材料(Graphite Epoxy Composite，GEC)。外封装202的材质可以是FeNi可伐合金。
请一并参阅图1和图16，在某些实施方式中，封装结构也可为单层封装层结构。单层封装层设置在热电模块20的外表面。第一电学输出导线115p穿过单层封装层接入第一电学输出电极114p，第二电学输出导线115n穿过单层封装层接入第二电学输出电极114n。热电模块20的外表面与单层封装层之间设置有绝缘夹层113。其中，绝缘夹层113仅设置在热电模块20的外表面的左右两侧(图1所示)。其中，单层封装层可以是内封装201，此时单层装封层的材质可以是碳纤维或石墨-环氧树脂导热复合材料，第一电学输出导线115p穿过内封装201接入第一电学输出电极114p，第二电学输出导线115n穿过内封装201接入第二电学输出电极114n，热电模块20的外表面与内封装201之间设置有绝缘夹层113。单层封装层也可以是外封装202，此时单层装封层的材质可以是FeNi可伐合金，第一电学输出导线115p穿过外封装202接入第一电学输出电极114p，第二电学输出导线115n穿过外封装202接入第二电学输出电极114n。热电模块20的外表面与外封装202之间设置有绝缘夹层113。
请再参阅图1，在某些实施方式中，封装结构为双层时，内封装201的厚度可根据高性能热电器件1的实际工作环境进行调节，外封装202的厚度也可根据高性能热电器件1的实际工作环境进行调节。封装结构为单层封装层时，单层封装层的厚度也可根据高性能 热电器件1的实际工作环境进行调节。
请再参阅图1，在某些实施方式中，绝缘夹层113中的声子散射层113a(图11所示)的厚度的取值范围为[1nm，100nm]，例如，声子散射层113a的厚度可为1nm、15nm、30nm、41.3nm、57nm、66nm、70nm、85nm、93nm、98nm或100nm等。声子散射层113a的层数的取值范围为[10,10000]，例如声子散射层113a的层数可为10层、68层、100层、827层、1000层、2500层、4000层、5100层、6015层、7777层、8000层、9000层或10000层等。声子散射层113a的材质可以是SiO2、Al2O3、AlN、MgO、TiO2、Si3N4或SiC中的一种或多种，例如，声子散射层113a的材质可以是SiO2、Al2O3、Si3N4或TiO2，声子散射层113a的材质也可以是SiO2、Al2O3的混合物，AlN、MgO、Si3N4和SiC的混合物，SiO2、Al2O3、AlN、MgO、TiO2、Si3N4和SiC的混合物等。由于声子散射层113a的层数可为多层，在本发明的具体实施例中，当第一层的声子散射层113a的材质确定后，剩余层数的声子散射层113a的材质应与第一层的声子散射层113a的材质相同，如此，以便声子散射层113a材质的选择，以及绝缘夹层113的制造。
请再参阅图1，在某些实施方式中，绝缘夹层113中的负热膨胀缓冲层113b(图11所示)的厚度的取值范围为[1nm，100nm]，例如，负热膨胀缓冲层113b的厚度可为1nm、15nm、30nm、41.3nm、57nm、66nm、70nm、85nm、93nm、98nm或100nm等。负热膨胀缓冲层113b的层数的取值范围为[10,10000]，例如负热膨胀缓冲层113b的层数可为10层、68层、100层、827层、1000层、2500层、4000层、5100层、6015层、7777层、8000层、9000层或10000层等。负热膨胀缓冲层113b的材质可以是SiO2、Al2O3、AlN、MgO、TiO2、Si3N4或SiC中的一种或多种，例如，负热膨胀缓冲层113b的材质可以是SiO2、Al2O3、Si3N4或TiO2，负热膨胀缓冲层113b的材质也可以是SiO2、Al2O3的混合物，AlN、MgO、Si3N4和SiC的混合物，SiO2、Al2O3、AlN、MgO、TiO2、Si3N4和SiC的混合物等。由于负热膨胀缓冲层113b的层数可为多层，在本发明的具体实施例中，当第一层的负热膨胀缓冲层113b的材质确定后，剩余层数的负热膨胀缓冲层113b的材质应与第一层的负热膨胀缓冲层113b的材质相同，如此，以便负热膨胀缓冲层113b材质的选择，以及绝缘夹层113的制造。
请再参阅图1，在某些实施方式中，第一电学输出电极114p的材质可以是金属Cu、Au、Ag、Mo、W、Fe、Pd、Pt、Al、Ni或Ti。第二电学输出电极114n的材质可以是金属Cu、Au、Ag、Mo、W、Fe、Pd、Pt、Al、Ni或Ti。在本发明的具体实施例中，第一电学输出电极114p的材质和第二电学输出电极114n的材质相同，如此，方便输出电极的材质的选择以及高性能热电器件1的制造。
请再参阅图1，在某些实施方式中，第一电学输出导线115p的材质与第二电学输出导线115n的材质相同，均为聚氯乙烯绝缘铜芯导线。
请一并参阅图8至图20，本发明还提供了一种高性能热电器件1的超快速制备方法。本发明实施方式的高性能热电器件1的超快速制备方法包括：
1)制备热电单元10
ST01：分别按照p型高温热电腿101p、p型中温热电腿105p、p型低温热电腿109p、n型高温热电腿101n、n型中温热电腿105n、n型低温热电腿109n中各元素化学计量比称量单质粉体以得到热电材料粉体。分别称量第一阻挡层102p、第二阻挡层104p、第三阻挡层106p、第四阻挡层108p、第五阻挡层102n、第六阻挡层104n、第七阻挡层106n、第八阻挡层108n、第九阻挡层110a、第十阻挡层112a各层材料粉体以得到阻挡层粉体。分别称量第一缓冲应力层103p、第二缓冲应力层107p、第三缓冲应力层103n、第四缓冲应力层107n、第五缓冲应力层111a各层材料粉体以得到缓冲应力层粉体。
具体地，例如，分别采用p型CoSb3基材料为p型高温热电腿101p材料、p型PbTe基材料为p型中温热电腿105p材料、p型Bi2Te3基材料为p型低温热电腿109p材料、n型CoSb3基材料为n型高温热电腿101n材料、n型PbTe基材料为n型中温热电腿105n材料、n型Bi2Te3基材料为n型低温热电腿109n材料，将上述各材料按照元素化学计量比称量单质粉体以获得热电材料粉体。将金属Mo作为第一阻挡层102p材料、将金属Cu作为第一缓冲应力层103p材料、将金属Mo作为第二阻挡层104p材料、将金属Mo作为第三阻挡层106p材料、将金属Cu作为第二缓冲应力层107p材料、将TiN作为第四阻挡层108p材料、将金属Mo作为第五阻挡层102n材料、将MoOx作为第三缓冲应力层103n材料、将金属Mo作为第六阻挡层104n材料、将金属Mo作为第七阻挡层106n材料、将MoOx作为第四缓冲应力层107n材料、将TiN作为第八阻挡层108n材料、将金属Mo作为第九阻挡层110a材料、将金属Cu作为第五缓冲应力层111a材料、将金属Mo作为第十阻挡层112a材料，分别称量各层阻挡层和缓冲应力层的材料粉体以得到阻挡层粉体和缓冲应力层粉体。
ST02：按照热电材料层、阻挡层、缓冲应力层的顺序将热电材料粉体、阻挡层粉体、缓冲应力层粉体依次铺设于模具302、上压头301与下压头306围成的空间中，并用第一隔板303、中间隔板305、第二隔板304将热电材料粉体中的p型热电腿10p各层材料粉体与n型热电腿10n各层材料粉体分离，并进行放电等离子体烧结形成热电块体(图9及图10所示)。
其中，上压头301和所述下压头306的材质均为石墨。模具302的材质包括石墨、合金、Al2O3基陶瓷、AlN基陶瓷、Si3N4基陶瓷或SiC基陶瓷中的一种或多种。例如，模具 302的材质可以是石墨、Al2O3基陶瓷、SiC基陶瓷等，模具302的材质还可以是石墨、合金的混合物，Al2O3基陶瓷、AlN基陶瓷、Si3N4基陶瓷的混合物等。第一隔板303、中间隔板305、第二隔板304的材料均可为石墨或陶瓷。在本发明的具体实施例中，第一隔板303、中间隔板305、所述第二隔板304的材质相同。
具体地，例如，以石墨作为上压头301、所述下压头306、第一隔板303、中间隔板305、第二隔板304材质，按照热电材料层、阻挡层、缓冲应力层的顺序将热电材料粉体、阻挡层粉体、缓冲应力层粉体依次铺设于模具302、上压头301与下压头306围成的空间中，并用第一隔板303、中间隔板305、第二隔板304将热电材料粉体中的p型热电腿10p各层材料粉体与n型热电腿10n各层材料粉体分离，且进行放电等离子体烧结形成热电块体。
ST03：切割热电块体形成热电单元10，并采用化学气相沉积法逐层交替制备声子散射层113a和负热膨胀缓冲层113b以形成绝缘夹层113，利用所述绝缘夹层113对热电单元10进行镶嵌固定(图11和12所示)。
具体地，例如，以SiO2作为声子散射层113a的材质，以ZrW2O8作为负热膨胀缓冲层113b的材质，采用化学气相沉积法逐层交替制备SiO2材质的声子散射层113a与ZrW2O8材质的负热膨胀缓冲层113b形成绝缘夹层113；并对热电单元10进行绝缘夹层113镶嵌固定，完成热电单元10的制备。
2)组配热电模块20
ST04：在相邻热电单元10的n型低温热电腿109n的凸起截面与p型低温热电腿109p的凸起截面之间电镀沉积第十一阻挡层110b、第六缓冲应力层111b和第十二阻挡层112b，交替堆叠热电单元10以得到热电模块20(图13至图16所示)；
具体地，例如，以TiN作为第十一阻挡层110b的材质、以金属Cu作为为第六缓冲应力层111b的材质，以TiN作为第十二阻挡层112b的材质，在相邻热电单元10的n型低温热电腿109n凸起截面与p型低温热电腿109p凸起截面之间电镀沉积TiN作为第十一阻挡层110b、金属Cu作为第六缓冲应力层111b、TiN作为第十二阻挡层112b，交替堆叠热电单元10得到热电模块20。
ST05：分别电镀制备热电模块20的第一电学输出电极114p和第二电学输出电极114n，并分别接入第一电学输出导线115p和第二电学输出导线115n(图17和图18所示)。
具体地，例如，以金属Cu作为第一电学输出电极114p和第二电学输出电极114n的材质，以聚氯乙烯绝缘铜芯导线作为第一电学输出导线115p与第二电学输出导线115n。在要组配的两个热电单元10中的一个p型低温热电腿109p上电镀金属Cu以形成第一电学输出电极114p，并以焊接的方式接入第一电学输出导线115p。在要组配的两个热电单元10 中的一个n型低温热电腿109n上电镀金属Cu以形成第二电学输出电极114n，并以焊接的方式接入第二电学输出导线115n，完成热电模块20的组配。
此外，还可以采用等离子体喷涂、蒸发或溅射方法制备第一电学输出电极114p、第二电学输出电极114n。
3)包覆内封装201与制备外封装202
ST06：采用高温密封胶将碳纤维包覆于热电模块20的外表面以形成内封装201；在内封装201的外表面固定包覆外封装202材料FeNi可伐合金，外封装202材料的接口处用密封胶固定以形成外封装202(图19和图20所示)。
当然，在封装结构为单层封装层时，仅需采用高温密封胶将碳纤维包覆于所述热电模块20的外表面以形成单层封装层，或者，仅需在热电模块20的外表面固定包覆材料FeNi可伐合金，FeNi可伐合金的接口处用密封胶固定以形成单层封装层。
本发明实施方式的高性能热电器件1的超快速制备方法采用热压工艺结合模具302与隔板一次成型制备热电单元10，实现高温段热电材料、中温段热电材料、低温段热电材料同阻挡层与缓冲应力层的直接烧结，减小了元素间相互扩散，增强了分段热电器件层间结合强度与热匹配度，降低接触电阻。
在本说明书的描述中，参考术语“一个实施例”、“一些实施例”、“示例”、“具体示例”、或“一些示例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含于本发明的至少一个实施例或示例中。在本说明书中，对上述术语的示意性表述不必须针对的是相同的实施例或示例。而且，描述的具体特征、结构、材料或者特点可以在任一个或多个实施例或示例中以合适的方式结合。此外，在不相互矛盾的情况下，本领域的技术人员可以将本说明书中描述的不同实施例或示例以及不同实施例或示例的特征进行结合和组合。
尽管上面已经示出和描述了本发明的实施例，可以理解的是，上述实施例是示例性的，不能理解为对本发明的限制，本领域的普通技术人员在本发明的范围内可以对上述实施例进行变化、修改、替换和变型。

Claims (20)

  1. 一种高性能热电器件(1)，其特征在于，所述高性能热电器件(1)包括热电模块(20)，所述热电模块(20)由热电单元(10)和绝缘夹层(113)依次堆叠形成；所述热电单元(10)包括p型热电腿(10p)和n型热电腿(10n)；所述p型热电腿(10p)包括自上而下依次设置的p型高温热电腿(101p)、第一阻挡层(102p)、第一缓冲应力层(103p)、第二阻挡层(104p)、p型中温热电腿(105p)、第三阻挡层(106p)、第二缓冲应力层(107p)、第四阻挡层(108p)、p型低温热电腿(109p)；所述n型热电腿(10n)包括自上而下依次设置的n型高温热电腿(101n)、第五阻挡层(102n)、第三缓冲应力层(103n)、第六阻挡层(104n)、n型中温热电腿(105n)、第七阻挡层(106n)、第四缓冲应力层(107n)、第八阻挡层(108n)、n型低温热电腿(109n)；所述p型高温热电腿(101p)与所述n型高温热电腿(101n)通过第九阻挡层(110a)、第五缓冲应力层(111a)、第十阻挡层(112a)相连以形成所述热电单元(10)，相邻所述热电单元(10)的所述n型低温热电腿(109n)与所述p型低温热电腿(109p)通过第十一阻挡层(110b)、第六缓冲应力层(111b)、第十二阻挡层(112b)固定连接并采用所述绝缘夹层(113)镶嵌形成所述热电模块(20)；所述热电模块(20)底端两侧的所述p型低温热电腿(109p)、所述n型低温热电腿(109n)分别设有第一电学输出电极(114p)和第二电学输出电极(114n)，所述第一电学输出电极(114p)连接第一电学输出导线(115p)，所述第二电学输出电极(114n)连接第二电学输出导线(115n)。
  2. 根据权利要求1所述的高性能热电器件(1)，其特征在于，所述高性能热电器件(1)为方形结构.
  3. 根据权利要求1所述的高性能热电器件(1)，其特征在于，多个所述高性能热电器件(1)通过串联方式、并联方式或串并联方式结合。
  4. 根据权利要求1所述的高性能热电器件(1)，其特征在于，所述p型高温热电腿(101p)的材质包括p型SiGe基材料、p型CoSb3基材料、p型SnSe基材料、p型PbSe基材料、p型Cu2Se基材料、p型BiCuSeO基材料、p型Half-Heusler材料、p型Cu(In,Ga)Te2材料、p型FeSi2基材料、CrSi2、MnSi1.73、CoSi、p型Cu1.8S基材料或p型氧化物材料；
    所述p型中温热电腿(105p)的材质包括p型PbTe基材料、p型CoSb3基材料、p型Half-Heusler材料、p型Cu1.8S基材料或p型AgSbTe2基材料；
    所述p型低温热电腿(109p)的材质包括p型Bi2Te3基材料、p型Sb2Se3基材料或p型Sb2Te3基材料。
  5. 根据权利要求1所述的高性能热电器件(1)，其特征在于，所述n型高温热电腿(101n)的材质包括n型SiGe基材料、n型CoSb3基材料、n型SnSe基材料、n型SnTe基材料、n型Cu2Se基材料、n型Half-Heusler材料或n型氧化物材料；
    所述n型中温热电腿(105n)的材质包括n型PbTe基材料、n型PbS基材料、n型CoSb3基材料、n型Mg2Si基材料、n型Zn4Sb3基材料、n型InSb基材料、n型Half-Heusler材料、n型氧化物材料或n型AgSbTe2基材料；
    所述n型低温热电腿(109n)的材质包括n型Bi2Te3基材料、n型BiSb基材料、n型Zn4Sb3基材料、n型Mg3Sb2基材料、n型Bi2Se3基材料或n型Sb2Se3基材料。
  6. 根据权利要求1所述的高性能热电器件(1)，其特征在于，所述第一阻挡层(102p)、所述第二阻挡层(104p)、所述第三阻挡层(106p)、所述第四阻挡层(108p)、所述第五阻挡层(102n)、所述第六阻挡层(104n)、所述第七阻挡层(106n)、所述第八阻挡层(108n)、所述第九阻挡层(110a)、所述第十阻挡层(112a)、所述第十一阻挡层(110b)、所述第十二阻挡层(112b)的厚度的取值范围均为[0.01mm,0.1mm]。
  7. 根据权利要求1所述的高性能热电器件(1)，其特征在于，所述第一阻挡层(102p)、所述第二阻挡层(104p)、所述第三阻挡层(106p)、所述第四阻挡层(108p)、所述第五阻挡层(102n)、所述第六阻挡层(104n)、所述第七阻挡层(106n)、所述第八阻挡层(108n)、所述第九阻挡层(110a)、所述第十阻挡层(112a)、所述第十一阻挡层(110b)、所述第十二阻挡层(112b)均以粉末、薄膜或箔片的形式存在。
  8. 根据权利要求1所述的高性能热电器件(1)，其特征在于，所述第一阻挡层(102p)、所述第二阻挡层(104p)、所述第三阻挡层(106p)、所述第四阻挡层(108p)、所述第五阻挡层(102n)、所述第六阻挡层(104n)、所述第七阻挡层(106n)、所述第八阻挡层(108n)、所述第九阻挡层(110a)、所述第十阻挡层(112a)、所述第十一阻挡层(110b)、所述第十二阻挡层(112b)的材质均包括金、银、钽、铜、钛、氮化钛、钛钨、镍或钼中的一种或多种；
    所述第一阻挡层(102p)与所述第九阻挡层(110a)的材质相同；所述第二阻挡层(104p)与所述第三阻挡层(106p)的材质相同；所述第四阻挡层(108p)与所述第十二阻挡层(112b)的材质相同；所述第五阻挡层(102n)与所述第十阻挡层(112a)的材质相同；所述第六阻挡层(104n)与所述第七阻挡层(106n)的材质相同；所述第八阻挡层(108n)与所述第十一阻挡层(110b)的材质相同。
  9. 根据权利要求1所述的高性能热电器件(1)，其特征在于，所述第一缓冲应力层(103p)、所述第二缓冲应力层(107p)、所述第三缓冲应力层(103n)、所述第四缓冲应力层(107n)、所述第五缓冲应力层(111a)和所述第六缓冲应力层(111b)的厚度的取值范围均为[0.01mm,0.1mm]。
  10. 所述第一缓冲应力层(103p)、所述第二缓冲应力层(107p)、所述第三缓冲应力层(103n)、所述第四缓冲应力层(107n)、所述第五缓冲应力层(111a)和所述第六缓冲应力层(111b)均以粉末、薄膜或箔片的形式存在。
  11. 根据权利要求1所述的高性能热电器件(1)，其特征在于，根据权利要求1所述的高性能热电器件(1)，其特征在于，所述第一缓冲应力层(103p)、所述第二缓冲应力层(107p)、所述第五缓冲应力层(111a)和所述第六缓冲应力层(111b)的材质均包括铜、铂、镍、铜钼合金中的一种或多种，所述第一缓冲应力层(103p)、所述第二缓冲应力层(107p)、所述第五缓冲应力层(111a)和所述第六缓冲应力层(111b)的材质相同；
    所述第三缓冲应力层(103n)和所述第四缓冲应力层(107n)的材料均包括氧化钼、铜、铂、镍、铜钼合金中的一种或多种，所述第三缓冲应力层(103n)和所述第四缓冲应力层(107n)的材质相同。
  12. 根据权利要求1所述的高性能热电器件(1)，其特征在于，所述第一电学输出电极(114p)与所述第二电学输出电极(114n)的材质均包括金、钯、铂、铝、铜、镍、钛中的一种或多种，所述第一电学输出电极(114p)与所述第二电学输出电极(114n)的材质相同；
    所述第一电学输出导线(115p)与所述第二电学输出导线(115n)的材质均为聚氯乙烯绝缘铜芯导线。
  13. 根据权利要求1所述的高性能热电器件(1)，其特征在于，所述绝缘夹层(113)包括声子散射层(113a)和负热膨胀缓冲层(113b)，所述声子散射层(113a)与所述负热膨胀缓冲层(113b)依次层叠设置，所述绝缘夹层(113)镶嵌固定于相邻的所述p型热电腿(10p)与所述n型热电腿(10n)之间。
  14. 根据权利要求1所述的高性能热电器件(1)，其特征在于，所述高性能热电器件(1)还包括封装结构，所述封装结构包括两层，分别为内封装(201)和外封装(202)，所述热电模 块(20)的外表面设置有所述内封装(201)，所述内封装(201)的外表面设置有所述外封装(202)；所述第一电学输出导线(115p)穿过所述外封装(202)与所述内封装(201)接入所述第一电学输出电极(114p)，所述第二电学输出导线(115n)穿过所述外封装(202)与所述内封装(201)接入所述第二电学输出电极(114n)；或
    所述封装结构包括单层封装层，所述单层封装层设置在所述热电模块(20)的外表面，所述第一电学输出导线(115p)穿过所述单层封装层接入所述第一电学输出电极(114p)，所述第二电学输出导线(115n)穿过所述单层封装层接入所述第二电学输出电极(114n)。
  15. 根据权利要求14所述的高性能热电器件(1)，其特征在于，所述绝缘夹层(113)包括声子散射层(113a)和负热膨胀缓冲层(113b)，所述声子散射层(113a)与所述负热膨胀缓冲层(113b)依次层叠设置，所述绝缘夹层(113)左右相对设置且位于所述热电模块(20)与所述内封装(201)之间；或
    所述绝缘夹层(113)左右相对设置且位于所述热电模块(20)与所述单层封装层之间。
  16. 根据权利要求13或15所述的高性能热电器件(1)，其特征在于，所述声子散射层(113a)为纳米绝缘颗粒层，所述声子散射层(113a)的厚度的取值范围为[1nm,100nm]，所述声子散射层(113a)的层数的取值范围为[10,10000]，所述声子散射层(113a)的材料包括SiO2、Al2O3、AlN、MgO、TiO2、Si3N4或SiC中的一种或多种；
    所述负热膨胀缓冲层(113b)的厚度的取值范围为[1nm,100nm]，所述负热膨胀缓冲层(113b)的层数的取值范围为[10,10000]，所述负热膨胀缓冲层(113b)的材料包括BaTiO3、PbTiO3、LaCrO3、ZrW2O8、ZrV2O7或HfW2O8中的一种或多种。
  17. 根据权利要求14所述的高性能热电器件(1)，其特征在于，所述封装结构包括两层时，所述内封装(201)的材质包括碳纤维或石墨-环氧树脂导热复合材料，所述外封装(202)的材质包括FeNi可伐合金。
  18. 一种高性能热电器件(1)的超快速制备方法，其特征在于，所述高性能热电器件(1)的超快速制备方法包括：
    分别按照p型高温热电腿(101p)、p型中温热电腿(105p)、p型低温热电腿(109p)、n型高温热电腿(101n)、n型中温热电腿(105n)、n型低温热电腿(109n)中各元素化学计量比称量单质粉体以得到热电材料粉体，分别称量第一阻挡层(102p)、第二阻挡层(104p)、第三阻挡 层(106p)、第四阻挡层(108p)、第五阻挡层(102n)、第六阻挡层(104n)、第七阻挡层(106n)、第八阻挡层(108n)、第九阻挡层(110a)、第十阻挡层(112a)各层材料粉体以得到阻挡层粉体；分别称量第一缓冲应力层(103p)、第二缓冲应力层(107p)、第三缓冲应力层(103n)、第四缓冲应力层(107n)、第五缓冲应力层(111a)各层材料粉体以得到缓冲应力层粉体；
    按照热电材料层、阻挡层、缓冲应力层的顺序将所述热电材料粉体、所述阻挡层粉体、所述缓冲应力层粉体依次铺设于模具(302)、上压头(301)与下压头(306)围成的空间中，并用第一隔板(303)、中间隔板(305)、第二隔板(304)将所述热电材料粉体中的p型热电腿(10p)各层材料粉体与n型热电腿(10n)各层材料粉体分离，并进行放电等离子体烧结形成热电块体；
    切割所述热电块体形成热电单元(10)；
    采用化学气相沉积法逐层交替制备声子散射层(113a)和负热膨胀缓冲层(113b)以形成绝缘夹层(113)，利用所述绝缘夹层(113)对所述热电单元(10)进行镶嵌固定；
    在相邻所述热电单元(10)的所述n型低温热电腿(109n)的凸起截面与所述p型低温热电腿(109p)的凸起截面之间电镀沉积第十一阻挡层(110b)、第六缓冲应力层(111b)和第十二阻挡层(112b)，交替堆叠热电单元(10)以得到热电模块(20)；
    分别电镀制备所述热电模块(20)的第一电学输出电极(114p)和第二电学输出电极(114n)，并分别接入第一电学输出导线(115p)和第二电学输出导线(115n)。
  19. 根据权利要求18所述的高性能热电器件(1)的超快速制备方法，其特征在于，所述高性能热电器件(1)的超快速制备方法还包括：
    采用高温密封胶将碳纤维包覆于所述热电模块(20)的外表面以形成内封装(201)；
    在所述内封装(201)的外表面固定包覆外封装(202)材料FeNi可伐合金，所述外封装(202)材料的接口处用密封胶固定以形成外封装(202)。
  20. 根据权利要求18所述的高性能热电器件(1)的超快速制备方法，其特征在于，所述上压头(301)和所述下压头(306)的材质均为石墨；
    所述模具(302)的材质包括石墨、合金、Al2O3基陶瓷、AlN基陶瓷、Si3N4基陶瓷或SiC基陶瓷中的一种或多种；
    所述第一隔板(303)、所述中间隔板(305)、所述第二隔板(304)的材料均包括石墨或陶瓷，所述第一隔板(303)、所述中间隔板(305)、所述第二隔板(304)的材质相同。
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