WO2019085267A1 - Tft基板及其制作方法 - Google Patents

Tft基板及其制作方法 Download PDF

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WO2019085267A1
WO2019085267A1 PCT/CN2018/071661 CN2018071661W WO2019085267A1 WO 2019085267 A1 WO2019085267 A1 WO 2019085267A1 CN 2018071661 W CN2018071661 W CN 2018071661W WO 2019085267 A1 WO2019085267 A1 WO 2019085267A1
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layer
insulating layer
gate
depositing
active layer
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PCT/CN2018/071661
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English (en)
French (fr)
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余赟
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武汉华星光电半导体显示技术有限公司
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Priority to US15/968,990 priority Critical patent/US20190140081A1/en
Publication of WO2019085267A1 publication Critical patent/WO2019085267A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays

Definitions

  • the present application relates to the field of display technologies, and in particular, to a TFT substrate and a method of fabricating the same.
  • OLED Organic Light-Emitting Diode
  • TFT thin film transistor
  • the present application provides a TFT substrate and a manufacturing method thereof to improve the bending resistance of the TFT substrate and improve the resolution and yield of the flexible OLED display device having the TFT substrate.
  • the present invention provides a method for fabricating a TFT substrate for fabricating a TFT substrate.
  • the manufacturing method includes the following steps:
  • the active layer is subjected to hydrogenation and activation treatment.
  • the gate layer is a three-layer structure of Ti/Al/Ti or Mo/Al/Mo.
  • the step of depositing a gate layer on the barrier layer comprises:
  • first Mo metal layer Depositing a first Mo metal layer on the barrier layer, the first Mo metal layer having a thickness of 30 to 50 nm;
  • the temperature of the hydrogenation and activation treatment is 330 to 370 ° C, and the time of the hydrogenation and activation treatment is 30 to 60 min.
  • the method comprises:
  • the flexible substrate is peeled from the substrate.
  • the step of forming an active layer on the gate insulating layer includes:
  • the amorphous silicon layer is processed by using excimer laser as a heat source to form the active layer.
  • the material of the gate insulating layer and the interlayer insulating layer is a stacked structure of silicon oxide or silicon nitride or silicon oxide and silicon nitride.
  • the barrier layer is a thermally conductive insulating layer.
  • a TFT substrate provided by the present application is applied to a flexible OLED display device, the TFT substrate comprising a flexible substrate, a barrier layer on the flexible substrate, a gate trace on the barrier layer, and a cover a gate insulating layer of the gate trace, an active layer on the gate insulating layer, and an interlayer insulating layer covering the active layer.
  • the TFT substrate further includes a via hole penetrating the interlayer insulating layer and a source and a drain on the via hole, and the source and the drain are electrically connected to the via hole through the via hole.
  • the active layer is not limited to the interlayer insulating layer and a source and a drain on the via hole, and the source and the drain are electrically connected to the via hole through the via hole.
  • the method for fabricating a TFT substrate sequentially prepares a blocking layer, a gate trace, a gate insulating layer, an active layer and an interlayer insulating layer on a flexible substrate, and the main material of the gate trace For Al, compared with the gate trace of the main material Mo, the thickness or width of the gate trace is reduced in the case of satisfying the gate trace impedance, thereby improving the resistance of the gate trace in the flexible display panel. Bend performance for high resolution display.
  • the temperature of the hydrogenation and activation process can be lowered while the hydrogenation and activation of the active layer are achieved, thereby reducing the influence of the hydrogenation and activation process temperature on the conductivity of the gate trace, and improving The performance of the TFT substrate.
  • FIG. 1 is a flow chart of a method for fabricating a TFT substrate according to an embodiment of the present application.
  • FIG. 2 is a flow chart of S100 in a method of fabricating a TFT substrate according to an embodiment of the present application.
  • FIG. 3 is a flowchart of S200 in a method for fabricating a TFT substrate according to an embodiment of the present application.
  • FIG. 4 is a flow chart of S300 in a method for fabricating a TFT substrate according to an embodiment of the present application.
  • FIG. 5 is a flowchart of S400 in a method for fabricating a TFT substrate according to an embodiment of the present application.
  • FIG. 6 is a flowchart of S500 in a method for fabricating a TFT substrate according to an embodiment of the present application.
  • FIG. 7 is a flowchart of S600 in a method for fabricating a TFT substrate according to an embodiment of the present application.
  • FIG. 8 is a flowchart of S800 in a method for fabricating a TFT substrate according to an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of a TFT substrate according to an embodiment of the present application.
  • FIG. 1 is a method for fabricating a TFT substrate provided by the present application.
  • the fabrication method can be used to fabricate a flexible TFT substrate for a flexible OLED display device.
  • the manufacturing method S10 includes the following steps.
  • a rigid substrate 100 is provided.
  • An organic material is coated on the rigid substrate 100 to form a flexible substrate 110.
  • the rigid substrate 100 may be a glass substrate.
  • Organic materials are deposited on a glass substrate using a chemical vapor deposition (CVD) method, including polycarbonate (PC), polyethylene terephthalate (PET), and polynaphthalene dicarboxylic acid. At least one of ethylene glycol ester (PEN), polyether sulfone resin (PES), and polyimide (PI).
  • the organic material comprises polyimide (PI).
  • a barrier layer 120 is deposited on the flexible substrate 110.
  • the material of the barrier layer 120 may be at least one of silicon oxide, silicon nitride, a high dielectric constant dielectric material, and an organic dielectric material, wherein the high dielectric constant dielectric material includes aluminum oxide and cerium oxide. , zirconia, etc.
  • the barrier layer 120 is deposited by plasma chemical vapor deposition (PECVD), magnetron sputtering or reactive sputtering, atomic layer deposition or spin coating techniques, and the like.
  • the barrier layer 120 has a thickness of 5 nm to 400 nm.
  • the barrier layer 120 is a silicon oxide (SiOx) layer, a silicon nitride (SiNx) layer, or a composite layer composed of a silicon oxide layer and a silicon nitride layer.
  • the barrier layer 120 is a thermally conductive insulating layer.
  • the material of the thermally conductive insulating layer is Al 2 O 3 .
  • thermally conductive insulating film is patterned to obtain a thermally conductive insulating layer.
  • the thermally conductive insulating layer is patterned by a yellow light and an etching process, and the size and shape of the thermally conductive insulating layer are preset sizes and shapes, and the predetermined size and shape are subsequent polysilicon to be fabricated.
  • the size and shape of the semiconductor layer is patterned by a yellow light and an etching process, and the size and shape of the thermally conductive insulating layer are preset sizes and shapes, and the predetermined size and shape are subsequent polysilicon to be fabricated.
  • the size and shape of the semiconductor layer is patterned by a yellow light and an etching process, and the size and shape of the thermally conductive insulating layer are preset sizes and shapes, and the predetermined size and shape are subsequent polysilicon to be fabricated.
  • a gate layer is deposited on the barrier layer 120, the gate layer is photolithographically and etched, and the gate layer is patterned to form a gate trace 130.
  • the main material of the gate trace 130 is Al.
  • a gate layer may be deposited on the barrier layer 120 by a physical vapor deposition (PVD) method.
  • PVD physical vapor deposition
  • the material of the gate layer is at least one of a metal, a conductive metal oxide or other conductive material.
  • the gate layer is a three-layer structure of Ti/Al/Ti or Mo/Al/Mo.
  • the step S300 of depositing a gate layer on the barrier layer 120 includes:
  • a metal molybdenum (Mo) conductive film having a thickness of 30 to 50 nm is deposited on the barrier layer 120 by magnetron sputtering.
  • the photoresist is spin-coated on the metal Mo conductive film, and is photolithographically and etched to form a first Mo metal layer.
  • the Al metal layer has a thickness of 100 to 120 nm.
  • a metal aluminum (Al) conductive film having a thickness of 100 to 120 nm is deposited on the first Mo metal layer by magnetron sputtering.
  • the photoresist is spin-coated on the metal aluminum conductive film, photolithographically and etched to form an Al metal layer, and the Al metal layer is on the first Mo metal layer.
  • the second Mo metal layer has a thickness of 30-50 nm.
  • a metal molybdenum (Mo) conductive film having a thickness of 30 to 50 nm is deposited on the Al metal layer by magnetron sputtering.
  • a photoresist is spin-coated on the metal Mo conductive film, and photolithographically and etched to form a second Mo metal layer.
  • the second Mo metal layer covers the Al metal layer.
  • a gate trace 130 of a three-layer structure of Mo/Al/Mo is formed on the barrier layer 120.
  • the process of forming the gate traces 130 of the three-layer structure of Ti/Al/Ti on the barrier layer 120 is the same as the above steps, and details are not described herein again.
  • Ti or Mo acts to protect Al.
  • the gate trace 130 whose main material is Mo metal
  • Al metal has lower resistivity and better flexibility.
  • the Mo metal is easily brittle, and the Mo metal resistance is larger than that of the Al metal.
  • the gate layer has a Mo metal thickness of 250 nm.
  • a gate layer is prepared using Ti/Al/Ti or Mo/Al/Mo, and the thickness of the Al metal layer is 100-120 nm to obtain the same impedance as Mo metal having a thickness of 250 nm.
  • the Al metal and the Mo metal have the same trace impedance, the thickness of the Al metal layer can be significantly reduced, or the Al metal line width can be made small to achieve a high resolution display.
  • the bending resistance of the gate trace 130 is improved, the problem of disconnection of the flexible TFT substrate during the bending process, peeling of the TFT device, and light leakage are prevented, the quality of the flexible TFT substrate is improved, and the service life of the flexible TFT substrate is prolonged.
  • a gate insulating layer 140 is deposited on the barrier layer 120.
  • the gate insulating layer 140 covers the gate traces 130.
  • the gate insulating layer 140 is deposited on the barrier layer 120 and the gate traces 130.
  • the deposition method may employ plasma chemical vapor deposition, magnetron sputtering or reactive sputtering, atomic layer deposition or spin coating techniques.
  • the gate insulating layer 140 may be deposited on the barrier layer 120 and the gate traces 130 using a chemical vapor deposition method.
  • the material of the gate insulating layer 140 is at least one of silicon oxide, silicon nitride, a high dielectric constant dielectric material, and an organic dielectric material, and has a thickness of 5 nm to 400 nm.
  • the material of the gate insulating layer 140 is a stacked structure of silicon oxide or silicon nitride or silicon oxide and silicon nitride.
  • an active layer 150 is formed on the gate insulating layer 140.
  • the exposed surface of the gate insulating layer 140 is plasma treated to enhance the adhesion of the surface of the gate insulating layer 140 before the active layer 150 is formed.
  • the problem of cracking or falling off of the interlayer insulating layer often occurs in a high-temperature process, and in the process of the present application, since the gate insulating layer 140 has been subjected to plasma before depositing the interlayer insulating layer.
  • the treatment enhances the adhesion, thereby enhancing the adhesion between the interlayer insulating layer and the gate insulating layer 140, and can effectively prevent the problem of cracking or falling off of the interlayer insulating layer after the high-temperature process, thereby improving the product yield.
  • the step S500 of forming the active layer 150 on the gate insulating layer 140 includes:
  • the amorphous silicon layer may have a thickness of 200 to 300 nm.
  • an amorphous silicon layer is converted into a polysilicon layer by Excimer Laser Annel (ELA) or Solid Phase Crystallization (SPC) method, and the polysilicon layer is patterned by photolithography and etching processes. A plurality of polysilicon islands are obtained to form the active layer 150.
  • the mobility of polycrystalline silicon after laser annealing is increased to meet the peripheral electric drive requirements.
  • an interlayer insulating layer 160 is deposited on the gate insulating layer 140.
  • the interlayer insulating layer 160 covers the active layer 150.
  • the material of the interlayer insulating layer 160 may be silicon oxide or silicon nitride or a stacked structure of silicon oxide and silicon nitride.
  • an interlayer insulating layer 160 is deposited on the gate insulating layer 140 by a chemical vapor deposition method, and the active layer 150 is coated on the interlayer insulating layer 160.
  • the upper and lower interfaces of the interlayer insulating layer 160 directly contact the gate insulating layer 140 and the interlayer insulating layer 160.
  • the temperature of the hydrogenation and activation treatment is 330-370 ° C, and the time of the hydrogenation and activation treatment is 30 ⁇ . 60min.
  • the interlayer insulating layer 160 and the H + in the gate insulating layer 140 are diffused into the polysilicon by the high temperature hydrogenation and activation process to compensate for the polysilicon. defect.
  • the gate insulating layer 140 and the interlayer insulating layer 160 cover the active layer 150 therebetween, so that the peripheral sides of the active layer 150 directly contact the gate insulating layer 140 and the interlayer insulating layer.
  • a gate insulating layer is conducive to the diffusion of H + up to 140 polycrystalline silicon, and the interlayer insulating layer 160 down to the diffusion of H + polysilicon, so as to enhance the effect of activation and hydrogenation of the active layer 150, reduced polysilicon
  • the structural defects improve the overall performance of the thin film transistor.
  • hydrogenation and activation of the active layer 150 by the gate insulating layer 140 and the interlayer insulating layer 160 generally require an effect of 450 ° C and 1 h.
  • the melting point of the Al metal is low, which is about 660 °C.
  • the Al metal undergoes oxidation or nitridation after being subjected to a high temperature to cause a change in film quality, which in turn causes the conductivity of the gate trace 130 to decrease.
  • the upper and lower interfaces of the active layer 150 directly contact the gate insulating layer 140 and the interlayer insulating layer 160 for hydrogen supplementation and activation processes, respectively, and have a good activation effect, so the process temperature can be lowered to 330-370 ° C. It does not affect the change of the film quality of the gate trace 130, and at the same time, the effect of hydrogenation activation can be achieved.
  • the gate traces 130 are disposed under the active layer 150 such that the gate traces 130 are farther away from the exposed surface, and the degree of oxidation or nitridation is small, which can reduce hydrogenation and activation treatment on the gate. The effect of the trace quality of the trace 130.
  • the gate insulating layer 140 and the interlayer insulating layer 160 may be a thermally conductive insulating layer such as an aluminum oxide layer or the like.
  • the thermally conductive insulating layer since the thermally conductive insulating layer has good insulating properties and thermal conductivity, the thermally conductive insulating layer can quickly absorb a large amount of heat and pass it to the amorphous silicon layer in contact with it during the hydrogenation and activation process.
  • the crystallization efficiency of the amorphous silicon is increased, so that the crystal grains of the polysilicon in the formed polysilicon layer are larger and the grain boundaries are less, so that the electrical properties of the active layer 150 are better, so that the corresponding TFT device carriers can be enhanced.
  • the mobility reduces the influence of the grain boundary on the leakage current and improves the electrical properties of the TFT.
  • a via hole is formed on the interlayer insulating layer 160.
  • the via hole penetrates through the interlayer insulating layer 160.
  • the first via 171 and the second via 172 are formed by patterning the interlayer insulating layer 160 by a photolithography and etching process, so that the first via 171 and the second via 172 are electrically connected to the active layer 150.
  • a source 181 and a drain 182 are deposited on the via, the source 181 and the drain 182 are electrically connected to the active layer 150 through the via, and finally The flexible substrate 110 is peeled off from the rigid substrate 100 to produce a flexible TFT substrate.
  • a metal layer is deposited on the first via 171 and the second via 172, and the metal layer is patterned by photolithography and etching processes to form a source 181 and a drain 182.
  • the source 181 and the drain 182 cover the first via 171 and the second via 172, respectively, and are electrically connected to the active layer 150 through the first via 171 and the second via 172.
  • the flexible substrate 110 is peeled off from the rigid substrate 100 to produce a flexible TFT substrate.
  • the gate layer 130 and the gate insulating layer 140 are first deposited, and the active layer 150 is formed on the gate insulating layer 140, and then the interlayer insulating layer 160 is deposited on the active layer 150.
  • the upper and lower interfaces of the source layer 150 directly contact the gate insulating layer 140 and the interlayer insulating layer 160, respectively, and then hydrogenate and activate the active layer 150, since the active layer 150 is covered by the gate insulating layer 140 and the interlayer insulating layer 160.
  • the encapsulation, hydrogenation, and activation processes cause H+ in the gate insulating layer 140 and the interlayer insulating layer 160 to diffuse from the peripheral side of the active layer 150 into the active layer 150, thereby increasing the activation effect of the active layer 150, thereby reducing Defects inside and on the surface of the active layer 150, thereby improving the performance of the TFT device.
  • the temperature of the hydrogenation and activation process can be lowered while the hydrogenation and activation of the active layer 150 is achieved, thereby reducing the conductivity of the hydrogenation and activation process temperature for the gate traces 130. Influence, improve the performance of the TFT substrate.
  • the present application also provides a TFT substrate 10 for preparing a flexible OLED display device.
  • the TFT substrate 10 is produced by the TFT substrate manufacturing method S10 described in any of the above embodiments.
  • the TFT substrate 10 includes a flexible substrate 110, a barrier layer 120 on the flexible substrate 110, a gate trace 130 on the barrier layer 120, and a gate covering the gate trace 130.
  • the main material of the gate trace 130 is Al.
  • the gate layer is a three-layer structure of Ti/Al/Ti or Mo/Al/Mo. In the three-layer structure, Ti or Mo acts to protect Al.
  • Al metal Compared with the gate trace 130 whose main material is Mo metal, Al metal has lower resistivity and better flexibility. When the Al metal and the Mo metal have the same trace impedance, the thickness of the Al metal layer can be significantly reduced, or the Al metal line width can be made small to achieve a high resolution display. Thereby, the bending resistance of the gate traces 130 is improved.
  • the TFT substrate 10 further includes vias 171, 172 penetrating the interlayer insulating layer 160 and a source 181 and a drain 182 on the vias 171, 172.
  • a source 181 and the drain 182 are electrically connected to the active layer 150 through the vias 171, 172.

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Abstract

一种TFT基板(10)及其制作方法，所述制作方法包括以下的步骤：提供基板(100)，在所述基板（100）上制备柔性衬底（110）（S100）；在所述柔性衬底（110）上沉积阻隔层（120）（S200）；在所述阻隔层（120）上沉积栅极层，刻蚀所述栅极层以形成栅极走线（130），所述栅极走线（130）的主要材质为Al（S300）；在所述阻隔层（120）上沉积栅极绝缘层（140），所述栅极绝缘层（140）覆盖所述栅极走线（130）（S400）；在所述栅极绝缘层（140）上形成有源层（150）（S500）；在所述栅极绝缘层（140）上沉积层间绝缘层（160），所述层间绝缘层（160）覆盖所述有源层（150）（S600）；对所述有源层（150）进行氢化和活化处理（S700）。

Description

TFT基板及其制作方法
本申请要求于2017年11月06日提交中国专利局、申请号为201711081722.4、申请名称为“TFT基板及其制作方法”的中国专利申请的优先权，上述在先申请的内容以引入的方式并入本文本中。
技术领域
本申请涉及显示技术领域，具体涉及一种TFT基板及其制作方法。
背景技术
随着显示技术的发展，有机发光二极管(Organic Light-Emitting Diode，OLED)由于其重量轻、自发光、广视角、驱动电压低、发光效率高功耗低、响应速度快等优点，应用范围越来越广泛，尤其是柔性OLED显示装置具有可弯折易携带的特点，成为显示技术领域研究和开发的主要领域。其中驱动OLED发光的柔性薄膜晶体管(Thin Film Transistor，TFT)是背板是关键技术之一。
如何提高TFT基板的抗弯折性能，以实现OLED显示装置高解析度、高良率是目前柔性OLED显示装置的主要研究方向之一。
发明内容
本申请提供了一种TFT基板及其制作方法，以提高TFT基板的抗弯折性能，提高具有该TFT基板的柔性OLED显示装置的解析度和良率。
本申请提供的一种TFT基板的制作方法，用以制作TFT基板，所述制作方法包括以下的步骤：
提供基板，在所述基板上制备柔性衬底；
在所述柔性衬底上沉积阻隔层；
在所述阻隔层上沉积栅极层，刻蚀所述栅极层以形成栅极走线，所述栅极走线的主要材质为Al；
在所述阻隔层上沉积栅极绝缘层，所述栅极绝缘层覆盖所述栅极走线；
在所述栅极绝缘层上形成有源层；
在所述栅极绝缘层上沉积层间绝缘层，所述层间绝缘层覆盖所述有源层；
对所述有源层进行氢化和活化处理。
其中，所述栅极层为Ti/Al/Ti或Mo/Al/Mo的三层结构。
其中，在所述阻隔层上沉积栅极层的步骤包括：
在所述阻隔层上沉积第一Mo金属层，所述第一Mo金属层的厚度为30～50nm；
在所述第一Mo金属层上沉积Al金属层，所述Al金属层的厚度为100～120nm；
在所述Al金属层上沉积第二Mo金属层，所述第二Mo金属层的厚度为30～50nm。
其中，在对所述有源层进行氢化和活化处理的步骤中，所述氢化和活化处理的温度是330～370℃，所述氢化和活化处理的时间是30～60min。
其中，在对所述有源层进行氢化和活化处理之后，包括：
在所述层间绝缘层上形成过孔，所述过孔贯穿所述层间绝缘层；
在所述过孔上沉积源极和漏极，所述源极和所述漏极通过所述过孔电连接至所述有源层；
将所述柔性衬底从所述基板上剥离。
其中，在所述栅极绝缘层上形成有源层的步骤包括：
在所述栅极绝缘层上沉积非晶硅层；
用准分子镭射作为热源加工所述非晶硅层，形成所述有源层。
其中，所述栅极绝缘层和所述层间绝缘层的材质为氧化硅或氮化硅或氧化硅和氮化硅的叠层结构。
其中，所述阻隔层为导热绝缘层。
本申请提供的一种TFT基板，应用于柔性OLED显示装置，所述TFT基板包括柔性衬底、位于所述柔性衬底上的阻隔层、位于所述阻隔层上的栅极走线、覆盖于所述栅极走线的栅极绝缘层、位于所述栅极绝缘层上的有源层、覆盖于所述有源层的层间绝缘层。
其中，所述TFT基板还包括贯穿所述层间绝缘层的过孔及位于所述过孔上的源极和漏极，所述源极和所述漏极通过所述过孔电连接至所述有源层。
本申请提供的一种TFT基板的制作方法，在柔性衬底上依次制备阻断层、栅极走线、栅极绝缘层、有源层及层间绝缘层，由于栅极走线的主要材质为Al，相较于主要材质为Mo的栅极走线，在满足栅极走线阻抗的情况下，降低了栅极走线的厚度或宽度，从而提高柔性显示面板中栅极走线的耐弯折性能，实现高解析度显示。
通过先沉积栅极走线和栅极绝缘层，并在栅极绝缘层上形成有源层，然后在有源层上沉积层间绝缘层，以使有源层的上下界面分别直接接触栅极绝缘层和层间绝缘层，然后对有源层进行氢化和活化处理，由于有源层被栅极绝缘层和层间绝缘层包围，氢化和活化处理过程使得栅极绝缘层和层间绝缘层中的H +从有源层的周侧面扩散至有源层中，从而增加有源层的活化效果，从而减少有源层内部及表面的缺陷，从而提高TFT器件的性能。此外，由于有源层的活化效果增加，可以在实现对有源层氢化和活化的同时，降低氢化和活化制程的温度，从而降低氢化和活化制程温度对于栅极走线的导电性能影响，提高TFT基板的性能。
附图说明
为了更清楚地说明本申请实施例的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例提供的一种TFT基板的制作方法的流程图。
图2是本申请实施例提供的TFT基板的制作方法中S100的流程图。
图3是本申请实施例提供的TFT基板的制作方法中S200的流程图。
图4是本申请实施例提供的TFT基板的制作方法中S300的流程图。
图5是本申请实施例提供的TFT基板的制作方法中S400的流程图。
图6是本申请实施例提供的TFT基板的制作方法中S500的流程图。
图7是本申请实施例提供的TFT基板的制作方法中S600的流程图。
图8是本申请实施例提供的TFT基板的制作方法中S800的流程图。
图9是本申请实施例提供的一种TFT基板的结构示意图。
具体实施方式
为了能够更清楚地理解本申请的上述目的、特征和优点，下面结合附图和具体实施方式对本申请进行详细描述。需要说明的是，在不冲突的情况下，本申请的实施方式及实施方式中的特征可以相互组合。
在下面的描述中阐述了很多具体细节以便于充分理解本申请，所描述的实施方式仅仅是本申请一部分实施方式，而不是全部的实施方式。基于本申请中的实施方式，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施方式，都属于本申请保护的范围。
此外，以下各实施例的说明是参考附加的图示，用以例示本申请可用以实施的特定实施例。本申请中所提到的方向用语，例如，“顶”、“底”、“上”、“下”、“前”、“后”、“左”、“右”、“内”、“外”、“侧面”等，仅是参考附加图式的方向，因此，使用的方向用语是为了更好、更清楚地说明及理解本申请，而不是指示或暗指所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。
请参阅图1，图1是本申请提供的一种TFT基板的制作方法，该制作方法可以用于制作柔性TFT基板，所述柔性TFT基板用于柔性OLED显示装置。请参阅图2～图9，所述制作方法S10包括以下的步骤。
S100、请参阅图2，提供一刚性基板100。在所述刚性基板100上涂布有机材料，形成柔性衬底110。
本实施方式中，所述刚性基板100可以为玻璃基板。使用化学气相沉积(CVD，Chemical Vapor Deposition)方法在玻璃基板上沉积有机材料，所述有机材料包括聚碳酸酯(PC)、聚乙二醇对苯二甲酸酯(PET)、聚萘二甲酸乙二醇酯(PEN)、聚醚砜树脂(PES)、及聚酰亚胺(PI)中的至少一种。可选的，所述有机材料包括聚酰亚胺(PI)。
S200、请参阅图3，在所述柔性衬底110上沉积阻隔层120。
本实施方式中，所述阻隔层120的材料可以是氧化硅、氮化硅、高介电常数介质材料以及有机介质材料中的至少一种，其中高介电常数介质材料包括氧化铝、氧化铪、氧化锆等。该阻隔层120的淀积方法采用等离子体化学气相淀积(PECVD)、磁控溅射或反应溅射、原子层淀积或旋涂技术等。该阻隔层120 厚度为5nm～400nm。
一种可能的实施方式中，所述阻隔层120为氧化硅(SiOx)层、氮化硅(SiNx)层、或者由氧化硅层与氮化硅层叠加构成的复合层。
另一种可能的实施方式中，所述阻隔层120为导热绝缘层。所述导热绝缘层的材质为的Al2O3。
进一步地，对该导热绝缘薄膜进行图案化处理，得到导热绝缘层。
具体地，通过黄光、蚀刻制程对所述导热绝缘层进行图案化处理，使所述导热绝缘层的尺寸和形状为预设尺寸和形状，所述预设尺寸和形状为后续要制作的多晶硅半导体层的尺寸和形状。
S300、请参阅图4，在所述阻隔层120上沉积栅极层，光刻和刻蚀所述栅极层，将栅极层图形化形成栅极走线130。所述栅极走线130的主要材质为Al。
可选的，可以采用物理气相沉积(PVD，Physical Vapor Deposition)方法在所述阻隔层120上沉积栅极层。
可选的，所述栅极层的材料为金属、导电金属氧化物或其他导电材料中的至少一种。
一种可能的实施方式中，所述栅极层为Ti/Al/Ti或Mo/Al/Mo的三层结构。
具体的，在所述阻隔层120上沉积栅极层的步骤S300包括：
S301、在所述阻隔层120上沉积第一Mo金属层，所述第一Mo金属层的厚度为30-50nm。
在所述阻隔层120上通过磁控溅射淀积一层厚度为30-50nm的金属钼(Mo)导电薄膜。在金属Mo导电薄膜上旋涂光刻胶，进行光刻、刻蚀后形成第一Mo金属层。
S302、在所述第一Mo金属层上沉积Al金属层。所述Al金属层的厚度为100-120nm。
在所述第一Mo金属层上通过磁控溅射淀积一层厚度为100-120nm的金属铝(Al)导电薄膜。在金属铝导电薄膜上旋涂光刻胶，进行光刻、刻蚀后形成Al金属层，所述Al金属层位于所述第一Mo金属层上。
S303、在所述Al金属层上沉积第二Mo金属层。所述第二Mo金属层的厚度为30-50nm。
在所述Al金属层上通过磁控溅射淀积一层厚度为30-50nm的金属钼(Mo) 导电薄膜。在金属Mo导电薄膜上旋涂光刻胶，进行光刻、刻蚀后形成第二Mo金属层。所述第二Mo金属层覆盖于所述Al金属层。
基于以上的步骤，在所述阻隔层120上形成Mo/Al/Mo的三层结构的栅极走线130。在所述阻隔层120上形成Ti/Al/Ti的三层结构的栅极走线130的工艺与上述的步骤相同，在此不再赘述。三层结构中Ti或Mo起到保护Al作用。
与主要材质为Mo金属的栅极走线130相比，Al金属的电阻率较低、柔韧性较好。Mo金属容易脆裂，Mo金属阻抗相对于Al金属大。一般工艺中，栅极层用Mo金属厚度为250nm。本申请中，使用Ti/Al/Ti或Mo/Al/Mo制备栅极层，Al金属层的厚度100-120nm即可获得与厚度为250nm的Mo金属相同阻抗。当Al金属与Mo金属具有相同走线阻抗时，Al金属层的厚度可明显降低，或者Al金属与Mo金属厚度相当情况下，Al金属线宽可以做到很小即可实现高解析度显示，从而提高栅极走线130的耐弯折性能，防止柔性TFT基板在弯曲过程中出现断线、TFT器件剥落及漏光等问题，提升柔性TFT基板的品质，延长柔性TFT基板的使用寿命。
S400、请参阅图5，在所述阻隔层120上沉积栅极绝缘层140。所述栅极绝缘层140覆盖所述栅极走线130。
一种可能的实施方式中，在阻隔层120和栅极走线130上沉积所述栅极绝缘层140。其中，沉积方法可以采用等离子体化学气相淀积、磁控溅射或反应溅射、原子层淀积或旋涂技术。本实施方式中，可以使用化学气相沉积方法在阻隔层120和栅极走线130上沉积所述栅极绝缘层140。其中，栅极绝缘层140的材质是氧化硅、氮化硅、高介电常数介质材料以及有机介质材料中的至少一种，其厚度为5nm～400nm。本实施方式中，所述栅极绝缘层140的材质为氧化硅或氮化硅或氧化硅和氮化硅的叠层结构。
S500、请参阅图6，在所述栅极绝缘层140上形成有源层150。
一种可能的实施方式中，在形成有源层150前，对暴露出来的栅极绝缘层140表面进行等离子体处理，以增强栅极绝缘层140表面的附着力。传统的TFT基板制程中，在高温制程中经常会发生层间绝缘层裂纹或者脱落的问题，而在本申请的制程中，由于在沉积层间绝缘层之前已经对栅极绝缘层140进行等离子体处理，增强了其附着力，从而增强了层间绝缘层与栅极绝缘层140之间的粘着力，可以有效防止后高温制程造成层间绝缘层裂纹或者脱落的问题，提高 产品良率。
一种可能的实施方式中，在所述栅极绝缘层140上形成有源层150的步骤S500包括：
S501、在所述栅极绝缘层140上沉积非晶硅层。所述非晶硅层的厚度可以为200-300nm。
S502、用准分子镭射作为热源加工所述非晶硅层，形成所述有源层150。
具体的，采用准分子激光退火(Excimer Laser Annel，ELA)或固相结晶(Solid Phase Crystallization，SPC)方法使非晶硅层转变为多晶硅层，再通过光刻、蚀刻工艺对多晶硅层图形化，得到多个多晶硅岛，以形成有源层150。经过激光退火后的多晶硅的迁移率增加，能够满足外围电动的驱动要求。
S600、请参阅图7，在所述栅极绝缘层140上沉积层间绝缘层160。所述层间绝缘层160覆盖所述有源层150。
一种可能的实施方式中，所述层间绝缘层160的材质可以为氧化硅或氮化硅或氧化硅和氮化硅的叠层结构。
具体的，采用化学气相沉积方法在栅极绝缘层140上沉积形成层间绝缘层160，并将有源层150包覆于层间绝缘层160。所述层间绝缘层160的上下界面直接接触栅极绝缘层140和层间绝缘层160。
S700、对所述有源层150进行氢化和活化处理。
一种可能的实施方式中，在对所述有源层150进行氢化和活化处理的步骤中，所述氢化和活化处理的温度是330-370℃，所述氢化和活化处理的时间是30～60min。
在非晶硅转变成多晶硅的工艺流程中，由于多晶硅内部与表面存在缺陷，通过高温氢化和活化制程使层间绝缘层160和栅极绝缘层140内的H +扩散到多晶硅中以弥补多晶硅的缺陷。
现有技术中，由于层间绝缘层160距离多晶硅较远，故活化和氢化的效果并不理想，因而容易造成TFT器件电性异常等问题。
本实施例中，栅极绝缘层140和层间绝缘层160将有源层150包覆于两者之间，使得有源层150的周侧面均直接接触栅极绝缘层140和层间绝缘层160，有利于栅极绝缘层140中的H +向上扩散到多晶硅中，及层间绝缘层160中的H +向下扩散到多晶硅中，从而提升有源层150的氢化和活化效果，降低多晶硅的结 构缺陷，从而提升了薄膜晶体管的整体性能。
一般地，通过栅极绝缘层140和层间绝缘层160进行对有源层150氢化和活化，一般需要450℃及1h达到效果。在栅极走线130的主要成分为Al金属的情况下，因Al金属的熔点较低，约为660℃。Al金属经高温后会发生氧化或氮化从而导致膜质改变，进而使得栅极走线130的导电性降低。
本实施例中，有源层150上下界面分别直接接触栅极绝缘层140和层间绝缘层160进行补氢和活化工艺，具有较好的活化效果，所以可以降低该制程温度到330-370℃，不会影响栅极走线130膜质的变化，同时可以达到氢化活化的效果。
此外，栅极走线130设于有源层150之下，以使栅极走线130与暴露在外的表面距离较远，受到的氧化或氮化程度小，可以降低氢化和活化处理对栅极走线130膜质的影响。
一种实施方式中，所述栅极绝缘层140和层间绝缘层160可以为导热绝缘层，如氧化铝层等。
本实施方式中，由于导热绝缘层具有很好的绝缘性能及导热性质，在氢化和活化处理过程中，导热绝缘层能很快吸收大量热量并且传给与之接触的非晶硅层，使此处的非晶硅结晶效率提高，以使形成的多晶硅层内的多晶硅的晶粒更大、晶界更少，以使有源层150的电性较好，从而可以增强相应TFT器件载流子的迁移率，减小晶界对漏电流的影响，改善TFT的电性。
S800、请参阅图8，在所述层间绝缘层160上形成过孔。所述过孔贯穿所述层间绝缘层160。
具体的，通过光刻、蚀刻工艺图形化层间绝缘层160，形成第一过孔171和第二过孔172，使第一过孔171和第二过孔172电连接至有源层150。
S900、请参阅图9，在所述过孔上沉积源极181和漏极182，所述源极181和所述漏极182通过所述过孔电连接至所述有源层150，最后将所述柔性衬底110从所述刚性基板100上剥离，制得一柔性TFT基板。
具体的，在第一过孔171和第二过孔172，沉积形成金属层，并通过光刻和蚀刻工艺图形化所述金属层，形成源极181和漏极182。所述源极181和漏极182分别覆盖第一过孔171和第二过孔172，并通过第一过孔171和第二过孔172电连接至有源层150。将所述柔性衬底110从所述刚性基板100上剥离，制得一柔性 TFT基板。
本申请中，通过先沉积栅极走线130和栅极绝缘层140，并在栅极绝缘层140上形成有源层150，然后在有源层150上沉积层间绝缘层160，以使有源层150的上下界面分别直接接触栅极绝缘层140和层间绝缘层160，然后对有源层150进行氢化和活化处理，由于有源层150被栅极绝缘层140和层间绝缘层160包围，氢化和活化处理过程使得栅极绝缘层140和层间绝缘层160中的H+从有源层150的周侧面扩散至有源层150中，从而增加有源层150的活化效果，从而减少有源层150内部及表面的缺陷，从而提高TFT器件的性能。此外，由于有源层150的活化效果增加，可以在实现对有源层150氢化和活化的同时，降低氢化和活化制程的温度，从而降低氢化和活化制程温度对于栅极走线130的导电性能影响，提高TFT基板的性能。
请参阅图9，本申请还提供了一种TFT基板10，用于制备柔性OLED显示装置。所述TFT基板10采用上述的任一实施方式所述的TFT基板制作方法S10制得。所述TFT基板10包括柔性衬底110、位于所述柔性衬底110上的阻隔层120、位于所述阻隔层120上的栅极走线130、覆盖于所述栅极走线130的栅极绝缘层140、位于所述栅极绝缘层140上的有源层150、覆盖于所述有源层150的层间绝缘层160。所述栅极走线130的主要材质为Al。一种可能的实施方式中，所述栅极层为Ti/Al/Ti或Mo/Al/Mo的三层结构。三层结构中Ti或Mo起到保护Al作用。
与主要材质为Mo金属的栅极走线130相比，Al金属的电阻率较低、柔韧性较好。当Al金属与Mo金属具有相同走线阻抗时，Al金属层的厚度可明显降低，或者Al金属与Mo金属厚度相当情况下，Al金属线宽可以做到很小即可实现高解析度显示，从而提高栅极走线130的耐弯折性能。
一种可能的实施方式中，所述TFT基板10还包括贯穿所述层间绝缘层160的过孔171、172及位于所述过孔171、172上的源极181和漏极182，所述源极181和所述漏极182通过所述过孔171、172电连接至所述有源层150。
最后应说明的是，以上实施方式仅用以说明本申请的技术方案而非限制，尽管参照以上较佳实施方式对本申请进行了详细说明，本领域的普通技术人员应当理解，可以对本申请的技术方案进行修改或等同替换都不应脱离本申请技术方案的精神和范围。

Claims (10)

  1. 一种TFT基板的制作方法，其中，所述制作方法包括以下的步骤：
    提供基板，在所述基板上制备柔性衬底；
    在所述柔性衬底上沉积阻隔层；
    在所述阻隔层上沉积栅极层，刻蚀所述栅极层以形成栅极走线，所述栅极走线的主要材质为Al；
    在所述阻隔层上沉积栅极绝缘层，所述栅极绝缘层覆盖所述栅极走线；
    在所述栅极绝缘层上形成有源层；
    在所述栅极绝缘层上沉积层间绝缘层，所述层间绝缘层覆盖所述有源层；
    对所述有源层进行氢化和活化处理。
  2. 如权利要求1所述的制作方法，其中，所述栅极层为Ti/Al/Ti或Mo/Al/Mo的三层结构。
  3. 如权利要求2所述的制作方法，其中，在所述阻隔层上沉积栅极层的步骤包括：
    在所述阻隔层上沉积第一Mo金属层，所述第一Mo金属层的厚度为30～50nm；
    在所述第一Mo金属层上沉积Al金属层，所述Al金属层的厚度为100～120nm；
    在所述Al金属层上沉积第二Mo金属层，所述第二Mo金属层的厚度为30～50nm。
  4. 如权利要求1所述的制作方法，其中，在对所述有源层进行氢化和活化处理的步骤中，所述氢化和活化处理的温度是330～370℃，所述氢化和活化处理的时间是30～60min。
  5. 如权利要求1所述的制作方法，其中，在对所述有源层进行氢化和活化处理之后，包括：
    在所述层间绝缘层上形成过孔，所述过孔贯穿所述层间绝缘层；
    在所述过孔上沉积源极和漏极，所述源极和所述漏极通过所述过孔电连接至所述有源层；
    将所述柔性衬底从所述基板上剥离。
  6. 如权利要求1所述的制作方法，其中，在所述栅极绝缘层上形成有源层的步骤包括：
    在所述栅极绝缘层上沉积非晶硅层；
    用准分子镭射作为热源加工所述非晶硅层，形成所述有源层。
  7. 如权利要求1所述的制作方法，其中，所述栅极绝缘层和所述层间绝缘层的材质为氧化硅或氮化硅或氧化硅和氮化硅的叠层结构。
  8. 如权利要求1所述的制备方法，其中，所述阻隔层为导热绝缘层。
  9. 一种TFT基板，其中，所述TFT基板包括柔性衬底、位于所述柔性衬底上的阻隔层、位于所述阻隔层上的栅极走线、覆盖于所述栅极走线的栅极绝缘层、位于所述栅极绝缘层上的有源层、覆盖于所述有源层的层间绝缘层。
  10. 如权利要求9所述的TFT基板，其中，所述TFT基板还包括贯穿所述层间绝缘层的过孔及位于所述过孔上的源极和漏极，所述源极和所述漏极通过所述过孔电连接至所述有源层。
PCT/CN2018/071661 2017-11-06 2018-01-05 Tft基板及其制作方法 WO2019085267A1 (zh)

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CN109411355A (zh) * 2018-12-03 2019-03-01 武汉华星光电半导体显示技术有限公司 一种薄膜晶体管的制备方法
CN109671623B (zh) * 2018-12-21 2020-11-24 深圳市华星光电技术有限公司 栅极与薄膜晶体管的制造方法
CN117016052A (zh) * 2022-01-28 2023-11-07 京东方科技集团股份有限公司 显示基板及其制作方法、显示装置
CN114678383A (zh) * 2022-04-25 2022-06-28 福建华佳彩有限公司 一种改善金属残留的tft阵列基板结构及其制造方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030183820A1 (en) * 1998-12-21 2003-10-02 Lg. Philips Lcd Co., Ltd. Liquid crystal display for preventing galvanic phenomenon
CN103137497A (zh) * 2013-02-26 2013-06-05 深圳市华星光电技术有限公司 低温多晶硅晶体管的制作方法
CN103985637A (zh) * 2014-04-30 2014-08-13 京东方科技集团股份有限公司 低温多晶硅薄膜晶体管及其制作方法和显示装置
CN106252214A (zh) * 2016-08-31 2016-12-21 武汉华星光电技术有限公司 一种制备柔性显示器件的离子活化方法
CN106920836A (zh) * 2017-03-29 2017-07-04 京东方科技集团股份有限公司 一种薄膜晶体管及其制作方法、阵列基板、显示装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030183820A1 (en) * 1998-12-21 2003-10-02 Lg. Philips Lcd Co., Ltd. Liquid crystal display for preventing galvanic phenomenon
CN103137497A (zh) * 2013-02-26 2013-06-05 深圳市华星光电技术有限公司 低温多晶硅晶体管的制作方法
CN103985637A (zh) * 2014-04-30 2014-08-13 京东方科技集团股份有限公司 低温多晶硅薄膜晶体管及其制作方法和显示装置
CN106252214A (zh) * 2016-08-31 2016-12-21 武汉华星光电技术有限公司 一种制备柔性显示器件的离子活化方法
CN106920836A (zh) * 2017-03-29 2017-07-04 京东方科技集团股份有限公司 一种薄膜晶体管及其制作方法、阵列基板、显示装置

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