WO2019075779A1 - 一种静电防护电路结构、显示面板及显示装置 - Google Patents

一种静电防护电路结构、显示面板及显示装置 Download PDF

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WO2019075779A1
WO2019075779A1 PCT/CN2017/108895 CN2017108895W WO2019075779A1 WO 2019075779 A1 WO2019075779 A1 WO 2019075779A1 CN 2017108895 W CN2017108895 W CN 2017108895W WO 2019075779 A1 WO2019075779 A1 WO 2019075779A1
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film transistor
thin film
signal line
conductive layer
display panel
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PCT/CN2017/108895
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English (en)
French (fr)
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石龙强
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深圳市华星光电半导体显示技术有限公司
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Priority to US15/740,704 priority Critical patent/US10720423B2/en
Publication of WO2019075779A1 publication Critical patent/WO2019075779A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0288—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H01L27/027—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements specially adapted to provide an electrical current path other than the field effect induced current path
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0292—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using a specific configuration of the conducting means connecting the protective devices, e.g. ESD buses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136204—Arrangements to prevent high voltage or static electricity failures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits

Definitions

  • the present invention relates to the field of display panel technologies, and in particular, to an electrostatic protection circuit structure, a display panel, and a display device.
  • the ESD is often introduced into the design of the display panel.
  • the display panel introduces a signal line 2 / of the input signal G_in in the second metal layer L2, and a signal line 1 / of the output signal G_out is drawn in the first metal layer L1, and is connected to the second via the conductive layer on the metal layer and the first metal layer L2 L1 3 / electrostatic protection achieved between the two signal lines, which is equivalent to the input signal of the signal line 2 G_in / output signal and a signal line G_out
  • An equivalent resistance R is set between / (as shown in FIG. 3), so that the static electricity accumulated on the second signal line 2 / by the input signal G_in can be released through the equivalent resistance R to prevent an instantaneous large current. Damage to the circuit.
  • the inventors have found that the above electrostatic protection measures have certain limitations. Once the static electricity accumulated on the signal line 2 / of the input signal G_in is too large, the via conductive layer 3 / bursting may cause a disconnection (see FIG. 4). As shown, the signal on the display panel cannot be output normally.
  • the technical problem to be solved by the embodiments of the present invention is to provide an electrostatic protection circuit structure, a display panel, and a display device, which can effectively solve the problem that the input signal end of the display panel on the display panel in the prior art cannot be normally output due to excessive static electricity.
  • the problem is to provide an electrostatic protection circuit structure, a display panel, and a display device, which can effectively solve the problem that the input signal end of the display panel on the display panel in the prior art cannot be normally output due to excessive static electricity.
  • an embodiment of the present invention provides an electrostatic protection circuit structure, which is disposed on a display panel, and includes a second signal line that bridges and communicates between an input signal and a first signal line that outputs an output signal.
  • the first via conductive layer further includes a thin film transistor; wherein the gate of the thin film transistor is in communication with the drain thereof, and the gate and/or the drain of the thin film transistor are connected to the second signal line, and the source of the thin film transistor A signal line is connected.
  • the gate of the thin film transistor and the first signal line are both disposed on the first metal layer of the display panel, and the drain and the source of the thin film transistor and the second signal line are both disposed on On the second metal layer of the display panel;
  • a gate of the thin film transistor is connected to a drain thereof through a second via conductive layer, and a drain of the thin film transistor is further in direct communication with the second signal line, and a source of the thin film transistor passes through a third A via conductive layer is in cross-connect with the first signal line.
  • An active layer formed as a conductive channel is disposed between a gate of the thin film transistor and a drain and a source thereof, and the active layer is disposed on the first metal layer and the second metal layer of the display panel between.
  • the first via conductive layer, the second via conductive layer and the third via conductive layer are all formed by using an indium tin oxide ITO material.
  • the first via conductive layer normally maintains communication between the first metal layer and the second metal layer, the potentials of the gate, the drain and the source of the thin film transistor are equal And the thin film transistor maintains an inoperative state.
  • the gate potential of the thin film transistor is greater than the source potential thereof, and Thin The membrane transistor starts up and works.
  • the embodiment of the present invention further provides a display panel, including an electrostatic protection circuit structure
  • the static electricity protection circuit structure is disposed on the display panel, and includes a first via conductive layer spanning and connecting between the second signal line for introducing the input signal and the first signal line for extracting the output signal, and further comprising a thin film transistor;
  • the gate of the thin film transistor is in communication with the drain thereof, and the gate and/or the drain of the thin film transistor are connected to the second signal line, and the source of the thin film transistor is connected to the first signal line.
  • the gate of the thin film transistor and the first signal line are both disposed on the first metal layer of the display panel, and the drain and the source of the thin film transistor and the second signal line are both disposed on On the second metal layer of the display panel;
  • a gate of the thin film transistor is connected to a drain thereof through a second via conductive layer, and a drain of the thin film transistor is further in direct communication with the second signal line, and a source of the thin film transistor passes through a third A via conductive layer is in cross-connect with the first signal line.
  • An active layer formed as a conductive channel is disposed between a gate of the thin film transistor and a drain and a source thereof, and the active layer is disposed on the first metal layer and the second metal layer of the display panel between.
  • the first via conductive layer, the second via conductive layer and the third via conductive layer are all formed by using an indium tin oxide ITO material.
  • the first via conductive layer normally maintains communication between the first metal layer and the second metal layer, the potentials of the gate, the drain and the source of the thin film transistor are equal And the thin film transistor maintains an inoperative state.
  • the gate potential of the thin film transistor is greater than the source potential thereof, and The thin film transistor is activated and operates.
  • an embodiment of the present invention further provides a display device, including a display panel, and the display panel includes an electrostatic protection circuit structure;
  • the static electricity protection circuit structure is disposed on the display panel, including connecting and connecting the input input signal a first via conductive layer between the second signal line of the number and the first signal line of the output signal, further comprising a thin film transistor;
  • a gate of the thin film transistor is connected to a drain thereof, and a gate and/or a drain of the thin film transistor are connected to the second signal line, and a source of the thin film transistor is connected to the first signal line .
  • the gate of the thin film transistor and the first signal line are both disposed on the first metal layer of the display panel, and the drain and the source of the thin film transistor and the second signal line are both disposed on On the second metal layer of the display panel;
  • a gate of the thin film transistor is connected to a drain thereof through a second via conductive layer, and a drain of the thin film transistor is further in direct communication with the second signal line, and a source of the thin film transistor passes through a third A via conductive layer is in cross-connect with the first signal line.
  • An active layer formed as a conductive channel is disposed between a gate of the thin film transistor and a drain and a source thereof, and the active layer is disposed on the first metal layer and the second metal layer of the display panel between.
  • the first via conductive layer, the second via conductive layer and the third via conductive layer are all formed by using an indium tin oxide ITO material.
  • the first via conductive layer normally maintains communication between the first metal layer and the second metal layer, the potentials of the gate, the drain and the source of the thin film transistor are equal And the thin film transistor maintains an inoperative state.
  • the gate potential of the thin film transistor is greater than the source potential thereof, and The thin film transistor is activated and operates.
  • the present invention additionally adds a thin film transistor connecting the two between the first metal layer and the second metal layer in the static electricity protection circuit structure, which is caused by excessive static electricity. After the original first via conductive layer is damaged, the thin film transistor can be activated to continue to maintain the signal transmission connectivity between the first metal layer and the second metal layer, thereby effectively solving the prior art.
  • the input signal terminal is disconnected due to excessive static electricity, and the signal cannot be output normally.
  • FIG. 1 is a schematic diagram of physical connection of an electrostatic protection circuit on a display panel in the prior art
  • Figure 2 is a partial cross-sectional, cross-sectional view of the static electricity protection circuit of Figure 1;
  • FIG. 3 is an equivalent circuit diagram of the static electricity protection circuit of FIG. 1;
  • FIG. 4 is a schematic view showing the physical connection of the electrostatic protection circuit of FIG. 1 after being injured;
  • FIG. 5 is a schematic diagram of physical connection of an electrostatic protection circuit structure according to Embodiment 1 of the present invention.
  • Figure 6 is an equivalent circuit diagram of the structure of the static electricity protection circuit of Figure 5.
  • an electrostatic protection circuit structure is provided on a display panel, including a second signal line 2 that bridges and connects the input input signal G_in and an output signal G_out.
  • the first via conductive layer 3 between the first signal lines 1 further includes a thin film transistor 4; wherein
  • the gate G of the thin film transistor 4 is in communication with its drain D, and the gate G and/or the drain D of the thin film transistor 4 are connected to the second signal line 2, and the source S of the thin film transistor 4 is connected to the first signal line 1. .
  • the gate G of the thin film transistor 4 and the first The signal line 1 is disposed on the first metal layer of the display panel, and the drain D and the source S and the second signal line 2 of the thin film transistor 4 are disposed on the second metal layer of the display panel;
  • the gate G of the thin film transistor 4 is connected in communication with the drain D thereof through the second via conductive layer 5, and the drain D of the thin film transistor 4 is also in direct communication with the second signal line 2, and the source S of the thin film transistor 4
  • the third via conductive layer 6 is in cross-connect with the first signal line 1.
  • the active layer T formed as a conductive channel is disposed between the gate G of the thin film transistor 4 and its drain D and source S. In one embodiment, the active layer T is disposed between the first metal layer and the second metal layer of the display panel.
  • the first via conductive layer 3, the second via conductive layer 5 and the third via conductive layer 6 are all formed of indium tin oxide ITO.
  • the structure of the static electricity protection circuit in the first embodiment of the present invention can be converted into an equivalent circuit as shown in FIG. 6, and the specific working states are as follows:
  • the film The transistor 4 is self-protected. At this time, the potentials of the gate G, the drain D and the source S of the thin film transistor 4 are equal, and the thin film transistor 4 is kept in an inoperative state, so that the thin film transistor 4 is not damaged even if a current is passed;
  • the second embodiment of the present invention further provides a display panel, including the electrostatic protection circuit structure in the first embodiment of the present invention.
  • the electrostatic protection circuit structure in the second embodiment of the present invention and the electrostatic protection circuit in the first embodiment of the present invention The structures have the same structure and connection relationship, and therefore will not be further described herein.
  • the third embodiment of the present invention further provides a display device, including the electrostatic protection circuit structure in the first embodiment of the present invention.
  • the display panel in the third embodiment of the present invention has the same structure and connection relationship as the display panel in the second embodiment of the present invention, and therefore will not be further described herein.
  • the present invention further adds a thin film transistor connecting the two between the first metal layer and the second metal layer in the static electricity protection circuit structure, If the over-conducting layer causes the first via-hole conductive layer to be damaged, the thin film transistor can be activated to continue to maintain the signal transmission connectivity between the first metal layer and the second metal layer, thereby effectively solving the prior art display panel.
  • the problem that the upper input signal terminal is disconnected due to excessive static electricity cannot output the signal normally.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)

Abstract

一种静电防护电路结构，设置于显示面板上，包括跨接并连通引入输入信号（G_in）的第二信号线（2）和引出输出信号（G_out）的第一信号线（1）之间的第一过孔导电层（3），还包括薄膜晶体管（4）；其中，薄膜晶体管（4）的栅极（G）与其漏极（D）相连通，且薄膜晶体管（4）的栅极（G）和/或漏极（D）与第二信号线（2）相连，薄膜晶体管（4）的源极（S）与第一信号线（1）相连；还涉及一种显示面板及一种显示装置，能够有效解决现有技术中显示面板上输入信号端因静电过大导致断线而无法正常输出信号的问题。

Description

一种静电防护电路结构、显示面板及显示装置
本申请要求于2017年10月18日提交中国专利局、申请号为201710972927.5、发明名称为“一种静电防护电路结构、显示面板及显示装置”的中国专利申请的优先权，上述专利的全部内容通过引用结合在本申请中。
技术领域
本发明涉及显示面板技术领域，尤其涉及一种静电防护电路结构、显示面板及显示装置。
背景技术
为了防止显示面板在制程和运输等过程的静电导致导电线路或导电层的炸伤，往往会在显示面板设计中引入静电防护设计ESD。
如图1和图2所示，显示面板在第二金属层L2引入输入信号G_in的信号线2/，在第一金属层L1引出输出信号G_out的信号线1/，并通过跨接于第二金属层L2和第一金属层L1上的过孔导电层3/实现上述两个信号线之间的静电保护，其等效于在输入信号G_in的信号线2/和输出信号G_out的信号线1/之间设置了一个等效电阻R(如图3所示)，这样就可以使得输入信号G_in在第二信号线2/上累积的静电经过该等效电阻R进行释放，防止瞬间大电流导致电路的损伤。
然而，发明人发现，上述静电保护措施具有一定的局限性，一旦输入信号G_in的信号线2/上累积的静电过大，会导致过孔导电层3/炸伤而导致断线(如图4所示)，使得显示面板上的信号不能正常输出。
发明内容
本发明实施例所要解决的技术问题在于，提供一种静电防护电路结构、显示面板及显示装置，能够有效解决现有技术中显示面板上输入信号端因静电过大导致断线而无法正常输出信号的问题。
为了解决上述技术问题，本发明实施例提供了一种静电防护电路结构，设置于显示面板上，包括跨接并连通引入输入信号的第二信号线和引出输出信号的第一信号线之间的第一过孔导电层，还包括薄膜晶体管；其中，薄膜晶体管的栅极与其漏极相连通，且薄膜晶体管的栅极和/或漏极与第二信号线相连，薄膜晶体管的源极与第一信号线相连。
其中，所述薄膜晶体管的栅极与所述第一信号线均设置于所述显示面板的第一金属层上，所述薄膜晶体管的漏极和源极与所述第二信号线均设置于所述显示面板的第二金属层上；其中，
所述薄膜晶体管的栅极通过第二过孔导电层与其漏极跨接连通，且所述薄膜晶体管的漏极还与所述第二信号线直接连通，所述薄膜晶体管的源极通过第三过孔导电层与所述第一信号线跨接连通。
其中，所述薄膜晶体管的栅极与其漏极和源极间设有形成为导电沟道的有源层，且所述有源层设置于所述显示面板的第一金属层和第二金属层之间。
其中，所述第一过孔导电层、第二过孔导电层和第三过孔导电层均采用氧化铟锡ITO材质形成。
其中，当所述第一过孔导电层正常保持所述第一金属层和所述第二金属层之间的连通时，则所述薄膜晶体管的栅极、漏极及源极的电位均相等，且所述薄膜晶体管维持不工作状态。
其中，当所述第一过孔导电层异常断开所述第一金属层和所述第二金属层之间的连通时，则所述薄膜晶体管的栅极电位大于其源极电位，且所述薄 膜晶体管启动并工作。
相应的，本发明实施例又提供了一种显示面板，包括静电防护电路结构；
所述静电防护电路结构设置于显示面板上，包括跨接并连通引入输入信号的第二信号线和引出输出信号的第一信号线之间的第一过孔导电层，还包括薄膜晶体管；其中，薄膜晶体管的栅极与其漏极相连通，且薄膜晶体管的栅极和/或漏极与第二信号线相连，薄膜晶体管的源极与第一信号线相连。
其中，所述薄膜晶体管的栅极与所述第一信号线均设置于所述显示面板的第一金属层上，所述薄膜晶体管的漏极和源极与所述第二信号线均设置于所述显示面板的第二金属层上；其中，
所述薄膜晶体管的栅极通过第二过孔导电层与其漏极跨接连通，且所述薄膜晶体管的漏极还与所述第二信号线直接连通，所述薄膜晶体管的源极通过第三过孔导电层与所述第一信号线跨接连通。
其中，所述薄膜晶体管的栅极与其漏极和源极间设有形成为导电沟道的有源层，且所述有源层设置于所述显示面板的第一金属层和第二金属层之间。
其中，所述第一过孔导电层、第二过孔导电层和第三过孔导电层均采用氧化铟锡ITO材质形成。
其中，当所述第一过孔导电层正常保持所述第一金属层和所述第二金属层之间的连通时，则所述薄膜晶体管的栅极、漏极及源极的电位均相等，且所述薄膜晶体管维持不工作状态。
其中，当所述第一过孔导电层异常断开所述第一金属层和所述第二金属层之间的连通时，则所述薄膜晶体管的栅极电位大于其源极电位，且所述薄膜晶体管启动并工作。
相应的，本发明实施例还提供了一种显示装置，其中，包括显示面板，且所述显示面板包括静电防护电路结构；其中，
所述静电防护电路结构设置于显示面板上，包括跨接并连通引入输入信 号的第二信号线和引出输出信号的第一信号线之间的第一过孔导电层，还包括薄膜晶体管；
所述薄膜晶体管的栅极与其漏极相连通，且所述薄膜晶体管的栅极和/或漏极与所述第二信号线相连，所述薄膜晶体管的源极与所述第一信号线相连。
其中，所述薄膜晶体管的栅极与所述第一信号线均设置于所述显示面板的第一金属层上，所述薄膜晶体管的漏极和源极与所述第二信号线均设置于所述显示面板的第二金属层上；其中，
所述薄膜晶体管的栅极通过第二过孔导电层与其漏极跨接连通，且所述薄膜晶体管的漏极还与所述第二信号线直接连通，所述薄膜晶体管的源极通过第三过孔导电层与所述第一信号线跨接连通。
其中，所述薄膜晶体管的栅极与其漏极和源极间设有形成为导电沟道的有源层，且所述有源层设置于所述显示面板的第一金属层和第二金属层之间。
其中，所述第一过孔导电层、第二过孔导电层和第三过孔导电层均采用氧化铟锡ITO材质形成。
其中，当所述第一过孔导电层正常保持所述第一金属层和所述第二金属层之间的连通时，则所述薄膜晶体管的栅极、漏极及源极的电位均相等，且所述薄膜晶体管维持不工作状态。
其中，当所述第一过孔导电层异常断开所述第一金属层和所述第二金属层之间的连通时，则所述薄膜晶体管的栅极电位大于其源极电位，且所述薄膜晶体管启动并工作。实施本发明实施例，具有如下有益效果：
与传统的静电防护电路结构相比，本发明在静电防护电路结构在第一金属层和第二金属层之间还新增跨接有将二者相连通的薄膜晶体管，在因静电过大导致原有第一过孔导电层炸伤后，可以启动该薄膜晶体管工作继续保持第一金属层和第二金属层之间信号传输的连通性，因此能够有效解决现有技 术中显示面板上输入信号端因静电过大导致断线而无法正常输出信号的问题。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，根据这些附图获得其他的附图仍属于本发明的范畴。
图1为现有技术中显示面板上静电防护电路的物理连接示意图；
图2为图1中静电防护电路的局部剖视截面图；
图3为图1中静电防护电路的等效电路图；
图4为图1中静电防护电路炸伤后的物理连接示意图；
图5为本发明实施例一提供的静电防护电路结构的物理连接示意图；
图6为图5中静电防护电路结构的等效电路图。
具体实施方式
下面参考附图对本发明的优选实施例进行描述。
如图5所示，为本发明实施例一中，提供的一种静电防护电路结构，设置于显示面板上，包括跨接并连通引入输入信号G_in的第二信号线2和引出输出信号G_out的第一信号线1之间的第一过孔导电层3，还包括薄膜晶体管4；其中，
薄膜晶体管4的栅极G与其漏极D相连通，且薄膜晶体管4的栅极G和/或漏极D与第二信号线2相连，薄膜晶体管4的源极S与第一信号线1相连。
在本发明实施例一中，为了便于制程，该薄膜晶体管4的栅极G与第一 信号线1均设置于显示面板的第一金属层上，薄膜晶体管4的漏极D和源极S与第二信号线2均设置于显示面板的第二金属层上；其中，
该薄膜晶体管4的栅极G通过第二过孔导电层5与其漏极D跨接连通，且该薄膜晶体管4的漏极D还与第二信号线2直接连通，薄膜晶体管4的源极S通过第三过孔导电层6与第一信号线1跨接连通。
在本发明实施例一中，该薄膜晶体管4的栅极G与其漏极D和源极S间设有形成为导电沟道的有源层T。在一个实施例中，该有源层T设置于显示面板的第一金属层和第二金属层之间。
在本发明实施例一中，第一过孔导电层3、第二过孔导电层5和第三过孔导电层6均采用氧化铟锡ITO材质形成。
本发明实施例一中的静电防护电路结构可转换为如图6所示的等效电路，其具体工作状态如下：
(1)当传统的静电防护电路正常工作时，即第一过孔导电层3正常保持第一信号线1和第二信号线2之间的连通，使得输入信号G_in能正常输出信号G_out，薄膜晶体管4自保护，此时薄膜晶体管4的栅极G、漏极D及源极S的电位均相等，则薄膜晶体管4维持不工作状态，因此即便有电流通过也不会损伤薄膜晶体管4；
(2)当传统的静电防护电路发生炸伤时，即第一过孔导电层3异常断开第一信号线1和第二信号线2之间的连通时，此时薄膜晶体管4的栅极G电位大于其源极S电位，则薄膜晶体管4启动并工作，使得输入信号G_in继续能正常输出信号G_out。这时，因薄膜晶体管4通过第二过孔导电层5与第二信号线2连通以及第三过孔导电层6与第一信号线1连通，会继续起到静电防护作用。
相应于本发明实施例一中的一种静电防护电路结构，本发明实施例二还提供了一种显示面板，包括本发明实施例一中的静电防护电路结构。由于本发明实施例二中的静电防护电路结构与本发明实施例一中静电防护电路结 构具有相同的结构及连接关系，因此在此不再一一赘述。
相应于本发明实施例二中的一种显示面板，本发明实施例三还提供了一种显示装置，包括本发明实施例一中的静电防护电路结构。由于本发明实施例三中的显示面板与本发明实施例二中显示面板具有相同的结构及连接关系，因此在此不再一一赘述。
综上，与传统的静电防护电路结构相比，本发明在静电防护电路结构在第一金属层和第二金属层之间还新增跨接有将二者相连通的薄膜晶体管，在因静电过大导致原有第一过孔导电层炸伤后，可以启动该薄膜晶体管工作继续保持第一金属层和第二金属层之间信号传输的连通性，因此能够有效解决现有技术中显示面板上输入信号端因静电过大导致断线而无法正常输出信号的问题。
以上所揭露的仅为本发明一种较佳实施例而已，当然不能以此来限定本发明之权利范围，因此依本发明权利要求所作的等同变化，仍属本发明所涵盖的范围。

Claims (18)

  1. 一种静电防护电路结构，设置于显示面板上，其中，包括跨接并连通引入输入信号的第二信号线和引出输出信号的第一信号线之间的第一过孔导电层，还包括薄膜晶体管；
    所述薄膜晶体管的栅极与其漏极相连通，且所述薄膜晶体管的栅极和/或漏极与所述第二信号线相连，所述薄膜晶体管的源极与所述第一信号线相连。
  2. 如权利要求1所述的静电防护电路结构，其中，所述薄膜晶体管的栅极与所述第一信号线均设置于所述显示面板的第一金属层上，所述薄膜晶体管的漏极和源极与所述第二信号线均设置于所述显示面板的第二金属层上；其中，
    所述薄膜晶体管的栅极通过第二过孔导电层与其漏极跨接连通，且所述薄膜晶体管的漏极还与所述第二信号线直接连通，所述薄膜晶体管的源极通过第三过孔导电层与所述第一信号线跨接连通。
  3. 如权利要求2所述的静电防护电路结构，其中，所述薄膜晶体管的栅极与其漏极和源极间设有形成为导电沟道的有源层，且所述有源层设置于所述显示面板的第一金属层和第二金属层之间。
  4. 如权利要求3所述的静电防护电路结构，其中，所述第一过孔导电层、第二过孔导电层和第三过孔导电层均采用氧化铟锡ITO材质形成。
  5. 如权利要求4所述的静电防护电路结构，其中，当所述第一过孔导电层正常保持所述第一信号线和所述第二信号线之间的连通时，则所述薄膜晶体管的栅极、漏极及源极的电位均相等，且所述薄膜晶体管维持不工作状态。
  6. 如权利要求5所述的静电防护电路结构，其中，当所述第一过孔导电层异常断开所述第一信号线和所述第二信号线之间的连通时，则所述薄膜 晶体管的栅极电位大于其源极电位，且所述薄膜晶体管启动并工作。
  7. 一种显示面板，其中，包括静电防护电路结构；
    所述静电防护电路结构设置于显示面板上，其中，包括跨接并连通引入输入信号的第二信号线和引出输出信号的第一信号线之间的第一过孔导电层，还包括薄膜晶体管；
    所述薄膜晶体管的栅极与其漏极相连通，且所述薄膜晶体管的栅极和/或漏极与所述第二信号线相连，所述薄膜晶体管的源极与所述第一信号线相连。
  8. 如权利要求7所述的显示面板，其中，所述薄膜晶体管的栅极与所述第一信号线均设置于所述显示面板的第一金属层上，所述薄膜晶体管的漏极和源极与所述第二信号线均设置于所述显示面板的第二金属层上；其中，
    所述薄膜晶体管的栅极通过第二过孔导电层与其漏极跨接连通，且所述薄膜晶体管的漏极还与所述第二信号线直接连通，所述薄膜晶体管的源极通过第三过孔导电层与所述第一信号线跨接连通。
  9. 如权利要求8所述的显示面板，其中，所述薄膜晶体管的栅极与其漏极和源极间设有形成为导电沟道的有源层，且所述有源层设置于所述显示面板的第一金属层和第二金属层之间。
  10. 如权利要求9所述的显示面板，其中，所述第一过孔导电层、第二过孔导电层和第三过孔导电层均采用氧化铟锡ITO材质形成。
  11. 如权利要求10所述的显示面板，其中，当所述第一过孔导电层正常保持所述第一信号线和所述第二信号线之间的连通时，则所述薄膜晶体管的栅极、漏极及源极的电位均相等，且所述薄膜晶体管维持不工作状态。
  12. 如权利要求11所述的显示面板，其中，当所述第一过孔导电层异常断开所述第一信号线和所述第二信号线之间的连通时，则所述薄膜晶体管的栅极电位大于其源极电位，且所述薄膜晶体管启动并工作。
  13. 一种显示装置，其中，包括显示面板，且所述显示面板包括静电防 护电路结构；其中，
    所述静电防护电路结构设置于显示面板上，包括跨接并连通引入输入信号的第二信号线和引出输出信号的第一信号线之间的第一过孔导电层，还包括薄膜晶体管；
    所述薄膜晶体管的栅极与其漏极相连通，且所述薄膜晶体管的栅极和/或漏极与所述第二信号线相连，所述薄膜晶体管的源极与所述第一信号线相连。
  14. 如权利要求13所述的显示装置，其中，所述薄膜晶体管的栅极与所述第一信号线均设置于所述显示面板的第一金属层上，所述薄膜晶体管的漏极和源极与所述第二信号线均设置于所述显示面板的第二金属层上；其中，
    所述薄膜晶体管的栅极通过第二过孔导电层与其漏极跨接连通，且所述薄膜晶体管的漏极还与所述第二信号线直接连通，所述薄膜晶体管的源极通过第三过孔导电层与所述第一信号线跨接连通。
  15. 如权利要求14所述的显示装置，其中，所述薄膜晶体管的栅极与其漏极和源极间设有形成为导电沟道的有源层，且所述有源层设置于所述显示面板的第一金属层和第二金属层之间。
  16. 如权利要求15所述的显示装置，其中，所述第一过孔导电层、第二过孔导电层和第三过孔导电层均采用氧化铟锡ITO材质形成。
  17. 如权利要求16所述的显示装置，其中，当所述第一过孔导电层正常保持所述第一信号线和所述第二信号线之间的连通时，则所述薄膜晶体管的栅极、漏极及源极的电位均相等，且所述薄膜晶体管维持不工作状态。
  18. 如权利要求17所述的显示装置，其中，当所述第一过孔导电层异常断开所述第一信号线和所述第二信号线之间的连通时，则所述薄膜晶体管的栅极电位大于其源极电位，且所述薄膜晶体管启动并工作。
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