CN105204257A - 一种esd保护单元、阵列基板、液晶面板及显示装置 - Google Patents

一种esd保护单元、阵列基板、液晶面板及显示装置 Download PDF

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CN105204257A
CN105204257A CN201510746641.6A CN201510746641A CN105204257A CN 105204257 A CN105204257 A CN 105204257A CN 201510746641 A CN201510746641 A CN 201510746641A CN 105204257 A CN105204257 A CN 105204257A
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曹昆
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BOE Technology Group Co Ltd
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Abstract

本发明公开一种ESD保护单元、阵列基板、液晶面板及显示装置，涉及液晶显示技术领域，以解决阵列基板制备过程中ESD保护效果差的问题。该ESD保护单元包括薄膜晶体管、栅极线以及数据线；薄膜晶体管的栅极裸露在数据线和栅极线所形成的区域，薄膜晶体管的源极与数据线相连，薄膜晶体管的漏极与栅极线相连；或薄膜晶体管的源极与栅极线相连，薄膜晶体管的漏极与数据线相连。液晶显示面板包括上含有该ESD保护单元的阵列基板，且各ESD保护单元中薄膜晶体管的栅极与直流负电压源相连。本发明提供的ESD保护单元用于显示装置中。

Description

一种ESD保护单元、阵列基板、液晶面板及显示装置
技术领域
本发明涉及液晶显示技术领域，尤其涉及一种ESD保护单元、阵列基板、液晶面板及显示装置。
背景技术
目前，液晶面板的制作工艺主要包括阵列基板制备工艺、液晶盒制备工艺以及模块组装工艺三个过程。其中，在阵列基板制备工艺中，由于需要不断传送玻璃基板和在玻璃基板上制备薄膜晶体管；因此，在传送玻璃基板和在玻璃基板上制备薄膜晶体管的过程中玻璃基板会不断地被摩擦、移动，从而持续产生静电；而且，由于玻璃基板为绝缘体，在阵列基板制备工艺中产生的静电散逸速度缓慢，所以，与液晶盒制备工艺和模块组装工艺相比，阵列基板制备工艺中更容易出现静电释放(又称为Electro-Staticdischarge，简称ESD)的问题；尤其是在阵列基板制备过程中，采用等离子体增强化学气相沉积法成膜和干法刻蚀时，阵列基板上的走线中更容易收集到大量电荷，从而与相邻的走线之间发生击穿，造成短路或断路，影响了阵列基板的良率，因此，需要在阵列基板走线间设置ESD保护单元，以提高阵列基板良率。
现有的ESD保护单元一般是将接成二极管的薄膜晶体管反向连接在具有电压差的相邻走线之间，或者在具有电压差的相邻走线之间引入与避雷针原理相同的结构。经过实践证明，这些ESD保护单元在某种程度上可以起到一定的保护作用，但是由于具有电压差的相邻走线之间不能发生相互串扰，因此，即使在具有电压差的相邻走线之间设置了ESD保护单元，ESD保护单元泄放的电流也往往比较有限，导致ESD保护效果差。
发明内容
本发明的目的在于提供一种ESD保护单元、阵列基板、液晶面板及显示装置，以解决阵列基板制备过程中ESD保护效果差的问题。
为了实现上述目的，本发明提供如下技术方案：
一种ESD保护单元，包括薄膜晶体管、栅极线以及数据线，所述薄膜晶体管的栅极裸露在数据线和栅极线所形成的与像素单元对应的区域，以收集所述数据线和所述栅极线之间产生的电荷；
其中，所述薄膜晶体管的源极与所述数据线相连，所述薄膜晶体管的漏极与所述栅极线相连；或
所述薄膜晶体管的源极与所述栅极线相连，所述薄膜晶体管的漏极与所述数据线相连。
优选的，所述薄膜晶体管为顶栅型薄膜晶体管。
本发明还提供了一种阵列基板，包括多个上述技术方案所述ESD保护单元，各所述ESD保护单元中，所述薄膜晶体管的栅极与用于使所述薄膜晶体管保持关闭的直流负电压源相连。
优选的，所述薄膜晶体管的栅极通过半导体走线连接在的焊盘上，所述焊盘与所述直流负电压源相接。
较佳的，所述半导体走线为ITO走线。
优选的，所述直流负电压源由与所述阵列基板相连的集成电路提供。
本发明还提供了一种液晶显示面板，包括上述技术方案所述的阵列基板。
本发明还提供了一种显示装置，包括上述技术方案所述的液晶面板。
与现有技术相比，本发明具有以下有益效果：
本发明提供的ESD保护单元中，薄膜晶体管的栅极裸露在数据线和栅极线所形成的与像素单元对应的区域，因此，当数据线和栅极线之间未产生静电释放时，薄膜晶体管处在关闭状态；当数据线和栅极线之间产生静电释放时，薄膜晶体管的栅极就能够收集静电释放产生的电荷，使原来关闭的薄膜晶体管开启，从而释放积累在相邻走线的电荷，减小压差，降低击穿机率，从而从根本上解决阵列基板制备过程中ESD保护效果差的问题。
附图说明
此处所说明的附图用来提供对本发明的进一步理解，构成本发明的一部分，本发明的示意性实施例及其说明用于解释本发明，并不构成对本发明的不当限定。在附图中：
图1为本发明实施例提供的ESD保护单元的结构示意图；
图2为本发明实施例提供的阵列基板的结构示意图；
附图标记：
1-第一引线，2-第二引线，3-薄膜晶体管。
具体实施方式
为了进一步说明本发明实施例提供的ESD保护单元、阵列基板、液晶面板及显示装置，下面结合说明书附图进行详细描述。
请参阅图1，本发明实施例提供的ESD保护单元，包括薄膜晶体管3、第一引线1和第二引线2，第一引线1和第二引线2之间具有电压差；其中，薄膜晶体管的源极与第一引线相连，薄膜晶体管的漏极与第二引线相连，薄膜晶体管的栅极表面裸露在第一引线1和第二引线2之间所形成的与像素单元对应的区域，以收集第一引线1和第二引线2之间产生的电荷。
而且，第一引线1作为数据线或栅极线均是由实际情况决定的。因此，实施例中的第一引线1为数据线，第二引线2为栅极线；或，第一引线为栅极线1，第二引线2为数据线。
为了便于说明，下面以第一引线1为数据线，第二引线2为栅极线时的ESD保护单元为例，对本实施例中的ESD保护单元的使用方法进行说明。
使用时，当数据线和栅极线之间发生静电释放，栅极吸收静电释放所产生的电荷，使薄膜晶体管3导通，从而收集静电释放所产生的电荷，以泄放的因静电释放所产生的电流。
从上述使用过程可以看出，本实施例提供的ESD保护单元中，薄膜晶体管的栅极裸露在数据线和栅极线之间所形成的与像素单元对应的区域，因此，当数据线和栅极线之间未产生静电释放时，薄膜晶体管处在关闭状态；当数据线和栅极线之间产生静电释放时，栅极就能够收集静电释放所述产生的电荷，使原来关闭的薄膜晶体管开启，从而释放积累在相邻走线之间的电荷，减小压差，降低击穿机率，从而从根本上解决了阵列基板制备过程中ESD保护效果差的问题。
为了便于使薄膜晶体管的栅极能够方便的收集静电释放所产生的电荷，上述薄膜晶体管为顶栅型薄膜晶体管或底栅型薄膜晶体管。由于顶栅型薄膜晶体管的栅极位于顶部，因此，相对于底栅型薄膜晶体管，这种顶栅型薄膜晶体管更容易使栅极金属裸露。
请参阅图2，本发明实施例还提供了一种阵列基板，包括多个ESD保护单元，各上述技术方案所述ESD保护单元中，薄膜晶体管的栅极与用于使薄膜晶体管保持关闭的直流负电压源相连。
使用时，在数据线和栅极线之间未发生静电释放时，薄膜晶体管3的栅极通过直流负电压源提供的负电压使薄膜晶体管3保持关闭状态，当数据线和栅极线之间发生静电释放时，薄膜晶体管3的栅极吸收静电释放所产生的电荷，使薄膜晶体管3导通从而收集静电释放的电荷，泄放的因静电释放所产生的电流。
从上述使用过程可知，由于薄膜晶体管的栅极是与用于使薄膜晶体管保持关闭的直流负电压源相连的，因此，在没有静电释放现象发生时，薄膜晶体管处于关闭状态，避免了相邻信号线之间发生串扰。而当栅极线和源极线之间发生静电释放时，由于薄膜晶体管3的栅极裸露在数据线和栅极线所形成的与像素单元对应的区域，因此，栅极能够吸收静电释放所产生的电荷，使薄膜晶体管3瞬间导通，以泄放了数据线和栅极线之间因静电释放所产生的电流。
为了便于薄膜晶体管3的栅极连接在直流负电压源上，上述实施例中薄膜晶体管3的栅极通过半导体走线连接在的焊盘上，焊盘与直流负电压源相接。焊盘可以是阵列基板上与直流负电压源相连的焊盘，也可以是重新制作的焊盘，只要该焊盘能够保证半导体走线和直流负电压源的连接即可；另外焊盘的材料可以选择泪滴式焊盘、多边形焊盘或椭圆形焊盘；其中优选泪滴式焊盘，以适应较细的半导体走线与直流负电压源的连接，而且，由于采用较细的半导体走线，因此，阵列基板的重量也相对减轻。
进一步，半导体走线为ITO走线，但半导体走线的种类很多，只要能够传输电流即可，不仅限于此。
另外，上述实施例中的直流负电压源由与阵列基板相连的集成电路提供，采用与阵列基板相连的集成电路提供直流负电压源，这样能够减少成本，不用重新设置直流负电压源，减少了成本。
本发明实施例还提供了一种液晶面板，包括上述技术方案的阵列基板。
与现有技术相比，本实施例提供的液晶面板的有益效果与上述阵列基板的有益效果相同，此处不再赘述。
本发明实施例还提供了一种显示装置，包括上述技术方案液晶面板。
与现有技术相比，本实施例提供的显示装置的有益效果与上述阵列基板的有益效果相同，此处不再赘述。
在上述实施方式的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。

Claims (8)

1.一种ESD保护单元，其特征在于，包括薄膜晶体管、栅极线以及数据线，所述薄膜晶体管的栅极裸露在数据线和栅极线所形成的与像素单元对应的区域，以收集所述数据线和所述栅极线之间产生的电荷；
其中，所述薄膜晶体管的源极与所述数据线相连，所述薄膜晶体管的漏极与所述栅极线相连；或
所述薄膜晶体管的源极与所述栅极线相连，所述薄膜晶体管的漏极与所述数据线相连。
2.根据权利要求1所述的ESD保护单元，其特征在于，所述薄膜晶体管为顶栅型薄膜晶体管。
3.一种阵列基板，其特征在于，包括多个如权利要求1～2中任意一种所述ESD保护单元，各所述ESD保护单元中，所述薄膜晶体管的栅极与用于使所述薄膜晶体管保持关闭的直流负电压源相连。
4.根据权利要求3所述的阵列基板，其特征在于，各所述ESD保护单元中，所述薄膜晶体管的栅极通过半导体走线连接在的焊盘上，所述焊盘与所述直流负电压源连接。
5.根据权利要求4所述的阵列基板，其特征在于，所述半导体走线为ITO走线。
6.根据权利要求3-5中任一项所述的阵列基板，其特征在于，所述直流负电压源由与所述阵列基板相连的集成电路提供。
7.一种液晶面板，其特征在于，包括如权利要求3-6中任意一项所述的阵列基板。
8.一种显示装置，其特征在于，包括如权利要求7所述的液晶面板。
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