WO2019061920A1 - 电路板电镀方法 - Google Patents

电路板电镀方法 Download PDF

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Publication number
WO2019061920A1
WO2019061920A1 PCT/CN2017/120109 CN2017120109W WO2019061920A1 WO 2019061920 A1 WO2019061920 A1 WO 2019061920A1 CN 2017120109 W CN2017120109 W CN 2017120109W WO 2019061920 A1 WO2019061920 A1 WO 2019061920A1
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Prior art keywords
plating
hard gold
circuit board
gold thickness
target value
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PCT/CN2017/120109
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English (en)
French (fr)
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邱勇萍
宫立军
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广州兴森快捷电路科技有限公司
深圳市兴森快捷电路科技股份有限公司
宜兴硅谷电子科技有限公司
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Publication of WO2019061920A1 publication Critical patent/WO2019061920A1/zh

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing the conductive pattern

Definitions

  • the present invention relates to the field of circuit board production technology, and in particular to a circuit board plating method.
  • the customer In the process of producing the circuit board, the customer has certain requirements for the thickness of the electroplated hard gold. Affected by the distribution of the power line, the current in the isolated DUT (semiconductor device) region on the circuit board is concentrated, resulting in an excessively large hard gold thickness in the DUT region, which is prone to undesirable gold seepage. However, the hard gold thickness of the TC (transistor unit) is often insufficient to meet the production requirements.
  • the present invention overcomes the deficiencies of the prior art and provides a method for electroplating a circuit board, on the one hand, avoiding the occurrence of gold in the DUT region, and on the other hand, ensuring that the hard gold thickness of the TC position is sufficient.
  • a circuit board plating method comprising the following steps:
  • step S40 measuring the hard gold thickness of the DUT area and the TC bit, if the hard gold thickness of the DUT area is greater than the target value K, and the hard gold thickness of the TC bit is less than the target value K, step S50 is performed;
  • S50 providing an anti-plating protection layer on the DUT area
  • S70 The hard gold thickness of the TC bit is measured. If the hard gold thickness of the TC bit is greater than the target value K, a subsequent production step is performed.
  • the first plating of the circuit board is first performed so that the hard gold thickness of the DUT region satisfies the production requirement, and then an anti-plating protective layer is disposed on the DUT region to avoid re-plating, and finally the second plating of the circuit board is performed.
  • the hard gold thickness of the TC position meets the production requirements. In this way, it is possible to avoid the occurrence of gold seepage in the DUT region, and to ensure that the hard gold thickness of the TC bit is sufficient, and the plating effect is good.
  • step S40 if the hard gold thickness of the DUT region is less than the target value K, and the hard gold thickness of the TC bit is less than the target value K, step S30 is re-executed.
  • the first plating can be performed multiple times, and the first plating of the board is performed until the hard gold thickness of the DUT area meets the production requirements to ensure the plating quality.
  • step S40 if the hard gold thickness of the DUT region is greater than the target value K and the hard gold thickness of the TC bit is greater than the target value K, a subsequent production step is performed.
  • the subsequent production steps are performed, and the second plating is not performed to avoid over-plating.
  • step S20 the following steps are further included:
  • S21 measuring an area S1 of the DUT area and an area S2 of the TC bit. If the ratio of S2 to S1 is less than a preset value, performing a subsequent production step after performing step S30.
  • the electroplating is performed by performing the first electroplating, and the electroplating efficiency is improved without performing the second electroplating.
  • the preset value is 25-35. If the preset value is too large, some boards with larger DUT area and TC bit area will not be plated for the second time, and the DUT area is prone to gold seepage. The hard gold thickness of the TC position is not easy; if the preset value is too Small, some boards with smaller DUT area and TC bit area need to be electroplated a second time, and the plating efficiency is low.
  • the preset value is 30.
  • the preset value is 30 is a preferred value. If the ratio of S2 to S1 is greater than 30, the second plating is performed to complete the plating; if the ratio of S2 to S1 is less than 30, the first plating is performed to complete the plating, and the second time is not performed. plating.
  • step S70 if the hard gold thickness of the TC bit is smaller than the target value K, step S60 is re-executed.
  • the second plating can be performed multiple times, and the second plating of the board is performed until the hard gold thickness of the TC position meets the production requirements to ensure the plating quality.
  • step S30 specifically includes the following steps:
  • the first plating parameter is calculated based on the hard gold thickness target value K, and the first plating is performed on the board using the first plating parameter.
  • the plating efficiency is improved by performing the first plating to make the hard gold thickness of the DUT region meet the production requirements.
  • step S60 specifically includes the following steps:
  • the second plating parameter is calculated in combination with the hard gold thickness of the TC bit, and the second plating is performed on the circuit board using the second plating parameter.
  • the anti-electroplating protective layer is a peelable blue glue, has good plating resistance and strong toughness.
  • FIG. 1 is a schematic flow chart of a method for plating a circuit board according to an embodiment of the invention.
  • the circuit board plating method described in this embodiment includes the following steps:
  • the hard gold thickness target value K should be set on the basis of customer requirements.
  • S21 measuring an area S1 of the DUT area and an area S2 of the TC bit. If the ratio of S2 to S1 is less than a preset value, performing a subsequent production step after performing step S30.
  • the electroplating is performed by performing the first electroplating, and the electroplating efficiency is improved without performing the second electroplating.
  • the preset value is 25-35. If the preset value is too large, some boards with larger DUT area and TC bit area will not be plated for the second time, and the DUT area is prone to gold seepage. The hard gold thickness of the TC position is not easy; if the preset value is too Small, some boards with smaller DUT area and TC bit area need to be electroplated a second time, and the plating efficiency is low.
  • the preset value is 30.
  • the preset value is 30 is a preferred value. If the ratio of S2 to S1 is greater than 30, the second plating is performed to complete the plating; if the ratio of S2 to S1 is less than 30, the first plating is performed to complete the plating, and the second time is not performed. plating.
  • step S30 includes the following steps:
  • the first plating parameter is calculated based on the hard gold thickness target value K, and the first plating is performed on the board using the first plating parameter.
  • the plating efficiency is improved by performing the first plating to make the hard gold thickness of the DUT region meet the production requirements.
  • step S40 measuring the hard gold thickness of the DUT region and the TC bit. If the hard gold thickness of the DUT region is greater than the target value K, and the hard gold thickness of the TC bit is less than the target value K, step S50 is performed.
  • step S40 if the hard gold thickness of the DUT region is smaller than the target value K, and the hard gold thickness of the TC bit is smaller than the target value K, step S30 is re-executed.
  • the first plating can be done multiple times, and the first plating of the board is performed until the hard gold thickness of the DUT area meets the production requirements to ensure the quality of the plating.
  • step S40 if the hard gold thickness of the DUT region is greater than the target value K and the hard gold thickness of the TC bit is greater than the target value K, a subsequent production step is performed.
  • the subsequent production steps are performed, and the second plating is not performed to avoid over-plating.
  • S50 an anti-plating protection layer is disposed on the DUT area.
  • the anti-electroplating protective layer described in this embodiment is a peelable blue rubber, has good plating resistance and strong toughness.
  • step S60 includes the following steps:
  • the second plating parameter is calculated in combination with the hard gold thickness of the TC bit, and the second plating is performed on the circuit board using the second plating parameter.
  • S70 The hard gold thickness of the TC bit is measured. If the hard gold thickness of the TC bit is greater than the target value K, a subsequent production step is performed.
  • step S70 if the hard gold thickness of the TC bit is smaller than the target value K, step S60 is re-executed.
  • the second plating can be performed multiple times, and the second plating of the board is performed until the hard gold thickness of the TC position meets the production requirements to ensure the plating quality.
  • the first plating of the circuit board is first performed so that the hard gold thickness of the DUT region satisfies the production requirement, and then an anti-plating protective layer is disposed on the DUT region to avoid re-plating, and finally the second plating of the circuit board is performed.
  • the hard gold thickness of the TC position meets the production requirements. In this way, it is possible to avoid the occurrence of gold seepage in the DUT region, and to ensure that the hard gold thickness of the TC bit is sufficient, and the plating effect is good.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Electroplating Methods And Accessories (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

本发明涉及一种电路板电镀方法，包括以下步骤：S10：提供具有DUT区和TC位的电路板；S20：设定硬金厚度目标值K；S30：根据硬金厚度目标值K，对电路板进行第一次电镀；S40：测量DUT区和TC位的硬金厚度，若DUT区的硬金厚度大于目标值K，且TC位的硬金厚度小于目标值K，则执行步骤S50；S50：在DUT区上设置防电镀保护层；S60：根据硬金厚度目标值K，对电路板进行第二次电镀；S70：测量TC位的硬金厚度，若TC位的硬金厚度大于目标值K，则执行后续生产步骤。上述电路板电镀方法，既能避免DUT区出现渗金，又能保证TC位的硬金厚度足够，电镀效果好。

Description

电路板电镀方法 技术领域
本发明涉及电路板生产技术领域，特别是涉及一种电路板电镀方法。
背景技术
在生产电路板的过程中，客户对电镀硬金厚度有一定的要求。受电力线分布的影响，电路板上孤立的DUT(半导体器件)区电流集中，导致DUT区的硬金厚度过大，容易出现渗金的不良现象。而TC(晶体管单元)位的硬金厚度容易不足，无法满足生产要求。
发明内容
基于此，本发明在于克服现有技术的缺陷，提供一种电路板电镀方法，一方面避免DUT区出现渗金，另一方面保证TC位的硬金厚度足够。
一种电路板电镀方法，包括以下步骤：
S10：提供具有DUT区和TC位的电路板；
S20：设定硬金厚度目标值K；
S30：根据硬金厚度目标值K，对电路板进行第一次电镀；
S40：测量DUT区和TC位的硬金厚度，若DUT区的硬金厚度大于目标值K，且TC位的硬金厚度小于目标值K，则执行步骤S50；
S50：在DUT区上设置防电镀保护层；
S60：根据硬金厚度目标值K，对电路板进行第二次电镀；
S70：测量TC位的硬金厚度，若TC位的硬金厚度大于目标值K，则执行后续生产步骤。
上述电路板电镀方法，首先对电路板进行第一次电镀使得DUT区的硬金厚度满足生产要求，接着在DUT区上设置防电镀保护层避免再次电镀，最后对电路板进行第二次电镀使得TC位的硬金厚度满足生产要求。如此，既能避免DUT 区出现渗金，又能保证TC位的硬金厚度足够，电镀效果好。
进一步地，在步骤S40中，若DUT区的硬金厚度小于目标值K，且TC位的硬金厚度小于目标值K，则重新执行步骤S30。
第一次电镀可为多次，对电路板进行第一次电镀直至DUT区的硬金厚度满足生产要求，确保电镀质量。
进一步地，在步骤S40中，若DUT区的硬金厚度大于目标值K，TC位的硬金厚度大于目标值K，则执行后续生产步骤。
在对电路板进行第一次电镀后，若DUT区和的TC位的硬金厚度均满足生产要求，则执行后续生产步骤，不再进行第二次电镀，避免过电镀。
进一步地，在步骤S20和步骤S30之间，还包括以下步骤：
S21：测量DUT区的面积S1及TC位的面积S2，若S2与S1的比值小于预设值，则执行步骤S30后执行后续生产步骤。
当DUT区与TC位的面积之比较小时，通过进行第一次电镀完成电镀，不进行第二次电镀，提高电镀效率。
进一步地，所述预设值为25-35。若预设值过大，某些DUT区与TC位的面积之比较大的电路板不进行第二次电镀，DUT区容易出现渗金，TC位的硬金厚度容易不足；若预设值过小，某些DUT区与TC位的面积之比较小的电路板需要进行第二次电镀，电镀效率较低。
进一步地，所述预设值为30。预设值为30是优选值，若S2与S1的比值大于30，则进行第二次电镀完成电镀；若S2与S1的比值小于30，则进行第一次电镀完成电镀，不进行第二次电镀。
进一步地，在步骤S70中，若TC位的硬金厚度小于目标值K，则重新执行步骤S60。
第二次电镀可为多次，对电路板进行第二次电镀直至TC位的硬金厚度满足生产要求，确保电镀质量。
进一步地，步骤S30具体包括以下步骤：
根据硬金厚度目标值K计算第一电镀参数，使用第一电镀参数对电路板进 行第一次电镀。
如此，尽量通过进行一次第一次电镀使得DUT区的硬金厚度满足生产要求，提高电镀效率。
进一步地，步骤S60具体包括以下步骤：
根据硬金厚度目标值K，结合TC位的硬金厚度计算第二电镀参数，使用第二电镀参数对电路板进行第二次电镀。
如此，尽量通过进行一次第二次电镀使得TC位的硬金厚度满足生产要求，提高电镀效率。
进一步地，所述防电镀保护层为可剥蓝胶，抗镀效果好，韧性强。
附图说明
图1为本发明实施例所述的电路板电镀方法的流程示意图。
具体实施方式
为了便于理解本发明，下面将参照相关附图对本发明进行更全面的描述。附图中给出了本发明的较佳实施方式。但是，本发明可以以许多不同的形式来实现，并不限于本文所描述的实施方式。相反地，提供这些实施方式的目的是使对本发明的公开内容理解的更加透彻全面。
需要说明的是，当元件被称为“固定于”另一个元件，它可以直接在另一个元件上或者也可以存在居中的元件。当一个元件被认为是“连接”另一个元件，它可以是直接连接到另一个元件或者可能同时存在居中元件。相反，当元件被称作“直接在”另一元件“上”时，不存在中间元件。本文所使用的术语“垂直的”、“水平的”、“左”、“右”以及类似的表述只是为了说明的目的，并不表示是唯一的实施方式。
除非另有定义，本文所使用的所有的技术和科学术语与属于本发明的技术领域的技术人员通常理解的含义相同。本文中在本发明的说明书中所使用的术语只是为了描述具体的实施方式的目的，不是旨在于限制本发明。本文所使用 的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
结合图1所示，本实施例所述的电路板电镀方法，包括以下步骤：
S10：提供具有DUT区和TC位的电路板。
S20：设定硬金厚度目标值K。
硬金厚度目标值K应该在客户要求的基础上进行设定。
S21：测量DUT区的面积S1及TC位的面积S2，若S2与S1的比值小于预设值，则执行步骤S30后执行后续生产步骤。
当DUT区与TC位的面积之比较小时，通过进行第一次电镀完成电镀，不进行第二次电镀，提高电镀效率。
优选地，所述预设值为25-35。若预设值过大，某些DUT区与TC位的面积之比较大的电路板不进行第二次电镀，DUT区容易出现渗金，TC位的硬金厚度容易不足；若预设值过小，某些DUT区与TC位的面积之比较小的电路板需要进行第二次电镀，电镀效率较低。
在本实施例中，所述预设值为30。预设值为30是优选值，若S2与S1的比值大于30，则进行第二次电镀完成电镀；若S2与S1的比值小于30，则进行第一次电镀完成电镀，不进行第二次电镀。
S30：根据硬金厚度目标值K，对电路板进行第一次电镀。
具体地，步骤S30包括以下步骤：
根据硬金厚度目标值K计算第一电镀参数，使用第一电镀参数对电路板进行第一次电镀。
如此，尽量通过进行一次第一次电镀使得DUT区的硬金厚度满足生产要求，提高电镀效率。
S40：测量DUT区和TC位的硬金厚度，若DUT区的硬金厚度大于目标值K，且TC位的硬金厚度小于目标值K，则执行步骤S50。
在步骤S40中，若DUT区的硬金厚度小于目标值K，且TC位的硬金厚度小于目标值K，则重新执行步骤S30。
第一次电镀可为多次，对电路板进行第一次电镀直至DUT区的硬金厚度满 足生产要求，确保电镀质量。
在步骤S40中，若DUT区的硬金厚度大于目标值K，TC位的硬金厚度大于目标值K，则执行后续生产步骤。
在对电路板进行第一次电镀后，若DUT区和的TC位的硬金厚度均满足生产要求，则执行后续生产步骤，不再进行第二次电镀，避免过电镀。
S50：在DUT区上设置防电镀保护层。
本实施例所述的防电镀保护层为可剥蓝胶，抗镀效果好，韧性强。
S60：根据硬金厚度目标值K，对电路板进行第二次电镀。
具体地，步骤S60包括以下步骤：
根据硬金厚度目标值K，结合TC位的硬金厚度计算第二电镀参数，使用第二电镀参数对电路板进行第二次电镀。
如此，尽量通过进行一次第二次电镀使得TC位的硬金厚度满足生产要求，提高电镀效率。
S70：测量TC位的硬金厚度，若TC位的硬金厚度大于目标值K，则执行后续生产步骤。
在步骤S70中，若TC位的硬金厚度小于目标值K，则重新执行步骤S60。
第二次电镀可为多次，对电路板进行第二次电镀直至TC位的硬金厚度满足生产要求，确保电镀质量。
上述电路板电镀方法，首先对电路板进行第一次电镀使得DUT区的硬金厚度满足生产要求，接着在DUT区上设置防电镀保护层避免再次电镀，最后对电路板进行第二次电镀使得TC位的硬金厚度满足生产要求。如此，既能避免DUT区出现渗金，又能保证TC位的硬金厚度足够，电镀效果好。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的 普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (10)

  1. 一种电路板电镀方法，其特征在于，包括以下步骤：
    S10：提供具有DUT区和TC位的电路板；
    S20：设定硬金厚度目标值K；
    S30：根据硬金厚度目标值K，对电路板进行第一次电镀；
    S40：测量DUT区和TC位的硬金厚度，若DUT区的硬金厚度大于目标值K，且TC位的硬金厚度小于目标值K，则执行步骤S50；
    S50：在DUT区上设置防电镀保护层；
    S60：根据硬金厚度目标值K，对电路板进行第二次电镀；
    S70：测量TC位的硬金厚度，若TC位的硬金厚度大于目标值K，则执行后续生产步骤。
  2. 根据权利要求1所述的电路板电镀方法，其特征在于，在步骤S40中，若DUT区的硬金厚度小于目标值K，且TC位的硬金厚度小于目标值K，则重新执行步骤S30。
  3. 根据权利要求1所述的电路板电镀方法，其特征在于，在步骤S40中，若DUT区的硬金厚度大于目标值K，TC位的硬金厚度大于目标值K，则执行后续生产步骤。
  4. 根据权利要求1所述的电路板电镀方法，其特征在于，在步骤S20和步骤S30之间，还包括以下步骤：
    S21：测量DUT区的面积S1及TC位的面积S2，若S2与S1的比值小于预设值，则执行步骤S30后执行后续生产步骤。
  5. 根据权利要求4所述的电路板电镀方法，其特征在于，所述预设值为25-35。
  6. 根据权利要求5所述的电路板电镀方法，其特征在于，所述预设值为30。
  7. 根据权利要求1所述的电路板电镀方法，其特征在于，在步骤S70中，若TC位的硬金厚度小于目标值K，则重新执行步骤S60。
  8. 根据权利要求1所述的电路板电镀方法，其特征在于，步骤S30具体包括以下步骤：
    根据硬金厚度目标值K计算第一电镀参数，使用第一电镀参数对电路板进行第一次电镀。
  9. 根据权利要求8所述的电路板电镀方法，其特征在于，步骤S60具体包括以下步骤：
    根据硬金厚度目标值K，结合TC位的硬金厚度计算第二电镀参数，使用第二电镀参数对电路板进行第二次电镀。
  10. 根据权利要求1所述的电路板电镀方法，其特征在于，所述防电镀保护层为可剥蓝胶。
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