WO2019052290A1 - 一种薄膜晶体管制作方法、薄膜晶体管及背板、显示设备 - Google Patents

一种薄膜晶体管制作方法、薄膜晶体管及背板、显示设备 Download PDF

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WO2019052290A1
WO2019052290A1 PCT/CN2018/099527 CN2018099527W WO2019052290A1 WO 2019052290 A1 WO2019052290 A1 WO 2019052290A1 CN 2018099527 W CN2018099527 W CN 2018099527W WO 2019052290 A1 WO2019052290 A1 WO 2019052290A1
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layer
region
film transistor
thin film
regions
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PCT/CN2018/099527
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English (en)
French (fr)
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王治
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京东方科技集团股份有限公司
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Priority to US16/335,081 priority Critical patent/US10804405B2/en
Publication of WO2019052290A1 publication Critical patent/WO2019052290A1/zh

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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78609—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing leakage current
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
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    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78663—Amorphous silicon transistors
    • H01L29/78666—Amorphous silicon transistors with normal-type structure, e.g. with top gate
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78663—Amorphous silicon transistors
    • H01L29/78669—Amorphous silicon transistors with inverted-type structure, e.g. with bottom gate
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78678—Polycrystalline or microcrystalline silicon transistor with inverted-type structure, e.g. with bottom gate
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    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
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    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
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    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays

Definitions

  • the present disclosure generally relates to display technologies, and in particular, to a thin film transistor, and more particularly to a method of fabricating a thin film transistor, a thin film transistor and a back sheet, and a display device.
  • the structure of a TFT includes a Gate metal layer and a GI (gate insulation) disposed on the Gate metal layer.
  • the p-Si (polysilicon) layer provided on the GI layer has a large mobility and fewer defects, so that electrons easily pass through the channel even in the off state, thus causing leakage current. Larger.
  • a layer of a-Si amorphous silicon may be deposited thereon, and then the subsequent fabrication is performed, thus adding an a-Si layer.
  • the production steps increase the complexity of the process.
  • the p-Si layer is fabricated by MLA regionalized laser annealing technology.
  • the laser source beam selectively performs high-position precision laser annealing of a-Si in the TFT channel region through MLA (Micro Lens Array) Mask to form p. -Si.
  • MLA Micro Lens Array
  • This technology is also known as PLAS (Partial Laser Anneal Silicon) or SLA (Selective Laser-Annealing).
  • the mobility of the prepared TFT is 5-20cm2/V ⁇ s, which is 10-50 times of the a-Si mobility. Meet the backplane requirements of an AMOLED (Active-matrix organic light emitting diode).
  • AMOLED Active-matrix organic light emitting diode
  • the laser effective spot length is about 1000 micrometers, that is, the effective channel length of the fabricated TFT is 1000 micrometers, and the GOA (Gate driver On Array) of the AMOLED backplane is driven.
  • the design requirements must achieve >1500 micron large-channel TFTs, so it is difficult to achieve mass production due to the limitation of the laser effective spot length.
  • the TFT has a large leakage current.
  • a layer of a-Si layer needs to be fabricated, and the process complexity is high.
  • the process is more difficult.
  • an embodiment of the present disclosure provides a thin film transistor including: a gate, a source, a drain, a dielectric layer, and
  • the active layer includes an a-Si region, and the a-Si region is disposed at a center of the active layer.
  • the active layer includes at least two a-Si regions symmetrically disposed with respect to a central axis of the source and the drain.
  • each a-Si region and p-Si region in the active layer are disposed in series.
  • the active layer comprises 2 or 4 a-Si regions and 3 p-Si regions; or
  • the active layer includes 4 or 6 a-Si regions and 5 p-Si regions.
  • the dielectric layer is a gate insulating layer
  • the thin film transistor further includes:
  • the dielectric layer is a buffer layer
  • the thin film transistor further includes:
  • each of the p-Si regions has a length of 2 ⁇ m to 1000 ⁇ m;
  • Each side of each a-Si region has a length greater than or equal to 2 microns.
  • an embodiment of the present disclosure further provides a method for fabricating a thin film transistor, the method comprising:
  • Laser irradiation is performed at one or more locations on the a-Si layer to form a polysilicon p-Si region and to retain at least one a-Si region that is not irradiated with laser light.
  • the a-Si region is disposed at a center of the active layer when an a-Si region not irradiated with laser light is retained;
  • the a-Si region is symmetrically disposed with respect to the central axes of the source and the drain when at least two a-Si regions that are not irradiated with laser light are retained.
  • each a-Si region and p-Si region in the active layer are disposed in series.
  • laser irradiation is performed at one or more locations on the a-Si layer to form a p-Si region, and at least one a-Si region not irradiated with laser light is retained, specifically:
  • Laser irradiation was performed at five positions on the a-Si layer to form a p-Si region, and 4 or 6 a-Si regions not irradiated with laser light were left.
  • the dielectric layer is a gate insulating layer
  • laser irradiation is performed at one or more positions on the a-Si layer to form a polysilicon p-Si region, and at least one is not irradiated with laser light.
  • the a-Si area it also includes:
  • a heavily doped amorphous silicon layer is directly formed on the silicon oxide layer.
  • each of the p-Si regions has a length of 2 ⁇ m to 1000 ⁇ m;
  • Each side of each a-Si region has a length greater than or equal to 2 microns.
  • an embodiment of the present disclosure further provides a backplane, including the thin film transistor described in the first aspect.
  • an embodiment of the present disclosure further provides a display device, including the thin film transistor described in the first aspect.
  • FIG. 1 is a schematic cross-sectional view showing a structure of a thin film transistor in the related art
  • FIG. 2 is a schematic cross-sectional view showing a structure of a thin film transistor according to an embodiment of the present disclosure
  • FIG. 3 to FIG. 8 are schematic top views of a specific thin film transistor structure according to an embodiment of the present disclosure.
  • FIG. 9 is a schematic structural diagram of a thin film transistor of a top gate structure according to an embodiment of the present disclosure.
  • FIG. 10 is a flow chart of a method for fabricating a thin film transistor according to an embodiment of the present disclosure.
  • FIG. 1 is a schematic cross-sectional view showing a structure of a thin film transistor including a Gate metal layer, a GI (gate insulating) layer provided on a Gate metal layer, and p-Si (polysilicon) provided on the GI layer. )Floor.
  • FIG. 2 is a thin film transistor according to an embodiment of the present disclosure.
  • the thin film transistor includes a gate 200, a source 203, a drain 204, a dielectric layer 201, and an active layer 202 disposed on the dielectric layer 201.
  • the active layer 202 includes at least one a-Si region 2021 and at least A p-Si region 2022.
  • p-Si has a large mobility and few defects, and a-Si has many defects, strong blocking ability to electrons, and large resistance.
  • the a-Si region 2021 is provided in the active layer 202, which corresponds to a large resistance connected in series in the middle of the channel, thereby reducing leakage current.
  • the p-Si region 2022 is formed by laser irradiation in a partial region in the channel.
  • laser irradiation can be performed in a plurality of regions to form a plurality of p-Si regions 2022 having a channel width and
  • the length is not limited by the effective spot length of the laser, which reduces the process difficulty of the large-channel TFT.
  • Each of the a-Si regions 2021 and the p-Si regions 2022 may be arranged in an arbitrary manner as long as the active layer 202 has the a-Si region 2021 and the p-Si region 2022.
  • an a-Si region 2021 is included in the active layer, it is preferable to arrange the a-Si region 2021 at the center of the active layer.
  • the a-Si region 2021 is preferably symmetrically disposed with respect to the central axes of the source 203 and the drain 204.
  • the a-Si region 2021 is symmetrically disposed with respect to the central axes of the source electrode 203 and the drain electrode 204, when a thin film transistor is used, the electric field formed is symmetrical, thereby improving the stability of the thin film transistor.
  • the a-Si region 2021 is symmetrically disposed with respect to the central axes of the source 203 and the drain 204, and the broken lines in FIGS. 3 and 4 are the central axes of the source 203 and the drain 204.
  • Each of the a-Si regions 2021 and the p-Si regions 2022 in the active layer 202 may be disposed in series as shown in FIG. At this time, the width of each of the a-Si region 2021 and the p-Si region 2022 is equal to the width of the active layer 202. Since each of the a-Si region 2021 and the p-Si region 2022 are in a series relationship, the leakage current in the active layer 202 can be effectively reduced. At the same time, the structure of the active layer 202 is relatively simple and the effect is relatively controllable.
  • the active layer 202 may include two a-Si regions 2021 and three p-Si regions 2022; or
  • the active layer 202 may include four a-Si regions 2021 and three p-Si regions 2022;
  • the active layer includes four a-Si regions 2021 and five p-Si regions 2022;
  • the active layer includes six a-Si regions 2021 and five p-Si regions 2022.
  • the dielectric layer 201 may be a gate insulating layer in the bottom gate structure or a buffer layer in the top gate structure.
  • the dielectric layer 201 is specifically a gate insulating layer, and
  • the thin film transistor further includes:
  • the silicon oxide layer 205 may be a silicon dioxide material or a silicon oxide material.
  • the heavily doped amorphous silicon layer 206 may be an electron conductive type (N + ) heavily doped amorphous silicon layer or a hole conductive type (P + ) heavily doped amorphous silicon layer.
  • a second layer of a-Si can no longer be disposed on the silicon oxide layer 205.
  • the directly doped heavily doped amorphous silicon layer 206 reduces the fabrication process of the second a-Si layer and reduces process complexity.
  • the second layer a-Si layer may not be disposed, thereby reducing the manufacturing process and reducing the process complexity.
  • the thin film transistor includes a gate electrode 200, a source electrode 203, a drain electrode 204, a dielectric layer 201, and an active layer disposed on the dielectric layer 201.
  • the active layer 202 includes at least one a-Si region 2021 and at least one p-Si region 2022.
  • the thin film transistor further includes a silicon oxide layer 205 disposed on the active layer 202, the gate electrode 200 is disposed on the silicon oxide layer 205, and the dielectric layer 207 is disposed on the gate electrode.
  • the source 203 and the drain 204 are connected to the active layer 202 through via holes.
  • the p-Si region 2022 is formed by laser irradiation in a partial region in the channel.
  • laser irradiation may be performed in a plurality of regions to form a plurality of p-Si regions 2022.
  • the laser effective spot is a rectangle having a length of less than 1000 micrometers per side. Therefore, it is preferable that each side of each p-Si region has a length of less than or equal to 1000 ⁇ m.
  • each side of each p-Si region and a-Si region is longer than or equal to 2 micrometers. Therefore, the length of each side of each p-Si region is from 2 micrometers to 1000 micrometers, and the length of each side of each a-Si region is preferably greater than or equal to 2 micrometers.
  • each side of the p-Si region is 2 micrometers to 1000 micrometers, which is smaller than the length of the effective laser spot length of the general laser, mass production of the TFT is facilitated.
  • Multiple p-Si regions and a-Si regions are alternately connected in series, and TFTs of any length and width channel can be fabricated.
  • the channel length and width of the TFT are no longer limited by the effective spot length of the laser, so the W/L of the channel
  • the (width-to-length ratio) value is no longer limited by the laser effective spot length, and a TFT having an arbitrary W/L value can be fabricated.
  • the embodiment of the present disclosure further provides a method for manufacturing a thin film crystal tube. As shown in FIG. 10, the method includes:
  • Step S901 forming an a-Si layer on the dielectric layer
  • Step S902 laser irradiation is performed at one or more positions on the a-Si layer to form a p-Si region, and at least one a-Si region not irradiated with laser light is retained.
  • the a-Si region is disposed at the center of the active layer.
  • the a-Si region is symmetrically disposed with respect to the central axes of the source and the drain.
  • the a-Si region is symmetrically disposed with respect to the central axes of the source and the drain, when the thin film transistor is used, the electric field formed is symmetrical, thereby improving the stability of the thin film transistor.
  • the a-Si region is symmetrically disposed with respect to the central axes of the source and the drain.
  • each a-Si region and p-Si region in the active layer are arranged in series, i.e., the width of each of the a-Si region and the p-Si region is equal to the width of the active layer.
  • step 902 laser irradiation is performed at one or more positions on the a-Si layer to form a p-Si region, and at least one a-Si region not irradiated with laser light is retained, specifically:
  • Laser irradiation is performed at three positions on the a-Si layer to form a p-Si region, and two or four a-Si regions not irradiated with laser light are left to form a thin film transistor as shown in FIG. 5 or FIG. 6;
  • Laser irradiation is performed at five positions on the a-Si layer to form a p-Si region, and 4 or 6 a-Si regions not irradiated with laser light are left to form an active layer structure as shown in FIG. 7 or FIG. .
  • the dielectric layer may be a gate insulating layer in the bottom gate structure or a buffer layer in the top gate structure.
  • the dielectric layer is specifically a gate insulating layer.
  • a heavily doped amorphous silicon layer is directly formed on the silicon oxide layer.
  • the silicon oxide layer 205 may be a silicon dioxide material or a silicon oxide material.
  • the heavily doped amorphous silicon layer 206 may be an electron conductive type (N + ) heavily doped amorphous silicon layer or a hole conductive type (P + ) heavily doped amorphous silicon layer.
  • the SD layer is usually formed on the heavily doped amorphous silicon layer after the heavily doped amorphous silicon layer is formed.
  • the fabrication of the second layer a-Si layer is also reduced, thereby reducing the fabrication process and reducing the process complexity.
  • the second layer of a-Si layer is not required, and the heavily doped amorphous silicon layer can be directly formed, the fabrication process of the second layer a-Si layer is reduced, and the process complexity is reduced. .
  • each of the p-Si regions has a length of 2 ⁇ m to 1000 ⁇ m;
  • Each side of each a-Si region has a length greater than or equal to 2 microns.
  • each side of the p-Si region is 2 micrometers to 1000 micrometers, which is smaller than the length of the effective laser spot length of the general laser, mass production of the TFT is facilitated.
  • Multiple p-Si regions and a-Si regions are alternately connected in series to form TFTs of arbitrary length and width channels.
  • the TFT channel length and width are no longer limited by the laser effective spot length, so the W/L (width to length ratio) value of the channel is no longer limited by the effective laser spot length, and an arbitrary W/L TFT can be fabricated. .
  • the embodiment of the present disclosure further provides a backplane including the thin film transistor provided by the embodiment of the present disclosure.
  • the embodiment of the present disclosure further provides a display device, which includes the thin film transistor provided by the embodiment of the present disclosure.
  • Embodiments of the present disclosure provide a method of fabricating a thin film transistor, a thin film transistor and a backplane, and a display device.
  • the thin film transistor is provided with an active layer on a dielectric layer, the active layer including: at least one a-Si region and at least one In the p-Si region, in the active layer, p-Si has a large mobility and fewer defects, while a-Si has many defects, strong electron blocking ability, large resistance, and simultaneous presence in the active layer.
  • the a-Si region and the p-Si region which corresponds to a large resistance in series in the middle of the channel, reduce leakage current, and usually the p-Si region is formed by laser irradiation in a partial region of the channel, when the laser is effective
  • a plurality of p-Si regions can be formed by laser irradiation in a plurality of regions, and the channel width and length are not limited by the laser effective spot length, which reduces the process difficulty of the large-channel TFT.

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Abstract

本申请提供一种薄膜晶体管的制作方法、薄膜晶体管及背板、显示设备。该薄膜晶体管包括：栅极、源极、漏极、介电层，以及设置在所述介电层上的有源层，所述有源层包括至少一个非晶硅a-Si区域和至少一个多晶硅p-Si区域，降低了漏电流，并且，降低了大沟道TFT的工艺难度。

Description

一种薄膜晶体管制作方法、薄膜晶体管及背板、显示设备
相关申请的交叉引用
本申请主张在2017年9月15日在中国提交的中国专利申请号No.201710840881.1的优先权，其全部内容通过引用包含于此。
技术领域
本公开一般涉及显示技术，具体涉及一种薄膜晶体管，尤其涉及一种薄膜晶体管的制作方法、薄膜晶体管及背板、显示设备。
背景技术
在基于MLA(微透镜阵列技术)的AMOLED背板制作中，其TFT(Thin Film Transistor，是薄膜晶体管)的结构包括Gate(栅极)金属层、设置在Gate金属层上的GI(栅极绝缘)层、设置在GI层上的p-Si(多晶硅)层，由于p-Si的迁移率较大、缺陷较少，所以即使关闭状态下，电子也很容易通过沟道，所以会导致漏电流较大。为了降低漏电流，可以在形成p-Si和SiO 2岛后，在其上再沉积一层a-Si(非晶硅)层，进而再进行后续的制作，这样多了一个a-Si层的制作步骤，提高了工艺复杂度。
通常，p-Si层是通过MLA区域化激光退火技术制作的，激光源光束通过MLA(Micro Lens Array)Mask选择性对TFT沟道区域的a-Si进行高位置精度激光退火，使其形成p-Si。该技术又被称为PLAS(Partial Laser Anneal Silicon)或SLA(Selective Laser-Annealing)，该技术制备TFT迁移率在5-20cm2/V·s，是a-Si迁移率的10-50倍，可以满足AMOLED(Active-matrix organic light emitting diode，有源矩阵有机发光二极体)的背板要求。但是，由于激光器以及光路硬件的限制，激光有效光斑长度在1000微米左右，即所制作的TFT的有效沟道长度在1000微米，而对于AMOLED背板的GOA(Gate driver On Array，阵列基板行驱动)设计要求，必须要实现＞1500微米大沟道TFT，所以，由于激光有效光斑长度的限制，难以实现量产。
可见，目前的基于MLA的AMOLED背板中，其TFT制作漏电流较大， 若要降低漏电流需要多一层a-Si层的制作，工艺复杂度较高，同时，由于激光有效光斑长度的限制，对于大沟道TFT，其工艺难度较高。
发明内容
第一方面，本公开实施例提供一种薄膜晶体管，所述薄膜晶体管包括：栅极、源极、漏极、介电层，以及
设置在介电层上的有源层，所述有源层包括：
至少一个非晶硅a-Si区域和至少一个多晶硅p-Si区域。
可选地，，所述有源层包括一个a-Si区域，所述a-Si区域设置在有源层的中心。
可选地，所述有源层包括至少两个a-Si区域，所述a-Si区域相对于源极和漏极的中轴线对称设置。
可选地，所述有源层中的各a-Si区域和p-Si区域串联设置。
可选地，所述有源层包括2或4个a-Si区域和3个p-Si区域；或者
所述有源层包括4或6个a-Si区域和5个p-Si区域。
可选地，，所述介电层为栅极绝缘层；
所述薄膜晶体管还包括：
设置在有源层上的氧化硅层，以及仅在所述氧化硅层与所述源极和所述漏极之间设置的重掺杂非晶硅层。
可选地，所述介电层为缓冲层；
所述薄膜晶体管还包括：
设置在有源层上的氧化硅层，以及在所述氧化硅层与所述源极和所述漏极之间并且在栅极之上设置的介质层。
优选地，每个p-Si区域各边边长均为2微米-1000微米；
每个a-Si区域各边边长均大于或等于2微米。
第二方面，本公开实施例还提供一种薄膜晶体管的制作方法，该方法包括：
在介电层上制作非晶硅a-Si层；
在所述a-Si层上的一个或多个位置进行激光照射，形成多晶硅p-Si区域， 并留存至少一个未经激光照射的a-Si区域。
可选地，当留存一个未经激光照射的a-Si区域时，所述a-Si区域设置在有源层的中心；
当留存至少两个未经激光照射的a-Si区域时，所述a-Si区域相对于源极和漏极的中轴线对称设置。
可选地，所述有源层中的各a-Si区域和p-Si区域串联设置。
可选地，在所述a-Si层上的一个或多个位置进行激光照射，形成p-Si区域，并留存至少一个未经激光照射的a-Si区域，具体为：
在所述a-Si层上的3个位置进行激光照射，形成p-Si区域，并留存2或4个未经激光照射的a-Si区域；或者
在所述a-Si层上的5个位置进行激光照射，形成p-Si区域，并留存4或6个未经激光照射的a-Si区域。
可选地，当所述介电层为栅极绝缘层时，在所述a-Si层上的一个或多个位置进行激光照射，形成多晶硅p-Si区域，并留存至少一个未经激光照射的a-Si区域之后，还包括：
制作氧化硅层；
在氧化硅层上直接制作重掺杂非晶硅层。
优选地，每个p-Si区域各边边长均为2微米-1000微米；
每个a-Si区域各边边长均大于或等于2微米。
第三方面，本公开实施例还相应提供一种背板，包括第一方面中所述的薄膜晶体管。
第四方面，本公开实施例还相应提供一种显示设备，包括第一方面中所述的薄膜晶体管。
附图说明
通过阅读参照以下附图所作的对非限制性实施例所作的详细描述，本申请的其它特征、目的和优点将会变得更明显：
图1为相关技术中薄膜晶体管结构截面示意图；
图2为本公开实施例提供的薄膜晶体管结构截面示意图；
图3-图8为本公开实施例提供的具体的薄膜晶体管结构俯视示意图；
图9为本公开实施例提供的顶栅结构的薄膜晶体管的结构示意图；
图10为本公开实施例提供的薄膜晶体管的制作方法流程图。
具体实施方式
下面结合附图和实施例对本申请作进一步的详细说明。可以理解的是，此处所描述的具体实施例仅仅用于解释相关公开，而非对该公开的限定。另外还需要说明的是，为了便于描述，附图中仅示出了与公开相关的部分。
需要说明的是，在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互组合。下面将参考附图并结合实施例来详细说明本申请。
图1为相关技术中薄膜晶体管结构截面示意图，该薄膜晶体管包括Gate(栅极)金属层、设置在Gate金属层上的GI(栅极绝缘)层、设置在GI层上的p-Si(多晶硅)层。
请参考图2，图2是本公开实施例提供的一种薄膜晶体管。该薄膜晶体管包括：栅极200、源极203、漏极204、介电层201，以及设置在介电层201上的有源层202，有源层202包括至少一个a-Si区域2021和至少一个p-Si区域2022。
在该薄膜晶体管的有源层202中，p-Si的迁移率较大、缺陷较少，而a-Si的缺陷多，对电子的阻挡能力强，电阻较大。在有源层202中设置有a-Si区域2021，即相当于在沟道中间串联了大电阻，降低了漏电流。通常，p-Si区域2022是在沟道中的部分区域进行激光照射形成的，当激光有效光斑长度较小时，可以在多个区域进行激光照射形成多个p-Si区域2022，其沟道宽度和长度均不受激光有效光斑长度的限制，降低了大沟道TFT的工艺难度。
各个a-Si区域2021和p-Si区域2022可以以任意方式排列，只要有源层202中，具有a-Si区域2021和p-Si区域2022即可。
进一步，在有源层中包括一个a-Si区域2021时，将a-Si区域2021设置在有源层的中心较佳。在有源层202中包括至少两个a-Si区域2021时，a-Si区域2021相对于源极203和漏极204的中轴线对称设置较佳。
由于a-Si区域2021相对于源极203和漏极204的中轴线对称设置，在使 用薄膜晶体管时，所形成的电场是对称的，进而提高薄膜晶体管的稳定性。
如图3和图4所示，a-Si区域2021相对于源极203和漏极204的中轴线对称设置，图3和图4中的虚线为源极203和漏极204的中轴线。
有源层202中的各a-Si区域2021和p-Si区域2022可以串联设置，如图5所示。此时，每个a-Si区域2021和p-Si区域2022的宽度均等于有源层202的宽度。由于各a-Si区域2021和p-Si区域2022是串联关系，可以有效地降低有源层202中的漏电流，同时，有源层202的结构比较简单，效果比较可控。
优选地，如图5所示，有源层202中可以包括2个a-Si区域2021和3个p-Si区域2022；或者，
如图6所示，有源层202中可以包括4个a-Si区域2021和3个p-Si区域2022；或者
如图7所示，有源层中包括4个a-Si区域2021和5个p-Si区域2022；或者
如图8所示，有源层中包括6个a-Si区域2021和5个p-Si区域2022。
在本公开实施例中，介电层201可以是底栅结构中的栅极绝缘层，也可以是顶栅结构中的缓冲层。当该薄膜晶体管是底栅结构的薄膜晶体管时，如图2所示，介电层201具体为栅极绝缘层，并且，
该薄膜晶体管还包括：
设置在有源层202上的氧化硅层205，以及在氧化硅层205上直接设置的重掺杂非晶硅层206。
氧化硅层205可以是二氧化硅材料，也可以是多氧化硅材料。
重掺杂非晶硅层206可以是电子导电类型(N +)重掺杂非晶硅层，也可以是空穴导电类型(P +)重掺杂非晶硅层。
可见，在氧化硅层205上可以不再设置第二层a-Si层。可直接设置的重掺杂非晶硅层206减少了第二层a-Si层的制作工艺，减小了工艺复杂度。
同样地，对于顶栅结构的TFT，也可以不再设置第二层a-Si层，进而减少制作工艺流程，减小工艺复杂度。如图9所示，在顶栅结构的薄膜晶体管中，所述薄膜晶体管包括：栅极200、源极203、漏极204、介电层201，以 及设置在介电层201上的有源层202。有源层202包括至少一个a-Si区域2021和至少一个p-Si区域2022。所述薄膜晶体管还包括：设置在有源层202上的氧化硅层205，栅极200设置在氧化硅层205上，栅极之上设置介质层207。源极203和漏极204通过过孔与有源层202连接。
进一步，在通常情况下，p-Si区域2022是在沟道中的部分区域进行激光照射形成的。当激光有效光斑长度较小时，可以在多个区域进行激光照射形成多个p-Si区域2022。一般激光有效光斑是每边边长均在1000微米以下的矩形，所以，每个p-Si区域各边边长均小于或等于1000微米较佳。为保证较好的串联效果，每个p-Si区域和a-Si区域的各边边长均大于或等于2微米。所以每个p-Si区域各边的长度为2微米-1000微米，每个a-Si区域各边的长度均大于或等于2微米较佳。
由于p-Si区域各边边长均为2微米-1000微米，小于一般的激光有效光斑边长长度，因此便于进行TFT量产。多个p-Si区域和a-Si区域交替串联组合，能够制作出任意长度和宽度沟道的TFT，TFT沟道长度和宽度不再受激光有效光斑长度的限制，所以沟道的W/L(宽长比)值也不再受激光有效光斑长度的限制，可以制作出任意W/L值的TFT。
本公开实施例还提供一种薄膜晶体的管制作方法，如图10所示，该方法包括：
步骤S901：在介电层上制作a-Si层；
步骤S902：在a-Si层上的一个或多个位置进行激光照射，形成p-Si区域，并留存至少一个未经激光照射的a-Si区域。
进一步，当留存一个未经激光照射的a-Si区域时，a-Si区域设置在有源层的中心。
当留存至少两个未经激光照射的a-Si区域时，a-Si区域相对于源极和漏极的中轴线对称设置。
由于a-Si区域相对于源极和漏极的中轴线对称设置，因此在使用薄膜晶体管时，所形成的电场是对称的，进而提高薄膜晶体管的稳定性。
如图3和图4所示，a-Si区域相对于源极和漏极的中轴线对称设置。
进一步，有源层中的各a-Si区域和p-Si区域串联设置，即，每个a-Si区 域和p-Si区域的宽度均等于有源层的宽度。
具体地，步骤902中，在a-Si层上的一个或多个位置进行激光照射，形成p-Si区域，并留存至少一个未经激光照射的a-Si区域，具体为：
在a-Si层上的3个位置进行激光照射，形成p-Si区域，并留存2或4个未经激光照射的a-Si区域，形成如图5或图6所示的薄膜晶体管；或者
在a-Si层上的5个位置进行激光照射，形成p-Si区域，并留存4或6个未经激光照射的a-Si区域，形成如图7或图8所示的有源层结构。
在本公开实施例中，介电层可以是底栅结构中的栅极绝缘层，也可以是顶栅结构中的缓冲层。当该薄膜晶体管是底栅结构的薄膜晶体管时，介电层具体为栅极绝缘层。此时，步骤S902，在a-Si层上的一个或多个位置进行激光照射，形成多晶硅p-Si区域，并留存至少一个未经激光照射的a-Si区域之后，还包括：
制作氧化硅层；
在氧化硅层上直接制作重掺杂非晶硅层。
通过上述步骤，即可形成如图2所示的薄膜晶体管。氧化硅层205可以是二氧化硅材料，也可以是多氧化硅材料。
重掺杂非晶硅层206可以是电子导电类型(N +)重掺杂非晶硅层，也可以是空穴导电类型(P +)重掺杂非晶硅层。
通常在制作重掺杂非晶硅层之后，在重掺杂非晶硅层上制作SD层。
同样地，对于顶栅结构的TFT，也减少了第二层a-Si层的制作，进而减少制作工艺流程，减小工艺复杂度。
可见，在制作氧化硅层后，不需要制作第二层a-Si层，可直接制作重掺杂非晶硅层，减少了第二层a-Si层的制作工艺，减小了工艺复杂度。
优选地，每个p-Si区域各边边长均为2微米-1000微米；
每个a-Si区域各边边长均大于或等于2微米。
由于p-Si区域各边边长均为2微米-1000微米，小于一般的激光有效光斑边长长度，便于进行TFT量产。多个p-Si区域和a-Si区域交替串联组合能够制作出任意长度和宽度沟道的TFT。TFT沟道长度和宽度不再受激光有效光斑长度的限制，所以沟道的W/L(宽长比)值也不再受激光有效光斑长度 的限制，可以制作出任意W/L值的TFT。
本公开实施例还相应提供一种背板，该背板中包括本公开实施例提供的薄膜晶体管。
本公开实施例还相应提供一种显示设备，该显示设备中包括本公开实施例提供的薄膜晶体管。
本公开实施例提供一种薄膜晶体管的制作方法、薄膜晶体管及背板、显示设备，该薄膜晶体管在介电层上设置有源层，该有源层包括：至少一个a-Si区域和至少一个p-Si区域，在有源层中，p-Si的迁移率较大、缺陷较少，而a-Si的缺陷多，对电子的阻挡能力强，电阻较大，在有源层中同时存在a-Si区域和p-Si区域，即相当于在沟道中间串联了大电阻，降低了漏电流，并且，通常p-Si区域是在沟道中的部分区域进行激光照射形成的，当激光有效光斑长度较小时，可以在多个区域进行激光照射形成多个p-Si区域，其沟道宽度和长度均不受激光有效光斑长度的限制，降低了大沟道TFT的工艺难度。
以上描述仅为本申请的较佳实施例以及对所运用技术原理的说明。本领域技术人员应当理解，本申请中所涉及的公开范围，并不限于上述技术特征的特定组合而成的技术方案，同时也应涵盖在不脱离所述公开构思的情况下，由上述技术特征或其等同特征进行任意组合而形成的其它技术方案。例如上述特征与本申请中公开的(但不限于)具有类似功能的技术特征进行互相替换而形成的技术方案。

Claims (17)

  1. 一种薄膜晶体管，包括：栅极、源极、漏极、介电层，以及
    设置在所述介电层上的有源层，所述有源层包括至少一个非晶硅a-Si区域和至少一个多晶硅p-Si区域。
  2. 如权利要求1所述的薄膜晶体管，其中，所述有源层包括一个a-Si区域，所述a-Si区域设置在所述有源层的中心。
  3. 如权利要求1所述的薄膜晶体管，其中，所述有源层包括至少两个a-Si区域，所述a-Si区域相对于源极和漏极的中轴线对称设置。
  4. 如权利要求1所述的薄膜晶体管，其中，所述有源层中的各a-Si区域和p-Si区域串联设置。
  5. 如权利要求4所述的薄膜晶体管，其中，所述有源层包括2或4个a-Si区域和3个p-Si区域；或者
    所述有源层包括4或6个a-Si区域和5个p-Si区域。
  6. 如权利要求1所述的薄膜晶体管，其中，所述介电层为栅极绝缘层；
    所述薄膜晶体管还包括：
    设置在有源层上的氧化硅层，以及仅在所述氧化硅层与所述源极和所述漏极之间设置的重掺杂非晶硅层。
  7. 如权利要求1所述的薄膜晶体管，其中，所述介电层为缓冲层；
    所述薄膜晶体管还包括：
    设置在有源层上的氧化硅层，以及在所述氧化硅层与所述源极和所述漏极之间并且在栅极之上设置的介质层。
  8. 如权利要求1所述的薄膜晶体管，其中，每个p-Si区域各边边长均为2微米-1000微米；
    每个a-Si区域的各边边长均大于或等于2微米。
  9. 一种薄膜晶体管的制作方法，包括：
    在介电层上制作非晶硅a-Si层；
    在所述非晶硅a-Si层上的一个或多个位置进行激光照射，形成多晶硅p-Si区域，并留存至少一个未经激光照射的a-Si区域。
  10. 如权利要求9所述的方法，其中，留存一个未经激光照射的a-Si区域，所述a-Si区域设置在有源层的中心。
  11. 如权利要求9所述的方法，其中，留存至少两个未经激光照射的a-Si区域，所述a-Si区域相对于源极和漏极的中轴线对称设置。
  12. 如权利要求9所述的方法，其中，所述有源层中的各a-Si区域和p-Si区域串联设置。
  13. 如权利要求12所述的方法，其中，在所述a-Si层上的一个或多个位置进行激光照射，形成p-Si区域，并留存至少一个未经激光照射的a-Si区域，具体为：
    在所述a-Si层上的3个位置进行激光照射，形成p-Si区域，并留存2或4个未经激光照射的a-Si区域；或者
    在所述a-Si层上的5个位置进行激光照射，形成p-Si区域，并留存4或6个未经激光照射的a-Si区域。
  14. 如权利要求9所述的方法，其中，当所述介电层为栅极绝缘层时，在所述a-Si层上的一个或多个位置进行激光照射，形成多晶硅p-Si区域，并留存至少一个未经激光照射的a-Si区域之后，还包括：
    制作氧化硅层；
    在氧化硅层上直接制作重掺杂非晶硅层。
  15. 如权利要求9所述的方法，其中，每个p-Si区域各边边长均为2微米-1000微米；
    每个a-Si区域的各边边长均大于或等于2微米。
  16. 一种背板，包括如权利要求1-8中任一项所述的薄膜晶体管。
  17. 一种显示设备，包括如权利要求1-8中任一项所述的薄膜晶体管。
PCT/CN2018/099527 2017-09-15 2018-08-09 一种薄膜晶体管制作方法、薄膜晶体管及背板、显示设备 WO2019052290A1 (zh)

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Publication number Priority date Publication date Assignee Title
CN107482065A (zh) 2017-09-15 2017-12-15 京东方科技集团股份有限公司 一种薄膜晶体管制作方法、薄膜晶体管及背板、显示设备
CN108231869B (zh) * 2018-01-02 2021-04-30 京东方科技集团股份有限公司 晶体管、显示基板、显示装置及其制造方法
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050139923A1 (en) * 2003-12-30 2005-06-30 Samsung Electronics Co., Ltd. Semiconductor device with modified mobility and thin film transistor having the same
CN102468232A (zh) * 2010-11-02 2012-05-23 乐金显示有限公司 制造阵列基板的方法
CN105789327A (zh) * 2016-05-17 2016-07-20 京东方科技集团股份有限公司 一种薄膜晶体管及其制备方法、阵列基板、显示装置
CN107482065A (zh) * 2017-09-15 2017-12-15 京东方科技集团股份有限公司 一种薄膜晶体管制作方法、薄膜晶体管及背板、显示设备

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI256515B (en) * 2004-04-06 2006-06-11 Quanta Display Inc Structure of LTPS-TFT and fabricating method thereof
KR100841365B1 (ko) * 2006-12-06 2008-06-26 삼성에스디아이 주식회사 박막트랜지스터와 그 제조방법 및 이를 구비한유기전계발광표시장치
US9773921B2 (en) * 2015-10-30 2017-09-26 Applied Materials, Inc. Combo amorphous and LTPS transistors

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050139923A1 (en) * 2003-12-30 2005-06-30 Samsung Electronics Co., Ltd. Semiconductor device with modified mobility and thin film transistor having the same
CN102468232A (zh) * 2010-11-02 2012-05-23 乐金显示有限公司 制造阵列基板的方法
CN105789327A (zh) * 2016-05-17 2016-07-20 京东方科技集团股份有限公司 一种薄膜晶体管及其制备方法、阵列基板、显示装置
CN107482065A (zh) * 2017-09-15 2017-12-15 京东方科技集团股份有限公司 一种薄膜晶体管制作方法、薄膜晶体管及背板、显示设备

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