CN107482065A - 一种薄膜晶体管制作方法、薄膜晶体管及背板、显示设备 - Google Patents
一种薄膜晶体管制作方法、薄膜晶体管及背板、显示设备 Download PDFInfo
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- 239000010409 thin film Substances 0.000 title claims abstract description 50
- 238000002360 preparation method Methods 0.000 title claims abstract description 10
- 238000000034 method Methods 0.000 claims abstract description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 60
- 229920005591 polysilicon Polymers 0.000 claims description 60
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 39
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 18
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 18
- 239000012212 insulator Substances 0.000 claims description 9
- 229910021419 crystalline silicon Inorganic materials 0.000 claims description 5
- 240000007594 Oryza sativa Species 0.000 claims 1
- 235000007164 Oryza sativa Nutrition 0.000 claims 1
- 235000009566 rice Nutrition 0.000 claims 1
- 230000007547 defect Effects 0.000 abstract description 7
- 230000000903 blocking effect Effects 0.000 abstract description 3
- 238000004519 manufacturing process Methods 0.000 description 7
- 229920001621 AMOLED Polymers 0.000 description 6
- 239000010408 film Substances 0.000 description 5
- 230000037230 mobility Effects 0.000 description 5
- 239000013078 crystal Substances 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 230000002829 reductive effect Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000005224 laser annealing Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- -1 polyoxy silicon Polymers 0.000 description 2
- 241000790917 Dioxys <bee> Species 0.000 description 1
- VYQRBKCKQCRYEE-UHFFFAOYSA-N ctk1a7239 Chemical compound C12=CC=CC=C2N2CC=CC3=NC=CC1=C32 VYQRBKCKQCRYEE-UHFFFAOYSA-N 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000000670 limiting effect Effects 0.000 description 1
- 230000036961 partial effect Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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Abstract
本申请公开了本发明实施例提供一种薄膜晶体管制作方法、薄膜晶体管及背板、显示设备,涉及显示技术,该薄膜晶体管在介电层上设置有源层,该有源层包括:至少一个a‑Si区域和至少一个p‑Si区域,在有源层中,p‑Si的迁移率较大、缺陷较少,而a‑Si的缺陷多,对电子的阻挡能力强,电阻较大,在有源层中同时存在a‑Si区域和p‑Si区域,即相当于在沟道中间串联了大电阻,降低了漏电流,并且,通常p‑Si区域是在沟道中的部分区域进行激光照射形成的,当激光有效光斑长度较小时,可以在多个区域进行激光照射形成多个p‑Si区域,其沟道宽度和长度均不受激光有效光斑长度的限制,降低了大沟道TFT的工艺难度。
Description
技术领域
本公开一般涉及显示技术,具体涉及一种薄膜晶体管,尤其涉及一种薄膜晶体管制作方法、薄膜晶体管及背板、显示设备。
背景技术
在基于MLA(微透镜阵列技术)的AMOLED背板制作中,其TFT(Thin FilmTransistor,是薄膜晶体管)的结构如图1所示,包括Gate(栅极)金属层、设置在Gate金属层上的GI(栅极绝缘)层、设置在GI层上的p-Si(多晶硅)层,由于p-Si的迁移率较大、缺陷较少,所以即使关闭状态下,电子也很容易通过沟道,所以会导致漏电流较大。
为了降低漏电流,可以在在形成p-Si和SiO2岛后,在其上再沉积一层a-Si(非晶硅)层,进而再进行后续的制作,这样多了一个a-Si层的制作步骤,提高了工艺复杂度。
并且,通常,p-Si层是通过MLA区域化激光退火技术制作的,激光源光束通过MLA(Micro Lens Array)Mask选择性对TFT沟道区域的a-Si进行高位置精度激光退火,使其形成p-Si。该技术又被称为PLAS(Partial Laser Anneal Silicon)或SLA(Selective Laser-Annealing),该技术制备TFT迁移率在5-20cm2/V·s,是a-Si迁移率的10-50倍,可以满足AMOLED(Active-matrix organic light emitting diode,有源矩阵有机发光二极体)的背板要求。但是,由于激光器以及光路硬件的限制,激光有效光斑长度在1000微米左右,即所制作的TFT的有效沟道长度在1000微米,而对于AMOLED背板的GOA(Gate driver On Array,阵列基板行驱动)设计要求,必须要实现>1500微米大沟道TFT,所以,由于激光有效光斑长度的限制,难以实现量产。
可见,目前的基于MLA的AMOLED背板中,其TFT制作漏电流较大,若要降低漏电流需要多一层a-Si层的制作,工艺复杂度较高,同时,由于激光有效光斑长度的限制,对于大沟道TFT,其工艺难度较高。
发明内容
鉴于现有技术中的上述缺陷或不足,期望提供一种薄膜晶体管制作方法、薄膜晶体管及背板、显示设备,以实现降低TFT漏电流,降低大沟道TFT的工艺难度。
第一方面,本发明实施例提供一种薄膜晶体管,包括:
设置在介电层上的有源层,所述有源层包括:
至少一个非晶硅a-Si区域和至少一个多晶硅p-Si区域,各a-Si区域和p-Si区域串联设置。
进一步,所述有源层中包括一个a-Si区域时,所述a-Si区域设置在有源层的中心;
所述有源层中包括至少两个a-Si区域时,所述a-Si区域相对于源极和漏极的中轴线对称设置。
更进一步,所述有源层中包括2或4个a-Si区域和3个p-Si区域;或者
所述有源层中包括4或6个a-Si区域和5个p-Si区域。
进一步,所述介电层具体为栅极绝缘层;
所述薄膜晶体管还包括:
设置在有源层上的氧化硅层,以及在所述氧化硅层上直接设置的重掺杂非晶硅层。
优选的,每个p-Si区域长度为2-1000微米;
每个a-Si区域长度均大于或等于2微米。
第二方面,本发明实施例还相应提供一种薄膜晶体管制作方法,包括:
在介电层上制作非晶硅a-Si层;
在所述a-Si层上的一个或多个位置进行激光照射,形成多晶硅p-Si区域,并留存至少一个未经激光照射的a-Si区域。
进一步,当留存一个未经激光照射的a-Si区域时,所述a-Si区域设置在有源层的中心;
当留存至少两个未经激光照射的a-Si区域时,所述a-Si区域相对于源极和漏极的中轴线对称设置。
更进一步,在所述a-Si层上的一个或多个位置进行激光照射,形成p-Si区域,并留存至少一个未经激光照射的a-Si区域,具体为:
在所述a-Si层上的3个位置进行激光照射,形成p-Si区域,并留存2或4个未经激光照射的a-Si区域;或者
在所述a-Si层上的5个位置进行激光照射,形成p-Si区域,并留存4或6个未经激光照射的a-Si区域。
进一步,当所述介电层具体为栅极绝缘层时,在所述a-Si层上的一个或多个位置进行激光照射,形成多晶硅p-Si区域,并留存至少一个未经激光照射的a-Si区域之后,还包括:
制作氧化硅层;
在氧化硅层上直接制作重掺杂非晶硅层。
优选的,每个p-Si区域长度为2-1000微米;
每个a-Si区域长度均大于或等于2微米。
第三方面,本发明实施例还相应提供一种背板,包括第一方面中所述的薄膜晶体管。
第四方面,本发明实施例还相应提供一种显示设备,包括第一方面中所述的薄膜晶体管。
本发明实施例提供一种薄膜晶体管制作方法、薄膜晶体管及背板、显示设备,该薄膜晶体管在介电层上设置有源层,该有源层包括:至少一个a-Si区域和至少一个p-Si区域,在有源层中,p-Si的迁移率较大、缺陷较少,而a-Si的缺陷多,对电子的阻挡能力强,电阻较大,在有源层中同时存在a-Si区域和p-Si区域,即相当于在沟道中间串联了大电阻,降低了漏电流,并且,通常p-Si区域是在沟道中的部分区域进行激光照射形成的,当激光有效光斑长度较小时,可以在多个区域进行激光照射形成多个p-Si区域,其沟道宽度和长度均不受激光有效光斑长度的限制,降低了大沟道TFT的工艺难度。
附图说明
通过阅读参照以下附图所作的对非限制性实施例所作的详细描述,本申请的其它特征、目的和优点将会变得更明显:
图1为现有技术中薄膜晶体管结构截面示意图;
图2为本发明实施例提供的薄膜晶体管结构截面示意图;
图3-图8为本发明实施例提供的具体的薄膜晶体管结构俯视示意图;
图9为本发明实施例提供的顶栅结构的薄膜晶体管的结构示意图;
图10为本发明实施例提供的薄膜晶体管制作方法流程图。
具体实施方式
下面结合附图和实施例对本申请作进一步的详细说明。可以理解的是,此处所描述的具体实施例仅仅用于解释相关发明,而非对该发明的限定。另外还需要说明的是,为了便于描述,附图中仅示出了与发明相关的部分。
需要说明的是,在不冲突的情况下,本申请中的实施例及实施例中的特征可以相互组合。下面将参考附图并结合实施例来详细说明本申请。
请参考图2,本发明实施例提供的一种薄膜晶体管,包括:栅极200、源极203、漏极204、介电层201,以及
设置在介电层201上的有源层202,有源层202包括至少一个a-Si区域2021和至少一个p-Si区域2022。
在该薄膜晶体管的有源层202中,p-Si的迁移率较大、缺陷较少,而a-Si的缺陷多,对电子的阻挡能力强,电阻较大,在有源层202中设置有a-Si区域2021,即相当于在沟道中间串联了大电阻,降低了漏电流,并且,通常,p-Si区域2022是在沟道中的部分区域进行激光照射形成的,当激光有效光斑长度较小时,可以在多个区域进行激光照射形成多个p-Si区域2022,其沟道宽度和长度均不受激光有效光斑长度的限制,降低了大沟道TFT的工艺难度。
各个a-Si区域2021和p-Si区域2022可以以任意方式排列,只要有源层202中,具有a-Si区域2021和p-Si区域2022即可。
进一步,在有源层中包括一个a-Si区域2021时,将a-Si区域2021设置在有源层的中心较佳;在有源层202中包括至少两个a-Si区域2021时,a-Si区域2021相对于源极203和漏极204的中轴线对称设置较佳。
由于a-Si区域2021相对于源极203和漏极204的中轴线对称设置,在使用薄膜晶体管时,所形成的电场是对称的,进而提高薄膜晶体管的稳定性。
如图3和图4所示,a-Si区域2021相对于源极203和漏极204的中轴线对称设置,图3和图4中的虚线为源极203和漏极204的中轴线。
有源层202中的各a-Si区域2021和p-Si区域2022可以串联设置,如图5所示,此时,每个a-Si区域2021和p-Si区域2022的宽度均等于有源层202的宽度,由于各a-Si区域2021和p-Si区域2022是串联关系,可以有效的降低有源层202中的漏电流,同时,有源层202的结构比较简单,效果比较可控。
优选的,如图5所示,有源层202中可以包括2个a-Si区域2021和3个p-Si区域2022;或者,
如图6所示,有源层202中可以包括4个a-Si区域2021和3个p-Si区域2022;或者
如图7所示,有源层中包括4个a-Si区域2021和5个p-Si区域2022;或者
如图8所示,有源层中包括6个a-Si区域2021和5个p-Si区域2022。
在本发明实施例中,介电层201可以是底栅结构中的栅极绝缘层,也可以是顶栅结构中的缓冲层,当该薄膜晶体管是底栅结构的薄膜晶体管时,如图2所示,介电层201具体为栅极绝缘层,并且,
该薄膜晶体管还包括:
设置在有源层202上的氧化硅层205,以及在氧化硅层205上直接设置的重掺杂非晶硅层206。
其中,氧化硅层205可以是二氧化硅材料,也可以是多氧化硅材料;
重掺杂非晶硅层206可以是电子导电类型(N+)重掺杂非晶硅层,也可以是空穴导电类型(P+)重掺杂非晶硅层。
可见,在氧化硅层205上可以不再设置第二层a-Si层,可直接设置的重掺杂非晶硅层206,减少了第二层a-Si层的制作工艺,减小了工艺复杂度。
同样的,对于顶栅结构的TFT,也可以不再设置第二层a-Si层,进而减少制作工艺流程,减小工艺复杂度。如图9所示,在顶栅结构的薄膜晶体管中,包括:栅极200、源极203、漏极204、介电层201,以及设置在介电层201上的有源层202,有源层202包括至少一个a-Si区域2021和至少一个p-Si区域2022,还包括:设置在有源层202上的氧化硅层205,栅极200设置在氧化硅层205上,栅极之上设置介质层207,源极203和漏极204通过过孔与有源层202连接。
进一步,在通常情况下,p-Si区域2022是在沟道中的部分区域进行激光照射形成的,当激光有效光斑长度较小时,可以在多个区域进行激光照射形成多个p-Si区域2022,一般激光有效光斑是每边边长均在1000微米以下的矩形,所以,每个p-Si区域各边边长均小于或等于1000微米较佳;为保证较好的串联效果,每个p-Si区域和a-Si区域的各边边长均大于或等于2微米,所以每个p-Si区域各边的长度为2-1000微米、每个a-Si区域各边长度均大于或等于2微米较佳。
由于p-Si区域各边边长均为2-1000微米,小于一般的激光有效光斑边长长度,便于进行TFT量产,多个p-Si区域和a-Si区域交替串联组合,能够制作出任意长度和宽度沟道的TFT,TFT沟道长度和宽度不再受激光有效光斑长度的限制,所以沟道的W/L(宽长比)值也不再受激光有效光斑长度的限制,可以制作出任意W/L值的TFT。
本发明实施例还提供一种薄膜晶体管制作方法,如图10所示,该方法包括:
步骤S901、在介电层上制作a-Si层;
步骤S902、在a-Si层上的一个或多个位置进行激光照射,形成p-Si区域,并留存至少一个未经激光照射的a-Si区域。
进一步,当留存一个未经激光照射的a-Si区域时,a-Si区域设置在有源层的中心;
当留存至少两个未经激光照射的a-Si区域时,a-Si区域相对于源极和漏极的中轴线对称设置。
由于a-Si区域相对于源极和漏极的中轴线对称设置,在使用薄膜晶体管时,所形成的电场是对称的,进而提高薄膜晶体管的稳定性。
如图3和图4所示,a-Si区域相对于源极和漏极的中轴线对称设置。
进一步,有源层中的各a-Si区域和p-Si区域串联设置,即,每个a-Si区域和p-Si区域的宽度均等于有源层的宽度。
具体的,步骤902中,在a-Si层上的一个或多个位置进行激光照射,形成p-Si区域,并留存至少一个未经激光照射的a-Si区域,具体为:
在a-Si层上的3个位置进行激光照射,形成p-Si区域,并留存2或4个未经激光照射的a-Si区域,形成如图5或图6所示的薄膜晶体管;或者
在a-Si层上的5个位置进行激光照射,形成p-Si区域,并留存4或6个未经激光照射的a-Si区域,形成如图7或图8所示的有源层结构。
在本发明实施例中,介电层可以是底栅结构中的栅极绝缘层,也可以是顶栅结构中的缓冲层,当该薄膜晶体管是底栅结构的薄膜晶体管时,介电层具体为栅极绝缘层,此时,步骤S902,在a-Si层上的一个或多个位置进行激光照射,形成多晶硅p-Si区域,并留存至少一个未经激光照射的a-Si区域之后,还包括:
制作氧化硅层;
在氧化硅层上直接制作重掺杂非晶硅层。
通过上述步骤,即可形成如图2所示的薄膜晶体管,其中,氧化硅层205可以是二氧化硅材料,也可以是多氧化硅材料;
重掺杂非晶硅层206可以是电子导电类型(N+)重掺杂非晶硅层,也可以是空穴导电类型(P+)重掺杂非晶硅层。
通常在制作重掺杂非晶硅层之后,在重掺杂非晶硅层上制作SD层。
同样的,对于顶栅结构的TFT,也减少了第二层a-Si层的制作,进而减少制作工艺流程,减小工艺复杂度。
可见,在制作氧化硅层后,不需要制作第二层a-Si层,可直接制作重掺杂非晶硅层,减少了第二层a-Si层的制作工艺,减小了工艺复杂度。
优选的,每个p-Si区域各边边长均为2-1000微米;
每个a-Si区域各边边长均大于或等于2微米。
由于p-Si区域各边边长均为2-1000微米,小于一般的激光有效光斑边长长度,便于进行TFT量产,多个p-Si区域和a-Si区域交替串联组合,能够制作出任意长度和宽度沟道的TFT,TFT沟道长度和宽度不再受激光有效光斑长度的限制,所以沟道的W/L(宽长比)值也不再受激光有效光斑长度的限制,可以制作出任意W/L值的TFT。
本发明实施例还相应提供一种背板,该背板中包括本发明实施例提供的薄膜晶体管。
本发明实施例还相应提供一种显示设备,该显示设备中包括本发明实施例提供的薄膜晶体管。
以上描述仅为本申请的较佳实施例以及对所运用技术原理的说明。本领域技术人员应当理解,本申请中所涉及的发明范围,并不限于上述技术特征的特定组合而成的技术方案,同时也应涵盖在不脱离所述发明构思的情况下,由上述技术特征或其等同特征进行任意组合而形成的其它技术方案。例如上述特征与本申请中公开的(但不限于)具有类似功能的技术特征进行互相替换而形成的技术方案。
Claims (14)
1.一种薄膜晶体管,其特征在于,所述薄膜晶体管包括:栅极、源极、漏极、介电层,以及
设置在所述介电层上的有源层,所述有源层包括至少一个非晶硅a-Si区域和至少一个多晶硅p-Si区域。
2.如权利要求1所述的薄膜晶体管,其特征在于,所述有源层中包括一个a-Si区域时,所述a-Si区域设置在所述有源层的中心;
所述有源层中包括至少两个a-Si区域时,所述a-Si区域相对于源极和漏极的中轴线对称设置。
3.如权利要求2所述的薄膜晶体管,其特征在于,所述有源层中的各a-Si区域和p-Si区域串联设置。
4.如权利要求3所述的薄膜晶体管,其特征在于,所述有源层中包括2或4个a-Si区域和3个p-Si区域;或者
所述有源层中包括4或6个a-Si区域和5个p-Si区域。
5.如权利要求1所述的薄膜晶体管,其特征在于,所述介电层为栅极绝缘层;
所述薄膜晶体管还包括:
设置在有源层上的氧化硅层,以及在所述氧化硅层和所述源极和所述漏极之间仅设置的重掺杂非晶硅层。
6.如权利要求1所述的薄膜晶体管,其特征在于,每个p-Si区域各边边长均为2-1000微米;
每个a-Si区域的各边边长均大于或等于2微米。
7.一种薄膜晶体管制作方法,其特征在于,包括:
在介电层上制作非晶硅a-Si层;
在所述非晶硅a-Si层上的一个或多个位置进行激光照射,形成多晶硅p-Si区域,并留存至少一个未经激光照射的a-Si区域。
8.如权利要求7所述的方法,其特征在于,当留存一个未经激光照射的a-Si区域时,所述a-Si区域设置在有源层的中心;
当留存至少两个未经激光照射的a-Si区域时,所述a-Si区域相对于源极和漏极的中轴线对称设置。
9.如权利要求8所述的方法,其特征在于,所述有源层中的各a-Si区域和p-Si区域串联设置。
10.如权利要求9所述的方法,其特征在于,在所述a-Si层上的一个或多个位置进行激光照射,形成p-Si区域,并留存至少一个未经激光照射的a-Si区域,具体为:
在所述a-Si层上的3个位置进行激光照射,形成p-Si区域,并留存2或4个未经激光照射的a-Si区域;或者
在所述a-Si层上的5个位置进行激光照射,形成p-Si区域,并留存4或6个未经激光照射的a-Si区域。
11.如权利要求7所述的方法,其特征在于,当所述介电层具体为栅极绝缘层时,在所述a-Si层上的一个或多个位置进行激光照射,形成多晶硅p-Si区域,并留存至少一个未经激光照射的a-Si区域之后,还包括:
制作氧化硅层;
在氧化硅层上直接制作重掺杂非晶硅层。
12.如权利要求7所述的方法,其特征在于,每个p-Si区域各边边长均为2-1000微米;
每个a-Si区域的各边边长均大于或等于2微米。
13.一种背板,其特征在于,包括如权利要求1-6任一所述的薄膜晶体管。
14.一种显示设备,其特征在于,包括如权利要求1-6任一所述的薄膜晶体管。
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- 2017-09-15 CN CN201710840881.1A patent/CN107482065A/zh active Pending
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CN105789327A (zh) * | 2016-05-17 | 2016-07-20 | 京东方科技集团股份有限公司 | 一种薄膜晶体管及其制备方法、阵列基板、显示装置 |
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Publication number | Priority date | Publication date | Assignee | Title |
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WO2019052290A1 (zh) * | 2017-09-15 | 2019-03-21 | 京东方科技集团股份有限公司 | 一种薄膜晶体管制作方法、薄膜晶体管及背板、显示设备 |
US10804405B2 (en) | 2017-09-15 | 2020-10-13 | Boe Technology Group Co., Ltd. | Method for making thin film transistor, thin film transistor, back plate and display device |
WO2019134313A1 (en) * | 2018-01-02 | 2019-07-11 | Boe Technology Group Co., Ltd. | Thin film transistor, display substrate, display panel, and method of fabricating thin film transistor |
CN109411531A (zh) * | 2018-10-18 | 2019-03-01 | 京东方科技集团股份有限公司 | 一种薄膜晶体管及其制作方法、阵列基板、显示装置 |
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US20190214501A1 (en) | 2019-07-11 |
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US10804405B2 (en) | 2020-10-13 |
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