WO2022028203A1 - 薄膜晶体管及其制备方法、显示装置 - Google Patents

薄膜晶体管及其制备方法、显示装置 Download PDF

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WO2022028203A1
WO2022028203A1 PCT/CN2021/105319 CN2021105319W WO2022028203A1 WO 2022028203 A1 WO2022028203 A1 WO 2022028203A1 CN 2021105319 W CN2021105319 W CN 2021105319W WO 2022028203 A1 WO2022028203 A1 WO 2022028203A1
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pattern
semiconductor
thin film
polysilicon
active
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PCT/CN2021/105319
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English (en)
French (fr)
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吕杨
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京东方科技集团股份有限公司
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Priority to US17/779,327 priority Critical patent/US20220406820A1/en
Publication of WO2022028203A1 publication Critical patent/WO2022028203A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1229—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with different crystal properties within a device or between different devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
    • H01L27/1285—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor using control of the annealing or irradiation parameters, e.g. using different scanning direction or intensity for different transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a thin film transistor, a preparation method thereof, and a display device.
  • the most used device is the thin film transistor (Thin Film Transistor, TFT), and the thin film transistor is a field effect transistor.
  • TFT Thin Film Transistor
  • the function of the TFT is a three-terminal switch, with three terminals such as gate, source and drain. When the gate is turned on, the signal can be transmitted from the source to the drain.
  • a thin film transistor in one aspect, includes: an active layer disposed on a substrate.
  • the active layer has a channel region, the active layer includes a first active pattern and a second active pattern, at least a part of the first active pattern is located in the channel region.
  • the first active pattern includes a bottom surface, a top surface and at least one side surface, the bottom surface and the top surface are disposed opposite to each other along the thickness direction of the substrate, and the bottom surface is closer to the substrate;
  • the at least one side surface connects the bottom surface and the top surface, the at least one side surface is in contact with the second active pattern, and the length direction of each side surface of the at least one side surface is the same as that of the channel region.
  • the length direction is vertical or approximately vertical; the material of at least the top surface of the first active pattern includes first polysilicon, and the material of the second active pattern includes second polysilicon; along the channel In the length direction of the region, the average grain size of the first polysilicon is larger than the average grain size of the second polysilicon.
  • the thin film transistor further includes: an etch blocking pattern disposed on the top surface of the first active pattern; an orthographic projection of the first active pattern on the substrate is on the The etch stop pattern is within the orthographic projection of the substrate, and the orthographic projection of the etch stop pattern on the substrate is different from the orthographic projection of the second active pattern on the substrate. overlapping.
  • the at least one side surface includes: a first side surface and a second side surface disposed opposite to each other along a length direction of the channel region; the second active pattern is connected to the first side surface and the second side surface. The second side contacts.
  • the active layer further includes: a third active pattern, and the material of the third active pattern is amorphous silicon.
  • the third active pattern is disposed on at least one side of the active pattern group.
  • the third active patterns are arranged around the active pattern group.
  • the active pattern group includes the first active pattern and the second active pattern.
  • the edge of the orthographic projection of the first active pattern on the substrate coincides with or substantially coincides with the edge of the orthographic projection of the etch stop pattern on the substrate.
  • the thin film transistor further includes: an ohmic contact pattern disposed on a side of the active layer away from the substrate, and the ohmic contact pattern is in contact with the active layer.
  • the thin film transistor further includes: a gate disposed on a side of the active layer close to the substrate; or, disposed on a side of the active layer away from the substrate.
  • the material of the first active pattern is a first polysilicon or further includes a third polysilicon, and the average grain size of the third polysilicon is smaller than that of the first polysilicon Average grain size of silicon.
  • the thin film transistor further includes: a source electrode and a drain electrode disposed on a side of the second active pattern away from the substrate, the source electrode and the drain electrode are respectively connected to the active layer electrical connection.
  • a display device in another aspect, includes: the thin film transistor according to any one of the above embodiments.
  • a method for preparing a thin film transistor comprising:
  • a stacked first semiconductor pattern and an etch stop pattern are formed on a substrate, wherein the first semiconductor pattern has a channel region, the first semiconductor pattern includes a bottom surface, a top surface and at least one side surface, the bottom surface and all the The top surface is oppositely disposed along the thickness direction of the substrate, and the bottom surface is closer to the substrate, the at least one side surface connects the bottom surface and the top surface, and each side surface of the at least one side surface is The length direction of the channel region is perpendicular or approximately perpendicular to the length direction of the channel region, the orthographic projection of the first semiconductor pattern on the substrate is within the orthographic projection of the etch stop pattern on the substrate,
  • the material of the first semiconductor pattern is amorphous silicon or third polysilicon.
  • a second semiconductor thin film is formed on the substrate on which the first semiconductor pattern and the etch stop pattern are formed, the second semiconductor thin film is in contact with at least the etch stop pattern and the first semiconductor pattern, and the second semiconductor thin film is in contact with the etch stop pattern and the first semiconductor pattern.
  • the material is amorphous silicon, and the second semiconductor thin film is patterned to form a second semiconductor pattern, the second semiconductor pattern being in contact with the at least one side surface of the first semiconductor pattern.
  • the first semiconductor pattern and at least part of the second semiconductor pattern are irradiated with a first laser, and the at least part of the second semiconductor pattern is in contact with the first semiconductor pattern, so that the irradiated at least part of the second semiconductor pattern is Amorphous silicon in the semiconductor pattern material is converted into second polysilicon, so that at least the material of the top surface in the first semiconductor pattern is converted into first polysilicon, along the length direction of the channel region,
  • the average grain size of the first polysilicon is larger than the average grain size of the second polysilicon and the third polysilicon.
  • the third active pattern is formed by a portion of the second semiconductor pattern that is not irradiated by the laser light.
  • forming the stacked first semiconductor pattern and the etch stop pattern on the substrate includes:
  • a first semiconductor thin film is formed on one side of the substrate, and the material of the first semiconductor thin film is amorphous silicon or third polysilicon.
  • a first insulating film is formed on the side of the first semiconductor film away from the substrate.
  • the first insulating film and the first semiconductor film are patterned through the same patterning process to form the stacked first semiconductor pattern and the etch stop pattern.
  • a first semiconductor thin film is formed on one side of the substrate, the material of the first semiconductor thin film is amorphous silicon or a third polysilicon, and the first semiconductor thin film is patterned to form the first semiconductor pattern.
  • a first insulating film is formed on the substrate on which the first semiconductor pattern is formed, and the first insulating film is patterned to form the etch stopper pattern.
  • the method for fabricating a thin film transistor further includes: forming an ohmic contact pattern on a side of the active layer away from the substrate, the ohmic contact pattern being in contact with the active layer.
  • the method for fabricating a thin film transistor further includes: forming a source electrode and a drain electrode on a side of the ohmic contact pattern away from the substrate, the source electrode and the drain electrode respectively passing through the ohmic contact The pattern is electrically connected to the active layer.
  • the preparation method before forming the first semiconductor thin film, the preparation method further includes: forming a gate metal thin film on one side of the substrate, and patterning to form a gate electrode.
  • the method for fabricating a thin film transistor further includes: forming a gate metal film on a side of the etch stop pattern away from the substrate, and patterning to form a gate.
  • forming the first semiconductor thin film on one side of the substrate includes:
  • An amorphous silicon thin film is formed on the substrate.
  • the amorphous silicon film is irradiated with a second laser to convert the amorphous silicon in the amorphous silicon film into a third polysilicon to form the first semiconductor film.
  • the material of the first semiconductor film is the third polysilicon.
  • the first laser performs a zoned laser annealing process and the second laser performs an excimer laser annealing process.
  • the method for fabricating the thin film transistor further includes: removing the etch stop pattern.
  • FIG. 1A-1C are top-view structural views of a thin film transistor provided according to some embodiments of the present disclosure.
  • FIGS. 2A-2G are top-view structural views of another thin film transistor provided according to some embodiments of the present disclosure.
  • 3A-3B are longitudinal cross-sectional structural views of a first active pattern provided according to some embodiments of the present disclosure.
  • FIG. 4 is a process diagram of converting amorphous silicon into polycrystalline silicon provided according to some embodiments of the present disclosure
  • 5A-5B are a comparison diagram of the average grain size of the first polysilicon in the first active pattern and the second polysilicon in the second active pattern according to some embodiments of the present disclosure
  • 6A is a structural diagram of a crystal grain of a third polysilicon provided according to some embodiments of the present disclosure.
  • 6B is a structural diagram of a crystal grain of a first polysilicon provided according to some embodiments of the present disclosure.
  • FIG. 7 is a structural diagram of a crystal grain of a third polysilicon in an active layer provided by the related art.
  • FIG. 8A is a top view of another thin film transistor provided according to some embodiments of the present disclosure.
  • FIG. 8B is a longitudinal cross-sectional view of FIG. 8A along A-A';
  • 8C is a top view of another thin film transistor provided according to some embodiments of the present disclosure.
  • Fig. 8D is a longitudinal cross-sectional view along the direction B-B' in Fig. 8C;
  • FIG. 9A is a top view of another thin film transistor provided according to some embodiments of the present disclosure.
  • FIG. 9B is a longitudinal cross-sectional view of FIG. 9A along C-C';
  • 9C is a top view of another thin film transistor provided according to some embodiments of the present disclosure.
  • FIG. 9D is a longitudinal sectional view in the direction D-D' in FIG. 9C;
  • 9E is a top view of another thin film transistor provided according to some embodiments of the present disclosure.
  • 9F is a top view of another thin film transistor provided according to some embodiments of the present disclosure.
  • FIG. 10A is a top view of another thin film transistor provided according to some embodiments of the present disclosure.
  • Fig. 10B is a longitudinal cross-sectional view along the E-E' direction in Fig. 10A;
  • FIG. 10C is a top view of another thin film transistor provided according to some embodiments of the present disclosure.
  • FIG. 10D is a top view of another thin film transistor provided according to some embodiments of the present disclosure.
  • Fig. 10E is a longitudinal cross-sectional view of Fig. 10C and Fig. 10D in the direction of F-F';
  • 10F is a top view of another thin film transistor provided according to some embodiments of the present disclosure.
  • Fig. 10G is a longitudinal sectional view in the direction G-G' in Fig. 10F;
  • 10H is a top view of another thin film transistor provided according to some embodiments of the present disclosure.
  • Fig. 10I is a longitudinal cross-sectional view in the direction of H-H' in Fig. 10H;
  • FIGS. 11A-11E are longitudinal cross-sectional structural views of another thin film transistor provided according to some embodiments of the present disclosure.
  • FIG. 12A is a flowchart of a method for fabricating a thin film transistor provided according to some embodiments of the present disclosure
  • 12B is a longitudinal cross-sectional view of a thin film transistor according to some embodiments of the present disclosure in a manufacturing process
  • 12C is a flowchart of another method for fabricating a thin film transistor provided according to some embodiments of the present disclosure.
  • 12D is a longitudinal cross-sectional view of another thin film transistor provided according to some embodiments of the present disclosure in a manufacturing process
  • FIG. 12E is a flowchart of yet another method for fabricating a thin film transistor provided according to some embodiments of the present disclosure.
  • 12F to 12H are longitudinal cross-sectional views of another thin film transistor provided according to some embodiments of the present disclosure in a manufacturing process
  • FIG. 12I is a top structural view of another thin film transistor provided in a manufacturing process according to some embodiments of the present disclosure.
  • Fig. 12J is a longitudinal sectional view in the direction of I-I' in Fig. 12I;
  • FIG. 12K and FIG. 12L are top-view structural views of another thin film transistor in a manufacturing process according to some embodiments of the present disclosure.
  • Fig. 12M is a longitudinal cross-sectional view along the J-J' direction in Figs. 12K and 12L;
  • FIGS. 12N and 12O are longitudinal cross-sectional views of another thin film transistor provided according to some embodiments of the present disclosure during the fabrication process.
  • first and second are only used for descriptive purposes, and should not be construed as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, a feature defined as “first” or “second” may expressly or implicitly include one or more of that feature.
  • plural means two or more.
  • the expressions “coupled” and “connected” and their derivatives may be used.
  • the term “connected” may be used in describing some embodiments to indicate that two or more components are in direct physical or electrical contact with each other.
  • the term “coupled” may be used in describing some embodiments to indicate that two or more components are in direct physical or electrical contact.
  • the terms “coupled” or “communicatively coupled” may also mean that two or more components are not in direct contact with each other, yet still co-operate or interact with each other.
  • the embodiments disclosed herein are not necessarily limited by the content herein.
  • At least one of A, B, and C has the same meaning as “at least one of A, B, or C”, and both include the following combinations of A, B, and C: A only, B only, C only, A and B , A and C, B and C, and A, B, and C.
  • a and/or B includes the following three combinations: A only, B only, and a combination of A and B.
  • the term “if” is optionally construed to mean “when” or “at” or “in response to determining” or “in response to detecting,” depending on the context.
  • the phrases “if it is determined that" or “if a [statement or event] is detected” are optionally interpreted to mean “in determining" or “in response to determining" or “on the detection of [the stated condition or event]” or “in response to the detection of the [ stated condition or event]”.
  • an "average" value in this disclosure should be understood to mean the arithmetic mean, eg, the average grain size should be understood to mean the arithmetic mean of the grain sizes.
  • Exemplary embodiments are described herein with reference to cross-sectional and/or plan views that are idealized exemplary drawings.
  • the thickness of layers and regions are exaggerated for clarity. Accordingly, variations from the shapes of the drawings due to, for example, manufacturing techniques and/or tolerances, are contemplated.
  • example embodiments should not be construed as limited to the shapes of the regions shown herein, but to include deviations in shapes due, for example, to manufacturing. For example, an etched area shown as a rectangle will typically have curved features.
  • the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example embodiments.
  • Embodiments of the present disclosure provide a display device, which may be, for example, an LCD (Liquid Crystal Display, liquid crystal display), an OLED (Organic Light-Emitting Diode, organic light-emitting diode) display device, and a QLED (Quantum Dot Light Emitting Diodes, Quantum dot light-emitting diode) any of the display devices.
  • a display device which may be, for example, an LCD (Liquid Crystal Display, liquid crystal display), an OLED (Organic Light-Emitting Diode, organic light-emitting diode) display device, and a QLED (Quantum Dot Light Emitting Diodes, Quantum dot light-emitting diode) any of the display devices.
  • LCD Liquid Crystal Display, liquid crystal display
  • OLED Organic Light-Emitting Diode, organic light-emitting diode
  • QLED Quantum Dot Light Emitting Diodes, Quantum dot light-e
  • the drive circuit of the above-mentioned display device includes a plurality of thin film transistors 1 and some other devices that are electrically connected.
  • the drive circuit includes, for example, a pixel drive circuit and a GOA (Gate Driver On Array, array substrate row drive) circuit; some other devices are, for example, capacitors, such as storage capacitors.
  • GOA Gate Driver On Array, array substrate row drive
  • the pixel driving circuit is, for example, a 2T1C type, a 7T1C type, or the like.
  • the GOA circuit is, for example, 3T1C type, 8T2C type, etc.
  • the GOA circuit can be a Gate GOA circuit (gate drive circuit) or an EM GOA circuit (light-emitting control circuit).
  • T stands for thin film transistor
  • C stands for capacitance
  • 2T1C is a pixel driving circuit including two thin film transistors and one capacitance.
  • the number of thin film transistors and capacitors in the pixel driving circuit and the GOA circuit can be selected according to actual needs. Therefore, the present disclosure does not limit the number of thin film transistors and capacitors in the pixel driving circuit and the GOA circuit. Only The pixel driving circuit and the GOA circuit listed above are used to illustrate that these driving circuits need to be formed by using thin film transistors.
  • a thin film transistor comprising: an active layer disposed on a substrate; the active layer has a channel region.
  • the thickness of the active layer is, for example,
  • the thin film transistor may further include a source electrode and a drain electrode.
  • the source electrode and the drain electrode are respectively electrically connected to the active layer, and the region between the source electrode and the drain electrode in the active layer is the channel region, and the channel region can make the signal transfer from the source electrode to the drain electrode through the channel region .
  • the top view of the thin film transistor 1 is shown.
  • the shape of the channel region 100 on the active layer 10 is Examples include rectangles and U shapes.
  • the channel region 100 on the active layer 10 in the thin film transistor 1 is rectangular, and the length is L, for example, and L also represents the length direction of the channel region 100 .
  • the channel region 100 on the active layer 10 in the thin film transistor 1 is U-shaped, and the maximum length is, for example, L, which also represents the length direction of the channel region 100 .
  • L which also represents the length direction of the channel region 100 .
  • the length direction L of the channel region 100 may vary along the U-shaped track.
  • the active layer 10 includes: a first active pattern 11 and a second active pattern 12, and at least part of the first active pattern 11 is located in the channel region 100 out of 100.
  • the first active pattern 11 includes a bottom surface, a top surface and at least one side surface, the bottom surface and the top surface are disposed opposite to each other along the thickness direction of the substrate 2 , and the bottom surface is closer to the substrate 2 .
  • At least one side surface connects the bottom surface and the top surface, at least one side surface is in contact with the second active pattern 12 , and the length direction of each side surface of the at least one side surface is perpendicular or approximately perpendicular to the length direction of the channel region 100 .
  • At least one side surface should be understood as a side surface that is in contact with the second active pattern 12 and whose length direction is perpendicular to the length direction L of the channel region 100 , excluding those that can be connected to the bottom surface and the top surface of the first active pattern 11 . , but the side surfaces whose length direction is not perpendicular to the length direction L of the channel region 100 , and/or the side surfaces that are not in contact with the second active pattern 12 .
  • the contact with the second active pattern 12 may be understood as being in direct contact with the second active pattern 12 .
  • the structure of the active layer 10 thereof is, for example, as shown in FIGS. 2A and 2B .
  • the channel region 100 is rectangular, the length direction is perpendicular to the length direction L of the channel region 100 and the side surface in contact with the second active pattern 12 is the first side surface S1 .
  • the channel region 100 is rectangular, the lengthwise direction is perpendicular to the lengthwise direction L of the channel region 100 and the side surfaces in contact with the second active pattern 12 are the first side surface S1 and the second side surface S2 , wherein the first side surface S1 It is opposite to the second side surface S2 along the length direction L of the channel region 100 .
  • the first side surface S1 and the second side surface S2 among the first side surfaces S1 and the second side surfaces S2 disposed opposite to each other along the length direction L of the channel region 100 may be one side surface or a plurality of them.
  • the multiple first side surfaces S1 there is a corner between two adjacent side surfaces; among the multiple second side surfaces S2, two adjacent side surfaces are There are also corners in between.
  • FIGS. 2C to 2E For the structure of the thin film transistor 1 shown in FIG. 1B , for example, refer to FIGS. 2C to 2E for the structure of the active layer 10 , wherein the channel region 100 in the active layer 10 is U-shaped, and the length direction is the same as that of the channel region 100 .
  • the side surfaces that are perpendicular to the length direction L and are in contact with the second active patterns 12 include at least one first side surface S1 and at least one second side surface S2.
  • the multiple first side surfaces S1 are, for example, the first side surface S1 -1 , the first side surface S1 -2 and the first side surface S1 -3 which are connected in sequence
  • the plurality of second side surfaces S2 are, for example, the second side surfaces S2 -1 , the second side surfaces S2 -2 and the second side surfaces S1 -3 which are connected in sequence.
  • both the first side S1 -1 and the second side S2 -1 whose length direction is perpendicular to the length direction L of the channel region 100 and are in contact with the second active pattern 12 are one, wherein the second active pattern 12 In contact with the first side S1 -1 and/or the second side S2 -1 .
  • first side surfaces S1 whose length direction is perpendicular to the length direction L of the channel region 100 and which are in contact with the second active pattern 12 , that is, the first side surfaces S1 -1 and the first side surfaces S1 - which are connected in sequence. 2 and the first side S1-3 .
  • first side surfaces S1 and second side surfaces S2 whose length direction is perpendicular to the length direction L of the channel region 100 and which are in contact with the second active pattern 12 , wherein the multiple first side surfaces S1 are, for example, The first side surface S1-1 , the first side surface S1-2 and the first side surface S1-3 connected in sequence; the plurality of second side surfaces S2 are, for example, the second side surface S2-1 , the second side surface S2-2 and the first side surface S2-1 connected in sequence.
  • Two side surfaces S2-3 wherein, the first side surface S1-1 and the second side surface S2-1 are oppositely arranged along the length direction L of the channel region 100, and the first side surface S1-2 and the second side surface S2-2 are along the channel region.
  • the length direction L of the channel region 100 is oppositely arranged, and the first side surface S1 -3 and the second side surface S2 -3 are oppositely arranged along the length direction L of the channel region 100 .
  • FIGS. 2F and 2G For the structure of the thin film transistor 1 shown in FIG. 1C , for example, refer to FIGS. 2F and 2G for the structure of the active layer 10 .
  • the channel region 100 is U-shaped, the length direction is perpendicular to the length direction L of the channel region 100 , and the side surfaces in contact with the second active pattern 12 include a plurality of first side surfaces S1 , that is, connected in sequence.
  • the channel region 100 is U-shaped, and the lengthwise direction is perpendicular to the lengthwise direction L of the channel region 100 and the side surfaces in contact with the second active pattern 12 include a plurality of first side surfaces S1 and a plurality of second side surfaces S2;
  • the plurality of first side surfaces S1 are, for example, the first side surfaces S1-1 , the first side surfaces S1-2 and the first side surfaces S1-3 which are connected in sequence;
  • the plurality of second side surfaces S2 are, for example, the second side surfaces S2-3 which are connected in sequence . 1.
  • the second side S2-2 and the second side S2-3 wherein, the first side S1-1 and the second side S2-1 are oppositely arranged along the length direction L of the channel region 100, and the first side S1-2 and The second side surface S2 -2 is oppositely arranged along the length direction L of the channel region 100 , and the first side surface S1 -3 and the second side surface S2 -3 are arranged oppositely along the length direction L of the channel region 100 .
  • the second active pattern 12 when the second active pattern 12 is in contact with the oppositely disposed first side S1 and the second side S2 , it is beneficial to fabricate the first active pattern 11 .
  • 2B, 2E and 2G there are two second active patterns 12, and each second active pattern 12 is in contact with at least one first side S1 and at least one second side S2.
  • the material of at least the top surface of the first active pattern 11 includes the first polysilicon, and the material of the second active pattern 12 includes the second polysilicon; along the length direction L of the channel region 100, the first polysilicon is The average grain size is larger than the average grain size of the second polysilicon.
  • amorphous silicon a-si
  • p-si polycrystalline silicon
  • 3A is a longitudinal cross-sectional structural view of the first active pattern 11 in the thin film transistor 1, the longitudinal cross-section is a cross-section extending along the thickness direction of the substrate 2, the first active pattern 11 includes a two-layer structure, wherein the The first sub-pattern 101 is on the first bottom surface D1, and the second sub-pattern 102 is near the second bottom surface D2.
  • the material of the first sub-pattern 101 is the third polysilicon, and along the length direction L of the channel region 100, the average grain size of the third polysilicon is smaller than that of the first polysilicon, and the second sub-pattern
  • the material of 102 is the first polysilicon.
  • the material of the second sub-pattern 102 is the first polysilicon
  • the material of the second sub-pattern 102 is the first polysilicon
  • the first active pattern 11 has a two-layer structure, the interface between the first sub-pattern 101 and the second sub-pattern 102 can be seen in the longitudinal cross-sectional view of the first active pattern 11 .
  • FIG. 3B is a longitudinal cross-sectional structural view of the first active pattern 11 in the thin film transistor 1
  • the first active pattern 11 is a single-layer structure, and the material only includes the first polysilicon, that is, the first active pattern 11 has a single-layer structure.
  • the entire source pattern 11 is made of the first polysilicon material.
  • both the bottom surface D1 and the top surface D2 and the portion between the bottom surface D1 and the top surface D2 are the first polysilicon.
  • the p-si grains formed by the LTPS process are composed of small-scale crystallites (crystallites) of many Si atoms.
  • the boundary between two adjacent grains is called grain boundary. Since the carriers migrate along the length direction of the channel region 100 during operation of the TFT, the less grain boundaries existing along the length direction of the channel region 100, the higher the carrier mobility will be. .
  • excimer laser crystallization ELC can be used to prepare p-si grains.
  • ELC may include excimer laser annealing (Excimer Laser Annealing, ELA) and localized laser annealing (Micro lens array Laser Annealing, MLA).
  • FIG. 4 is a process diagram of the lateral (along the length direction of the channel region 100 ) growth of p-si crystal grains, when a shot (the number of shots of the laser 3 ) laser 3 is irradiated to a on the substrate 2 a
  • the surface of the a-si film 19 reaches the crystallization threshold energy density when the temperature reaches the melting point, the melting front of the surface of the a-si film 19 will penetrate into the a-si film at a speed of about 10 m/s.
  • the inside of the si film 19 The inside of the si film 19 .
  • the temperature of the a-si thin film 19 after being irradiated is high in the middle and low at the two ends along its length direction, and crystal nuclei 19' are formed at the boundary between the melted a-si and the unmelted a-si.
  • the molten layer is first cooled from both sides at a rate of 108K/s to 1010K/s.
  • the interface between the solid phase and the liquid phase will move to the middle and the surface at a speed of 1 m/s to 2 m/s, and crystallization nuclei 19' will be formed in the middle in turn.
  • the portion a-si of the a-si thin film 19 irradiated with the laser beam 3 is crystallized into p-si, and p-si crystal grains are formed with the crystal nucleus 19' as a boundary.
  • the energy is limited by the laser and cannot be increased indefinitely. Too much energy density will actually decrease the p-si mobility.
  • the energy crystallization threshold of the excimer laser defines the lateral production range of p-si grains in each shot, and a large number of crystalline nuclei 19' are distributed on the boundary of p-si grains, and the material of crystalline nuclei 19' is mainly p -si.
  • the energy density of the laser 3 in the above process is 300mj/cm 2 -400mj/cm 2
  • the frequency is 100HZ - 100HZ.
  • the grain growth process is divided into two steps, the first step is to form a crystal nucleus, and the second step is to grow.
  • the first step is to form a crystal nucleus
  • the second step is to grow.
  • the a-si randomly forms the crystal nucleus 19' in the a-si film 19. , resulting in a smaller size (eg, length) of the resulting p-si grains.
  • the crystal nucleus 19' can play a guiding role, so that the crystallization of polysilicon can be completely melted through the crystal nucleus 19' , so the lateral grains (eg, the length of the grains) tend to be larger than the film thickness, a process called super lateral growth.
  • the randomly generated p-si grains that are not super laterally grown are referred to as the second polysilicon and the third polysilicon, and the p-si grains formed by super lateral growth are referred to as the first polysilicon.
  • the average grain size of the first polysilicon is larger than the average grain size of the second polysilicon and the third polysilicon, and the average grain size here can be understood as, for example, the average grain size
  • the grain length, ie, the average grain length of the first polysilicon is greater than the average grain length of the second polysilicon.
  • the second polysilicon and the third polysilicon are randomly generated, they are affected by the laser parameters used in the generation process, as well as the thickness of the film used to generate the second polysilicon and the Because of the influence of the film thickness of the third polysilicon, the average grain size of the second polysilicon and the average grain size of the third polysilicon may be the same or different, but both are smaller than those of the third polysilicon.
  • the average grain size of a polysilicon is the average grain size of a polysilicon.
  • the length of the channel region 100 in the active layer 10 can be reduced.
  • the number of grain boundaries of L which can improve the mobility of carriers in the TFT.
  • the second polysilicon 1200 in the second active pattern 12 is mainly used to form the crystal nucleus 19 ′ when the first polysilicon 1100 in the first active pattern 11 is formed, so as to The crystal grains of the first polysilicon 1100 can be grown laterally along the length direction L of the channel region 100 to form the crystal grains of the first polysilicon 1100 with a larger size.
  • the crystal nucleus 19' formed by the second polysilicon 1200 in the second active pattern 12 makes the first
  • the polysilicon 1100 is grown, for example, in a direction away from the second active pattern 12 (the direction indicated by the arrow in FIG. 5A ), so that the length of each first polysilicon 1100 grain is relatively large.
  • the crystal nucleus 19' formed by the second polysilicon 1200 in each second active pattern 12 is grown along a direction close to the center line of the first active pattern 11 (directions shown by two arrows in FIG. 5B ).
  • FIG. 6A it is a schematic structural diagram of the third polysilicon 1300 under a scanning electron microscope (SEM).
  • SEM scanning electron microscope
  • the boundary between two adjacent third polysilicons 1300 is a grain boundary
  • FIG. 6B it is A schematic structural diagram of the first polysilicon 1100 under a scanning electron microscope, the boundary between two adjacent first polysilicons 1100 is a grain boundary.
  • the average length of the first polysilicon 1100 is greater than the average length of the third polysilicon 1300 . Since carriers migrate along the length direction L of the channel region 100 , the mobility of the carriers increases if there are fewer grain boundaries in the length direction L of the channel region 100 .
  • At least a portion of the first active pattern 11 is located in the channel region 100 . Since the material of the first active pattern 11 includes the first polysilicon 1100 , and at least a part of the first active pattern 11 is located in the channel region 100 , there will be relatively small dimensions in the length direction L of the channel region 100 .
  • the large first polysilicon 1100 can reduce the number of grain boundaries in the length direction L of the channel region 100 and improve the mobility of carriers.
  • the first active pattern 11 includes the first polysilicon 1100 in the thickness direction, the number of grain boundaries in the first active pattern 11 along the length direction L of the channel region 100 can be further reduced, and the channel region can be further improved.
  • the mobility of carriers in 100 can be further reduced.
  • the first active patterns 11 may all be located in the channel region 100, or may be partially located in the channel region 100. In the drawings in the present disclosure, all the first active patterns 11 are located in the channel region 100, and the first active pattern 11 is located in the channel region 100.
  • the two active patterns 12 do not belong to the channel region 100 as an example for illustration. Those skilled in the art can understand that, no matter all or part of the first active pattern 11 is located in the channel region 100, the second active pattern 12 may be located in the channel region 100 or not located in the channel region 100 , that is to say, in the embodiments of the present disclosure, there is no limitation on whether part or all of the second active pattern 12 belongs to the channel region 100 .
  • first polysilicon 1100 with a larger size in the channel region 100 of the present disclosure, which can reduce the amount of friction along the channel region 100 .
  • the active layer 10 in the related art only includes one active pattern, and the material of the active pattern is polysilicon with an average grain size smaller than that of the first polysilicon 1100 , such as is the third polysilicon 1300 . Since the average grain size of the third polysilicon 1300 along the length direction L of the channel (the direction indicated by the arrow in FIG. 7 ) is relatively small, the number of grain boundaries existing among the plurality of third polysilicon 1300 is relatively small. Therefore, the mobility of carriers is less affected by the number of grain boundaries.
  • the active layer 10 includes a first active pattern 11 and a second active pattern 12, wherein the material of at least the top surface of the first active pattern 11 includes the first polysilicon 1100, the first At least part of an active pattern 11 is located in the channel region 100 , the material of the second active pattern 12 includes a second polysilicon 1200 , and along the length direction of the channel region 100 , the size of the first polysilicon 1100 is larger than that of the first polysilicon 1100 . Two polysilicon 1200 dimensions.
  • the size of the first polysilicon 1100 is larger than The size of the third polysilicon 1300 is such that on the premise of the channel region 100 of the same size, the number of grain boundaries of the channel region 100 in the present disclosure is larger than that of the channel region 100 in the related art. The smaller the number of grain boundaries, the higher the mobility of carriers, so the present disclosure can improve the mobility of carriers in the channel region 100 .
  • the thin film transistor 1 further includes: an etch stop pattern 14 disposed on the top surface D2 of the first active pattern 11 .
  • the first active pattern 11 is a rectangle, and the etching blocking pattern 14 covers the upper side of the first active pattern 11 as an example.
  • the orthographic projection of the first active pattern 11 on the substrate 2 is within the orthographic projection of the etch barrier pattern 14 on the substrate 2, and the orthographic projection of the etch barrier pattern 14 on the substrate 2 is the same as the second active pattern
  • the orthographic projections of 12 on substrate 2 do not overlap.
  • the width of the etching stopper pattern 14 is greater than or equal to the first active pattern 11, the edge of the orthographic projection of the first active pattern 11 on the substrate 2 can be made to fall within the edge of the orthographic projection of the etching barrier pattern 14 on the substrate 2, and the etching barrier pattern 14 is on the substrate 2.
  • the orthographic projection on the base 2 does not overlap with the orthographic projection of the second active pattern 12 on the substrate 2 .
  • FIG. 8A is a top view of the etch stop pattern 14 , the first active pattern 11 and the second active pattern 12 in the thin film transistor 1 .
  • the length of the etching blocking pattern 14 is equal to the length of the first active pattern 11
  • the width of the etching blocking pattern 14 is greater than the width of the first active pattern 11 .
  • FIG. 8B which is a cross-sectional view in the direction of AA′ in FIG. 8A , the length of the etching stopper pattern 14 is equal to the length of the first active pattern 11 , and the etching stopper pattern 14 is located far from the first active pattern 11 . one side of the substrate 2.
  • FIG. 8C is a top view of the etch stop pattern 14 , the first active pattern 11 and the second active pattern 12 in the thin film transistor 1
  • FIG. 8D is a cross-sectional view of FIG. 8C along B-B′.
  • the length of the etching stopper pattern 14 is equal to the length of the first active pattern 11
  • the width of the etching stopper pattern 14 is equal to the width of the first active pattern 11 .
  • width direction in the present disclosure can be understood as, for example, a direction perpendicular to the length direction L of the channel region 100 .
  • the thickness of the etch stop pattern 14 is, for example,
  • the material of the etch stop pattern 14 is, for example, SiO x (silicon oxide).
  • the etching stopper pattern 14 is located on the upper side of the first active pattern 11, when the first polysilicon film layer located on the top surface D2 is formed, due to the gravitational effect of the etching stopper pattern 14, the first polysilicon The surface roughness of the film layer is reduced, thereby reducing the defects in the first polysilicon film layer and reducing the leakage current of the thin film transistor 1 .
  • At least one side surface includes: a first side surface S1 and a second side surface S2 oppositely disposed along the length direction L of the channel region 100 ; the second active pattern 12 In contact with the first side S1 and the second side S2.
  • both the first side S1 and the second side S2 are one, and there are two second active patterns 12 , one of which is in contact with the first side S1 and the other is in contact with the second side S2 .
  • the first side S1 is multiple, that is, the first side S1-1 , the first side S1-2 and the first side S1-3 ;
  • the second side S2 is also multiple, that is, the second side S2 -1 , the second side S2 -2 and the second side S2 -3 .
  • the first polysilicon 1100 can be removed from the first active pattern Both ends of the lengthwise direction of the first active pattern 11 are grown in a direction close to the centerline of the lengthwise direction of the first active pattern 11, which can ensure that the length of the grown first polysilicon 1100 is greater than that of the second polysilicon 1200, It can also reduce the difficulty in the process of growing the first polysilicon 1100 , thereby reducing the difficulty in fabricating the first active pattern 11 .
  • the active layer 10 further includes: a third active pattern 13 , and the material of the third active pattern 13 is, for example, amorphous silicon.
  • the third active patterns 13 are disposed on opposite sides of the active pattern group 110 , and the active pattern group 110 includes the first active pattern 11 and the second active pattern 12 .
  • FIGS. 9A and 9B wherein FIG. 9A is a top view of the thin film transistor 1 , there are two third active patterns 13 , and the active pattern group 110 includes a second active pattern 12 and a first active pattern 11 .
  • the active pattern group 110 includes a second active pattern 12 and a first active pattern 11 .
  • two third active patterns 13 are located on opposite sides of the active pattern group 110 , one of the third active patterns 13 is in contact with the second active pattern 12 , and the other is in contact with the second active pattern 12 .
  • the active pattern 13 is in contact with the first active pattern 11 .
  • FIGS. 9C and 9D wherein FIG. 9C is a top view of the thin film transistor 1 , there are two third active patterns 13 , and the active pattern group 110 includes one first active pattern 11 and two second active patterns 12. Along the length direction L of the channel region 100 , the third active patterns 13 are disposed on opposite sides of the active pattern group 110 , wherein each third active pattern 13 is in contact with the second active pattern 12 .
  • the third active pattern 13 is arranged around the active pattern group 110 , and the active pattern group 110 includes the first active pattern 11 and the second active pattern 12 .
  • the third active pattern 13 is arranged around the active pattern group 110 , it is convenient to manufacture the third active pattern 13 , and the area of the third active pattern 13 is large, which can further reduce the leakage current of the thin film transistor 1 .
  • the edge of the orthographic projection of the first active pattern 11 on the substrate 2 is coincident with the edge of the orthographic projection of the etch blocking pattern 14 on the substrate 2 or roughly coincident.
  • the size of the first active pattern 11 and the etching stopper pattern 14 are the same or approximately the same, so that the first active pattern 11 and the etching stopper pattern 14 can be patterned through the same patterning process during fabrication. , so the fabrication process and fabrication difficulty of the first active pattern 11 and the etch stop pattern 14 can be simplified.
  • the patterning process includes, for example, process steps such as film formation, exposure, development, and etching.
  • the thin film transistor 1 further includes: an ohmic contact pattern 15 disposed on a side of the active layer 10 away from the substrate 2 , and the ohmic contact pattern 15 is in contact with the active layer 10 .
  • the ohmic contact pattern 15 is used to form ohmic contact with the source electrode 111 and the drain electrode 112.
  • the material of the ohmic contact pattern 15 is, for example, N+a-si, and the thickness is, for example,
  • the width of the ohmic contact pattern 15 may be greater than the width of the active layer 10, or may be less than or equal to the width of the active layer 10, both of which can achieve electrical connection with the active layer 10. Therefore, in the embodiments of the present disclosure, for The width of the ohmic contact pattern 15 is not limited.
  • FIG. 10A is a top view of the thin film transistor 1
  • the ohmic contact pattern 15 is located on the side of the third active pattern 13 away from the substrate 2
  • one of the ohmic contact patterns 15 and the second active pattern 12 is in contact with the third active pattern 13
  • another ohmic contact pattern 15 is in contact with the third active pattern 13 .
  • FIG. 10C and FIG. 10D are top-view structural views of the thin film transistor 1
  • the ohmic contact pattern 15 is located on the side of the second active pattern 12 and the third active pattern 13 away from the substrate 2, And it is in contact with the second active pattern 12 and the third active pattern 13 .
  • FIG. 10F is a top view of the thin film transistor 1
  • the ohmic contact pattern 15 is located on the side of the third active pattern 13 away from the substrate 2 and only contacts the third active pattern 13 .
  • FIG. 10H is a top view of the thin film transistor 1, and the ohmic contact pattern 15 is located on the side of the second active pattern 12 and the third active pattern 13 away from the substrate 2, which is different from the second active pattern 15.
  • the source pattern 12 is in contact with the third active pattern 13 and has a gap with the etch stop pattern 14 .
  • the above-mentioned various ohmic contact patterns 15 have simple structures and can be electrically connected to the active layer 10. After the source electrode 111 and the drain electrode 112 are subsequently fabricated on the ohmic contact pattern 15, the source electrode 111 and the drain electrode 112 pass through. The ohmic contact pattern 15 can realize electrical connection with the active layer 10 .
  • the thin film transistor 1 further includes: a gate electrode 16 disposed on a side of the active layer 10 close to the substrate 2 .
  • FIGS. 11A and 11B are longitudinal cross-sectional structural views of the thin film transistor 1, the gate 16 is disposed on the substrate 2, and a gate insulating layer 17 is also disposed between the gate 16 and the active layer 10, and the gate insulating layer 17 is used for The gate electrode 16 and the active layer 10 are insulated from each other.
  • the material of the gate insulating layer 17 is, for example, silicon oxide (SiO) and/or silicon nitride (SiN).
  • the gate insulating layer 17 includes a two-layer structure, wherein a side close to the gate 16 is a silicon nitride layer, and the thickness of the silicon nitride layer is, for example,
  • the side close to the active layer 10 is a silicon oxide layer, and the thickness of the silicon oxide layer is, for example,
  • the thin film transistor 1 is a bottom gate type structure, and the source electrode 111 and the drain electrode 112 can be directly disposed on the ohmic contact pattern 15 away from the substrate
  • the source electrode 111 is electrically connected to the active layer 10 through an ohmic contact pattern
  • the drain electrode 112 is electrically connected to the active layer 10 through an ohmic contact pattern 15;
  • the portion between the source electrode 111 and the drain electrode 112 is the channel region 100 , and the length of the channel region is L, for example.
  • FIGS. 11C to 11E which are longitudinal cross-sectional structural views of the thin film transistor 1 , the gate electrode 16 is disposed on the side of the active layer 10 away from the substrate 2 .
  • the gate 16 is disposed on the side of the etching barrier pattern 14 away from the substrate 2 , and the etching barrier pattern 14 insulates the active layer 10 and the gate 16 from each other.
  • the thin film transistor 1 when the gate 16 is disposed on the side of the active layer 10 away from the substrate 2, the thin film transistor 1 is a top-gate structure; in this structure, the gate 16 is away from the substrate 2
  • An interlayer insulating layer 18 is provided on one side of the interlayer insulating layer 18 , the source electrode 111 and the drain electrode 112 are arranged on the side of the interlayer insulating layer 18 away from the substrate 2 , and are connected to the active layer 10 through the via holes on the interlayer insulating layer 18 . electrical connection between.
  • the second active pattern 12 and the third active pattern 13 are further doped with N+ ions, and the doping concentration of N+ ions in the third active pattern 13 is greater than that in the second active pattern 12 At this time, the third active pattern 13 can be called a heavily doped pattern, and the second active pattern 12 can be called a lightly doped pattern.
  • the source electrode 111 is electrically connected to one third active pattern 13 through a via hole on the interlayer insulating layer 18
  • the drain electrode 112 is electrically connected to another third active pattern 13 through another via hole on the interlayer insulating layer 18 . connect.
  • the source electrode 111 is in contact with an ohmic contact pattern 15 through a via hole on the interlayer insulating layer 18
  • the drain electrode 112 is in contact with an ohmic contact pattern 15 through another via hole on the interlayer insulating layer 18 .
  • the ohmic contact pattern 15 contacts.
  • the portion of the active layer 10 located between the source electrode 111 and the drain electrode 112 is the channel region 100 , and the length of the channel region is L, for example.
  • the reference sign L not only represents the length of the channel region 100 but also the length direction of the channel region 100 .
  • the material of the gate electrode 16 in the bottom-gate thin film transistor and the top-gate thin film transistor is, for example, molybdenum (Mo), and the thickness is, for example,
  • the carriers in the channel region 100 thereof have high mobility.
  • an embodiment of the present disclosure further provides a method for fabricating a thin film transistor 1 , including:
  • a stacked first semiconductor pattern 11 ′ and an etch stop pattern 14 are formed on the substrate 2 .
  • the first semiconductor pattern 11 ′ is used to form the channel region 100 , and the length and length direction of the channel region 100 are L, for example.
  • the first semiconductor pattern 11 ′ includes a bottom surface D1 , a top surface D2 and at least one side surface, the bottom surface D1 and the top surface D2 are oppositely disposed along the thickness direction of the substrate 2 , and the bottom surface D1 is closer to the substrate 2 .
  • At least one side surface connects the bottom surface D1 and the top surface D2.
  • the length direction of each of the at least one side surface is perpendicular or approximately perpendicular to the length direction L of the channel region 100 .
  • the orthographic projection of the first semiconductor pattern 11 ′ on the substrate 2 is within the orthographic projection of the etch stop pattern 14 on the substrate 2 .
  • a stacked first semiconductor pattern 11 ′ and an etch stop pattern 14 are formed on the substrate 2 , which specifically includes:
  • a first semiconductor thin film 21 ′ is formed on one side of the substrate 2 , and the material of the first semiconductor thin film 21 ′ is amorphous silicon or third polysilicon 1300 .
  • the thickness of the first semiconductor thin film 21' is, for example,
  • a first insulating film 24 is formed on the side of the first semiconductor film 21 ′ away from the substrate 2 .
  • the thickness of the first insulating film 24 is, for example,
  • the material is, for example, silicon oxide.
  • the first semiconductor thin film 21 ′ and the first insulating thin film 24 are patterned through the same patterning process to form the stacked first semiconductor pattern 11 ′ and the etch stop pattern 14 .
  • the first insulating film 24 is first etched through a dry etching process to form an etch stop pattern 14, and the first insulating film is etched
  • the gas of 24 is, for example, chlorine-containing or fluorine-containing gas, such as CF 4 (tetrafluoromethane); and then the first semiconductor thin film 21 ′ is etched through a dry etching process to form a first semiconductor pattern 11 ′, wherein the first semiconductor film 21 ′ is etched
  • the gas of the semiconductor thin film 21' is, for example, Cl 2 (chlorine gas).
  • a stacked first semiconductor pattern 11 ′ and an etch stop pattern 14 are formed on the substrate 2 , which specifically includes:
  • a first semiconductor thin film 21 ′ is formed on one side of the substrate 2 , the material of the first semiconductor thin film 21 ′ is amorphous silicon or the third polysilicon 1300 , and the first semiconductor thin film 21 ′ is patterned to form the first semiconductor pattern 11'.
  • the thickness of the formed first semiconductor thin film 21' is, for example,
  • the gas for etching the first semiconductor thin film 21' is, for example, Cl 2 (chlorine).
  • a first insulating film 24 is formed on the substrate 2 on which the first semiconductor pattern 11' is formed, and the first insulating film 24 is patterned to form the etch stop pattern 14.
  • the thickness of the formed first insulating film 24 is, for example,
  • the material is, for example, silicon oxide, and the gas for etching the first insulating film 24 is, for example, CF 4 .
  • the material of the first semiconductor film 21' is amorphous silicon
  • the material of the first semiconductor pattern 11' is amorphous silicon
  • the material of the first semiconductor film 21' is the third polysilicon 1300
  • the material of the first semiconductor pattern 11' is amorphous silicon.
  • the material of 11 ′ is the third polysilicon 1300 , that is, the material of the first semiconductor pattern 11 ′ is amorphous silicon or the third polysilicon 1300 .
  • a second semiconductor thin film 22' is formed on the substrate 2 on which the first semiconductor pattern 11' and the etch stop pattern 14 are formed, and the second semiconductor thin film 22' is patterned to form a second semiconductor The pattern 12', the second semiconductor pattern 12' is in contact with at least one side surface of the first semiconductor pattern 11'.
  • the second semiconductor thin film 22' is in contact with the etching stopper pattern 14 and the first semiconductor pattern 11', and the material of the second semiconductor thin film 22' is amorphous silicon, that is, the second semiconductor thin film 22' covers the entire layer on substrate 2.
  • the second semiconductor thin film 22' is fabricated in a whole layer, covering the film layer located thereunder.
  • the second semiconductor thin film 22' will cover the buffer layer.
  • the second semiconductor thin film 22' is not in direct contact with the substrate 2, wherein the buffer layer
  • the material of the layer is, for example, at least one of silicon oxide and silicon nitride.
  • FIG. 12I is a top view of the structure diagram of the first semiconductor pattern 11 ′ and the second semiconductor pattern 12 ′ in the thin film transistor 1 , and one of the second semiconductor pattern 12 ′ and the first semiconductor pattern 11 ′
  • the side surface is in contact, for example, the side surface is the first side surface S1 whose length direction is perpendicular to the length direction L of the channel region 100 .
  • FIG. 12K is a top view of the first semiconductor pattern 11 ′ and the second semiconductor pattern 12 ′ in the thin film transistor 1 , and two of the second semiconductor pattern 12 ′ and the first semiconductor pattern 11 ′ In contact with each other, the side surfaces are, for example, the first side surface S1 and the second side surface S2 whose length direction is perpendicular to the length direction L of the channel region 100 .
  • FIG. 12L is a top view of the first semiconductor pattern 11 ′ and the second semiconductor pattern 12 ′ in the thin film transistor 1 .
  • the second semiconductor pattern 12 ′ is arranged around the first semiconductor pattern 11 ′.
  • the first semiconductor pattern 11' and at least a part of the second semiconductor pattern 12' are irradiated with the first laser 31, and at least part of the second semiconductor pattern 12' is in contact with the first semiconductor pattern 11', so that at least part of the irradiated second semiconductor pattern 12' is in contact with the first semiconductor pattern 11'.
  • the amorphous silicon in the material of the second semiconductor pattern 12 ′ is converted into the second polysilicon 1200 , so that the material of at least the top surface D2 in the first semiconductor pattern 11 ′ is converted into the first polysilicon 1100 , along the channel region 100 .
  • the average grain size of the first polysilicon 1100 is larger than the average grain size of the second polysilicon 1200 and the third polysilicon 1300 .
  • the first semiconductor pattern 11' and all of the second semiconductor patterns 12' are irradiated with the first laser 31, so that the first semiconductor pattern 11' is transformed into the first active pattern 11 , so that the one second semiconductor pattern 12 ′ is transformed into a second active pattern 12 .
  • the first semiconductor pattern 11' and all the second semiconductor patterns 12' are irradiated with the first laser 31, so that the first semiconductor pattern 11' is transformed into the first active pattern 11 , converting the two second semiconductor patterns 12 ′ into two second active patterns 12 .
  • the third active pattern 13 After the entire second semiconductor pattern 12 ′ is irradiated with the first laser 31 to form the second active pattern 12 , when fabricating the third active pattern 13 , it is necessary to fabricate the substrate 2 on which the second active pattern 12 is fabricated. A layer of amorphous silicon film is formed on top, and finally a patterning process is performed to form a third active pattern 13 on the amorphous silicon film.
  • the material of the third active pattern is a-si.
  • the first semiconductor pattern 11' and a part of the second semiconductor pattern 12' are irradiated with the first laser 31 to convert the first semiconductor pattern 11'
  • the part of the second semiconductor pattern 12 ′ irradiated by the first laser 31 is converted into the second active pattern 12
  • the material of the second active pattern 12 is the second polysilicon 1200 .
  • the material of the remaining portion of the second semiconductor pattern 12' that is not irradiated by the first laser 31 is amorphous silicon
  • the portion of the second semiconductor pattern 12' that is not irradiated by the laser 3 can be used to form the third active pattern 13, therefore, the second active pattern 12 and the third active pattern 13 can be simultaneously prepared through the second semiconductor pattern 12', and the preparation process is simple.
  • the first laser 31 irradiates part of the second semiconductor pattern 12 ′
  • the part of the second semiconductor pattern 12 ′ irradiated by the first laser 31 must be in contact with the first semiconductor pattern 11 ′ at the same time, so that the first semiconductor pattern 11 ' is converted into the first active pattern 11 .
  • the amorphous silicon in the first semiconductor pattern 11 ′ and the second semiconductor pattern 12 ′ is simultaneously melted;
  • the heat preservation effect of the etch stop pattern 14 on the semiconductor pattern 11 ′, the molten amorphous silicon in the second semiconductor pattern 12 ′ crystallizes first relative to the molten amorphous silicon in the first semiconductor pattern 11 ′, so that the molten amorphous silicon in the second semiconductor pattern 12 ′ can be Crystal nuclei are formed at at least one side surface of the semiconductor pattern 11 ′.
  • the amorphous silicon in the second semiconductor pattern 12 ′ forms a plurality of crystal nuclei near the first side surface S1 in the first semiconductor pattern 11 ′.
  • the molten amorphous silicon in the first semiconductor pattern 11 ′ can laterally grow into the first polysilicon 1100 along its length direction.
  • the material of the first semiconductor pattern 11 ′ is the third polysilicon 1300
  • the third polysilicon 1300 has no effect on the first laser
  • the absorptivity of 31 is lower than the absorptivity of amorphous silicon to the first laser 31, so when the amorphous silicon in the second semiconductor pattern 12' is completely melted, there may be only the first laser beam on the top surface D2 in the first semiconductor pattern 11'.
  • the three-polysilicon 1300 material is melted; in this way, during cooling, due to the heat preservation effect of the etch stop pattern 14 on the first semiconductor pattern 11 ′, the molten amorphous silicon in the second semiconductor pattern 12 ′ is relatively opposite to the first semiconductor pattern 11 .
  • the third polysilicon 1300 melted in the A plurality of crystal nuclei are formed at the first side surface S1 in the first semiconductor pattern 11 ′.
  • the molten third polysilicon 1300 in the first semiconductor pattern 11 ′ can laterally grow into the first polysilicon 1100 along the length direction thereof.
  • the first semiconductor pattern 11 ′ and at least part of the second semiconductor pattern 12 ′ are irradiated at a fixed point by, for example, the MLA technique, so that the first semiconductor pattern 11 ′ is transformed into the first active pattern 11 and at least part of the second semiconductor pattern 12 ′.
  • 12 ′ is transformed into the second active pattern 12 .
  • the first semiconductor pattern 11 ′ and at least part of the second semiconductor pattern 11 ′ and at least a part of the second semiconductor pattern 11 ′ and at least a part of the second semiconductor pattern 11 ′ and at least a part of the second semiconductor pattern 11 ′ and at least a part of the second semiconductor pattern 11 ′ and at least a part of the second laser beam 31 can be used for the MLA technology.
  • the semiconductor pattern 12' is irradiated.
  • the laser irradiates the entire film (for example, the film is an amorphous silicon film), while in the MLA technology, the laser irradiates a part of the film (which can be matched with a mask).
  • the plate realizes the irradiation of a partial area), so it is called spot irradiation to distinguish it from laser irradiation in ELA technology.
  • the preparation method of the thin film transistor 1 further includes:
  • an ohmic contact pattern 15 is formed on the side of the active layer 10 away from the substrate 2 , and the ohmic contact pattern 15 is in contact with the active layer 10 .
  • the material of the ohmic contact pattern 15 is, for example, N+a-si, and the thickness is, for example,
  • an ohmic contact film can be formed first, and after patterning, the ohmic contact film can form the ohmic contact pattern 15 , wherein the gas for etching the ohmic contact film is, for example, chlorine gas.
  • the N+a-si material can be directly deposited on the active layer 10 to form an ohmic contact film; an amorphous silicon film can also be formed first, and then the ohmic contact film can be formed by doping N+ particles into the amorphous silicon film.
  • the preparation method of the thin film transistor 1 further includes:
  • a source electrode 111 and a drain electrode 112 are formed on the side of the ohmic contact pattern 15 away from the substrate 2 , and the source electrode 111 and the drain electrode 112 are respectively electrically connected to the active layer 10 through the ohmic contact pattern 15 .
  • the materials of the source electrode 111 and the drain electrode 112 are, for example, conductive metals such as Mo (molybdenum), Ag (silver), and Al (aluminum).
  • the method for fabricating the thin film transistor 1 before forming the first semiconductor thin film 21 ′, the method for fabricating the thin film transistor 1 further includes:
  • a gate metal film is formed on one side of the substrate 2 and patterned to form the gate electrode 16 .
  • the thin film transistor 1 formed by this preparation method is a bottom gate thin film transistor 1 .
  • the preparation method of the thin film transistor 1 further includes:
  • a gate metal film is formed on the side of the etch stop pattern 14 away from the substrate 2 , and patterned to form the gate electrode 16 .
  • the thin film transistor 1 formed by this preparation method is a top-gate thin film transistor 1 .
  • the material of the above-mentioned gate metal film is, for example, Mo, and the thickness is, for example,
  • the method for fabricating the thin film transistor 1 includes:
  • An interlayer insulating layer 18 is formed on the side of the gate 16 away from the substrate 2 , and a source electrode 111 and a drain electrode 112 are formed on the side of the interlayer insulating layer 18 away from the substrate, wherein the source electrode 111 passes through the interlayer insulating layer 18
  • the via hole on the upper contact is in contact with the third active pattern 13, and the drain 112 is in contact with another third active pattern 13 through another via hole on the interlayer insulating layer 18; the second active pattern 12 and the third active pattern
  • the patterns 13 are all doped with N+ ions, and the doping concentration of the third active pattern 13 is greater than the doping concentration of the second active pattern 12 .
  • forming the first semiconductor thin film 21 ′ on one side of the substrate 2 includes:
  • An amorphous silicon thin film is formed on the substrate 2 .
  • the amorphous silicon film is irradiated with the second laser to convert the amorphous silicon in the amorphous silicon film into the third polysilicon 1300 to form the first semiconductor film 21 ′.
  • the material of the first semiconductor film 21 ′ is the third polysilicon film 21 ′. Polysilicon 1300.
  • the amorphous silicon in the entire amorphous silicon film can be converted into the third polysilicon 1300 by the ELA technology to form the first semiconductor film 21 ′ made of the third polysilicon 1300 , so that the material can be obtained as The first semiconductor pattern 11 ′ of the third polysilicon 1300 .
  • the energy density of the second laser used in the ELA technique is, for example, 300 mj/cm 2 to 400 mj/cm 2
  • the frequency is, for example, 100 Hz to 300 Hz.
  • the parameters of the first laser 31 and the parameters of the second laser 32 are not exactly the same, and the first laser 31 performs a localized laser annealing process, and the second laser performs an excimer laser annealing process.
  • the third polysilicon 1300 may also be directly deposited on the substrate 2 to form the first semiconductor thin film 21'.
  • the third polysilicon 1300 is formed by deposition through a PVD (Physical Vapor Deposition, physical vapor deposition) process.
  • the method for fabricating the thin film transistor 1 further includes:
  • the etch stop pattern 14 is removed.
  • the etch stop pattern 14 is removed, for example, by CF 4 .
  • the first active pattern 11 can be subjected to sample cutting detection, and the sample is placed in a 1% concentration HF (hydrofluoric acid) solution for 20S immersion, and then The sample was soaked for 20S in SECOO, which is a mixture of HF and potassium dichromate (K 2 Cr 2 O 7 ). Finally, the morphology of the first polysilicon 1100 in the first active pattern 11 was observed by SEM.
  • HF hydrofluoric acid
  • the above-mentioned method for preparing the thin film transistor 1 has the same beneficial effects as the above-mentioned thin film transistor 1 , and thus will not be repeated here.

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Abstract

一种薄膜晶体管包括：有源层；有源层具有沟道区，有源层包括：第一有源图案和第二有源图案，第一有源图案的至少部分位于沟道区中；其中，第一有源图案包括底面、顶面和至少一个侧面，至少一个侧面连接底面和顶面，至少一个侧面与第二有源图案接触，且至少一个侧面中的每个侧面的长度方向与沟道区的长度方向垂直或近似垂直；第一有源图案中至少顶面的材料包括第一多晶硅，第二有源图案的材料包括第二多晶硅；沿沟道区的长度方向，第一多晶硅的平均晶粒尺寸大于第二多晶硅的平均晶粒尺寸。

Description

薄膜晶体管及其制备方法、显示装置
本申请要求于2020年08月04日提交的、申请号为202010774215.4的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，尤其涉及一种薄膜晶体管及其制备方法、显示装置。
背景技术
在显示面板的驱动电路中，使用的最多的器件是薄膜晶体管(Thin Film Transistor，TFT)，薄膜晶体管是一种场效应晶体管。在驱动电路中，TFT的功能是一个三端开关管，三端例如栅极、源极和漏极，当栅极开启时，信号可以从源极传输至漏极。
发明内容
一方面，提供一种薄膜晶体管。所述薄膜晶体管包括：设置于衬底上的有源层。
所述有源层具有沟道区，所述有源层包括：第一有源图案和第二有源图案，所述第一有源图案的至少部分位于所述沟道区中。
其中，所述第一有源图案包括底面、顶面和至少一个侧面，所述底面和所述顶面沿所述衬底的厚度方向相对设置，且所述底面更靠近所述衬底；所述至少一个侧面连接所述底面和所述顶面，所述至少一个侧面与所述第二有源图案接触，且所述至少一个侧面中的每个侧面的长度方向与所述沟道区的长度方向垂直或近似垂直；所述第一有源图案中至少所述顶面的材料包括第一多晶硅，所述第二有源图案的材料包括第二多晶硅；沿所述沟道区的长度方向，所述第一多晶硅的平均晶粒尺寸大于所述第二多晶硅的平均晶粒尺寸。
在一些实施例中，薄膜晶体管还包括：刻蚀阻挡图案，设置于所述第一有源图案的所述顶面上；所述第一有源图案在所述衬底上的正投影在所述刻蚀阻挡图案在所述衬底上的正投影内，且所述刻蚀阻挡图案在所述衬底上的正投影与所述第二有源图案在所述衬底上的正投影不重叠。
在一些实施例中，所述至少一个侧面包括：沿所述沟道区的长度方向，相对设置的第一侧面和第二侧面；所述第二有源图案与所述第一侧面和所述第二侧面接触。
在一些实施例中，所述有源层还包括：第三有源图案，所述第三有源图案的材料为非晶硅。
沿所述沟道区的长度方向，所述第三有源图案设置于有源图案组的至少一侧。
或者，所述第三有源图案围绕所述有源图案组一周设置。
其中，所述有源图案组包括所述第一有源图案和所述第二有源图案。
在一些实施例中，所述第一有源图案在所述衬底上的正投影的边缘与所述刻蚀阻挡图案在所述衬底上的正投影的边缘重合或大致重合。
在一些实施例中，薄膜晶体管还包括：设置于所述有源层远离所述衬底的一侧的欧姆接触图案，且所述欧姆接触图案与所述有源层接触。
在一些实施例中，薄膜晶体管还包括：栅极，设置于所述有源层靠近所述衬底的一侧；或者，设置于所述有源层远离所述衬底的一侧。
在一些实施例中，所述第一有源图案的材料均为第一多晶硅或者还包括第三多晶硅，所述第三多晶硅的平均晶粒尺寸小于所述第一多晶硅的平均晶粒尺寸。
在一些实施例中，薄膜晶体管还包括：设置于所述第二有源图案远离所述衬底一侧的源极和漏极，所述源极和所述漏极分别与所述有源层电连接。
另一方面，提供一种显示装置。所述显示装置包括：如上述任一实施例所述的薄膜晶体管。
又一方面，提供一种薄膜晶体管的制备方法，包括：
在衬底上形成层叠的第一半导体图案和刻蚀阻挡图案其中，所述第一半导体图案具有沟道区，所述第一半导体图案包括底面、顶面和至少一个侧面，所述底面和所述顶面沿所述衬底的厚度方向相对设置，且所述底面更靠近所述衬底，所述至少一个侧面连接所述底面和所述顶面，所述至少一个侧面中的每个侧面的长度方向与所述沟道区的长度方向垂直或近似垂直，所述第一半导体图案在所述衬底上的正投影在所述刻蚀阻挡图案在所述衬底上的正投影内，所述第一半导体图案的材料为非晶硅或者第三多晶硅。
在形成有第一半导体图案和刻蚀阻挡图案的衬底上形成第二半导体薄膜，所述第二半导体薄膜至少与所述刻蚀阻挡图案和第一半导体图案接触，所述第二半导体薄膜的材料为非晶硅，图案化所述第二半导体薄膜以形成第二半导体图案，所述第二半导体图案与所述第一半导体图案中的所述至少一个侧面接触。
利用第一激光照射所述第一半导体图案和至少部分所述第二半导体图案，且所述至少部分第二半导体图案与所述第一半导体图案接触，以使被照射的所述至少部分第二半导体图案材料中的非晶硅转化为第二多晶硅，以使 所述第一半导体图案中至少所述顶面的材料转化为第一多晶硅，沿所述沟道区的长度方向，所述第一多晶硅的平均晶粒尺寸大于所述第二多晶硅和所述第三多晶硅的平均晶粒尺寸。
在一些实施例中，通过所述第二半导体图案中未被激光照射的部分形成第三有源图案。
在一些实施例中，在所述衬底上形成层叠的所述第一半导体图案和所述刻蚀阻挡图案，包括：
在所述衬底的一侧形成第一半导体薄膜，所述第一半导体薄膜的材料为非晶硅或第三多晶硅。
在所述第一半导体薄膜远离所述衬底的一侧形成第一绝缘薄膜。
通过同一次构图工艺图案化所述第一绝缘薄膜和所述第一半导体薄膜，以形成层叠的所述第一半导体图案和所述刻蚀阻挡图案。
或者，在所述衬底的一侧形成第一半导体薄膜，所述第一半导体薄膜的材料为非晶硅或第三多晶硅，图案化所述第一半导体薄膜以形成所述第一半导体图案。
在形成有所述第一半导体图案的所述衬底上形成第一绝缘薄膜，图案化所述第一绝缘薄膜以形成所述刻蚀阻挡图案。
在一些实施例中，薄膜晶体管的制备方法还包括：在所述有源层远离所述衬底的一侧形成欧姆接触图案，所述欧姆接触图案与所述有源层接触。
在一些实施例中，薄膜晶体管的制备方法还包括：在所述欧姆接触图案远离所述衬底的一侧形成源极和漏极，所述源极和所述漏极分别通过所述欧姆接触图案与所述有源层电连接。
在一些实施例中，在形成所述第一半导体薄膜之前，所述制备方法还包括：在所述衬底的一侧形成栅极金属薄膜，图案化以形成栅极。
在一些实施例中，薄膜晶体管的制备方法还包括：在所述刻蚀阻挡图案远离所述衬底的一侧形成栅极金属薄膜，图案化以形成栅极。
在一些实施例中，在所述衬底的一侧形成所述第一半导体薄膜包括：
在所述衬底上形成非晶硅薄膜。
利用第二激光照射所述非晶硅薄膜，以使所述非晶硅薄膜中的非晶硅转化成第三多晶硅，以形成所述第一半导体薄膜，所述第一半导体薄膜的材料为第三多晶硅。
在一些实施例中，所述第一激光执行区域化激光退火工艺，所述第二激光执行准分子激光退火工艺。
在一些实施例中，薄膜晶体管的制备方法还包括：去除所述刻蚀阻挡图案。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1A～图1C为根据本公开的一些实施例提供的一种薄膜晶体管的俯视结构图；
图2A～图2G为根据本公开的一些实施例提供的另一种薄膜晶体管的俯视结构图；
图3A～图3B为根据本公开的一些实施例提供的一种第一有源图案的纵截面结构图；
图4为根据本公开的一些实施例提供的一种非晶硅转化为多晶硅的过程图；
图5A～图5B为根据本公开的一些实施例提供的一种第一有源图案中第一多晶硅和第二有源图案中的第二多晶硅的平均晶粒尺寸的对比图；
图6A为根据本公开的一些实施例提供的一种第三多晶硅的晶粒的结构图；
图6B为根据本公开的一些实施例提供的一种第一多晶硅的晶粒的结构图；
图7为相关技术提供的一种有源层中第三多晶硅的晶粒的结构图；
图8A为根据本公开的一些实施例提供的另一种薄膜晶体管俯视图；
图8B为图8A中A-A′向的纵截面图；
图8C为根据本公开的一些实施例提供的另一种薄膜晶体管俯视图；
图8D为图8C中B-B′向的纵截面图；
图9A为根据本公开的一些实施例提供的另一种薄膜晶体管俯视图；
图9B为图9A中C-C′向的纵截面图；
图9C为根据本公开的一些实施例提供的另一种薄膜晶体管俯视图；
图9D为图9C中D-D′向的纵截面图；
图9E为根据本公开的一些实施例提供的另一种薄膜晶体管俯视图；
图9F为根据本公开的一些实施例提供的另一种薄膜晶体管俯视图；
图10A为根据本公开的一些实施例提供的另一种薄膜晶体管俯视图；
图10B为图10A中E-E′向的纵截面图；
图10C为根据本公开的一些实施例提供的另一种薄膜晶体管俯视图；
图10D为根据本公开的一些实施例提供的另一种薄膜晶体管俯视图；
图10E为图10C和图10D中F-F′向的纵截面图；
图10F为根据本公开的一些实施例提供的另一种薄膜晶体管俯视图；
图10G为图10F中G-G′向的纵截面图；
图10H为根据本公开的一些实施例提供的另一种薄膜晶体管俯视图；
图10I为图10H中H-H′向的纵截面图；
图11A～图11E为根据本公开的一些实施例提供的另一种薄膜晶体管的纵截面结构图；
图12A为根据本公开的一些实施例提供的一种薄膜晶体管的制备方法的流程图；
图12B为根据本公开的一些实施例提供的一种薄膜晶体管的制备过程中的纵截面图；
图12C为根据本公开的一些实施例提供的另一种薄膜晶体管的制备方法的流程图；
图12D为根据本公开的一些实施例提供的另一种薄膜晶体管的制备过程中的纵截面图；
图12E为根据本公开的一些实施例提供的又一种薄膜晶体管的制备方法的流程图；
图12F～图12H为根据本公开的一些实施例提供的另一种薄膜晶体管的制备过程中的纵截面图；
图12I为根据本公开的一些实施例提供的另一种薄膜晶体管的制备过程中的俯视结构图；
图12J为图12I中I-I′向的纵截面图；
图12K和图12L为根据本公开的一些实施例提供的另一种薄膜晶体管的制备过程中的俯视结构图；
图12M为图12K和图12L中J-J′向的纵截面图；
图12N和图12O为根据本公开的一些实施例提供的另一种薄膜晶体管的制备过程中的纵截面图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“耦接”和“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。又如，描述一些实施例时可能使用了术语“耦接”以表明两个或两个以上部件有直接物理接触或电接触。然而，术语“耦接”或“通信耦合(communicatively coupled)”也可能指两个或两个以上部件彼此间并无直接接触，但仍彼此协作或相互作用。这里所公开的实施例并不必然限制于本文内容。
“A、B和C中的至少一个”与“A、B或C中的至少一个”具有相同含义，均包括以下A、B和C的组合：仅A，仅B，仅C，A和B的组合，A和C的组合，B和C的组合，及A、B和C的组合。
“A和/或B”，包括以下三种组合：仅A，仅B，及A和B的组合。
如本文中所使用，根据上下文，术语“如果”任选地被解释为意思是“当……时”或“在……时”或“响应于确定”或“响应于检测到”。类似地，根据上下文，短语“如果确定……”或“如果检测到[所陈述的条件或事件]”任选地被解释为是指“在确定……时”或“响应于确定……”或“在检 测到[所陈述的条件或事件]时”或“响应于检测到[所陈述的条件或事件]”。
本文中“适用于”或“被配置为”的使用意味着开放和包容性的语言，其不排除适用于或被配置为执行额外任务或步骤的设备。
另外，“基于”的使用意味着开放和包容性，因为“基于”一个或多个所述条件或值的过程、步骤、计算或其他动作在实践中可以基于额外条件或超出所述的值。
如本文所使用的那样，“约”或“近似”包括所阐述的值以及处于特定值的可接受偏差范围内的平均值，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。
如本文所使用的那样，本公开中的“平均”值应当理解为算术平均值，例如平均晶粒的尺寸应当理解为晶粒尺寸的算术平均值。
本文参照作为理想化示例性附图的剖视图和/或平面图描述了示例性实施方式。在附图中，为了清楚，放大了层和区域的厚度。因此，可设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此，示例性实施方式不应解释为局限于本文示出的区域的形状，而是包括因例如制造而引起的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设备的区域的实际形状，并且并非旨在限制示例性实施方式的范围。
本公开的实施例提供一种显示装置，该显示装置例如可以是LCD(Liquid Crystal Display，液晶显示器)、OLED(Organic Light-Emitting Diode，有机发光二极管)显示装置和QLED(Quantum Dot Light Emitting Diodes，量子点发光二极管)显示装置中的任一种。
上述显示装置的驱动电路包括：电连接的多个薄膜晶体管1和一些其它器件。其中，驱动电路例如包括像素驱动电路和GOA(Gate Driver On Array，阵列基板行驱动)电路；一些其它器件例如为电容，该电容例如为存储电容。
示例的，像素驱动电路例如为2T1C型、7T1C型等。GOA电路例如为3T1C型、8T2C型等，GOA电路可以是Gate GOA电路(栅极驱动电路)，也可以是EM GOA电路(发光控制电路)。其中，T代表薄膜晶体管、C代表电容，例如2T1C即为包括2个薄膜晶体管和1个电容的像素驱动电路。像素驱动电路和GOA电路中的薄膜晶体管和电容的数量，均可根据实际需求而进行选择，因此，本公开中对像素驱动电路和GOA电路中的薄膜晶体管和电容的数量均不做限制，仅以上述列举的像素驱动电路和GOA电路，以说明该 些驱动电路需要使用薄膜晶体管构成而已。
基于上述，本公开的实施例提供一种薄膜晶体管，包括：设置于衬底上的有源层；有源层具有沟道区。
示例的，有源层的厚度例如为
Figure PCTCN2021105319-appb-000001
在一些实施例中，薄膜晶体管还可以包括源极和漏极。源极和漏极分别与有源层电连接，有源层中位于源极和漏极之间的区域为沟道区，沟道区可以使得信号例如从源极经过沟道区传输至漏极。
参考图1A～图1C示出了薄膜晶体管1的俯视结构图，根据有源层10、源极111和漏极112之间的结构以及连接关系，有源层10上的沟道区100的形状例如包括矩形和U形。
示例的，参考图1A，薄膜晶体管1中有源层10上的沟道区100为矩形，长度例如为L，同时L也表示沟道区100的长度方向。
参考图1B和图1C，薄膜晶体管1中有源层10上的沟道区100为U形，最大长度例如为L，L也表示沟道区100的长度方向。参考图1C，当沟道区100为U形时，沟道区100的长度方向L可能是沿着U形轨迹变化的。
参考图2A～图2F为有源层10的俯视结构图，该有源层10包括：第一有源图案11和第二有源图案12，第一有源图案11的至少部分位于沟道区100中。
其中，第一有源图案11包括底面、顶面和至少一个侧面，底面和顶面沿衬底2的厚度方向相对设置，且底面更靠近衬底2。
至少一个侧面连接底面和顶面，至少一个侧面与第二有源图案12接触，且至少一个侧面中的每个侧面的长度方向与沟道区100的长度方向垂直或近似垂直。
至少一个侧面应当理解为与第二有源图案12接触，且长度方向与沟道区100长度的方向L垂直的侧面，并不包括那些虽然可以连接第一有源图案11中的底面和顶面，但长度方向却与沟道区100的长度方向L不垂直的侧面，和/或未与第二有源图案12接触的侧面。其中，与第二有源图案12接触，可以理解为与第二有源图案12直接接触。
示例的，针对图1A所示的薄膜晶体管1的结构，其有源层10结构例如如图2A和图2B所示。
其中，参考图2A，沟道区100为矩形，长度方向与沟道区100的长度方向L垂直且与第二有源图案12接触的侧面为第一侧面S1。
参考图2B，沟道区100为矩形，长度方向与沟道区100的长度方向L垂 直且与第二有源图案12接触的侧面为第一侧面S1和第二侧面S2，其中第一侧面S1和第二侧面S2沿沟道区100的长度方向L相对设置。
沿沟道区100的长度方向L相对设置的第一侧面S1和第二侧面S2中的第一侧面S1和第二侧面S2可以为一个侧面也可以为多个。示例的，第一侧面S1和第二侧面S2均为多个，在多个第一侧面S1中，相邻两个侧面之间存在拐角；在多个第二侧面S2中，相邻两个侧面之间也存在拐角。
针对图1B所示的薄膜晶体管1的结构，其有源层10的结构例如参考图2C～图2E，其中有源层10中的沟道区100为U形，长度方向与沟道区100的长度方向L垂直且与第二有源图案12接触的侧面包括至少一个第一侧面S1和至少一个第二侧面S2。当第一侧面S1和第二侧面S2均为多个时，其中，多个第一侧面S1例如为依次连接的第一侧面S1 -1、第一侧面S1 -2和第一侧面S1 -3，多个第二侧面S2例如为依次连接的第二侧面S2 -1、第二侧面S2 -2和第二侧面S1 -3。
参考图2C，长度方向与沟道区100的长度方向L垂直且与第二有源图案12接触的第一侧面S1 -1和第二侧面S2 -1均为一个，其中第二有源图案12与第一侧面S1 -1和/或第二侧面S2 -1接触。
参考图2D，长度方向与沟道区100的长度方向L垂直且与第二有源图案12接触的第一侧面S1为多个，即依次连接的第一侧面S1 -1、第一侧面S1 -2和第一侧面S1 -3。
参考图2E，长度方向与沟道区100的长度方向L垂直且与第二有源图案12接触的第一侧面S1和第二侧面S2均为多个，其中，多个第一侧面S1例如为依次连接的第一侧面S1 -1、第一侧面S1 -2和第一侧面S1 -3；多个第二侧面S2例如为依次连接的第二侧面S2 -1、第二侧面S2 -2和第二侧面S2 -3；其中，第一侧面S1 -1与第二侧面S2 -1沿沟道区100的长度方向L相对设置、第一侧面S1 -2与第二侧面S2 -2沿沟道区100的长度方向L相对设置、第一侧面S1 -3与第二侧面S2 -3沿沟道区100的长度方向L相对设置。
针对图1C所示的薄膜晶体管1的结构，其有源层10的结构例如参考图2F和图2G。
其中，参考图2F，沟道区100为U形，长度方向与沟道区100的长度方向L垂直，且与第二有源图案12接触的侧面包括多个第一侧面S1，即依次连接的第一侧面S1 -1、第一侧面S1 -2和第一侧面S1 -3。
参考图2G，沟道区100为U形，长度方向与沟道区100的长度方向L垂直且与第二有源图案12接触的侧面包括多个第一侧面S1和多个第二侧面S2； 其中，多个第一侧面S1例如为依次连接的第一侧面S1 -1、第一侧面S1 -2和第一侧面S1 -3；多个第二侧面S2例如为依次连接的第二侧面S2 -1、第二侧面S2 -2和第二侧面S2 -3；其中，第一侧面S1 -1与第二侧面S2 -1沿沟道区100的长度方向L相对设置、第一侧面S1 -2与第二侧面S2 -2沿沟道区100的长度方向L相对设置、第一侧面S1 -3与第二侧面S2 -3沿沟道区100的长度方向L相对设置。
在一些实施例中，当第二有源图案12与相对设置的第一侧面S1和第二侧面S2接触时，有利于制作第一有源图案11。示例的，参考图2B、图2E和图2G，第二有源图案12为两个，每个第二有源图案12与至少一个第一侧面S1和至少一个第二侧面S2接触。
第一有源图案11中至少顶面的材料包括第一多晶硅，第二有源图案12的材料包括第二多晶硅；沿沟道区100的长度方向L，第一多晶硅的平均晶粒尺寸大于第二多晶硅的平均晶粒尺寸。
由于非晶硅(amorphous silicon，a-si)的电子迁移率低于1cm 2/V·s，从而制约着TFT中载流子的迁移率。采用工艺温度低于600℃的低温多晶硅(Low Temperature Poly-Silicon，LTPS)技术，可以使TFT的中电子的迁移率达到300cm 2/V·s，其中的多晶硅(polycrystalline silicon，p-si)是单质硅的一种形态。
示例的，参考图3A为薄膜晶体管1中第一有源图案11的纵截面结构图，纵截面为沿衬底2的厚度方向延伸的截面，第一有源图案11包括两层结构，其中靠近第一底面D1的为第一子图案101，靠近第二底面D2的为第二子图案102。第一子图案101的材料为第三多晶硅，沿沟道区100的长度方向L，第三多晶硅的平均晶粒尺寸小于第一多晶硅的均晶粒尺寸，第二子图案102的材料为第一多晶硅。当第二子图案102的材料为第一多晶硅时，在制备第一有源图案11时，由于第二子图案102位于远离衬底2的一侧，因此便于将第二子图案102中的材料制备为第一多晶硅。当第一有源图案11为两层结构时，可以在第一有源图案11的纵截面剖视图中看到第一子图案101和第二子图案102的分界面。
又示例的，参考图3B为薄膜晶体管1中第一有源图案11的纵截面结构图，第一有源图案11为单层结构，且材料中仅包括第一多晶硅，即第一有源图案11整体均为第一多晶硅材料的。在该种结构中，底面D1和顶面D2以及位于底面D1和顶面D2之间的部分中均为第一多晶硅。
LTPS工艺形成的p-si晶粒是由许多Si原子的小规模结晶颗粒(crystallites，晶粒)组合而成。相邻两个晶粒之间的边界称为晶界。由于TFT 在工作时，载流子是沿着沟道区100的长度方向迁移的，因此沿沟道区100的长度方向上存在的晶界越少时，载流子的迁移率则会越高。在LTPS工艺中例如可以使用准分子激光结晶化法(Excimer Laser Crystallization，ELC)制备p-si晶粒。根据具体工艺条件的不同，ELC又可以包括准分子激光退火(Excimer Laser Annealing，ELA)和区域化激光退火(Micro lens array Laser Annealing，MLA)。在ELA和MLA技术中，均需要使用激光脉冲照射待制作为p-si的薄膜，而在形成p-si晶粒的过程中，需要先形成结晶核。示例的，参考图4为p-si晶粒横向(沿沟道区100的长度方向)生长的过程图，当一个shot(激光3的射击次数)的激光3照射到位于衬底2上的a-si薄膜19的表面时，使a-si薄膜19的表面在温度到达熔点时即达到了晶化阈值能量密度，a-si薄膜19的表面融化前沿会以10m/s左右的速度深入a-si薄膜19的内部。a-si薄膜19照射后的温度，沿其长度方向，中间高两头低，在熔融的a-si和未熔融的a-si的边界处形成了结晶核19′。停止激光3照射后，融层首先从两边开始以108K/s～1010K/s的速度冷却。固相和液相之间的界面将以1m/s～2m/s的速度移动到中间和表面，中间依次形成结晶核19′。冷却之后a-si薄膜19中被激光3照射到的部分a-si晶化为p-si，以结晶核19′为界形成p-si晶粒。激光3的照射强度(能量密度)越大，p-si晶粒的尺寸越大，迁移率越大。但是，能量受激光器的限制，不能无限地增大，太大的能量密度反而会使p-si迁移率下降。准分子激光的能量晶化阈值限定了每次shot的p-si晶粒横向生产的范围，在p-si晶粒的边界分布这大量的结晶核19′，结晶核19′的材料主要为p-si。示例的，上述过程中的激光3的能量密度为300mj/cm 2～400mj/cm 2，频率为100HZ～100HZ。
通过上述过程可以理解，晶粒的生长过程分为两步，第一步是形成结晶核，第二步是生长。在上述形成p-si晶粒的过程中，在a-si薄膜19熔融的区域，由于边缘无结晶核19′的引导，在a-si薄膜19中a-si是随机形成结晶核19′的，从而导致最终形成的p-si晶粒尺寸(例如长度)较小。通过实验发现，当在a-si薄膜19的熔融区域的边缘位置处有结晶核19′存在时，结晶核19′可以起到引导作用，使得多晶硅的晶化可通过结晶核19′往完全熔融的方向生长，因此横向晶粒(例如晶粒的长度)往往比膜厚大，该过程称为超级横向生长。在本公开中，将不是超级横向生长，而是随机生成的p-si晶粒称为第二多晶硅和第三多晶硅，将超级横向生长而成的p-si晶粒称为第一多晶硅，从而可知第一多晶硅的平均晶粒尺寸是大于第二多晶硅和第三多晶硅的平均晶粒尺寸的，该处的平均晶粒尺寸例如可以理解为平均晶粒长度，即第一多晶硅的 平均晶粒长度是大于第二多晶硅的平均晶粒长度的。
基于上述，虽然第二多晶硅和第三多晶硅均是随机生成的，但是受到生成的过程中所使用的激光参数，以及用于生成第二多晶硅的膜层厚度和用于生成第三多晶硅的膜层厚度的影响，所以第二多晶硅的平均晶粒尺寸和第三多晶硅的平均晶粒尺寸可能是相同的，也可能是不同的，但均是小于第一多晶硅的平均晶粒尺寸的。
示例的，参考图5A和图5B，沿沟道区100的长度方向L，当第一多晶硅的平均晶粒尺寸较大时，可以减少有源层10中沿沟道区100的长度方向L的晶界的数量，从而可以提高TFT中载流子的迁移率。
在本公开的实施例中，第二有源图案12中的第二多晶硅1200主要用于在形成第一有源图案11中的第一多晶硅1100时，形成结晶核19′，以使得第一多晶硅1100的晶粒可以沿沟道区100的长度方向L定向横向生长，形成较大尺寸的第一多晶硅1100晶粒。
示例的，参考图5A，当第二有源图案12为一个时，沿沟道区100的长度方向L，第二有源图案12中第二多晶硅1200形成的结晶核19′使得第一多晶硅1100例如沿着远离第二有源图案12的方向(图5A中箭头所示方向)生长，从而使得每个第一多晶硅1100晶粒的长度较大。
示例的，参考图5B，当第二有源图案12为两个时，沿沟道区100的长度方向L，每一个第二有源图案12中第二多晶硅1200形成的结晶核19′使得第一多晶硅1100沿着靠近第一有源图案11中心线的方向(图5B中两个箭头所示的方向)生长。
参考图6A，为第三多晶硅1300在扫描电子显微镜(Scanning Electron Microscope，SEM)下的结构示意图，相邻两个第三多晶硅1300之间的边界为晶界；参考图6B，为第一多晶硅1100在扫描电子显微镜下的结构示意图，相邻两个第一多晶硅1100之间的边界为晶界。从图6A和图6B中可以明显看出，沿沟道区100的长度方向L，第一多晶硅1100的平均长度大于第三多晶硅1300的平均长度。由于载流子沿着沟道区100的长度方向L迁移，因此若在沟道区100的长度方向L上的晶界越少，载流子的迁移率则会越大。
第一有源图案11的至少部分位于沟道区100中。由于第一有源图案11的材料中包括第一多晶硅1100，而第一有源图案11的至少部分位于沟道区100中，所以在沟道区100的长度方向L上会存在尺寸较大的第一多晶硅1100，从而可以减少在沟道区100的长度方向L上的晶界数量，提高载流子的迁移率。当第一有源图案11沿厚度方向上均包括第一多晶硅1100时，第一有源 图案11中沿沟道区100的长度方向L的晶界数量可以进一步减少，进一步提高沟道区100中的载流子的迁移率。
第一有源图案11可以全部位于沟道区100中，也可以部分位于沟道区100中，本公开中的附图中以第一有源图案11的全部位于沟道区100中，且第二有源图案12不属于沟道区100为例进行示意。而本领域技术人员可以理解的是，无论第一有源图案11的全部或者部分位于沟道区100中时，第二有源图案12可以位于沟道区100中，也可以不位于沟道区100中，也就是说本公开的实施例中对于第二有源图案12的部分或者全部是否属于沟道区100不做限定。而无论第二有源图案12的至少部分是否位于沟道区100中，在本公开的沟道区100中始终存在尺寸较大的第一多晶硅1100，均可以减少沿沟道区100的长度方向上的晶界的数量。
示例的，参考图2B、图2E和图2G，第一有源图案11的全部位于沟道区100中，第二有源图案12位于沟道区100外；此时第一有源图案11的形状与沟道区100的形状完全相同。
结合图6A和图7所示，相关技术中的有源层10仅包括一个有源图案，且该有源图案的材料均为平均晶粒尺寸小于第一多晶硅1100的多晶硅，该多晶硅例如为第三多晶硅1300。由于沿沟道的长度方向L(图7中箭头所示方向)，第三多晶硅1300的平均晶粒尺寸较小，因此，多个第三多晶硅1300之间存在的晶界数量较多，从而导致载流子的迁移率受晶界数量的影响较低。
而在本公开的实施例中，有源层10包括第一有源图案11和第二有源图案12，其中第一有源图案11中至少顶面的材料包括第一多晶硅1100，第一有源图案11的至少部分位于沟道区100，第二有源图案12的材料包括第二多晶硅1200，且沿沟道区100的长度方向，第一多晶硅1100的尺寸大于第二多晶硅1200的尺寸。由于第一有源图案11的至少部分位于沟道区100中，使得沟道区100中存在第一多晶硅1100，且沿沟道区100的长度方向，第一多晶硅1100的尺寸大于第三多晶硅1300的尺寸，从而使得在相同尺寸的沟道区100的前提下，本公开中的沟道区100的晶界数量相对于相关技术中的沟道区100的晶界数量较少，而晶界数越少，载流子的迁移率越高，所以本公开可以提高沟道区100中载流子的迁移率。
在一些实施例中，参考图8A～图8D，薄膜晶体管1还包括：刻蚀阻挡图案14，设置于第一有源图案11的顶面D2上。
参考图8A～图8D，以第一有源图案11为矩形，刻蚀阻挡图案14覆盖在第一有源图案11的上侧为例。
第一有源图案11在衬底2上的正投影在刻蚀阻挡图案14在衬底2上的正投影内，且刻蚀阻挡图案14在衬底2上的正投影与第二有源图案12在衬底2上的正投影不重叠。
由于第一有源图案11与第二有源图案12接触，因此，当刻蚀阻挡图案14的长度等于第一有源图案11的长度，刻蚀阻挡图案14的宽度大于等于第一有源图案11的宽度时，可以使得第一有源图案11在衬底2上的正投影的边缘落在刻蚀阻挡图案14在衬底2上的正投影的边缘以内，且刻蚀阻挡图案14在衬底2上的正投影与第二有源图案12在衬底2上的正投影不重叠。
示例的，参考图8A为薄膜晶体管1中刻蚀阻挡图案14、第一有源图案11和第二有源图案12的俯视图。其中，刻蚀阻挡图案14的长度等于第一有源图案11的长度，刻蚀阻挡图案14的宽度大于第一有源图案11的宽度。
在此基础上，参考图8B为图8A中A-A′向的截面图，刻蚀阻挡图案14的长度等于第一有源图案11的长度，且刻蚀阻挡图案14位于第一有源图案11远离衬底2的一侧。
又示例的，参考图8C为薄膜晶体管1中刻蚀阻挡图案14、第一有源图案11和第二有源图案12的俯视图，参考图8D为图8C中B-B′向的截面图。刻蚀阻挡图案14的长度等于第一有源图案11的长度，刻蚀阻挡图案14的宽度等于第一有源图案11的宽度。
本领域技术人员可以理解的是，本公开中的宽度方向例如可以理解为与沟道区100的长度方向L垂直的方向。
示例的，刻蚀阻挡图案14的厚度例如为
Figure PCTCN2021105319-appb-000002
刻蚀阻挡图案14的材料例如为SiO x(氧化硅)。
因为刻蚀阻挡图案14位于第一有源图案11的上侧，在形成位于顶面D2的第一多晶硅膜层时，由于刻蚀阻挡图案14的重力作用，可以使得第一多晶硅膜层的表面粗糙度降低，从而以减少第一多晶硅膜层中的缺陷，降低薄膜晶体管1的漏电流大小。
在一些实施例中，参考图2B、图2E和图2G，至少一个侧面包括：沿沟道区100的长度方向L，相对设置的第一侧面S1和第二侧面S2；第二有源图案12与第一侧面S1和第二侧面S2接触。
其中，参考图2B，第一侧面S1和第二侧面S2均为一个，第二有源图案12为两个，其中一个与第一侧面S1接触，另一个与第二侧面S2接触。
参考图2E和图2G，第一侧面S1为多个，即第一侧面S1 -1、第一侧面S1 -2和第一侧面S1 -3；第二侧面S2也为多个，即第二侧面S2 -1、第二侧面S2 -2和 第二侧面S2 -3。第二有源图案12为两个，其中一个与第一侧面S1 -1、第一侧面S1 -2和第一侧面S1 -3接触，另一个与第二侧面S2 -1、第二侧面S2 -2和第二侧面S2 -3接触。
由于第一多晶硅1100生长时的最大长度有限，因此当第二有源图案12与第一侧面S1和第二侧面S2同时接触时，可以使得第一多晶硅1100从第一有源图案11的长度方向的两端向靠近第一有源图案11中的长度方向的中心线的方向生长，既可以保证生长出的第一多晶硅1100的长度大于第二多晶硅1200的长度，还可以降低第一多晶硅1100生长时的工艺难度，从而降低制作第一有源图案11的难度。
在一些实施例中，参考图9A～图9F，有源层10还包括：第三有源图案13，第三有源图案13的材料例如为非晶硅。
沿沟道区100的长度方向，第三有源图案13设置于有源图案组110的相对两侧，有源图案组110包括第一有源图案11和第二有源图案12。
参考图9A和图9B，其中图9A为薄膜晶体管1的俯视结构图，第三有源图案13为两个，有源图案组110包括一个第二有源图案12和一个第一有源图案11。沿沟道区100的长度方向L，两个第三有源图案13位于有源图案组110的相对两侧，其中一个第三有源图案13与第二有源图案12接触，另一个第三有源图案13与第一有源图案11接触。
参考图9C和图9D，其中图9C为薄膜晶体管1的俯视结构图，第三有源图案13为两个，有源图案组110包括一个第一有源图案11和两个第二有源图案12。沿沟道区100的长度方向L，第三有源图案13设置于有源图案组110的相对两侧，其中每个第三有源图案13均与第二有源图案12接触。
在另一些实施例中，参考图9E和图9F均为薄膜晶体管1的俯视结构图，第三有源图案13围绕有源图案组110一周设置，有源图案组110包括第一有源图案11和第二有源图案12。第三有源图案13围绕有源图案组110一周设置时，便于制作第三有源图案13，且第三有源图案13的面积较大，可以进一步降低薄膜晶体管1的漏电流。
在一些实施例中，参考图8C、图9C和图9F，第一有源图案11在衬底2上的正投影的边缘与刻蚀阻挡图案14在衬底2上的正投影的边缘重合或大致重合。在该种结构中，第一有源图案11和刻蚀阻挡图案14的尺寸相同或者大致相同，从而在制作时，可以通过同一次构图工艺图案化第一有源图案11和刻蚀阻挡图案14，因此可以简化第一有源图案11和刻蚀阻挡图案14的制作工艺和制作难度。其中的构图工艺例如包括：成膜、曝光、显影和刻蚀等 工艺步骤。
在一些实施例中，参考图10A～图10I，薄膜晶体管1还包括：设置于有源层10远离衬底2的一侧的欧姆接触图案15，且欧姆接触图案15与有源层10接触。
欧姆接触图案15用于与源极111和漏极112之间形成欧姆接触，欧姆接触图案15的材料例如为N+a-si，厚度例如为
Figure PCTCN2021105319-appb-000003
欧姆接触图案15的宽度例如可以大于有源层10的宽度，也可以小于等于有源层10的宽度，均能实现与有源层10之间的电连接，因此本公开的实施例中，对于欧姆接触图案15的宽度不做限定。
参考图10A和图10B，其中图10A为薄膜晶体管1的俯视结构图，欧姆接触图案15位于第三有源图案13远离衬底2的一侧，其中一个欧姆接触图案15与第二有源图案12和第三有源图案13接触，另一个欧姆接触图案15与第三有源图案13接触。
参考图10C～图10E，其中，图10C和图10D均为薄膜晶体管1的俯视结构图，欧姆接触图案15位于第二有源图案12和第三有源图案13远离衬底2的一侧，且与第二有源图案12和第三有源图案13接触。
参考图10F和图10G，其中，图10F为薄膜晶体管1的俯视结构图，欧姆接触图案15位于第三有源图案13远离衬底2的一侧，且仅与第三有源图案13接触。
参考图10H和图10I，其中，图10H为薄膜晶体管1的俯视结构图，欧姆接触图案15位于第二有源图案12和第三有源图案13远离衬底2的一侧，与第二有源图案12和第三有源图案13接触，且与刻蚀阻挡图案14之间具有间隙。
上述的多种欧姆接触图案15的结构简单，且均可以实现与有源层10的电连接，后续在欧姆接触图案15上制作源极111和漏极112之后，源极111和漏极112通过欧姆接触图案15便可以实现与有源层10之间的电连接。
在一些实施例中，参考图11A，薄膜晶体管1还包括：栅极16，设置于有源层10靠近衬底2的一侧。
参考图11A和图11B为薄膜晶体管1的纵截面结构图，栅极16设置于衬底2上，栅极16与有源层10之间还设置有栅绝缘层17，栅绝缘层17用于使栅极16与有源层10之间相互绝缘。栅绝缘层17的材料例如为氧化硅(SiO)和/或氮化硅(SiN)。
在另一些实施例中，栅绝缘层17包括两层结构，其中，靠近栅极16的 一侧为氮化硅层，该氮化硅层的厚度例如为
Figure PCTCN2021105319-appb-000004
靠近有源层10的一侧为氧化硅层，该氧化硅层的厚度例如为
Figure PCTCN2021105319-appb-000005
参考图11B，当栅极16设置于有源层10靠近衬底2的一侧时，该薄膜晶体管1为底栅型结构，源极111和漏极112可以直接设置在欧姆接触图案15远离衬底2的一侧，其中，源极111通过一个欧姆接触图案15与有源层10实现电连接，漏极112通过一个欧姆接触图案15与有源层10实现电连接；有源层10中位于源极111和漏极112之间的部分为沟道区100，沟道区的长度例如为L。
在另一些实施例中，参考图11C～图11E为薄膜晶体管1的纵截面结构图，栅极16设置于有源层10远离衬底2的一侧。
示例的，参考图11C和图11D，栅极16设置于刻蚀阻挡图案14远离衬底2的一侧，刻蚀阻挡图案14使得有源层10与栅极16之间相互绝缘。
参考图11D和图11E，当栅极16设置于有源层10远离衬底2的一侧时，该薄膜晶体管1为顶栅型结构；在该种结构中，在栅极16远离衬底2的一侧设置有层间绝缘层18，源极111和漏极112设置在层间绝缘层18远离衬底2的一侧，且通过层间绝缘层18上的过孔实现与有源层10之间的电连接。
在一些实施例中，第二有源图案12和第三有源图案13中还掺杂有N+离子，且第三有源图案13中N+离子的掺杂浓度大于第二有源图案12中N+的掺杂浓度，此时，第三有源图案13可称为重掺杂图案，第二有源图案12可称为轻掺杂图案。源极111通过层间绝缘层18上的一个过孔与一个第三有源图案13电连接，漏极112通过层间绝缘层18上的另一个过孔与另一个第三有源图案13电连接。
在另一些实施例中，参考图11E，源极111通过层间绝缘层18上的一个过孔与一个欧姆接触图案15接触，漏极112通过层间绝缘层18上的另一个过孔与一个欧姆接触图案15接触。
有源层10中位于源极111和漏极112之间的部分为沟道区100，沟道区的长度例如为L。
需要说明的是，在本公开的实施例中，附图标记L既表示沟道区100的长度，也可以表示沟道区100的长度方向。
上述底栅型薄膜晶体管和顶栅型薄膜晶体管中的栅极16的材料例如为钼(Mo)，厚度例如为
Figure PCTCN2021105319-appb-000006
无论本公开中的薄膜晶体管1为底栅型结构还是顶栅型结构，其沟道区100中的载流子均具有较高的迁移率。
参考图12A，本公开的实施例还提供一种薄膜晶体管1的制备方法，包括：
S1、参考图12B，在衬底2上形成层叠的第一半导体图案11′和和刻蚀阻挡图案14。
其中，第一半导体图案11′的至少部分用于形成沟道区100，沟道区100的长度和长度方向例如为L。第一半导体图案11′包括底面D1、顶面D2和至少一个侧面，底面D1和顶面D2沿衬底2的厚度方向相对设置，且底面D1更靠近衬底2。至少一个侧面连接底面D1和顶面D2。至少一个侧面中的每个侧面的长度方向与沟道区100的长度方向L垂直或近似垂直。第一半导体图案11′在衬底2上的正投影在刻蚀阻挡图案14在衬底2上的正投影内。
在一些实施例中，参考图12C，在衬底2上形成层叠的第一半导体图案11′和刻蚀阻挡图案14，具体包括：
S11、参考图12D，在衬底2的一侧形成第一半导体薄膜21′，第一半导体薄膜21′的材料为非晶硅或第三多晶硅1300。
第一半导体薄膜21′的厚度例如为
Figure PCTCN2021105319-appb-000007
S12、参考图12D，在第一半导体薄膜21′远离衬底2的一侧形成第一绝缘薄膜24。
第一绝缘薄膜24的厚度例如为
Figure PCTCN2021105319-appb-000008
材料例如为氧化硅。
S13、参考图12B，通过同一次构图工艺图案化第一半导体薄膜21′和第一绝缘薄膜24，以形成层叠的第一半导体图案11′和刻蚀阻挡图案14。
在通过同一次构图工艺图案化第一半导体薄膜21′和第一绝缘薄膜24时，其中先通过干刻工艺刻蚀第一绝缘薄膜24，以形成刻蚀阻挡图案14，刻蚀第一绝缘薄膜24的气体例如为含氯或者含氟气体，例如CF 4(四氟甲烷)；再通过干刻工艺刻蚀第一半导体薄膜21′，以形成第一半导体图案11′，其中，刻蚀第一半导体薄膜21′的气体例如为Cl 2(氯气)。
在另一些实施例中，参考图12E，在衬底2上形成层叠的第一半导体图案11′和刻蚀阻挡图案14，具体包括：
S11′、参考图12F，在衬底2的一侧形成第一半导体薄膜21′，第一半导体薄膜21′的材料为非晶硅或第三多晶硅1300，图案化第一半导体薄膜21′以形成第一半导体图案11′。
形成的第一半导体薄膜21′的厚度例如为
Figure PCTCN2021105319-appb-000009
刻蚀第一半导体薄膜21′的气体例如为Cl 2(氯气)。
S12′、参考图12G和图12B，在形成有第一半导体图案11′的衬底2上形 成第一绝缘薄膜24，图案化第一绝缘薄膜24以形成刻蚀阻挡图案14。
形成的第一绝缘薄膜24的厚度例如为
Figure PCTCN2021105319-appb-000010
材料例如为氧化硅，刻蚀第一绝缘薄膜24的气体例如为CF 4。
当第一半导体薄膜21′的材料为非晶硅时，第一半导体图案11′的材料为非晶硅，当第一半导体薄膜21′的材料为第三多晶硅1300时，第一半导体图案11′的材料为第三多晶硅1300，即第一半导体图案11′的材料为非晶硅或者第三多晶硅1300。
S2、参考图12H～图12J，在形成有第一半导体图案11′和刻蚀阻挡图案14的衬底2上形成第二半导体薄膜22′，图案化第二半导体薄膜22′以形成第二半导体图案12′，第二半导体图案12′与第一半导体图案11′中的至少一个侧面接触。
其中，参考图12H，第二半导体薄膜22′与刻蚀阻挡图案14和第一半导体图案11′接触，第二半导体薄膜22′的材料为非晶硅，即第二半导体薄膜22′整层覆盖在衬底2上。
本领域技术人员可以理解的是，第二半导体薄膜22′是整层制作的，覆盖位于其下的膜层。例如当衬底2上存在其它膜层时，比如缓冲层时，第二半导体薄膜22′将覆盖在缓冲层上，此时，第二半导体薄膜22′并未与衬底2直接接触，其中缓冲层的材料例如为氧化硅和氮化硅中的至少一种。
参考图12I和图12J，其中图12I为俯视的薄膜晶体管1中的第一半导体图案11′和第二半导体图案12′结构图，第二半导体图案12′与第一半导体图案11′中的一个侧面接触，该侧面例如为长度方向与沟道区100的长度方向L垂直的第一侧面S1。
参考图12K和图12M，其中图12K为俯视的薄膜晶体管1中的第一半导体图案11′和第二半导体图案12′结构图，第二半导体图案12′与第一半导体图案11′中的两个侧面接触，该侧面例如为长度方向与沟道区100的长度方向L垂直的第一侧面S1和第二侧面S2。
参考图12L和图12M，其中图12L为俯视的薄膜晶体管1中的第一半导体图案11′和第二半导体图案12′结构图，第二半导体图案12′围绕第一半导体图案11′一周设置。
S3、利用第一激光31照射第一半导体图案11′和至少部分第二半导体图案12′，且至少部分第二半导体图案12′与第一半导体图案11′接触，以使被照射的至少部分第二半导体图案12′材料中的非晶硅转化为第二多晶硅1200，以使第一半导体图案11′中至少顶面D2的材料转化为第一多晶硅1100，沿沟道 区100的长度方向L，第一多晶硅1100的平均晶粒尺寸大于第二多晶硅1200和第三多晶硅1300的平均晶粒尺寸。
示例的，结合图12I、图12J和图8B，利用第一激光31照射第一半导体图案11′和全部的第二半导体图案12′，以使第一半导体图案11′转化为第一有源图案11，以使该一个第二半导体图案12′转化为一个第二有源图案12。
示例的，结合图12K、图12M和图8D，利用第一激光31照射第一半导体图案11′和全部的第二半导体图案12′，以使第一半导体图案11′转化为第一有源图案11，使该两个第二半导体图案12′转化为两个第二有源图案12。
在利用第一激光31照射第二半导体图案12′的全部以形成第二有源图案12后，则在制作第三有源图案13时，需要在制作有第二有源图案12的衬底2上再制作一层非晶硅薄膜，最后再通过构图工艺以使该非晶硅薄膜形成第三有源图案13，第三有源图案的材料为a-si。
结合图12K、图12L和图12N或者结合图12K、图12L和图12O，利用第一激光31照射第一半导体图案11′和部分第二半导体图案12′，以使第一半导体图案11′转化为第一有源图案11，使该部分被第一激光31照射到的第二半导体图案12′转化为第二有源图案12，第二有源图案12的材料为第二多晶硅1200。由于在第二半导体图案12′中未被第一激光31照射到的剩余部分的材料为非晶硅，因此第二半导体图案12′中未被激光3照射的部分可用于形成第三有源图案13，因此可以通过第二半导体图案12′同时制备出第二有源图案12和第三有源图案13，制备工艺简单。在第一激光31照射部分第二半导体图案12′时，第一激光31照射到的部分第二半导体图案12′必须同时与第一半导体图案11′是接触的，这样才能使得第一半导体图案11′转化为第一有源图案11。
在第一半导体图案11′转化为第一有源图案11，至少部分第二半导体图案12′转化为第二有源图案12的过程中，当第一半导体图案11′的材料为非晶硅时，通过第一激光31照射第一半导体图案11′和第二半导体图案12′之后，第一半导体图案11′和第二半导体图案12′中的非晶硅同时熔融；在冷却时，由于第一半导体图案11′上的刻蚀阻挡图案14的保温作用，第二半导体图案12′中熔融的非晶硅相对于第一半导体图案11′中熔融的非晶硅先结晶，从而可以在靠近第一半导体图案11′的至少一个侧面处形成结晶核，例如参考图12J，第二半导体图案12′中的非晶硅在靠近第一半导体图案11′中的第一侧面S1处形成多个结晶核。当有结晶核存在作为引导时，第一半导体图案11′中熔融的非晶硅便可以沿着其长度方向横向生长为第一多晶硅1100。
当第一半导体图案11′的材料为第三多晶硅1300时，通过第一激光31照射第一半导体图案11′和第二半导体图案12′之后，由于第三多晶硅1300对于第一激光31的吸收率低于非晶硅对第一激光31的吸收率，因此当第二半导体图案12′中的非晶硅全部熔融时，第一半导体图案11′中可能只有顶面D2上的第三多晶硅1300材料熔融；这样在冷却时，由于第一半导体图案11′上的刻蚀阻挡图案14的保温作用，第二半导体图案12′中熔融的非晶硅相对于第一半导体图案11′中熔融的第三多晶硅1300先结晶，从而可以在靠近第一半导体图案11′的至少一个侧面处形成结晶核，例如参考图12J，第二半导体图案12′中的非晶硅在靠近第一半导体图案11′中的第一侧面S1处形成多个结晶核。当有结晶核存在作为引导时，第一半导体图案11′中熔融的第三多晶硅1300便可以沿着其长度方向横向生长为第一多晶硅1100。
在上述过程中，例如通过MLA技术定点照射第一半导体图案11′和至少部分第二半导体图案12′，以使得第一半导体图案11′转化为第一有源图案11，至少部分第二半导体图案12′转化为第二有源图案12。在MLA技术中，例如可以利用能量密度为300mj/cm 2～400mj/cm 2、频率为100HZ～300HZ、Shot数为5～40的第一激光31对第一半导体图案11′和至少部分第二半导体图案12′进行照射。
需要说明的是，在ELA技术中，激光照射的是整个膜层(该膜层例如为非晶硅薄膜)，而在MLA技术中，激光照射的是膜层中的部分区域(可搭配掩膜板实现照射部分区域)，因此被称为定点照射，以区别ELA技术中的激光照射。
在一些实施例中，薄膜晶体管1的制备方法还包括：
参考图10A～图10I、在有源层10远离衬底2的一侧形成欧姆接触图案15，欧姆接触图案15与有源层10接触。
欧姆接触图案15的材料例如为N+a-si，厚度例如为
Figure PCTCN2021105319-appb-000011
形成欧姆接触图案例如可以先形成欧姆接触薄膜，图案化后欧姆接触薄膜形成欧姆接触图案15，其中刻蚀欧姆接触薄膜的气体例如为氯气。
可以直接在有源层10上沉积N+a-si材料，以形成欧姆接触薄膜；也可以先形成非晶硅薄膜，再通过向非晶硅薄膜中掺杂N+粒子以形成欧姆接触薄膜。
在一些实施例中，薄膜晶体管1的制备方法还包括：
参考图11B和图11E，在欧姆接触图案15远离衬底2的一侧形成源极111和漏极112，源极111和漏极112分别通过欧姆接触图案15与有源层10电连接。
源极111和漏极112的材料例如为Mo(钼)、Ag(银)、Al(铝)等导电金属。
在一些实施例中，在形成第一半导体薄膜21′之前，薄膜晶体管1的制备方法还包括：
参考图11A和图11B，在衬底2的一侧形成栅极金属薄膜，图案化以形成栅极16。通过该制备方法形成薄膜晶体管1为底栅型薄膜晶体管1。
在另一些实施例中，薄膜晶体管1的制备方法还包括：
参考图11C、图11D和图11E，在刻蚀阻挡图案14远离衬底2的一侧形成栅极金属薄膜，图案化以形成栅极16。通过该制备方法形成薄膜晶体管1为顶栅型薄膜晶体管1。
上述栅极金属薄膜的材料例如为Mo，厚度例如为
Figure PCTCN2021105319-appb-000012
在另一些实施例中，参考图11D，薄膜晶体管1的制备方法包括：
在栅极16远离衬底2的一侧形成层间绝缘层18，在层间绝缘层18远离衬底的一侧形成源极111和漏极112，其中，源极111通过层间绝缘层18上的过孔与第三有源图案13接触，漏极112通过层间绝缘层18上的另一个过孔与另一个第三有源图案13接触；第二有源图案12和第三有源图案13中均掺杂有N+离子，且第三有源图案13的掺杂浓度大于第二有源图案12的掺杂浓度。
在一些实施例中，在衬底2的一侧形成第一半导体薄膜21′包括：
在衬底2上形成非晶硅薄膜。
利用第二激光照射非晶硅薄膜，以使非晶硅薄膜中的非晶硅转化成第三多晶硅1300，以形成第一半导体薄膜21′，第一半导体薄膜21′的材料为第三多晶硅1300。
示例的，可通过ELA技术将整个非晶硅薄膜中的非晶硅转化成第三多晶硅1300，以形成材料为第三多晶硅1300的第一半导体薄膜21′，从而可以得到材料为第三多晶硅1300的第一半导体图案11′。ELA技术中使用的第二激光的能量密度例如为300mj/cm 2～400mj/cm 2，频率例如为100HZ～300HZ。因此，在本公开的实施例中，第一激光31的参数和第二激光32的参数并不完全相同，且第一激光31执行区域化激光退火工艺，第二激光执行准分子激光退火工艺。
在另一些实施例中，还可以直接在衬底2上沉积第三多晶硅1300，以形成第一半导体薄膜21′。示例的，通过PVD(Physical Vapor Deposition，物理气相沉积)工艺沉积形成第三多晶硅1300。
在一些实施例中，参考图2A～图2G，薄膜晶体管1的制备方法还包括：
去除刻蚀阻挡图案14。例如通过CF 4去除刻蚀阻挡图案14。
在一些实施例中，在形成第一有源图案11后，可以对第一有源图案11进行切样检测，将样品放置在1％浓度的HF(氢氟酸)溶液中浸泡20S，再将样品放置在SECOO中浸泡20S，SECOO为HF与重铬酸钾(K 2Cr 2O 7)的混合物，最后通过SEM观察第一有源图案11中第一多晶硅1100的形态。
上述薄膜晶体管1的制备方法与上述的薄膜晶体管1具有相同的有益效果，因此不再赘述。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (13)

  1. 一种薄膜晶体管，包括：
    设置于衬底上的有源层，所述有源层具有沟道区，所述有源层包括：第一有源图案和第二有源图案，所述第一有源图案的至少部分位于所述沟道区中；
    其中，所述第一有源图案包括底面、顶面和至少一个侧面，所述底面和所述顶面沿所述衬底的厚度方向相对设置，且所述底面更靠近所述衬底，所述至少一个侧面连接所述底面和所述顶面，所述至少一个侧面与所述第二有源图案接触，且所述至少一个侧面中的每个侧面的长度方向与所述沟道区的长度方向垂直或近似垂直；
    所述第一有源图案中至少所述顶面的材料包括第一多晶硅，所述第二有源图案的材料包括第二多晶硅；沿所述沟道区的长度方向，所述第一多晶硅的平均晶粒尺寸大于所述第二多晶硅的平均晶粒尺寸。
  2. 根据权利要求1所述的薄膜晶体管，还包括：
    刻蚀阻挡图案，设置于所述第一有源图案的所述顶面上；所述第一有源图案在所述衬底上的正投影在所述刻蚀阻挡图案在所述衬底上的正投影内，且所述刻蚀阻挡图案在所述衬底上的正投影与所述第二有源图案在所述衬底上的正投影不重叠。
  3. 根据权利要求1或2所述的薄膜晶体管，其中，所述至少一个侧面包括：沿所述沟道区的长度方向，相对设置的第一侧面和第二侧面；所述第二有源图案与所述第一侧面和所述第二侧面接触。
  4. 根据权利要求1～3任一项所述的薄膜晶体管，其中，所述有源层还包括：第三有源图案，所述第三有源图案的材料为非晶硅；
    沿所述沟道区的长度方向，所述第三有源图案设置于有源图案组的至少一侧；
    或者，所述第三有源图案围绕所述有源图案组一周设置；
    其中，所述有源图案组包括所述第一有源图案和所述第二有源图案。
  5. 根据权利要求2～4任一项所述的薄膜晶体管，其中，在所述薄膜晶体管包括刻蚀阻挡图案的情况下：
    所述第一有源图案在所述衬底上的正投影的边缘与所述刻蚀阻挡图案在所述衬底上的正投影的边缘重合或大致重合。
  6. 根据权利要求1～5任一项所述的薄膜晶体管，其中，所述第一有源图案的材料均为第一多晶硅或者还包括第三多晶硅，所述第三多晶硅的平均晶粒尺寸小于所述第一多晶硅的平均晶粒尺寸。
  7. 根据权利要求1～6任一项所述的薄膜晶体管，还包括：设置于所述第二有源图案远离所述衬底一侧的源极和漏极，所述源极和所述漏极分别与所述有源层电连接。
  8. 一种显示装置，包括：如权利要求1～7任一项所述的薄膜晶体管。
  9. 一种薄膜晶体管的制备方法，包括：
    在衬底上形成层叠的第一半导体图案和刻蚀阻挡图案，其中，所述第一半导体图案的至少部分用于形成沟道区，所述第一半导体图案包括底面、顶面和至少一个侧面，所述底面和所述顶面沿所述衬底的厚度方向相对设置，且所述底面更靠近所述衬底，所述至少一个侧面连接所述底面和所述顶面，所述至少一个侧面中的每个侧面的长度方向与所述沟道区的长度方向垂直或近似垂直，所述第一半导体图案在所述衬底上的正投影在所述刻蚀阻挡图案在所述衬底上的正投影内，所述第一半导体图案的材料为非晶硅或者第三多晶硅；
    在形成有第一半导体图案和刻蚀阻挡图案的衬底上形成第二半导体薄膜，所述第二半导体薄膜至少与所述刻蚀阻挡图案和第一半导体图案接触，所述第二半导体薄膜的材料为非晶硅，图案化所述第二半导体薄膜以形成第二半导体图案，所述第二半导体图案与所述第一半导体图案中的所述至少一个侧面接触；
    利用第一激光照射所述第一半导体图案和至少部分所述第二半导体图案，且所述至少部分第二半导体图案与所述第一半导体图案接触，以使被照射的所述至少部分第二半导体图案材料中的非晶硅转化为第二多晶硅，以使所述第一半导体图案中至少所述顶面的材料转化为第一多晶硅，沿所述沟道区的长度方向，所述第一多晶硅的平均晶粒尺寸大于所述第二多晶硅和所述第三多晶硅的平均晶粒尺寸。
  10. 根据权利要求9所述的薄膜晶体管的制备方法，其中，所述第二半导体图案中未被激光照射的部分形成第三有源图案。
  11. 根据权利要求9或10所述的薄膜晶体管的制备方法，其中，在所述衬底上形成层叠的所述第一半导体图案和所述刻蚀阻挡图案，包括：
    在所述衬底的一侧形成第一半导体薄膜，所述第一半导体薄膜的材料为非晶硅或第三多晶硅；
    在所述第一半导体薄膜远离所述衬底的一侧形成第一绝缘薄膜；
    通过同一次构图工艺图案化所述第一绝缘薄膜和所述第一半导体薄膜，以形成层叠的所述第一半导体图案和所述刻蚀阻挡图案；
    或者，
    在所述衬底的一侧形成第一半导体薄膜，所述第一半导体薄膜的材料为非晶硅或第三多晶硅，图案化所述第一半导体薄膜以形成所述第一半导体图案；
    在形成有所述第一半导体图案的所述衬底上形成第一绝缘薄膜，图案化所述第一绝缘薄膜以形成所述刻蚀阻挡图案。
  12. 根据权利要求11所述的薄膜晶体管的制备方法，其中，
    在所述衬底的一侧形成所述第一半导体薄膜包括：
    在所述衬底上形成非晶硅薄膜；
    利用第二激光照射所述非晶硅薄膜，以使所述非晶硅薄膜中的非晶硅转化成第三多晶硅，以形成所述第一半导体薄膜，所述第一半导体薄膜的材料为第三多晶硅。
  13. 根据权利要求9～12任一项所述的薄膜晶体管的制备方法，还包括：
    去除所述刻蚀阻挡图案。
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