WO2019049876A1 - Substrat de silicium destiné à être utilisé dans la production d'une couche mince de silicium épitaxial, et son procédé de production - Google Patents

Substrat de silicium destiné à être utilisé dans la production d'une couche mince de silicium épitaxial, et son procédé de production Download PDF

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WO2019049876A1
WO2019049876A1 PCT/JP2018/032815 JP2018032815W WO2019049876A1 WO 2019049876 A1 WO2019049876 A1 WO 2019049876A1 JP 2018032815 W JP2018032815 W JP 2018032815W WO 2019049876 A1 WO2019049876 A1 WO 2019049876A1
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silicon
layer
thin film
silicon substrate
porosity layer
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学 伊原
馨 長谷川
千明 高澤
明 松浦
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国立大学法人東京工業大学
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    • C30BSINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02Epitaxial-layer growth
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    • C30BSINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
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Definitions

  • the present invention relates to a silicon substrate for manufacturing an epitaxial silicon thin film used for a single crystal silicon solar cell or the like and a method for manufacturing the same.
  • the present invention also relates to a method of reducing defects, which reduces crystal defects in an epitaxial silicon thin film used for a single crystal silicon solar cell or the like.
  • a single crystal silicon solar cell using a high purity silicon single crystal wafer as a semiconductor substrate has been used since the oldest, and has high energy conversion efficiency, but has a drawback that the cost tends to be high.
  • a single crystal thin film silicon solar cell has been proposed in which the raw material cost and the like are reduced by thinning the silicon layer.
  • DLPS double layer porous silicon
  • HPL high porosity layer
  • LPL low porosity layer
  • the low porosity layer (LPL) acts as a seed layer for epitaxially growing a silicon thin film thereon, and the high porosity layer (HPL) is a sacrificial layer for exfoliation.
  • the underlying single crystal silicon substrate after peeling off the high porosity layer (HPL) can be reused.
  • a method of epitaxially growing a single crystal silicon thin film there are a physical vapor deposition (PVD) method, a chemical vapor deposition (CVD) method, and the like.
  • PVD physical vapor deposition
  • CVD chemical vapor deposition
  • a rapid vapor deposition (RVD; Rapid Vapor Deposition) method capable of achieving a growth rate of about 10 times or more compared to the conventional method has been reported (Non-patent Document 3).
  • the RVD method is a method of heating a silicon source to about 2000 ° C., which is much higher than the melting point of silicon, and a film forming speed of about 10 to 20 ⁇ m / min can be realized.
  • the present inventors conducted zone heating recrystallization (ZHR; Zone-Heating Recrystallization) which smoothes the low porosity layer (LPL) surface by scanning the surface of two-layer porous silicon (DLPS) with a lamp heater at high speed. )
  • ZHR zone heating recrystallization
  • LPL low porosity layer
  • DLPS two-layer porous silicon
  • the zone melting recrystallization method is also called zone melting recrystallization (ZMR; Zone-Melting Recrystallization) method, and a layer of amorphous silicon thin film sandwiched between silicon oxide layers at the top and bottom is the melting point of silicon (1414 ° C.) It is a method of improving the crystallinity of the amorphous silicon layer by heating and melting to a temperature exceeding and recrystallizing.
  • the zone heating recrystallization (ZHR) method is a method of smoothing the low porosity layer (LPL) surface by high-speed scanning and heating the surface of the two-layer porous silicon (DLPS) with a lamp heater. In the ZHR method, an apparatus similar to the apparatus used in the ZMR method can be used.
  • JP 2001-274084 A Japanese Patent Application Publication No. 2003-160396
  • the present invention has been made in view of the above background art, and the problem is that the quality is higher in the manufacture of an epitaxial silicon thin film used for a single crystal silicon solar cell or the like using two-layer porous silicon (DLPS). It is an object of the present invention to provide an epitaxial silicon thin film and to provide a highly efficient single crystal silicon solar cell etc. at low cost.
  • DLPS two-layer porous silicon
  • the inventor of the present invention has found that the low surface roughness of the low porosity layer (LPL) of the two-layer porous silicon (DLPS) is reduced to reduce the surface roughness. It has been found that crystal defects in a silicon thin film formed by epitaxial growth using a porosity layer (LPL) as a seed layer can be reduced.
  • LPL low porosity layer
  • the present invention is a silicon substrate having a two-layer porous silicon layer composed of a low porosity layer and a high porosity layer for producing an epitaxial silicon thin film
  • the present invention provides a silicon substrate characterized in that the surface roughness (R ms ) represented by the following formula (1) of the low porosity layer is 0.3 nm or less.
  • Equation (1) l is the reference length, and Z (x) is the height difference from the reference line at position x.
  • the present invention is also a method for producing a silicon substrate having a two-layer porous silicon layer comprising a low porosity layer and a high porosity layer, for producing an epitaxial silicon thin film,
  • the surface roughness (R ms ) represented by the following formula (1) of the low porosity layer is 0.3 nm by subjecting the surface of the low porosity layer to heat treatment by zone heating recrystallization. It is an object of the present invention to provide a method of manufacturing a silicon substrate which is characterized by reducing the temperature to the following.
  • Equation (1) l is the reference length, and Z (x) is the height difference from the reference line at position x.
  • the present invention is also a method of reducing defects, which reduces crystal defects in an epitaxial silicon thin film, Forming a two-layer porous silicon layer comprising a low porosity layer and a high porosity layer on the single crystal silicon substrate by an anodic oxidation method (A); Heat treating the surface of the low porosity layer by zone heating recrystallization (B); Forming an epitaxial silicon thin film on the surface of the low porosity layer (C); To provide a method for reducing defects.
  • A anodic oxidation method
  • B Heat treating the surface of the low porosity layer by zone heating recrystallization
  • C Forming an epitaxial silicon thin film on the surface of the low porosity layer
  • a higher quality epitaxial silicon thin film can be provided in the manufacture of an epitaxial silicon thin film used for a single crystal silicon solar cell or the like using two-layer porous silicon (DLPS).
  • the silicon substrate of the present invention can be used not only as a solar cell but also as a substrate for low-cost and high-performance electronic devices such as Si power devices that require high-quality silicon thin films.
  • the thin film The surface of the low porosity layer (LPL) to be the seed layer for growth does not have "surface roughness that causes defects in the epitaxial silicon thin film", so low defects in the epitaxial silicon thin film formed on it are realized Be done.
  • the film formation of the epitaxial silicon thin film on the seed layer (LPL) is carried out by the RVD method, a high quality (low defect) thin film can be formed.
  • the RVD method has high productivity because high-speed film formation of about 10 to 20 ⁇ m / min is possible.
  • high-speed film formation by the RVD method or the like can be achieved by treating the surface of the DLPS which is the base of the epitaxial silicon thin film to a specific surface roughness (R ms ).
  • R ms surface roughness
  • the silicon substrate after peeling off the high porosity layer (HPL) of the two-layer porous silicon (DLPS) can be reused
  • the silicon substrate (wafer after repeated use) ) Is sufficiently usable as a silicon source of the RVD method even if it can not be reused for DLPS formation due to physical change. For this reason, in the present invention, if an epitaxial silicon thin film is formed by the RVD method, an expensive silicon wafer can be used without waste.
  • ZHR zone heating recrystallization
  • (A) out of plane (b) in plane Is a graph showing the relationship between the surface roughness of the low porosity layer (LPL) and (R ms) and crystal defects of the epitaxial silicon thin film.
  • Zone Heating recrystallization (ZHR) method by heat treatment conditions and the surface roughness is a graph showing the relationship between (R ms).
  • the present invention relates to a silicon substrate for manufacturing an epitaxial silicon thin film, a method of manufacturing the silicon substrate, and a method of reducing defects that reduce crystal defects in the epitaxial silicon thin film.
  • the silicon substrate of the present invention is used for applications such as single crystal silicon solar cells and silicon power devices.
  • FIG. 1 A schematic view of an example of a manufacturing process of a single crystal epitaxial silicon thin film utilizing the present invention is shown in FIG.
  • DLPS two-layer porous silicon
  • LPL low porosity layer
  • HPL high porosity layer
  • the surface of the low porosity layer (LPL) is heat-treated by the zone heating recrystallization (ZHR) method (step (B)).
  • the heat treatment by the ZHR method reduces the crystal defects in the single crystal epitaxial silicon thin film grown on the surface of the LPL by performing the step (C) described later. That is, a high quality silicon thin film used for a single crystal silicon solar cell etc. can be formed.
  • step (C) After heat treatment by ZHR method, after cleaning with hydrofluoric acid (HF) or the like, LPL is used as a seed layer, and an epitaxial silicon thin film is formed on the surface of LPL (step (C)).
  • step (C) may be performed by any method, it is particularly preferable to be performed by a rapid vapor deposition (RVD) method.
  • RVD rapid vapor deposition
  • the epitaxial silicon thin film is peeled off from the single crystal silicon substrate (wafer) using HPL as a sacrificial layer (step (D)).
  • the exfoliated epitaxial silicon thin film can be used for single crystal silicon solar cells and the like.
  • the wafer after peeling can be collected and reused.
  • epitaxial silicon thin film When an epitaxial silicon thin film is manufactured using the silicon substrate of the present invention, a porous structure derived from the LPL portion of DLPS remains as a base in the manufactured epitaxial silicon thin film.
  • Epitaxial silicon thin films manufactured using the silicon substrate of the present invention can be easily distinguished from silicon thin films manufactured by other methods.
  • the present invention is a defect reduction method for reducing crystal defects in an epitaxial silicon thin film.
  • the present invention by reducing the surface roughness of the LPL by the heat treatment in the step (B), crystal defects in the epitaxial silicon thin film formed in the step (C) can be significantly reduced.
  • the silicon substrate of the present invention is a substrate for producing an epitaxial silicon thin film.
  • the silicon substrate of the present invention has a layer of two-layer porous silicon (DLPS) consisting of a low porosity layer (LPL) and a high porosity layer (HPL).
  • FIG. 2 shows an example of a FE-SEM (field emission scanning electron microscope) image of the silicon substrate of the present invention.
  • the layer of DLPS is formed on a single crystal silicon substrate (wafer) by a known method (for example, the two-step anodic oxidation method described in Non-Patent Document 1 and Non-Patent Document 2).
  • the surface roughness (R ms ) represented by the following formula (1) of the low porosity layer (LPL) is 0.3 nm or less.
  • Equation (1) l is the reference length, and Z (x) is the height difference from the reference line at position x.
  • surface roughness refers to the surface roughness represented by the above-mentioned formula (1).
  • the surface roughness (R ms ) of the low porosity layer (LPL) is preferably 0.28 nm or less, more preferably 0.26 nm or less, still more preferably 0.24 nm or less, and 0 It is particularly preferable that the wavelength is 0.22 nm or less.
  • the low porosity layer (LPL) is a seed layer for forming an epitaxial silicon thin film thereon.
  • the average thickness of LPL is preferably 0.5 ⁇ m or more, and particularly preferably 0.8 ⁇ m or more. Moreover, it is preferable that it is 5 micrometers or less, and it is especially preferable that it is 3 micrometers or less. When the average thickness is in the above range, an epitaxial silicon thin film with few defects can be stably formed on LPL. Further, LPL can be used as an antireflective film for a silicon thin film for a solar cell, but when the average thickness is in the above range, the antireflective performance tends to be sufficient.
  • the average pore diameter of the pores in LPL is preferably 15 nm or more, and particularly preferably 20 nm or more.
  • the thickness is preferably 40 nm or less, and particularly preferably 35 nm or less. 20% or more is preferable and, as for the porosity of LPL, 30% or more is especially preferable. Moreover, 50% or less is preferable and 45% or less is especially preferable.
  • the average pore diameter and the porosity are in the above ranges, it is easy to stably form an epitaxial silicon thin film with few defects on the LPL.
  • the high porosity layer is a sacrificial layer which is exfoliated after epitaxial silicon thin film formation, it is desirable from the viewpoint of yield that the HPL is easily exfoliated.
  • the average thickness of the HPL is preferably 200 nm or more, more preferably 250 nm or more, and particularly preferably 300 nm or more.
  • the thickness is preferably 600 nm or less, more preferably 550 nm or less, and particularly preferably 500 nm or less.
  • the average thickness is at least the above lower limit, mechanical peeling easily occurs, and the yield is improved.
  • the ease of peeling does not improve so much, so the thickness of the HPL is sufficient at the above upper limit or less from the viewpoint of cost of anodic oxidation and the like.
  • the average pore diameter of the pores in the HPL is preferably 15 nm or more, and particularly preferably 20 nm or more.
  • the thickness is preferably 40 nm or less, and particularly preferably 35 nm or less. 50% or more is preferable and, as for the porosity of HPL, 60% or more is especially preferable. Further, 90% or less is preferable, and 80% or less is particularly preferable. When the average pore diameter and the porosity are in the above ranges, it is easy to peel off and easily manufactured in cost.
  • the two-layer porous silicon (DLPS) layer of the silicon substrate of the present invention may be entirely composed of silicon, or only the high porosity layer (HPL) may be composed of silicon oxide.
  • HPL high porosity layer
  • the HPL is a sacrificial layer for peeling, and can be mechanically peeled off with a scotch (registered trademark) tape or the like as in the examples described later.
  • a scotch registered trademark
  • the silicon substrate of the present invention is preferably one in which the surface of the low porosity layer (LPL) is heat-treated by the zone heating recrystallization (ZHR) method.
  • ZHR zone heating recrystallization
  • the heat treatment by the ZHR method is shown in FIG.
  • a sample (a silicon substrate having a DLPS layer) is set in the apparatus so that the LPL side is up, and while the sample is preheated by a bottom heater (BH), gas flows
  • BH bottom heater
  • UH upper lamp heater
  • the surface roughness of the LPL tends to be larger as the HPL is thicker. If the HPL is thinly formed, the surface roughness of the LPL will be reduced, but if so, peeling using the HPL as a sacrificial layer becomes difficult.
  • the LPL surface is selectively heat treated by the upper lamp heater to smooth the LPL surface. For this reason, by using the ZHR method, it is easy to smooth the LPL surface and to reduce the defect of the epitaxial thin film while maintaining the ease (yield) of the HPL peeling.
  • the percentage of the value obtained by dividing R ms by R ms ' is 80% or less It is preferably 70% or less, more preferably 60% or less.
  • the surface roughness of LPL after heat treatment is smaller, defects in the epitaxial silicon thin film deposited on LPL are reduced and a good thin film is obtained, but usually when formed by anodic oxidation
  • the fact that the surface roughness of LPL of (ie, the surface roughness of LPL before heat treatment by the ZHR method) is small means that the HPL is thin (that is, it is difficult to peel off). Therefore, as the “value obtained by dividing R ms by R ms ′” is smaller, it is possible to achieve both the quality of the epitaxial silicon thin film and the ease of separation (yield).
  • the sample is preheated by the lower heater (BH), but when the amount of heating by the lower heater (BH) is large, the surface roughness of LPL may decrease, but the structural change of DLPS The effect is also on HPL and exfoliation may be difficult. For this reason, it is necessary to prevent excessive heating by the lower heater (BH).
  • the lower heater heating amount represented by the following formula (2) (H B) is preferably at 0KJm -2 or more, and more preferably 10KJm -2 or more. Further, it is preferably 300KJm -2 or less, and more preferably 200KJm -2 or less.
  • the upper lamp heater is a line heater using, for example, a tungsten wire or the like.
  • the output of the upper lamp heater (ULH) is preferably 0.1 kW or more, and more preferably 0.5 kW or more. Moreover, it is preferable that it is 20 kW or less, and it is more preferable that it is 10 kW or less.
  • the scanning speed of the upper lamp heater (ULH) is preferably 0.1 mm / s or more, and more preferably 0.5 mm / s or more. Moreover, it is preferable that it is 100 mm / s or less, and it is more preferable that it is 50 mm / s or less.
  • the mechanism by which the surface roughness of LPL is reduced by heat treatment by ZHR method is not necessarily clear, but (a) smoothing by surface energy, (b) surface oxidation, (c) structural change including inside It is guessed that it progresses with three factors,. That is, by performing the heat treatment by the ZHR method, the LPL surface is reconstructed and smoothed so that the surface energy is reduced, but when the amount of heating is large, hydrogen atoms on the LPL surface may be released (note that The hydrogen atoms on the LPL surface are derived from hydrofluoric acid (HF) used for cleaning to dissolve excess SiO 2 after formation of the DLPS layer by anodic oxidation). The surface oxidation due to the elimination of hydrogen atoms may interfere with the surface smoothing. In addition, when the heating amount is large, structural change may extend to the inside of the DLPS layer, which may also affect the LPL surface.
  • HF hydrofluoric acid
  • the heat treatment by the ZHR method prevents oxidation of the surface of the low porosity layer (LPL), and is performed in a hydrogen partial pressure controlled gas atmosphere such that the surface of the low porosity layer (LPL) is not hydrogen terminated. Is preferred.
  • the gas atmosphere does not contain oxygen
  • the base gas is preferably an inert gas such as nitrogen, argon or helium.
  • inert gases are contaminated with a slight amount of oxygen of the order of ppm or less as an impurity. This slightly mixed oxygen may affect the surface of LPL, but if the concentration of hydrogen gas is above the above lower limit, oxygen is removed as water by the reaction of hydrogen gas and oxygen as an impurity. Can.
  • the hydrogen gas concentration is below the upper limit, it is below the explosion limit, so no special device is required, and the cost can be suppressed.
  • a silicon thin film is epitaxially grown thereon using LPL as a seed layer.
  • the deposition rate of the epitaxial silicon thin film is preferably 3 ⁇ m / min or more, more preferably 5 ⁇ m / min or more, and particularly preferably 10 ⁇ m / min or more from the viewpoint of productivity, cost and the like.
  • 20 ⁇ m / min or less is preferable.
  • the deposition rate is at least the above lower limit, but if the surface of the low porosity layer (LPL) in the silicon substrate of the present invention is used as a seed layer, the deposition rate is above Even if it is above the lower limit, low defects are realized, and the features of the present invention can be utilized.
  • LPL low porosity layer
  • the epitaxial silicon thin film formed by LPL is formed by rapid vapor deposition (RVD) method Is preferred.
  • RVD rapid vapor deposition
  • the film forming speed is large, and it is easy to form silicon at a high speed as described above.
  • the present invention by processing the underlying LPL surface by the ZHR method or the like, an epitaxial silicon thin film with low defects can be obtained even when the film is formed at a high speed using the RVD method or the like. , Both productivity and quality can be achieved.
  • the silicon substrate of the present invention is particularly well matched to the RVD method which enables film formation at high speed.
  • silicon is vaporized by heating a silicon source to a temperature much higher than the melting point of silicon, and silicon is deposited on a substrate placed in a reactor.
  • silicon can be epitaxially grown at a film forming speed of about 10 to 20 ⁇ m / min, which is much faster than the CVD method using gas (such as dichlorosilane) as a silicon source, which leads to cost reduction.
  • gas such as dichlorosilane
  • the effect of the smoothness of the seed layer on the quality (the amount of defects) of the epitaxial silicon thin film to be formed tends to be large.
  • the effect of reducing the surface roughness of the LPL is likely to be large.
  • the silicon source in the film formation by the RVD method, it is preferable to heat the silicon source so as to have a temperature of 1800 ° C. or more and 2200 ° C. or less and the temperature of the substrate 900 ° C. or more and 1200 ° C. or less.
  • the pressure in the reactor it is preferable that the pressure in the reactor be reduced to 5 ⁇ 10 ⁇ 4 Pa or less.
  • the deposition time is preferably 0.1 seconds to 10 seconds.
  • a silicon thin film of about 5 to 20 ⁇ m can be epitaxially grown on a silicon substrate of the present invention.
  • the epitaxial silicon thin film formed into a film by the RVD method etc. can be used for manufacture of a single crystal silicon solar cell etc.
  • the energy conversion efficiency of the single crystal silicon solar cell depends on the quality of the epitaxial silicon thin film.
  • the epitaxial silicon thin film with few crystal defects provides a highly efficient single crystal silicon solar cell.
  • LPL low porosity layer
  • the crystal defects of the epitaxial silicon thin film can be evaluated, for example, by electron spin resonance (ESR) as in the examples described later.
  • ESR electron spin resonance
  • the epitaxial silicon thin film formed on the substrate of the present invention is easily peeled off by ultrasonic treatment or roll to roll method, and is obtained as a self-supporting 40 ⁇ m thick single crystal silicon. If the raw material is p-type, p-type silicon can be obtained, and then a solar cell can be obtained by pn junction formation, electrode deposition, and the like in the same manner as in a conventional single crystal silicon solar cell manufacturing process.
  • Example 1 ⁇ Formation of Two-Layer Porous Silicon (DLPS) Layer> Two-step anodic oxidation was applied to a p-type single crystal Si (100) wafer (1 to 4 m ⁇ ⁇ cm) using a galvanostat apparatus (YR 6163, Advantest) with a platinum mesh as a cathode. A 1: 1 mixed solution of 48% by mass hydrofluoric acid (Wako Pure Chemical Industries, Ltd.) and 95% ethanol (Kanto Chemical Co., Ltd.) was used as the electrolytic solution. After forming LPL at 2 mA / cm 2 for 415 s, HPL was formed at 200 mA / cm 2 for 5 s to fabricate a silicon substrate having DLPS.
  • DLPS Two-step anodic oxidation was applied to a p-type single crystal Si (100) wafer (1 to 4 m ⁇ ⁇ cm) using a galvanostat apparatus (YR 6163, Advantest) with a platinum mesh
  • the thickness of LPL was about 1 ⁇ m, and the thickness of HPL was about 400 nm.
  • the thickness of this HPL is thicker than the value (about 300 nm) previously reported by the present inventors in Non-Patent Document 4 (that is, it is easy to peel but the surface roughness tends to be large).
  • the LPL surface was scanned by the upper lamp heater (ULH) using a tungsten wire.
  • the output of the lower heater (BH) was adjusted within the range of 0 to 17.9 kW, and the lower heater heating amount (H B ) was calculated by the equation (2).
  • the output of the upper lamp heater (ULH) was 2.9 kW, and the scanning speed (v scan ) was adjusted in the range of 1 to 26 mm / s.
  • FE-SEM field emission scanning electron microscope
  • R ms surface roughness
  • AFM Bruker MultiMode N3-IHA SPA System
  • the pressure in the reactor provided with the silicon substrate having DLPS was reduced to a pressure lower than 4.0 ⁇ Torr (5.3 ⁇ 10 ⁇ 4 Pa), and then the temperature of the silicon substrate having DLPS was raised to 1100 ° C.
  • the vaporized silicon was deposited on the LPL of the silicon substrate having the DLPS. It was possible to deposit a silicon thin film of about 9 ⁇ m with a deposition time of 1 minute.
  • the silicon thin film obtained on the silicon substrate having DLPS was peeled off with a Scotch (registered trademark) tape, with a portion of HPL as a sacrificial layer.
  • the crystal orientation of the surface and the cross section of the silicon thin film was observed by an FE-SEM or an X-Ray Diffraction (XRD) apparatus (PANalytical X'Pert-Pro-MRDBruker MultiMode N3-IHA SPA System).
  • the surface of the silicon thin film was observed by electron spin resonance (ESR) to evaluate crystal defects on the surface.
  • ESR electron spin resonance
  • Comparative Example 1 After forming a two-layer porous silicon (DLPS) layer on a p-type single crystal Si (100) wafer and washing with hydrofluoric acid, a silicon thin film was formed by RVD without heat treatment by ZHR. In the same manner as in Example 1, a silicon thin film was produced and peeled off from the substrate.
  • DLPS porous silicon
  • FIG. 5 An example of the XRD spectrum of the silicon thin film formed on LPL by the RVD method is shown in FIG. Since a peak is shown only at (400) as shown in FIG. 5 (a) and a four-fold symmetry is shown for (220) as shown in FIG. 5 (b), epitaxial growth is extremely fast It can be seen that the single crystal silicon thin film was successfully produced. Under the experimental conditions not shown in FIG. 5, a spectrum substantially similar to that of FIG. 5 was obtained, and a single crystal silicon thin film was obtained.
  • FIG. 6 shows the relationship between the surface roughness (R ms ) of the low porosity layer (LPL) and the crystal defects of the epitaxial silicon thin film.
  • Example 2 In the same manner as in Example 1 except that the atmosphere of the introduced gas was changed, the DLPS was subjected to a heat treatment by the ZHR method, and the surface roughness (R ms ) was measured.
  • the scanning speed (v scan ) of the upper lamp heater (ULH) was fixed at 5 mm / s, and the output of the lower heater (BH) was adjusted in the range of 0 to 17.9 kW.
  • the gas flow path of the apparatus was improved to suppress the oxygen inflow due to the back diffusion of the air.
  • the surface roughness (R ms ) of LPL behaves differently depending on the atmosphere of the introduced gas, and as the amount of hydrogen in the introduced gas increases, the minimum value of the surface roughness (R ms ) shifts to the lower heating side There was a trend towards
  • Example 3 A silicon thin film 1 having a thickness of about 48 ⁇ m was obtained by an RVD method using a silicon substrate obtained by heat-treating DLPS by ZHR method under the following conditions.
  • the silicon thin film 2 having a thickness of about 63 ⁇ m was obtained by the RVD method using the silicon substrate obtained without performing the heat treatment by the ZHR method on the DLPS under the following conditions.
  • the lifetime of the silicon thin film 2 measured in the same manner as the silicon thin film 1 was about 36 ⁇ s.
  • the thicker the film thickness is the longer the lifetime becomes longer, but the silicon thin film 1 subjected to the heat treatment by the ZHR method is thinner than the silicon thin film 2 not subjected to the heat treatment by the ZHR method.
  • the lifetime was long. This suggests that the heat treatment by the ZHR method is effective in improving the quality of the silicon thin film.
  • the process for producing an epitaxial silicon thin film using the present invention can produce a silicon thin film for a single crystal silicon solar cell with high efficiency at low cost. Therefore, the silicon substrate manufactured according to the present invention is widely used as a substrate for single-crystal silicon solar cells for general household use, factory use, etc., a substrate for electronic devices such as Si power devices, and the like.

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Abstract

La présente invention aborde le problème consistant à fournir une couche mince de silicium épitaxial de haute qualité qui présente peu de défauts dans la production d'une couche mince de silicium épitaxial à l'aide de silicium poreux bicouche (DLPS), et le problème consistant à fournir une photopile en silicium monocristallin ou similaire hautement efficace à faible coût. La solution porte sur un substrat en silicium comprenant une couche de silicium poreux bicouche (DLPS) composée d'une couche à faible porosité (LPL) et d'une couche à porosité élevée (HPL), qui est conçue de telle sorte que la couche à faible porosité (LPL) présente une rugosité de surface (Rms) inférieure ou égale à 0,3 nm représentée par la formule (1). (Dans la formule (1), l représente la longueur standard ; et Z(x) représente la différence de hauteur de la ligne de référence à la position x.)
PCT/JP2018/032815 2017-09-05 2018-09-05 Substrat de silicium destiné à être utilisé dans la production d'une couche mince de silicium épitaxial, et son procédé de production WO2019049876A1 (fr)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2617811A (en) * 2022-01-31 2023-10-25 Iqe Plc A layered structure

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000150839A (ja) * 1998-09-04 2000-05-30 Canon Inc 半導体基板の作製方法
JP2011529018A (ja) * 2008-07-23 2011-12-01 エレメント シックス リミテッド ダイヤモンド材料

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000150839A (ja) * 1998-09-04 2000-05-30 Canon Inc 半導体基板の作製方法
JP2011529018A (ja) * 2008-07-23 2011-12-01 エレメント シックス リミテッド ダイヤモンド材料

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
LUKIANOV ET AL.: "Formation of the seed layers for layer- transfer process silicon solar cells by zone-heating recrystallization of porous silicon structures", APPLIED PHYSICS LETTERS, vol. 108, 26 May 2016 (2016-05-26), pages 213904-1 - 213904-4, XP012208034, DOI: doi:10.1063/1.4951671 *
NODA, YU ET AL.: "Development of method for manufacturing single crystalline silicon thin film for solar battery", LECTURE ABSTRACTS OF THE 37TH FALL CONFERENCE RESEARCH PRESENTATION OF THE SOCIETY OF CHEMICAL ENGINEERS *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2617811A (en) * 2022-01-31 2023-10-25 Iqe Plc A layered structure

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