WO2019042002A1 - 阵列基板及显示装置 - Google Patents

阵列基板及显示装置 Download PDF

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Publication number
WO2019042002A1
WO2019042002A1 PCT/CN2018/093451 CN2018093451W WO2019042002A1 WO 2019042002 A1 WO2019042002 A1 WO 2019042002A1 CN 2018093451 W CN2018093451 W CN 2018093451W WO 2019042002 A1 WO2019042002 A1 WO 2019042002A1
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WIPO (PCT)
Prior art keywords
peripheral
trace
array substrate
coil
internal
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Ceased
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PCT/CN2018/093451
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English (en)
French (fr)
Inventor
王国华
任文明
高飞
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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Application filed by BOE Technology Group Co Ltd, Hefei Xinsheng Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to US16/474,527 priority Critical patent/US11112659B2/en
Publication of WO2019042002A1 publication Critical patent/WO2019042002A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136204—Arrangements to prevent high voltage or static electricity failures
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/911—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using passive elements as protective elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/931—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs characterised by the dispositions of the protective arrangements
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1337—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
    • G02F1/13378—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers by treatment of the surface, e.g. embossing, rubbing or light irradiation
    • G02F1/133784—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers by treatment of the surface, e.g. embossing, rubbing or light irradiation by rubbing
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
    • G02F2202/22—Antistatic materials or arrangements

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to an array substrate and a display device.
  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • Some embodiments of the present disclosure provide an array substrate including: a display area and a trace area.
  • the routing area includes a plurality of sets of signal line leads, and the same set of signal line leads extend to the same binding area located in the routing area.
  • the routing area further includes: an auxiliary routing structure disposed between adjacent sets of signal line leads.
  • the auxiliary routing structure includes a peripheral enclosed walking coil, and the peripheral enclosed walking coil is located at an outermost side of the auxiliary routing structure. The peripheral enclosed walk coil smoothly transitions through an arc at least at a corner near the display area.
  • the peripheral enclosed walk coil smoothly transitions through an arc at all of the corners.
  • the peripheral enclosed walk coil is formed by sequentially connecting at least three peripheral traces, and the peripheral closed walk coils are smoothly connected by the arc at the corners.
  • the auxiliary routing structure further includes an internal trace located within the peripheral enclosed winding coil, the peripheral enclosed winding coil being provided with at least one tip facing one side of the internal routing.
  • At least three of the peripheral traces of the peripheral enclosed coil include a first peripheral trace adjacent to a side of the display area of the array substrate. At least one of the tips is disposed on the first peripheral trace.
  • the first peripheral trace is aligned parallel to a plurality of the binding regions.
  • the at least three peripheral traces of the peripheral enclosed coil are four peripheral traces.
  • the four peripheral traces include a second peripheral trace disposed in parallel with the first peripheral trace, and a third peripheral trace on both sides of the first peripheral trace and the second peripheral trace And the fourth peripheral route.
  • the third peripheral trace is disposed in parallel with one of a set of signal line leads closest to the auxiliary trace structure, and the fourth peripheral trace is closest to the auxiliary among the other set of signal line leads
  • a signal line lead of the trace structure is arranged in parallel, and the two sets of signal line leads are adjacent.
  • the internal trace includes at least one first internal trace; each of the first internal traces includes: a second internal sub-line directly connected to the peripheral enclosed turn coil, and The first internal sub-line is disconnected by the second internal sub-line.
  • the first internal sub-line is disposed in parallel with the first peripheral trace, and the first internal sub-line is disposed at least opposite to a portion of the first peripheral trace in which the tip is disposed;
  • the first inner sub-line and the second inner sub-line are connected at a disconnection through a conductive connection, and the conductive connection has a resistivity greater than a resistivity of the first inner trace.
  • the first internal sub-line in the first internal trace is disposed adjacent to the first peripheral trace.
  • both ends of the first internal sub-wiring are connected to the second internal sub-route through the conductive connection.
  • the electrically conductive connection is comprised primarily of a transparent electrically conductive material.
  • the first peripheral trace is provided with a plurality of tips.
  • the peripheral enclosed coil is provided with a bent structure that constitutes the tip.
  • the peripheral enclosed coil is provided with a raised structure that constitutes the tip.
  • Some embodiments of the present disclosure provide a display device including the array substrate.
  • FIG. 1 is a schematic structural view of an array substrate provided in the related art
  • FIG. 2 is a partial structural schematic view of the array substrate of FIG. 1;
  • 3a is a schematic structural diagram of an array substrate according to some embodiments of the present disclosure.
  • 3b is a schematic structural diagram of another array substrate according to some embodiments of the present disclosure.
  • Figure 4a is a partial structural view of Figure 3a
  • Figure 4b is a partial structural view of Figure 3b;
  • FIG. 5 is a partial schematic structural diagram of an array substrate according to some embodiments of the present disclosure.
  • FIG. 6 is a partial schematic structural diagram of another array substrate according to some embodiments of the present disclosure.
  • FIG. 7 is a partial schematic structural diagram of another array substrate according to some embodiments of the present disclosure.
  • FIG. 8 is a partial schematic structural diagram of another array substrate according to some embodiments of the present disclosure.
  • FIG. 9 is a partial schematic structural diagram of another array substrate according to some embodiments of the present disclosure.
  • the liquid crystal display device is divided into a wiring area 01 and a display area 02, and the display area 02 includes an alignment film that aligns liquid crystal molecules in the liquid crystal layer.
  • a plurality of binding areas (Bongding Area) connected to the fan-shaped structure F are provided in the wiring area 01.
  • the alignment film is generally produced by a rubbing alignment process, that is, by rolling a rubbing roller, an alignment groove is formed on the alignment film.
  • the auxiliary routing structure 10 is generally disposed in an area between adjacent sector-shaped wiring structures F to prevent the friction roller from rolling from the display area 02 to the routing area 01 due to the adjacent sector-shaped wiring structure.
  • Rub Mura is caused by the excessive gap between the area between F and the surrounding area.
  • the alignment film since the alignment film has a high impedance, it can be regarded as an insulating plastic, and therefore, the electric charge generated by the friction easily accumulates on the surface of the rubbing roller 03.
  • the rubbing roller 03 rolls from the display area 02 in the direction T to the routing area 01, the electric charge of the surface of the rubbing roller 03 is transferred to the auxiliary wiring structure 10, resulting in the corner of the auxiliary wiring structure 10.
  • a tip discharge is prone to occur at A.
  • a large current is generated at the moment of discharge, and the current is transmitted to the display area 02 through the traces in the sector-shaped wiring structure F (only the portion of the sector-shaped wiring structure F is shown in FIG. 2).
  • the display device may display an abnormality or a display unevenness (Mura) during normal screen display.
  • Mura display unevenness
  • the array substrate includes a display area 02 and a trace area 01; the trace area 01 includes a plurality of sets of signal line leads 200, wherein the same group The signal line lead 200 extends to the same Bonding Area located in the trace area 01.
  • a set of signal line leads 200 refers to a sector-shaped trace structure formed by at least two signal line leads 200, which is located in a fan-shaped area 20 on the array substrate. That is, the same set of signal line leads 200 extend to the same binding area. And for different sets of signal line leads 200, one of which extends to one binding zone and the other extends to another set of bonding zones.
  • the trace area 01 further includes: an auxiliary trace structure 10 disposed between adjacent sets of signal line leads 200, that is, the auxiliary trace structure 10 is located adjacent to the sector trace. Between the districts 20.
  • the auxiliary wiring structure 10 includes a peripheral enclosed coil 100, and the peripheral enclosed coil 100 is located in the auxiliary path. The outermost side of the wire structure 10, and the peripheral closed walk coil 100 smoothly transitions through an arc at least at a corner near the display area 02.
  • auxiliary trace structure 10 is disposed between any two adjacent sets of signal line leads 200.
  • An alignment film is disposed on the array substrate, and the alignment film is generally fabricated by a rubbing alignment process, resulting in accumulation of electric charge on the surface of the rubbing roller 03 during the manufacturing process.
  • the rubbing roller 03 rolls from the display area 02 in the direction T to the routing area 01 the rubbing roller 03 first comes into contact with the peripheral trace of the auxiliary wiring structure 10 near the display area 02. That is, the rubbing roller 03 first comes into contact with the outer peripheral line of the peripheral closed coil 100 which is close to the display area 02.
  • the peripheral closed-going coil 100 at least at a corner close to the display area 02, it is set to smoothly transition through an arc such that there is no tip near the corner of the display area 02.
  • the peripheral winding circuit 100 in the auxiliary wiring structure is close to the peripheral line of the display area 02, the electric charge is accumulated first, and the periphery is accumulated.
  • the corner of the enclosed coil 100 near the display area 02 does not have the condition for performing tip discharge, thereby reducing the probability that the auxiliary wiring structure 10 will have a tip discharge at the corner. That is, the probability that the auxiliary wiring structure 10 causes a tip discharge to the adjacent signal line lead 200 to cause an adverse effect on the display area is reduced.
  • the peripheral enclosed walkway 100 smoothly transitions through the arc at all of the corners. Thereby, the probability of the tip line discharge occurring at the corner of the auxiliary wiring structure 10 is further reduced.
  • the peripheral enclosed coil 100 is sequentially connected by at least three peripheral traces 101, and the peripheral enclosed coil 100 is smoothly connected by arcs at the corners.
  • the shape of the peripheral enclosed coil 100 is a triangle formed by sequentially connecting three linear outer traces 101 that are smoothly connected by arcs at the corners. In other embodiments, the shape of the peripheral enclosed coil 100 is a quadrilateral formed by sequentially connecting four linear peripheral traces 101, which are smoothly connected by arcs at the corners. In other embodiments, the shape of the peripheral enclosed coil 100 is a pentagon formed by sequentially connecting five linear outer traces 101, which are smoothly connected by arcs at the corners. In other embodiments, the shape of the peripheral enclosed coil 100 is a hexagon formed by sequentially connecting six linear outer traces 101, which are smoothly connected by arcs at the corners.
  • any two adjacent peripheral traces 101 are necessarily non-parallel, that is, adjacent two The outer trace 101 will have a corner at the joint.
  • the arc in the "smooth connection by the arc at the corner" has a slope which is continuously changed from the slope of one of the two outer traces 101 connected at the corner to the other periphery.
  • the arc is arcuate.
  • the arc is elliptical in shape.
  • the arc has other arcs. For the setting of the arc, as long as the two outer traces 101 are smoothly connected at the corners through the arc, the embodiment of the present disclosure does not limit this.
  • the auxiliary routing structure 10 further includes internal traces 110 located within the peripheral enclosed routing coil 100.
  • the peripheral enclosed coil 100 is provided with at least one tip A toward the side of the inner trace 110 so that tip discharge can be performed between the tip A and the inner trace 110.
  • At least three peripheral traces 101 of the peripheral enclosed coil 100 include a first peripheral trace 1011 adjacent to the display area 02 side of the array substrate.
  • the first outer trace 1011 is provided with at least one tip end A.
  • the rubbing roller 03 rolls from the display area 02 in the direction T to the routing area 01, the rubbing roller 03 directly contacts the first outer wiring 1011, so that the larger density of the surface of the rubbing roller 03 passes through the first
  • the tip A on the outer trace 1011 is easier to discharge the tip so that it can be effectively discharged through the tip to achieve the purpose of consuming electric charges. It is avoided that the charge accumulated on the surface of the rubbing roller 03 is uniformly dispersed on the peripheral closed coil 100, resulting in a relatively low charge density on the tip A, which is disadvantageous in that the tip discharge is consumed by the tip A to consume electric charges.
  • the first peripheral trace 1011 is parallel to the plurality of binding regions.
  • the same type of signal line leads (such as data line leads or gate line leads) in the array substrate correspond to more The arrangement direction of the binding regions, which are generally arranged along the extending direction of the gate lines or the data lines.
  • the first peripheral trace 1011 is parallel to the arrangement direction of the plurality of bonding regions, which also means that the extending direction of the first peripheral trace 1011 coincides with the extending direction of the gate line or the data line.
  • the plurality of binding regions corresponding to the data line leads are generally arranged along the extending direction of the gate lines, and the first peripheral traces 1011 are parallel to the alignment direction of the plurality of binding regions.
  • the gate lines extend.
  • the plurality of binding regions corresponding to the gate line leads are arranged in the direction in which the data lines extend, and the first peripheral traces 1011 are parallel to the alignment direction of the plurality of binding regions. Also parallel to the direction in which the data lines extend.
  • the peripheral enclosed coil 100 employs four peripheral traces in actual fabrication.
  • the four peripheral traces include a second peripheral trace 1012 disposed in parallel with the first peripheral trace 1011, and a third peripheral trace 1013 on both sides of the first peripheral trace 1011 and the second peripheral trace 1012 and The fourth peripheral trace 1014.
  • the third peripheral trace 1013 is disposed in parallel with one of the set of signal line leads closest to the auxiliary trace structure 10, and the fourth peripheral trace 1014 and the other set of signal line leads are closest to the auxiliary trace structure 10
  • One of the signal line leads 200 is arranged in parallel, and the two sets of signal line leads are adjacent.
  • the four outer traces are sequentially connected to form a peripheral trapped turn coil 100 that is approximately trapezoidal.
  • the shorter bottom edge of the approximately trapezoidal peripheral closed loop coil 100 corresponds to the first outer trace 1011, and the other longer bottom edge corresponds to the second peripheral trace 1012, and the first periphery is walked Lines 1011 are arranged in parallel.
  • the third peripheral trace 1013 and the fourth peripheral trace 1014 are closed to the two sides of the coil 100 in a peripheral shape corresponding to a trapezoid, and are respectively disposed in parallel with the adjacent signal line leads 200.
  • the auxiliary routing structure 10 will be further described below by taking the approximately trapezoidal peripheral closed winding coil 100 as an example.
  • the internal trace 110 includes at least one first internal trace 110a.
  • Each of the first internal traces 110a includes a second internal sub-wiring 112 directly connected to the peripheral enclosing coil 100, and a first internal sub-wiring 111 disconnected from the second internal sub-wiring 112. It should be understood here that both ends of the first inner sub-wiring 111 and the outer peripheral enclosing coil 100 and the second inner sub-wiring 112 are both disconnected.
  • the second internal sub-line 112 may be a single trace or a plurality of traces, which is not specifically limited herein.
  • the first internal sub-line 111 is disposed in parallel with the first peripheral trace 1011, and the first internal sub-line 111 is disposed at least opposite to the portion of the first peripheral trace 1011 where the tip A is disposed. That is, the orthographic projection of the first internal sub-line 111 on the first peripheral trace 1011 covers at least the portion of the first peripheral trace 1011 where the tip A is disposed.
  • the first inner sub-wiring 111 and the second inner sub-wiring 112 are connected at the disconnection through the conductive connection portion 120, and the resistivity of the conductive connection portion 120 is greater than the resistivity of the first inner trace 110a.
  • the conductive connecting portion 120 can be effectively ensured by using the material having a larger resistivity than the material having a smaller resistivity.
  • the large resistance is such that the current flows through the conductive connection portion 120 to generate a large amount of heat, thereby further purging the charge on the auxiliary trace structure.
  • the actual shape of the conductive connecting portion 120 needs to be determined according to the actual situation (for example, the type of the array substrate, the trace density, etc.), which is not limited herein.
  • the conductive connection 120 is primarily comprised of a transparent conductive material.
  • a transparent conductive material such as indium tin oxide (ITO).
  • ITO indium tin oxide
  • the conductive connecting portion 120 and other devices in the array substrate composed of a transparent conductive material (for example, a pixel electrode) ), through the same layer of the same material, that is, through the same production process.
  • both ends of the first inner sub-wiring 111 are disposed through the conductive connection portion 120. Connected to the second internal sub-line 112.
  • the first internal sub-line 111 is disposed adjacent to the first peripheral trace 100.
  • the first internal trace 110a is one, in order to ensure that a large current generated at the tip end of the tip A can be effectively consumed by the first internal trace 110a, it is necessary to ensure the first
  • the first internal sub-line 111 in the internal trace 110a is disposed adjacent to the first peripheral trace 100.
  • the first internal traces 110a are plural (refer to FIG. 7)
  • at least one of the first internal traces 110a is disposed adjacent to the first peripheral traces 100.
  • the first internal traces 110a may exist, but the routing structures other than the first internal traces 110a are avoided.
  • the tip end A provided on the first peripheral trace 1011 it is one in some embodiments, and a plurality in other embodiments.
  • a plurality of tips A are disposed on the first peripheral trace 1011 in order to enable efficient consumption of charge by tip discharge.
  • the plurality of tips A are two.
  • the peripheral enclosed coil 100 is provided with a bent structure that constitutes the tip end A. In other embodiments, as shown in FIG. 8, the peripheral enclosed coil 100 is provided with a raised structure that constitutes the tip end A.
  • the signal line leads 200 are connected to the signal lines 300 in the display area 02 of the array substrate through a transparent conductive material (eg, ITO) disposed in the via holes 201.
  • a transparent conductive material eg, ITO
  • the tip discharge is prevented from occurring at the corner by smoothly connecting the peripherally enclosed coil 100 at a corner by an arc.
  • the tip discharge is prevented from occurring at the corner by smoothly connecting the peripherally enclosed coil 100 at a corner by an arc.
  • charge is transferred to the internal trace 110 by generating a tip discharge at the tip A.
  • the electric charge is further consumed. Significantly reduces the chance of adversely affecting the display area.
  • Some embodiments of the present disclosure provide a display device including the array substrate. It has the same structure and advantageous effects as the array substrate. Since the structure and beneficial effects of the array substrate have been described in detail above, details are not described herein again.
  • the display device includes one of a liquid crystal display panel and an organic light emitting diode display panel.
  • the display device is in any product or component having a display function, such as a liquid crystal display, a liquid crystal television, a digital photo frame, a cell phone, or a tablet.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

本公开的实施例提供一种阵列基板及显示装置，涉及显示技术领域，能够降低辅助走线结构在拐角处发生尖端放电的几率。该阵列基板显示区和走线区。所述走线区包括多组信号线引线，同一组信号线引线延伸至位于所述走线区的同一绑定区。该阵列基板还包括设置于相邻组信号线引线之间的辅助走线结构。辅助走线结构包括外围封闭走线圈，所述外围封闭走线圈位于所述辅助走线结构的最外侧。外围封闭走线圈至少在靠近显示区的拐角处通过弧线平滑过渡。

Description

阵列基板及显示装置
本申请要求于2017年8月31日提交的申请号为201710778808.6、申请名称为“一种阵列基板及显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，尤其涉及一种阵列基板及显示装置。
背景技术
TFT-LCD(Thin Film Transistor Liquid Crystal Display，薄膜晶体管-液晶显示器)因其具有体积小、功耗低、无辐射以及制作成本相对较低等特点，而越来越多地被应用于高性能显示领域当中。
发明内容
本公开的一些实施例提供一种阵列基板，包括：显示区和走线区。所述走线区包括多组信号线引线，同一组信号线引线延伸至位于所述走线区的同一绑定区。所述走线区还包括：设置于相邻组信号线引线之间的辅助走线结构。所述辅助走线结构包括外围封闭走线圈，所述外围封闭走线圈位于所述辅助走线结构的最外侧。所述外围封闭走线圈至少在靠近显示区的拐角处通过弧线平滑过渡。
在一些实施例中，所述外围封闭走线圈在所有所述拐角处通过弧线平滑过渡。
在一些实施例中，所述外围封闭走线圈由至少三条外围走线顺次连接而成，且所述外围封闭走线圈在所述拐角处通过弧线平滑连接。
在一些实施例中，所述辅助走线结构还包括位于所述外围封闭走线圈内的内部走线，所述外围封闭走线圈上设置有至少一个朝向所述内部走线一侧的尖端。
在一些实施例中，所述外围封闭走线圈的至少三条外围走线中包括靠近所述阵列基板的显示区一侧的第一外围走线。所述第一外围走线上设置有至少一个所述尖端。
在一些实施例中，所述第一外围走线与多个所述绑定区排列方向 平行。
在一些实施例中，所述外围封闭走线圈的至少三条外围走线为四条外围走线。所述四条外围走线中包括与所述第一外围走线平行设置的第二外围走线，以及位于所述第一外围走线和所述第二外围走线两侧的第三外围走线和第四外围走线。所述第三外围走线与一组信号线引线中最靠近所述辅助走线结构的一个信号线引线平行设置，所述第四外围走线与另一组信号线引线中最靠近所述辅助走线结构的一个信号线引线平行设置，该两组信号线引线相邻。
在一些实施例中，所述内部走线包括至少一条第一内部走线；每条所述第一内部走线包括：与所述外围封闭走线圈直接连接的第二内部子走线，以及与所述第二内部子走线断开的第一内部子走线。所述第一内部子走线与所述第一外围走线平行设置，且所述第一内部子走线至少与所述第一外围走线中设置所述尖端的部分正对设置；所述第一内部子走线与所述第二内部子走线在断开处通过导电连接部连接，所述导电连接部的电阻率大于所述第一内部走线的电阻率。
在一些实施例中，所述第一内部走线中的所述第一内部子走线与所述第一外围走线相邻设置。
在一些实施例中，所述第一内部子走线的两端均通过所述导电连接部与所述第二内部子走线连接。
在一些实施例中，所述导电连接部主要由透明导电材料构成。
在一些实施例中，所述第一外围走线上设置有多个尖端。
在一些实施例中，所述外围封闭走线圈上设置有弯折结构，所述弯折结构构成所述尖端。
在另一些实施例中，所述外围封闭走线圈上设置有凸起结构，所述凸起结构构成所述尖端。
本公开的一些实施例提供一种显示装置，包括所述阵列基板。
附图说明
为了更清楚地说明本公开实施例或相关技术中的技术方案，下面将对实施例或相关技术描述中所需要使用的附图作简单地介绍。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附 图。
图1为相关技术中提供的一种阵列基板的结构示意图；
图2为图1中的阵列基板的局部结构示意图；
图3a为本公开的一些实施例提供的一种阵列基板的结构示意图；
图3b为本公开的一些实施例提供的另一种阵列基板的结构示意图；
图4a为图3a的局部结构示意图；
图4b为图3b的局部结构示意图；
图5为本公开的一些实施例提供的一种阵列基板的局部结构示意图；
图6为本公开的一些实施例提供的另一种阵列基板的局部结构示意图；
图7为本公开的一些实施例提供的又一种阵列基板的局部结构示意图；
图8为本公开的一些实施例提供的又一种阵列基板的局部结构示意图；
图9为本公开的一些实施例提供的又一种阵列基板的局部结构示意图。
具体实施方式
下面将结合附图，对本公开的实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
如图1所示，液晶显示装置划分为走线区01和显示区02，显示区02中包括对液晶层中的液晶分子进行配向的配向膜。走线区01中设置有与扇形走线(Fanout)结构F连接的多个绑定区(Bongding Area)。配向膜一般采用摩擦配向工艺制作，即通过滚动摩擦辊，使配向膜上形成配向槽。
如图1所示，一般在相邻扇形走线结构F之间的区域设置辅助走线结构10，以避免摩擦辊在从显示区02滚动至走线区01时，因相邻 扇形走线结构F之间的区域与周围区域之间因断差过大而导致摩擦云纹现象(Rub Mura)。
然而，如图2所示，由于配向膜阻抗较高，可视为绝缘塑料，因此，摩擦产生的电荷容易积累在摩擦辊03的表面。这样一来，在摩擦辊03从显示区02沿方向T滚动至走线区01时，摩擦辊03的表面的电荷会转移至辅助走线结构10上，导致在该辅助走线结构10的拐角A处容易发生尖端放电。放电瞬间会产生较大电流，且电流会通过扇形走线结构F(图2中仅示出了扇形走线结构F的部分)中的走线传输至显示区02。进而造成显示装置在正常画面显示过程中出现显示异常或者显示不均的现象(Mura)。
本公开的一些实施例提供一种阵列基板，如图3a和图3b所示，该阵列基板包括显示区02和走线区01；走线区01包括多组信号线引线200，其中，同一组信号线引线200延伸至位于走线区01的同一绑定区(Bonding Area)。可以理解的是，一组信号线引线200是指由至少两条信号线引线200形成的一个扇形走线结构，该扇形走线结构在阵列基板上位于一个扇形走线(Fanout)区20。也就是说，同一组信号线引线200延伸至同一绑定区。而对于不同组信号线引线200，其中一组延伸至一个绑定区，另一组延伸至另一组绑定区。
如图3a和图3b所示，所述走线区01还包括：设置于相邻组信号线引线200之间的辅助走线结构10，也即辅助走线结构10位于相邻的扇形走线区20之间。如图4a(图3a中的局部放大图)和图4b(图4a中的局部放大图)所示，该辅助走线结构10包括外围封闭走线圈100，所述外围封闭走线圈100位于辅助走线结构10的最外侧，且该外围封闭走线圈100至少在靠近显示区02的拐角处通过弧线平滑过渡。
此处应当理解到，任意相邻的两组信号线引线200之间都会设置一个辅助走线结构10。
此外，对于液晶显示装置而言，参考图1和图2以及对应的文字描述。阵列基板上设置有配向膜，配向膜一般采用摩擦配向工艺制作，导致在制作过程中摩擦辊03表面会积累电荷。在摩擦辊03从显示区02沿方向T滚动至走线区01时，摩擦辊03会首先与辅助走线结构10中靠近显示区02的外围走线接触。即，摩擦辊03会首先与外围封闭 走线圈100中靠近显示区02的外围走线接触。
在本公开的一些实施例提供的阵列基板中，通过使外围封闭走线圈100至少在靠近显示区02的拐角处设置为通过弧线平滑过渡，使得靠近显示区02的拐角不存在尖端。这样一来，当摩擦辊03滚动至走线区01靠近显示区02的边缘时，由于辅助走线结构中外围封闭走线圈100靠近显示区02的外围走线上首先会积累有电荷，而外围封闭走线圈100靠近显示区02的拐角不具备进行尖端放电的条件，因而降低了辅助走线结构10在拐角处发生尖端放电的几率。也即，降低了因辅助走线结构10对临近的信号线引线200发生尖端放电进而造成对显示区域造成不良影响的几率。
在一些实施例中，如图3b和图4b所示，外围封闭走线圈100在所有所述拐角处通过弧线平滑过渡。从而进一步降低了辅助走线结构10在拐角处发生尖端放电的几率。
在一些实施例中，如图4a和图4b所示，外围封闭走线圈100由至少三条外围走线101顺次连接而成，且所述外围封闭走线圈100在拐角处通过弧线平滑连接。
在一些实例中，外围封闭走线圈100的形状为由三条直线形的外围走线101顺次连接而成的三角形，该三角形在拐角处通过弧线平滑连接。在另一些实施例中，外围封闭走线圈100的形状为由四条直线形的外围走线101顺次连接而成的四边形，该四边形在拐角处通过弧线平滑连接。在另一些实施例中，外围封闭走线圈100的形状为由五条直线形的外围走线101顺次连接而成的五边形，该五边形在拐角处通过弧线平滑连接。在另一些实施例中，外围封闭走线圈100的形状为由六条直线形的外围走线101顺次连接而成的六边形，该六边形在拐角处通过弧线平滑连接。
需要说明的是，对于由至少三条外围走线101顺次连接形成外围封闭圈100结构而言，其中任意相邻的两条外围走线101之间必然为非平行设置，也即相邻的两条外围走线101在连接处会出现拐角。
此外，所述“在拐角处通过弧线平滑连接”中的弧线，其斜率由在拐角处连接的两条外围走线101中的一条外围走线101的斜率依次连续变化至另一条外围走线101的斜率。在一些实施例中，该弧线呈 圆弧形。在另一些实施例中，该弧线呈椭圆弧形。在另一些实施例中，该弧线呈其他的弧形。对于弧线的设置，只要保证通过该弧线在拐角处将两条外围走线101平滑连接即可，本公开的实施例对此不作限定。
为了进一步避免因电荷的积累而造成的隐患，从而对阵列基板造成不良影响。在一些实施例中，如图5所示，该辅助走线结构10还包括位于外围封闭走线圈100内的内部走线110。该外围封闭走线圈100上设置有至少一个朝向内部走线110一侧的尖端A，以使得尖端A与内部走线110之间能够进行尖端放电。
当在外围封闭走线圈100上具有电荷积累时，由于在尖端A处电荷密度较大，因此，会使尖端A位置附近的电场增强，从而使得外围封闭走线圈100在尖端A与内部走线110之间产生尖端放电。这样一来，通过尖端放电，达到对外围封闭走线圈100上的电荷进行消耗的目的，进而降低了因电荷积累造成的不良影响。
由于配向膜制作过程中，摩擦辊03会首先与外围封闭走线圈100中靠近显示区02的外围走线接触因此，为了能使尖端A进行尖端放电而消耗电荷。在一些实施例中，如图6所示，该辅助走线结构10中，外围封闭走线圈100的至少三条外围走线101中包括靠近阵列基板的显示区02一侧的第一外围走线1011，该第一外围走线1011上设置有至少一个尖端A。
基于此，当摩擦辊03从显示区02沿方向T滚动至走线区01时，摩擦辊03会直接与第一外围走线1011接触，从而使得摩擦辊03表面的较大密度的电荷通过第一外围走线1011上的尖端A更容易进行尖端放电，从而能够有效的通过尖端放电以达到消耗电荷的目的。避免了因摩擦辊03表面积累的电荷均匀的分散在外围封闭走线圈100上，而导致尖端A上的聚集的电荷密度相对较低，从而不利于通过尖端A进行尖端放电而消耗电荷。
在一些实施例中，第一外围走线1011与多个绑定区排列方向平行。
需要说明的是，对于所述“多个绑定区排列方向”，本领域的技术人员应当理解到，为阵列基板中相同类型的信号线引线(例如数据线引线或者栅线引线)对应的多个绑定区的排列方向，其一般为沿栅线或者数据线的延伸方向排布。在此情况下，第一外围走线1011与多个绑定区 排列方向平行，也意味着第一外围走线1011的延伸方向与栅线或者数据线的延伸方向一致。例如，对应于数据线引线的多个绑定区而言，其排列方向一般沿栅线的延伸方向排布，此时第一外围走线1011在与多个绑定区排列方向平行的同时，也与栅线的延伸方向平行。又例如，对应于栅线引线的多个绑定区而言，其排列方向一般沿数据线的延伸方向排布，此时第一外围走线1011在与多个绑定区排列方向平行的同时，也与数据线的延伸方向平行。
在一些实施例中，如图6所示，外围封闭走线圈100在实际的制作中采用四条外围走线。该四条外围走线中包括与第一外围走线1011平行设置的第二外围走线1012，以及位于第一外围走线1011和第二外围走线1012的两侧的第三外围走线1013和第四外围走线1014。第三外围走线1013与一组信号线引线中最靠近辅助走线结构10的一个信号线引线200平行设置，第四外围走线1014与另一组信号线引线中最靠近辅助走线结构10的一个信号线引线200平行设置，该两组信号线引线相邻。
即，该四条外围走线顺次连接形成近似梯形的外围封闭走线圈100。该近似梯形的外围封闭走线圈100中较短的底边对应所述第一外围走线1011，另一个较长的底边对应的所述第二外围走线1012，与所述第一外围走线1011平行设置。第三外围走线1013和第四外围走线1014对应该近似梯形的外围封闭走线圈100中的两个侧边，且分别与紧邻的信号线引线200平行设置。以下均是以该近似梯形的外围封闭走线圈100为例对辅助走线结构10做进一步的说明。
在此基础上，为了更进一步的对辅助走线结构10上的电荷进行消耗，如图7所示，所述内部走线110包括至少一条第一内部走线110a。每条第一内部走线110a包括：与外围封闭走线圈100直接连接的第二内部子走线112，以及与第二内部子走线112断开的第一内部子走线111。此处应当理解到，第一内部子走线111的两端与外围封闭走线圈100以及第二内部子走线112均为断开状态。另外，对于第二内部子走线112而言，可以是一条走线，也可以是多条走线，在此不作具体限定。
其中，第一内部子走线111与第一外围走线1011平行设置，且第一内部子走线111至少与第一外围走线1011中设置尖端A的部分正对设 置。即，第一内部子走线111在第一外围走线1011上的正投影至少覆盖该第一外围走线1011中设置尖端A的部分。另外，第一内部子走线111与第二内部子走线112在断开处通过导电连接部120连接，且导电连接部120的电阻率大于第一内部走线110a的电阻率。
这样一来，当第一外围走线1011上的尖端A发生尖端放电，瞬间产生的大电流流经导电连接部120时，由于导电连接部120的电阻率大于第一内部走线110a的电阻率，因而会在导电连接部120上产生大量热量，使得导电连接部120被烧毁。即，在导电连接部120会发生静电击穿，使得靠近辅助走线结构10的信号线引线200不会被击穿。
需要说明的是，在导电连接部120形状大小一致的情况下，采用电阻率较大的材料相比于采用电阻率较小的材料制作导电连接部120能够有效的保证该导电连接部120具有较大的电阻，以使得上述电流流经导电连接部120产生大量热量，从而达到进一步对辅助走线结构上的电荷进行消耗的目的。当然对于实际中导电连接部120形状大小需要根据实际情况(例如阵列基板的类型、走线密度等)进行确定，在此不作限定。
在一些实施例中，导电连接部120主要由透明导电材料构成。透明导电材料，例如为氧化铟锡(ITO)。当然，考虑到阵列基板中具有其他主要由透明导电材料构成的器件，为了简化工艺，在一些实施例中，该导电连接部120与阵列基板中其他由透明导电材料构成的器件(例如，像素电极)，通过同层同材料，也即通过同一次制作工艺制作。
为了能够最大可能通过导电连接部120对辅助走线结构10上的电荷进行消耗，在一些实施例中，如图7所示，设置第一内部子走线111的两端均通过导电连接部120与第二内部子走线112连接。
为了避免电荷能有效的通过导电连接部120而进行消耗，在一些实施例中，如图7所示，第一内部子走线111与第一外围走线100相邻设置。
需要说明的是，在第一内部走线110a为一条的情况下，为了保证在尖端A发生尖端放电瞬间产生的较大电流能够有效的通过第一内部走线110a进行消耗，需要保证该第一内部走线110a中的第一内部子走线111与第一外围走线100相邻设置。在第一内部走线110a为多条的情况下(参考图7)，至少保证一条第一内部走线110a与第一外围走线100相邻设 置。当然，对于其他的第一内部走线110a与第一外围走线100之间，可以存在第一内部走线110a，但避免设置第一内部走线110a以外的走线结构。
此外，对于第一外围走线1011上设置的尖端A而言，在一些实施例中为一个，在另一些实施例中为多个。在一些实施例中，为了能够进行有效的通过尖端放电对电荷进行消耗，在第一外围走线1011上设置多个尖端A。在一些实施例中，多个尖端A为2个。
在一些实施例中，如图7所示，外围封闭走线圈100上设置有弯折结构，该弯折结构构成尖端A。在另一些实施例中，如图8所示，外围封闭走线圈100上设置有凸起结构，该凸起结构构成尖端A。
在一些实施例中，如图9所示，所述信号线引线200与阵列基板的显示区02中的信号线300通过设置于转接孔201中的透明导电材料(例如，ITO)连接。
对于该连接方式，如按图2中的辅助走线结构，则容易在外围封闭走线圈上的拐角位置发生尖端放电。而尖端放电产生的瞬间较大电流，会通过信号线引线200流经转接孔201，从而造成转接孔201位置处的透明导电材料产生大量的热量，并被烧毁，进而导致对应位置出现显示异常的现象。
相比于此，当本公开的一些实施例采用如图9所示的技术方案时，通过将外围封闭走线圈100在拐角处通过弧线平滑连接，避免在拐角处发生尖端放电。在此基础上，通过在第一外围走线1011上设置有朝向内部走线110一侧的尖端A，通过在尖端A处产生尖端放电，将电荷转移至内部走线110。同时，通过将与第一外围走线1011正对的第一内部子走线111的两端通过电阻率较大的导电连接部120与第二内部子走线112连接，进一步消耗上述电荷，从而能够显著的降低对显示区域造成不良影响的几率。
本公开的一些实施例提供一种显示装置，包括所述阵列基板。具有与所述阵列基板相同的结构和有益效果。由于前述已经对阵列基板的结构和有益效果进行了详细的描述，此处不再赘述。
需要说明的是，在本公开的一些实施例中，显示装置包括液晶显示面板和有机发光二极管显示面板中的一种。在一些实施例中，显示 装置为液晶显示器、液晶电视、数码相框、手机或平板电脑等任何具有显示功能的产品或者部件中。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (13)

  1. 一种阵列基板，包括：显示区和走线区；所述走线区包括多组信号线引线，同一组信号线引线延伸至位于所述走线区的同一绑定区；
    所述走线区还包括：设置于相邻组信号线引线之间的辅助走线结构；
    所述辅助走线结构包括外围封闭走线圈，所述外围封闭走线圈位于所述辅助走线结构的最外侧；所述外围封闭走线圈至少在靠近显示区的拐角处通过弧线平滑过渡。
  2. 根据权利要求1所述的阵列基板，其中，所述外围封闭走线圈在所有所述拐角处通过弧线平滑过渡。
  3. 根据权利要求2所述的阵列基板，其中，所述外围封闭走线圈由至少三条外围走线顺次连接而成。
  4. 根据权利要求3所述的阵列基板，其中，所述辅助走线结构还包括位于所述外围封闭走线圈内的内部走线，所述外围封闭走线圈上设置有至少一个朝向所述内部走线一侧的尖端。
  5. 根据权利要求4所述的阵列基板，其中，所述外围封闭走线圈的至少三条外围走线中包括靠近所述阵列基板的显示区一侧的第一外围走线；
    所述第一外围走线上设置有至少一个所述尖端。
  6. 根据权利要求5所述的阵列基板，其中，所述第一外围走线与多个所述绑定区排列方向平行。
  7. 根据权利要求6所述的阵列基板，其中，所述外围封闭走线圈的至少三条外围走线为四条外围走线；
    所述四条外围走线中包括与所述第一外围走线平行设置的第二外围走线，以及位于所述第一外围走线和所述第二外围走线两侧的第三外围走线和第四外围走线；所述第三外围走线与一组信号线引线中最靠近所述辅助走线结构的一个信号线引线平行设置，所述第四外围走线与另一组信号线引线中最靠近所述辅助走线结构的一个信号线引线平行设置，该两组信号线引线相邻。
  8. 根据权利要求4所述的阵列基板，其中，所述内部走线包括至少一条第一内部走线；
    每条所述第一内部走线包括：与所述外围封闭走线圈直接连接的 第二内部子走线，以及与所述第二内部子走线断开的第一内部子走线；所述第一内部子走线与所述第一外围走线平行设置，且所述第一内部子走线至少与所述第一外围走线中设置所述尖端的部分正对设置；
    所述第一内部子走线与所述第二内部子走线在断开处通过导电连接部连接，所述导电连接部的电阻率大于所述第一内部走线的电阻率。
  9. 根据权利要求8所述的阵列基板，其中，所述第一内部走线中的所述第一内部子走线与所述第一外围走线相邻设置。
  10. 根据权利要求8所述的阵列基板，其中，所述第一内部子走线的两端均通过所述导电连接部与所述第二内部子走线连接。
  11. 根据权利要求8所述的阵列基板，其中，所述导电连接部主要由透明导电材料构成。
  12. 根据权利要求4所述的阵列基板，其中，所述外围封闭走线圈上设置有弯折结构，所述弯折结构构成所述尖端；
    或者，所述外围封闭走线圈上设置有凸起结构，所述凸起结构构成所述尖端。
  13. 一种显示装置，包括权利要求1所述的阵列基板。
PCT/CN2018/093451 2017-08-31 2018-06-28 阵列基板及显示装置 Ceased WO2019042002A1 (zh)

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