WO2019037167A1 - 主动阵列开关基板及其显示面板 - Google Patents

主动阵列开关基板及其显示面板 Download PDF

Info

Publication number
WO2019037167A1
WO2019037167A1 PCT/CN2017/102011 CN2017102011W WO2019037167A1 WO 2019037167 A1 WO2019037167 A1 WO 2019037167A1 CN 2017102011 W CN2017102011 W CN 2017102011W WO 2019037167 A1 WO2019037167 A1 WO 2019037167A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
active
concentration
doped
doped layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2017/102011
Other languages
English (en)
French (fr)
Inventor
卓猷仁
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HKC Co Ltd
Chongqing HKC Optoelectronics Technology Co Ltd
Original Assignee
HKC Co Ltd
Chongqing HKC Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by HKC Co Ltd, Chongqing HKC Optoelectronics Technology Co Ltd filed Critical HKC Co Ltd
Priority to US15/578,539 priority Critical patent/US10263083B2/en
Publication of WO2019037167A1 publication Critical patent/WO2019037167A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y30/00—Nanotechnology for materials or surface science, e.g. nanocomposites
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • the present application relates to an active array switch substrate and a display panel thereof, and more particularly to an active array switch array substrate using a silicon germanium oxide nanocrystal (Si x Ge y O z ) as a filling material of an active layer.
  • Si x Ge y O z silicon germanium oxide nanocrystal
  • a TFT Thin Film Transistor
  • a TFT is a thin film transistor array substrate, which is an essential component for controlling the display of a display panel in a liquid crystal display panel.
  • a thin film transistor array substrate is provided with a source electrode and a drain electrode.
  • the intermediate layer must pass through the active layer channel formed above the active layer.
  • a driving voltage is applied to the gate electrode under the active layer, an induced electric field is generated in the active layer for controlling the turn-on or turn of the active layer channel, which is the working principle of the thin film transistor array substrate.
  • the above-mentioned thin film transistor array substrate is fabricated on a glass substrate, and such a process requires an input of a semiconductor process equipment such as physical vapor deposition (PVD) or chemical vapor deposition (CVD).
  • PVD physical vapor deposition
  • CVD chemical vapor deposition
  • the most important active layer channel above the thin film transistor array substrate is made of amorphous silicon (a-Si) or polysilicon (poly- Si) makes the electron mobility rate (Mobility) of the electron crossing channel not too small (less than 1cm 2 /Vs) or too large (up to 200cm 2 /Vs), which leads to the failure of the overall component characteristics of the thin film transistor array substrate.
  • a problem needs to be overcome technically in the process.
  • the purpose of the present application is to provide an active array switch substrate, including: a substrate; a plurality of active switches, the active switch is formed on the substrate, and each of the active switches includes: a gate electrode structure; An insulating protective layer is formed on the gate electrode structure; an active layer is formed on the insulating protective layer, wherein the active layer is filled with silicon germanium oxide, and the silicon germanium oxide nanometer
  • the crystal grain size is 1 to 20 nm; a source electrode layer is formed on one side of the active layer to form an ohmic contact with the active layer; and a drain electrode layer is formed on the active layer On the other side, forming an ohmic contact with the active layer; a first concentration doping layer formed on the active layer, between the source electrode layer and the drain electrode layer; a passivation layer overlying the active layer, the source electrode layer and the drain electrode layer; and a pixel electrode layer overlying the passivation layer and the drain electrode layer.
  • a second concentration doping layer is further formed between the first concentration doping layer and the active layer, wherein the concentration of the first concentration doping layer is greater than the second concentration doping layer concentration.
  • a further object of the present application is to provide an active array switch substrate, comprising: a substrate, a plurality of active switches, the active switch is formed on the substrate, and each of the active switches comprises: a gate electrode structure An insulating protective layer is formed on the gate electrode structure; an active layer is formed on the insulating protective layer, wherein the active layer is filled with silicon germanium oxide; a source electrode layer, Formed on one side of the active layer to form an ohmic contact with the active layer; a drain electrode layer formed on the other side of the active layer to form an ohmic contact with the active layer a multilayer doped layer formed on the active layer and between the source electrode layer and the drain electrode layer; a passivation layer covering the insulating protective layer and the source And a drain electrode layer; and a pixel electrode layer covering the passivation layer and the drain electrode layer.
  • the multi-layer doped layer comprises a first concentration doped layer and a second concentration doped layer, and adjacent doped layers have different polarities; wherein the active layer is formed on the insulating layer a protective layer, the passivation layer, and the source electrode layer and the drain electrode layer.
  • the silicon germanium oxide has a nanocrystalline particle size of 1 to 20 nanometers.
  • the multilayer doped layer is a doped layer of two or three layers.
  • the multi-layer doping layer includes a stacked first concentration doping layer, a second concentration doping layer and a first concentration doping layer, wherein a concentration of the first concentration doping layer is greater than The concentration of the second concentration doped layer.
  • the multi-layer doping layer includes a stacked second concentration doping layer, a first concentration doping layer and a second concentration doping layer, wherein the concentration of the first concentration doping layer is greater than The concentration of the second concentration doped layer.
  • the multi-layer doping layer includes a stacked first concentration doping layer and a second concentration doping layer, wherein a concentration of the first concentration doping layer is greater than a concentration of the second concentration doping layer concentration.
  • the upper surface of the left and right sides of the active layer is doped with phosphorus (P), arsenic (As), and antimony (Sb) to form a high concentration N-type semiconductor.
  • the material of the passivation layer is silicon nitride or silicon oxide.
  • Another object of the present application is to provide a display panel comprising: a color film substrate, and the active array switch substrate.
  • the active layer surface of the active array switch substrate is filled with a plurality of silicon germanium oxide nanocrystalline materials (NC-Si x Ge y O z , Nanocrystalline-Si x Ge y O z ),
  • the active layer carrier mobility can be effectively improved, and by increasing the low concentration of the second concentration doping layer, the leakage current of the active array switch substrate can be effectively reduced, the performance of the active array switch substrate device is improved, and the panel is improved. display effect.
  • FIG. 1A and FIG. 1B are schematic diagrams showing a lattice arrangement structure of silicon germanium nanocrystals on an active layer surface of an active array switch substrate of the present application.
  • FIG. 2 and FIG. 3 are schematic diagrams showing the structure of the active array switch substrate of the present application in a five-mask process.
  • FIG. 4 to FIG. 8 are schematic diagrams showing the structure of the active array switch substrate of the present application in a four-mask process.
  • the word “comprising” is to be understood to include the component, but does not exclude any other component.
  • “on” means located above or below the target component, and does not mean that it must be on the top based on the direction of gravity.
  • FIG. 1A and FIG. 1B are schematic diagrams showing the lattice arrangement structure of silicon germanium nanocrystals on the active layer surface of the active array switch substrate of the present application.
  • the active layer of the active array switch substrate is made of amorphous silicon (a-Si).
  • a-Si amorphous silicon
  • the advantage is that the crystal grains are small, but the disadvantage is that the crystal structure is unstable and the carrier mobility (Mobility) is small. In terms of mobility, the mobility is less than 1 cm 2 /Vs, and polycrystalline silicon (poly-Si) is also used as a material.
  • the present application fills the surface of the active layer with a predetermined size of silicon germanium oxide nanocrystals (NC-Si x Ge y O z ) on the surface of the active layer.
  • Silicon germanium oxide nanocrystals (NC-Si x Ge y O z ) have larger carrier mobility (about 2 to 3 cm 2 /Vs) than amorphous silicon (a-Si), and the grain size is far. It is much smaller than polycrystalline silicon (poly-Si) grains with a grain size of 1 to 20 nanometers (nm). As shown in Fig. 1A, silicon germanium oxide nanocrystals (NC-Si x Ge y O z ) are tightly packed.
  • each silicon germanium nanocrystal 112 can be regularly arranged and has a stable crystal structure, and each layer of nano-silicon clusters (Si-nanocluster) can be effectively
  • the Silica wall 114 is confined to form a nano-Si matrix 110 formed on the surface of the active layer as shown in FIG. 1B. In this way, a resistor having a small gate electrode current can be provided, thereby effectively blocking upward erbium (Ge) diffusion during heat treatment, improving active array switch substrate device performance, and performance of a display panel including the active array switch substrate.
  • FIG. 2 and FIG. 3 are schematic diagrams showing the structure of a five-mask process according to an embodiment of the active array switch substrate of the present application.
  • an active array switch substrate includes: a substrate 100, a plurality of active switches, and the active switch is formed on the substrate 100.
  • Each of the active switches includes: a gate electrode structure 1; an insulating protective layer 4 is formed on the gate electrode structure 1 to insulate the gate electrode structure 1; an active layer 11 is formed in the insulating layer On the protective layer 4, the surface of the active layer 11 is filled with a plurality of silicon germanium oxide nanocrystals (NC-Si x Ge y O z ); a source electrode layer 2 is formed on one side of the active layer 11 The active layer 11 forms an ohmic contact; a drain electrode layer 3 is formed on the other side of the active layer 11 to form an ohmic contact with the active layer 11; a first concentration doping layer 12 is formed on the active layer 11 Between the upper and the source electrode layer 2 and the drain electrode layer 3; a passivation layer 5 covering the active layer 11, the source electrode layer 2 and the drain electrode layer 3 for insulation protection; A pixel electrode layer (ITO) 6 covers the passivation layer 5 and the drain electrode layer 3 for conducting the components.
  • ITO pixel electrode layer
  • the material using the doped layer in this embodiment may include, for example, elements such as phosphorus (P), arsenic (As), antimony (Sb), and the like.
  • the upper surfaces of the left and right sides of the active layer 11 are doped to form a first doping layer 12 having a high doping concentration.
  • the first doping layer 12 is an N + -type doping layer. The doping forms an effective ohmic contact with the subsequently plated metal layer and is formed into the source electrode layer 2 and the drain electrode layer 3.
  • the intermediate layer When the current on the source electrode layer 2 on the left side is to flow to the drain electrode layer 3 on the right side, the intermediate layer must pass through the active layer channel formed above the active layer 11 (not shown).
  • the driving voltage is applied to the gate electrode layer 1 under the active layer 11, an induced electric field is generated in the active layer 11 to control the opening of the active layer channel, so that the current of the source electrode layer 2 can flow to the drain electrode layer. 3, and then flow to the ITO pixel electrode layer 6 connected to the drain electrode layer 3.
  • the liquid crystal display panel can be used to drive the liquid crystal molecules in the liquid crystal display panel to rotate.
  • the material of the passivation layer 5 may be, for example, silicon nitride or silicon oxide.
  • the active array switch substrate of the embodiment further includes a second concentration doping layer 13 formed on the first concentration doping layer 12 and the active layer 11.
  • the second concentration doped layer 13 is an N ⁇ -type doped layer
  • the concentration of the first concentration doping layer 12 is greater than the concentration of the second concentration doping layer 13
  • the second concentration doping layer 13 Forming an N ⁇ /N + structure layer with the first concentration doping layer 12 , since the second concentration doping layer 13 has the effect of reducing leakage current, the carrier migration of the active layer 11 of the active array switch substrate can be effectively improved. rate.
  • the present application provides a doped layer of a two-layer structure formed on the active layer 11 and between the source electrode layer 2 and the drain electrode layer 3, wherein the doped layer includes an N + type A concentration doped layer 12 and an N - type second concentration doped layer 13.
  • FIG. 4 to FIG. 8 are schematic diagrams showing the structure of a four-mask process according to an embodiment of the active array switch substrate of the present application.
  • the difference between this embodiment and the above embodiments is that the active array switch substrate of the embodiment is made of four photomasks.
  • an active array switch substrate includes a substrate 100 and a plurality of active switches, and the active switch is formed on the substrate 100.
  • Each of the active switches includes: a gate electrode structure 21; an insulating protective layer 24 is formed on the gate electrode structure 21 to insulate the gate electrode structure 21; an active layer 31 is formed in the insulating layer On the protective layer 24, the surface of the active layer 31 is filled with a plurality of silicon germanium oxide nanocrystals (NC-Si x Ge y O z ); a source electrode layer 22 is formed on one side of the active layer 31, The active layer 31 forms an ohmic contact; a drain electrode layer 23 is formed on the other side of the active layer 31 to form an ohmic contact with the active layer 31; and a first concentration doped layer 32 is formed on the active layer 31.
  • NC-Si x Ge y O z silicon germanium oxide nanocrystals
  • a passivation layer 25 covering the insulating protective layer 24, the source electrode layer 22 and the drain electrode layer 23 for use as an insulating protective layer;
  • a pixel electrode layer (ITO) 26 covering the passivation layer 25 and the drain electrode layer 23.
  • the active layer 31 is formed between the insulating protective layer 24, the passivation layer 25, the source electrode layer 22, and the drain electrode layer 23.
  • the upper and lower surfaces of the active layer 31 are doped with phosphorus (P), arsenic (As), and antimony (Sb) to form a high concentration doped layer, and the material of the passivation layer 25 is, for example, nitrogen. Silicon or silicon oxide.
  • the active array switch substrate of the embodiment further includes a second concentration doping layer 33 formed on the first concentration doping layer 32 and the active layer 31.
  • the second concentration doping layer 33 is an N ⁇ -type doping layer, and the concentration of the first concentration doping layer 32 is greater than the concentration of the second concentration doping layer 33 , and the second concentration doping layer 33 Forming an N ⁇ /N + structure layer with the first concentration doping layer 32, since the N ⁇ type second concentration doping layer 33 has the effect of reducing leakage current, the active layer 31 of the active array switch substrate can be effectively improved. Carrier mobility.
  • the active array switch substrate of the embodiment further includes a second concentration doping layer 33 formed on the first concentration doping layer 32 and the source electrode layer. 22, between the drain electrode layer 23, in the present embodiment, the second concentration doping layer 33 is an N - type doped layer, and the concentration of the first concentration doping layer 32 is greater than the concentration of the second concentration doping layer 33.
  • the second concentration doping layer 33 and the first concentration doping layer 32 form an N + /N - structure layer. Since the N - type second concentration doping layer 33 has the effect of reducing leakage current, the active array can be effectively improved.
  • the carrier mobility of the active layer 31 of the switch substrate is not limited to reduce leakage current.
  • the present application provides a doped layer of a two-layer structure formed on the active layer 31, and between the source electrode 22 layer and the drain electrode layer 23, wherein the doped layer includes the stacked second layer.
  • the doping layer 33 and the first concentration doping layer 32 are concentrated.
  • the active array switch substrate of the embodiment further includes a first concentration doping layer 32 formed on the second concentration doping layer 33 and the source electrode layer.
  • the first concentration doping layer 32 is an N + type doped layer, and the concentration of the first concentration doping layer 32 is greater than the concentration of the second concentration doping layer 33.
  • the first concentration doping layer 32 and the second concentration doping layer 33 form an N + /N - /N + structure layer, and the N - type second concentration doping layer 33 has an effect of reducing leakage current, which is effective
  • the carrier mobility of the active layer 31 of the active array switch substrate is increased.
  • the active array switch substrate of the embodiment further includes a second concentration doping layer 33 formed on the first concentration doping layer 32 and the source electrode layer.
  • the second concentration doping layer 33 is an N - type doped layer, and the concentration of the first concentration doping layer 32 is greater than the concentration of the second concentration doping layer 33,
  • the second concentration doping layer 33 and the first concentration doping layer 32 form an N ⁇ /N + /N ⁇ structure layer, and the N ⁇ type second concentration doping layer 33 has an effect of reducing leakage current, which is effective
  • the carrier mobility of the active layer 31 of the active array switch substrate is increased.
  • the present application provides a three-layered N-type doped layer formed on the active layer 31, and between the source electrode 22 layer and the drain electrode layer 23, wherein the doped layer includes stacked layers. a first concentration doping layer 32, a second concentration doping layer 33 and a first concentration doping layer 32, or the doped layer includes a stacked second concentration doping layer 33, a first concentration doping layer 32 and The second concentration doping layer 33 is an N - type doped layer in this embodiment, and the concentration of the first concentration doping layer 32 is greater than the concentration of the second concentration doping layer 33.
  • the present application provides a display panel including a color film substrate, and the active array switch substrate. Wherein one of the color film substrate or the active array switch substrate has a color filter layer.
  • the active layer carriers can be effectively improved.
  • the mobility, and by increasing the second concentration doping layer 13 and the second concentration doping layer 33, can effectively reduce the leakage current of the active array switch substrate, improve the performance of the active array switch substrate device, and improve the display effect of the panel.
  • the display panel may be, for example, a liquid crystal display panel, but is not limited thereto, and may also be an OLED display panel, a W-OLED display panel, a QLED display panel, a plasma display panel, and a curved display panel. Or other types of display panels.

Landscapes

  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Nanotechnology (AREA)
  • Physics & Mathematics (AREA)
  • Composite Materials (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Materials Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种主动阵列开关基板及显示面板，主动阵列开关基板包括：基板（100）和形成于基板上的多个主动开关，主动开关包括：栅极电极结构（1），形成于栅极电极结构上的绝缘保护层（4），形成于绝缘保护层上的有源层（11），形成于有源层的一侧上与有源层形成欧姆接触的源极电极层（2），形成于有源层的另一侧上与有源层形成欧姆接触的漏极电极层（3），形成于有源层上位于源极电极层与漏极电极层之间的第一浓度掺杂层（12），覆盖于有源层、源极电极层与漏极电极层上的钝化层（5），以及覆盖于钝化层与漏极电极层上的像素电极层（6）。

Description

主动阵列开关基板及其显示面板 技术领域
本申请涉及一种主动阵列开关基板及其显示面板，特别是涉及一种采用硅锗氧化物纳米晶体(SixGeyOz)作为有源层的填充材料的主动阵列开关阵列基板。
背景技术
TFT(Thin Film Transistor)为薄膜晶体管阵列基板，在液晶显示面板里用来控制显示面板的显像，是不可或缺的主要组件。
薄膜晶体管阵列基板，其配置有源极电极与漏极电极。当左侧的源极电极上的电流要流通到在右侧的漏极电极时，中间必须穿越在有源层上方所形成的有源层通道。当位于有源层下方的栅极电极施加驱动电压时，在有源层会产生一诱导电场，用来控制有源层通道的开通与否，此即为薄膜晶体管阵列基板的工作原理。
上述的薄膜晶体管阵列基板是制作在玻璃基板上，此种工艺需要有物理气相沉积(PVD)或化学气相沉积(CVD)等半导体制程设备的投入。当使用等离子体辅助化学气相沉积机台来沉积薄膜晶体管阵列基板的钝化层时，在薄膜晶体管阵列基板上方最重要的有源层通道因采用非晶硅(a-Si)或多晶硅(poly-Si)使得电子穿越信道的电子迁移速率(Mobility)不是太小(小于1cm2/V.s)就是过大(可达200cm2/V.s)，进而导致薄膜晶体管阵列基板整体的组件特性无法满足需求，此一问题有待制程技术上的克服。
发明内容
本申请的目的即在于提供一种主动阵列开关基板，包括：一基板；多个主动开关，所述主动开关形成于所述基板上，每一所述主动开关包括：一栅极电极结构；一绝缘保护层，形成于所述栅极电极结构上；一有源层，形成于所述绝缘保护层上，其中，所述有源层填充有硅锗氧化物，所述硅锗氧化物的纳米晶体颗粒大小为1～20纳米；一源极电极层，形成于所述有源层的一侧上，与所述有源层形成欧姆接触；一漏极电极层，形成于所述有源层的另一侧上，与所述有源层形成欧姆接触；一第一浓度掺杂层，形成于所述有源层上，与所述源极电极层及所述漏极电极层之间；一钝化层，覆盖于所述有源层、所述源极电极层与所述漏极电极层上；以及一像素电极层，覆盖于所述钝化层与所述漏极电极层上。
在本申请的实施例中，另包括一第二浓度掺杂层形成于所述第一浓度掺杂层与有源层之间，其中第一浓度掺杂层的浓度大于第二浓度掺杂层的浓度。
本申请的又一目的即在于提供一种主动阵列开关基板，包括：一基板，多个主动开关，所述主动开关形成于所述基板上，每一所述主动开关包括：一栅极电极结构；一绝缘保护层，形成于所述栅极电极结构上；一有源层，形成于所述绝缘保护层上，其中，所述有源层填充有硅锗氧化物；一源极电极层，形成于所述有源层的一侧上，与所述有源层形成欧姆接触；一漏极电极层，形成于所述有源层的另一侧上，与所述有源层形成欧姆接触；多层掺杂层，形成于所述有源层上，与所述源极电极层与所述漏极电极层之间；一钝化层，覆盖于所述绝缘保护层、所述源极电极层与所述漏极电极层上；以及一像素电极层，覆盖于所述钝化层与所述漏极电极层上。其中，所述多层掺杂层包括第一浓度掺杂层和第二浓度掺杂层，且相邻的掺杂层的极性为相异；其中，所述有源层形成于所述绝缘保护层、所述钝化层、所述源极电极层与所述漏极电极层之间。
在本申请的实施例中，所述硅锗氧化物的纳米晶体颗粒大小为1～20纳米。
在本申请的实施例中，所述多层掺杂层为两层或三层结构的掺杂层。
在本申请的实施例中，所述多层掺杂层包括叠置的第一浓度掺杂层，第二浓度掺杂层和第一浓度掺杂层，其中第一浓度掺杂层的浓度大于第二浓度掺杂层的浓度。
在本申请的实施例中，所述多层掺杂层包括叠置的第二浓度掺杂层，第一浓度掺杂层和第二浓度掺杂层，其中第一浓度掺杂层的浓度大于第二浓度掺杂层的浓度。
在本申请的实施例中，所述多层掺杂层包括叠置的第一浓度掺杂层和第二浓度掺杂层，其中第一浓度掺杂层的浓度大于第二浓度掺杂层的浓度。
在本申请的实施例中，所述有源层的左右两边上方表面为磷(P)、砷(As)、锑(Sb)掺杂形成高浓度的N型半导体。
在本申请的实施例中，所述钝化层的材料为氮化硅或氧化硅。
本申请的另一目的即在于提供一种显示面板，包括：一彩膜基板，以及所述的主动阵列开关基板。
在本申请的各实施例中，主动阵列开关基板的有源层表面填充有多个硅锗氧化物的纳米晶体材料(NC-SixGeyOz，Nanocrystalline-SixGeyOz)，可有效提高有源层载流子迁移率，且通过增加低浓度的第二浓度掺杂层，可有效降低主动阵列开关基板的漏电流，使得主动阵列开关基板器件的性能提升，并提升面板的显示效果。
附图说明
图1A与图1B是本申请主动阵列开关基板的有源层表面以硅锗纳米晶体的晶格排列结构示意图。
图2与图3是本申请主动阵列开关基板以五道光罩制程的结构示意图。
图4至图8是本申请主动阵列开关基板以四道光罩制程的结构示意图。
具体实施方式
以下各实施例的说明是参考附加的图式，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。
附图和说明被认为在本质上是示出性的，而不是限制性的。在图中，结构相似的单元是以相同标号表示。另外，为了理解和便于描述，附图中示出的每个组件的尺寸和厚度是任意示出的，但是本申请不限于此。
在附图中，为了清晰起见，夸大了层、膜、面板、区域等的厚度。在附图中，为了理解和便于描述，夸大了一些层和区域的厚度。可以理解的是，当例如层、膜、区域或基底的组件被称作“在”另一组件“上”时，所述组件可以直接在所述另一组件上，或者也可以存在中间组件。
另外，在说明书中，除非明确地描述为相反的，否则词语“包括”将被理解为意指包括所述组件，但是不排除任何其它组件。此外，在说明书中，“在......上”意指位于目标组件上方或者下方，而不意指必须位于基于重力方向的顶部上。
为更进一步阐述本申请为达成预定申请目的所采取的技术手段及功效，以下结合附图及较佳实施例，对依据本申请提出的一种主动阵列开关基板及其显示面板，其具体实施方式、结构、特征及其功效，详细说明如后。
请参阅图1A与图1B，图1A与图1B是本申请主动阵列开关基板的有源层表面以硅锗纳米晶体的晶格排列结构示意图。一般而言，主动阵列开关基板的有源层以非晶硅(a-Si)为材料，优点是晶粒小，但缺点是晶体结构不稳定且载流子迁移率(Mobility)很小，一般而言，其迁移率小于1cm2/V.s，也有以多晶硅(poly-Si)为材料，优点是晶体结构稳定且载流子迁移率(Mobility)较大(可如达到200cm2/V.s)，缺点是晶粒过大，因此，本申请在有源层表面采用预设大小的硅锗氧化物纳米晶体(NC-SixGeyOz)填充在有源层的表面。
硅锗氧化物纳米晶体(NC-SixGeyOz)比非晶硅(a-Si)具有较大的载流子迁移率(约为2～3cm2/V.s)，且晶粒大小远比多晶硅(poly-Si)的晶粒小很多，晶粒大小为1～20纳米(nm)，如图1A所示，硅锗氧化物纳米晶体(NC-SixGeyOz)具有紧密整齐排列的纳米硅晶体阵列(Nano-Si matrix)110，每个硅锗纳米晶体112可规则性的排列而有稳固的晶体结构，且每层纳米硅团簇(Si-nanocluster)可以有效地被二氧 化硅墙(Silica wall)114局限分开，进而形成如图1B所示的形成于有源层表面的纳米硅晶体阵列(Nano-Si matrix)110。如此，可提供栅极电极电流很小的电阻，从而在热处理期间可有效阻挡向上的锗(Ge)扩散，提升主动阵列开关基板器件性能，以及包括此主动阵列开关基板的显示面板的性能。
请参阅图2与图3，图2与图3是本申请主动阵列开关基板的一实施例，以五道光罩制程的结构示意图。如图2所示，在一实施例中，一种主动阵列开关基板，包括：一基板100，多个主动开关，所述主动开关形成于所述基板100上。其中，每一所述主动开关包括：一栅极电极结构1；一绝缘保护层4形成于栅极电极结构1上，可对栅极电极结构1作绝缘保护；一有源层11形成于绝缘保护层4上，且有源层11表面填充有多个硅锗氧化物纳米晶体(NC-SixGeyOz)；一源极电极层2形成于有源层11的一侧上，与有源层11形成欧姆接触；一漏极电极层3形成于有源层11的另一侧上，与有源层11形成欧姆接触；一第一浓度掺杂层12，形成于有源层11上、与源极电极层2及漏极电极层3之间；一钝化层5，覆盖于有源层11、源极电极层2与漏极电极层3上，用来作绝缘保护；以及一像素电极层(ITO)6，覆盖于钝化层5与漏极电极层3上，用来导通各部件。
为了使源极电极层2与漏极电极层3形成有效的欧姆接触，本实施例使用掺杂层的材料可例如包括磷(P)、砷(As)、锑(Sb)等元素，并在有源层11的左右两边上方表面进行掺杂，以形成具有高掺杂浓度的第一浓度掺杂层12，在本实施例中第一浓度掺杂层12为N+型掺杂层，通过掺杂与后续镀上的金属层形成有效的欧姆接触，并制作成源极电极层2与漏极电极层3。当左侧的源极电极层2上的电流要流通到在右侧的漏极电极层3时，中间必须穿越在有源层11上方所形成的有源层通道(图未示)，而位于有源层11下的栅极电极层1施加驱动电压时，在有源层11会产生一诱导电场来控制有源层通道的开通，让源极电极层2的电流可以流通到漏极电极层3，然后再流到与漏极电极层3连接的ITO像素电极层6，以液晶显示面板为例，可用以驱动液晶显示面板里的液晶分子转动。在本实施例中，钝化层5的材料可例如为氮化硅或氧化硅。
如图3所示，与图2实施例的差异之处在于，本实施例主动阵列开关基板，另包括一第二浓度掺杂层13形成于第一浓度掺杂层12与有源层11之间，在本实施例中第二浓度掺杂层13为N-型掺杂层，且第一浓度掺杂层12的浓度大于第二浓度掺杂层13的浓度，第二浓度掺杂层13与第一浓度掺杂层12形成一N-/N+结构层，由于第二浓度掺杂层13具有减少漏电流的效应，可有效提高主动阵列开关基板的有源层11的载流子迁移率。
前述实施例中，本申请提供了两层结构的掺杂层形成于有源层11上，与源极电极2层与漏极电极层3之间，其中，掺杂层包括N+型的第一浓度掺杂层12和N-型的第二浓度掺杂层13。
请参考图4至图8，图4至图8是本申请主动阵列开关基板的一实施例，以四道光罩制程的结构示意图。如图4所示，本实施例与上述各实施例的差异之处在于，本实施例的主动阵列开关基板是以 四道光罩制成。于本实施例中，一种主动阵列开关基板，包括：一基板100，多个主动开关，所述主动开关形成于所述基板100上。其中，每一所述主动开关包括：一栅极电极结构21；一绝缘保护层24形成于栅极电极结构21上，可对栅极电极结构21作绝缘保护；一有源层31形成于绝缘保护层24上，且有源层31表面填充有多个硅锗氧化物纳米晶体(NC-SixGeyOz)；一源极电极层22形成于有源层31的一侧上，与有源层31形成欧姆接触；一漏极电极层23形成于有源层31的另一侧上，与有源层31形成欧姆接触；一第一浓度掺杂层32，形成于有源层31上、与源极电极层22及漏极电极层23之间；一钝化层25，覆盖于绝缘保护层24、源极电极层22与漏极电极层23上，用来作绝缘保护层；以及一像素电极层(ITO)26，覆盖于钝化层25与漏极电极层23上。其中，有源层31形成于绝缘保护层24、钝化层25、源极电极层22与漏极电极层23之间。
在本实施例中，有源层31的左右两边上方表面为磷(P)、砷(As)、锑(Sb)掺杂形成高浓度的掺杂层，且钝化层25的材料例如为氮化硅或氧化硅。
如图5所示，与图4实施例的差异之处在于，本实施例主动阵列开关基板，另包括一第二浓度掺杂层33形成于第一浓度掺杂层32与有源层31之间，在本实施例中第二浓度掺杂层33为N-型掺杂层，且第一浓度掺杂层32的浓度大于第二浓度掺杂层33的浓度，第二浓度掺杂层33与第一浓度掺杂层32形成一N-/N+结构层，由于N-型的第二浓度掺杂层33具有减少漏电流的效应，可有效提高主动阵列开关基板的有源层31的载流子迁移率。
如图6所示，与图5实施例的差异之处在于，本实施例主动阵列开关基板，另包括一第二浓度掺杂层33形成于第一浓度掺杂层32上与源极电极层22、漏极电极层23之间，在本实施例中第二浓度掺杂层33为N-型掺杂层，且第一浓度掺杂层32的浓度大于第二浓度掺杂层33的浓度，第二浓度掺杂层33与第一浓度掺杂层32形成一N+/N-结构层，由于N-型的第二浓度掺杂层33具有减少漏电流的效应，可有效提高主动阵列开关基板的有源层31的载流子迁移率。
前述实施例中，本申请提供了两层结构的掺杂层形成于有源层31上，与源极电极22层与漏极电极层23之间，其中，掺杂层包括叠置的第二浓度掺杂层33和第一浓度掺杂层32。
如图7所示，与图6实施例的差异之处在于，本实施例主动阵列开关基板，另包括一第一浓度掺杂层32形成于第二浓度掺杂层33上与源极电极层22和漏极电极层23之间，在本实施例中第一浓度掺杂层32为N+型掺杂层，且第一浓度掺杂层32的浓度大于第二浓度掺杂层33的浓度，第一浓度掺杂层32与第二浓度掺杂层33形成一N+/N-/N+结构层，由于N-型的第二浓度掺杂层33具有减少漏电流的效应，可有效提高主动阵列开关基板的有源层31的载流子迁移率。
如图8所示，与图5实施例的差异之处在于，本实施例主动阵列开关基板，另包括一第二浓度掺杂层33形成于第一浓度掺杂层32上与源极电极层22和极电极层23之间，在本实施例中第二浓度掺杂 层33为N-型掺杂层，且第一浓度掺杂层32的浓度大于第二浓度掺杂层33的浓度，第二浓度掺杂层33与第第一浓度掺杂层32形成一N-/N+/N-结构层，由于N-型的第二浓度掺杂层33具有减少漏电流的效应，可有效提高主动阵列开关基板的有源层31的载流子迁移率。前述实施例中，本申请提供了三层结构的N型掺杂层形成于有源层31上，与源极电极22层与漏极电极层23之间，其中，掺杂层包括叠置的第一浓度掺杂层32，第二浓度掺杂层33和第一浓度掺杂层32，或是，掺杂层包括叠置的第二浓度掺杂层33，第一浓度掺杂层32和第二浓度掺杂层33，在本实施例中第二浓度掺杂层33为N-型掺杂层，且第一浓度掺杂层32的浓度大于第二浓度掺杂层33的浓度。请同时参考图1至图8，在一实施例中，本申请提供一种显示面板，包括一彩膜基板，还包括所述的主动阵列开关基板。其中，所述彩膜基板或所述主动阵列开关基板中之一具有一彩色滤光层。
经过上述各实施例主动阵列开关基板的有源层11及有源层31表面填充有多个硅锗氧化物纳米晶体(NC-SixGeyOz)，可有效提高有源层载流子迁移率，且通过增加第二浓度掺杂层13及第二浓度掺杂层33，可有效降低主动阵列开关基板的漏电流，使得主动阵列开关基板器件的性能提升，并提升面板的显示效果。
在某些实施例中，所述显示面板可例如为液晶显示面板，然不限于此，其亦可为OLED显示面板，W-OLED显示面板，QLED显示面板，等离子体显示面板，曲面型显示面板或其他类型显示面板。
“在本申请一实施例中”与“在各种实施例中”等用语被重复地使用。所述用语通常不是指相同的实施例；但它亦可以是指相同的实施例。“包含”、“具有”及“包括”等用词是同义词，除非其前后文意显示出其它意思。
以上所述，仅是本申请的实施例而已，并非对本申请作任何形式上的限制，虽然本申请已以具体实施例揭露如上，然而并非用以限定本申请，任何熟悉本专业的技术人员，在不脱离本申请技术方案范围内，当可利用上述揭示的技术内容作出些许更动或修饰为等同变化的等效实施例，但凡是未脱离本申请技术方案的内容，依据本申请的技术实质对以上实施例所作的任何简单修改、等同变化与修饰，均仍属本申请技术方案的范围内。

Claims (20)

  1. 一种主动阵列开关基板，包括：
    一基板；
    多个主动开关，所述主动开关形成于所述基板上，每一所述主动开关包括：
    一栅极电极结构；
    一绝缘保护层，形成于所述栅极电极结构上；
    一有源层，形成于所述绝缘保护层上，其中所述有源层填充有硅锗氧化物，所述硅锗氧化物的纳米晶体颗粒大小为1～20纳米；
    一源极电极层，形成于所述有源层的一侧上，与所述有源层形成欧姆接触；
    一漏极电极层，形成于所述有源层的另一侧上，与所述有源层形成欧姆接触；
    一第一浓度掺杂层，形成于所述有源层上，与所述源极电极层及所述漏极电极层之间；
    一钝化层，覆盖于所述有源层、所述源极电极层与所述漏极电极层上；
    以及一像素电极层，覆盖于所述钝化层与所述漏极电极层上。
  2. 如权利要求1所述的主动阵列开关基板，另包括一第二浓度掺杂层形成于所述第一浓度掺杂层与有源层之间，其中所述第一浓度掺杂层的浓度大于所述第二浓度掺杂层的浓度。
  3. 一种主动阵列开关基板，包括：
    一基板；
    多个主动开关，所述主动开关形成于所述基板上，每一所述主动开关包括：
    一栅极电极结构；
    一绝缘保护层，形成于所述栅极电极结构上；
    一有源层，形成于所述绝缘保护层上，其中，所述有源层填充有硅锗氧化物；
    一源极电极层，形成于所述有源层的一侧上，与所述有源层形成欧姆接触；
    一漏极电极层，形成于所述有源层的另一侧上，与所述有源层形成欧姆接触；
    多层掺杂层，形成于所述有源层上，与所述源极电极层与所述漏极电极层之间；
    一钝化层，覆盖于所述绝缘保护层、所述源极电极层与所述漏极电极层上；以及
    一像素电极层，覆盖于所述钝化层与所述漏极电极层上；
    其中，所述多层掺杂层包括第一浓度掺杂层和第二浓度掺杂层，且相邻的掺杂层的极性为相异；
    其中，所述有源层形成于所述绝缘保护层、所述钝化层、所述源极电极层与所述漏极电极层之间。
  4. 如权利要求3所述的主动阵列开关基板，其中，所述硅锗氧化物的纳米晶体颗粒大小为1～20纳 米。
  5. 如权利要求3所述的主动阵列开关基板，其中，所述钝化层的材料为氮化硅。
  6. 如权利要求3所述的主动阵列开关基板，其中，所述钝化层的材料为氧化硅。
  7. 如权利要求3所述的主动阵列开关基板，其中，所述多层掺杂层为两层结构的掺杂层。
  8. 如权利要求7所述的主动阵列开关基板，其中，所述多层掺杂层包括叠置的第二浓度掺杂层和第一浓度掺杂层，其中所述第一浓度掺杂层的浓度大于所述第二浓度掺杂层的浓度。
  9. 如权利要求3所述的主动阵列开关基板，其中，所述多层掺杂层为三层结构的掺杂层。
  10. 如权利要求9所述的主动阵列开关基板，其中，所述多层掺杂层包括叠置的第一浓度掺杂层，第二浓度掺杂层和第一浓度掺杂层，其中所述第一浓度掺杂层的浓度大于所述第二浓度掺杂层的浓度。
  11. 如权利要求9所述的主动阵列开关基板，其中，所述多层掺杂层包括叠置的第二浓度掺杂层，第一浓度掺杂层和第二浓度掺杂层，其中所述第一浓度掺杂层的浓度大于所述第二浓度掺杂层的浓度。
  12. 一种显示面板，包括：
    一彩膜基板；以及
    主动阵列开关基板，包括：
    一基板；
    多个主动开关，所述主动开关形成于所述基板上，每一所述主动开关包括：
    一栅极电极结构；
    一绝缘保护层，形成于所述栅极电极结构上；
    一有源层，形成于所述绝缘保护层上，其中，所述有源层填充有硅锗氧化物；
    一源极电极层，形成于所述有源层的一侧上，与所述有源层形成欧姆接触；
    一漏极电极层，形成于所述有源层的另一侧上，与所述有源层形成欧姆接触；
    多层掺杂层，形成于所述有源层上，与所述源极电极层与所述漏极电极层之间；
    一钝化层，覆盖于所述绝缘保护层、所述源极电极层与所述漏极电极层上；以及
    一像素电极层，覆盖于所述钝化层与所述漏极电极层上；
    其中，所述多层掺杂层包括第一浓度掺杂层和第二浓度掺杂层，且相邻的掺杂层的极性为相异；
    其中，所述有源层形成于所述绝缘保护层、所述钝化层、所述源极电极层与所述漏极电极层之间。
  13. 如权利要求12所述的显示面板，其中，所述硅锗氧化物的纳米晶体颗粒大小为1～20纳米。
  14. 如权利要求12所述的显示面板，其中，所述钝化层的材料为氮化硅。
  15. 如权利要求12所述的显示面板，其中，所述钝化层的材料为氧化硅。
  16. 如权利要求12所述的显示面板，其中，所述多层掺杂层为两层结构的掺杂层。
  17. 如权利要求16所述的显示面板，其中，所述多层掺杂层包括叠置的第二浓度掺杂层和第一浓度掺杂层，其中所述第一浓度掺杂层的浓度大于所述第二浓度掺杂层的浓度。
  18. 如权利要求12所述的显示面板，其中，所述多层掺杂层为三层结构的掺杂层。
  19. 如权利要求18所述的显示面板，其中，所述多层掺杂层包括叠置的第一浓度掺杂层，第二浓度掺杂层和第一浓度掺杂层，其中所述第一浓度掺杂层的浓度大于所述第二浓度掺杂层的浓度。
  20. 如权利要求18所述的显示面板，其中，所述多层掺杂层包括叠置的第二浓度掺杂层，第一浓度掺杂层和第二浓度掺杂层，其中所述第一浓度掺杂层的浓度大于所述第二浓度掺杂层的浓度。
PCT/CN2017/102011 2017-08-25 2017-09-18 主动阵列开关基板及其显示面板 Ceased WO2019037167A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US15/578,539 US10263083B2 (en) 2017-08-25 2017-09-18 Thin film transistor array substrate and display panel thereof

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201710744122.5 2017-08-25
CN201710744122.5A CN107527926B (zh) 2017-08-25 2017-08-25 主动阵列开关基板及其显示面板

Publications (1)

Publication Number Publication Date
WO2019037167A1 true WO2019037167A1 (zh) 2019-02-28

Family

ID=60682512

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/102011 Ceased WO2019037167A1 (zh) 2017-08-25 2017-09-18 主动阵列开关基板及其显示面板

Country Status (2)

Country Link
CN (1) CN107527926B (zh)
WO (1) WO2019037167A1 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108376691B (zh) * 2018-01-05 2021-01-08 惠科股份有限公司 显示面板和显示装置
CN109545690A (zh) * 2018-12-03 2019-03-29 惠科股份有限公司 薄膜晶体管结构及其制作方法、显示装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1680992A (zh) * 2004-04-06 2005-10-12 Lg.菲利浦Lcd株式会社 具有驱动电路的液晶显示器件及其制造方法
US20110133197A1 (en) * 2009-12-03 2011-06-09 Hitachi Displays, Ltd. Thin film transistor and manufacturing method thereof
CN104900654A (zh) * 2015-04-14 2015-09-09 深圳市华星光电技术有限公司 双栅极氧化物半导体tft基板的制作方法及其结构
CN105118839A (zh) * 2015-07-28 2015-12-02 京东方科技集团股份有限公司 显示面板及其制备方法和显示装置
JP2016115841A (ja) * 2014-12-16 2016-06-23 株式会社東芝 半導体装置及び表示装置

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100585111B1 (ko) * 2003-11-24 2006-06-01 삼성전자주식회사 게르마늄 채널 영역을 가지는 비평면 트랜지스터 및 그제조 방법
US8399314B2 (en) * 2010-03-25 2013-03-19 International Business Machines Corporation p-FET with a strained nanowire channel and embedded SiGe source and drain stressors
TWI470810B (zh) * 2012-09-21 2015-01-21 E Ink Holdings Inc 薄膜電晶體、陣列基板及顯示裝置
US9224734B2 (en) * 2013-09-13 2015-12-29 Taiwan Semiconductor Manufacturing Company, Ltd. CMOS devices with reduced leakage and methods of forming the same
US9484461B2 (en) * 2014-09-29 2016-11-01 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit structure with substrate isolation and un-doped channel
US9443949B1 (en) * 2015-03-27 2016-09-13 International Business Machines Corporation Techniques for multiple gate workfunctions for a nanowire CMOS technology
CN106024705B (zh) * 2016-06-01 2019-04-30 深圳市华星光电技术有限公司 Tft基板的制作方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1680992A (zh) * 2004-04-06 2005-10-12 Lg.菲利浦Lcd株式会社 具有驱动电路的液晶显示器件及其制造方法
US20110133197A1 (en) * 2009-12-03 2011-06-09 Hitachi Displays, Ltd. Thin film transistor and manufacturing method thereof
JP2016115841A (ja) * 2014-12-16 2016-06-23 株式会社東芝 半導体装置及び表示装置
CN104900654A (zh) * 2015-04-14 2015-09-09 深圳市华星光电技术有限公司 双栅极氧化物半导体tft基板的制作方法及其结构
CN105118839A (zh) * 2015-07-28 2015-12-02 京东方科技集团股份有限公司 显示面板及其制备方法和显示装置

Also Published As

Publication number Publication date
CN107527926B (zh) 2020-02-07
CN107527926A (zh) 2017-12-29

Similar Documents

Publication Publication Date Title
JP5704790B2 (ja) 薄膜トランジスタ、および、表示装置
CN105390551B (zh) 薄膜晶体管及其制造方法、阵列基板、显示装置
CN103403873B (zh) 偏移电极tft结构
CN104752420B (zh) 显示设备的抗静电装置及其制造方法
CN104241392B (zh) 一种薄膜晶体管及其制备方法、显示基板和显示设备
CN105161503B (zh) 非晶硅半导体tft背板结构
CN104362084B (zh) 低温多晶硅薄膜及其制备方法、低温多晶硅薄膜晶体管
WO2017092173A1 (zh) Tft背板结构及其制作方法
JP2011091110A (ja) 酸化物半導体素子を用いた回路及びその製造方法、並びに表示装置
US9070775B2 (en) Thin film transistor
WO2010032425A1 (ja) 半導体素子
CN107331669A (zh) Tft驱动背板的制作方法
WO2015043220A1 (zh) 薄膜晶体管及其制备方法、阵列基板和显示装置
CN106486495A (zh) 薄膜晶体管基板、显示器及其制造方法
WO2016098651A1 (ja) 半導体装置、その製造方法、および半導体装置を備えた表示装置
US20180197973A1 (en) Manufacturing method of top gate thin-film transistor
CN105895638A (zh) 一种tft阵列基板及其制作方法、液晶显示装置
WO2018152875A1 (zh) 薄膜晶体管的制作方法、薄膜晶体管及显示器
TWI424531B (zh) 半導體裝置及其製造方法
CN108376691B (zh) 显示面板和显示装置
CN105870201A (zh) Tft器件结构及其制作方法
WO2020118988A1 (zh) 显示面板及其制作方法
WO2019037167A1 (zh) 主动阵列开关基板及其显示面板
US10263083B2 (en) Thin film transistor array substrate and display panel thereof
CN107768384A (zh) 薄膜晶体管阵列面板

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17922833

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 17922833

Country of ref document: EP

Kind code of ref document: A1