WO2019028913A1 - 一种印制电路板和终端 - Google Patents

一种印制电路板和终端 Download PDF

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Publication number
WO2019028913A1
WO2019028913A1 PCT/CN2017/097269 CN2017097269W WO2019028913A1 WO 2019028913 A1 WO2019028913 A1 WO 2019028913A1 CN 2017097269 W CN2017097269 W CN 2017097269W WO 2019028913 A1 WO2019028913 A1 WO 2019028913A1
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WO
WIPO (PCT)
Prior art keywords
pad
circuit board
pads
pin
printed circuit
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Application number
PCT/CN2017/097269
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English (en)
French (fr)
Inventor
刘立平
谷日辉
庞佳
Original Assignee
华为技术有限公司
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Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to CN201780084357.4A priority Critical patent/CN110199578A/zh
Priority to US16/637,180 priority patent/US20210352803A1/en
Priority to PCT/CN2017/097269 priority patent/WO2019028913A1/zh
Priority to EP17921017.4A priority patent/EP3651556A4/en
Publication of WO2019028913A1 publication Critical patent/WO2019028913A1/zh

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
    • H05K1/116—Lands, clearance holes or other lay-out details concerning the surrounding of a via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3447—Lead-in-hole components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457—Solder materials or compositions; Methods of application thereof
    • H05K3/3468—Applying molten solder
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/0939—Curved pads, e.g. semi-circular or elliptical pads or lands
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/094—Array of pads or lands differing from one another, e.g. in size, pitch, thickness; Using different connections on the pads
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/09409—Multiple rows of pads, lands, terminals or dummy patterns; Multiple rows of mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/09418—Special orientation of pads, lands or terminals of component, e.g. radial or polygonal orientation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/09463—Partial lands, i.e. lands or conductive rings not completely surrounding the hole
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/0949—Pad close to a hole, not surrounding the hole
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09609—Via grid, i.e. two-dimensional array of vias or holes in a single plane
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09618—Via fence, i.e. one-dimensional array of vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09781—Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04—Soldering or other types of metallurgic bonding
    • H05K2203/044—Solder dip coating, i.e. coating printed conductors, e.g. pads by dipping in molten solder or by wave soldering
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04—Soldering or other types of metallurgic bonding
    • H05K2203/046—Means for drawing solder, e.g. for removing excess solder from pads

Definitions

  • the present application relates to the field of terminal technologies, and in particular, to a printed circuit board and a terminal.
  • Wave soldering technology refers to spraying molten solder into the solder peaks required by the design, and passing the pre-mounted printed circuit board through the solder peak to realize the component leads and printed circuit boards. The technique of soldering between the pads.
  • the printed circuit board includes a circuit board main body 01 and a pin pad row 02 disposed on the back surface of the circuit board main body 01.
  • the pin pad row 02 includes A plurality of pin pads 021 arranged in a straight line, as shown in FIG. 2, when soldering soldering soldering technology to solder a plurality of component leads 03 to the plurality of pin pads 021, respectively
  • the solder wave is formed into a solder peak 04 required by the design, and the board main body 01 is moved upward and upward (that is, the N direction shown in FIG. 2) at an inclination angle of 6 to 8 degrees along the extending direction of the pin pad row 02.
  • Solder wave peak 04 such that the plurality of pin pads 021 in the pin pad row 02 sequentially enter the solder peak 04, and the latter pin pad 021 will give the solder on the previous pin pad 021 a moving direction
  • the opposite force is to prevent the solder from accumulating on the previous one of the pin pads 021. If the last one of the plurality of pin pads 021 is defined, the pin pad 021 of the solder peak 04 is the end pin pad a, Then the end pin pad a does not have this force, therefore, the solder is easily at this end pin pad a Stacking occurs, so that solder joints are easily formed between the end pin pads a and the adjacent pin pads in the same row, and between the adjacent rows of pin pads (as shown in FIGS. 3 and 4). ), resulting in a short circuit.
  • the tin pad 05 is usually disposed on the circuit board and the pin pad row 02 is along the tail of the wave soldering board direction N, and the tin pad 05 is passed.
  • the solder on the end pin pad a has a force opposite to the wave soldering direction N to prevent the solder from accumulating on the end pin pad a, thereby reducing the end pin pad a and the same row.
  • the possibility of solder sticking between adjacent pin pads and between adjacent rows of pin pads prevents short circuiting of the printed circuit board.
  • the shape of the stud bump 05 is rectangular, and the outline of the side edge of the stud bump 05 near the end pin pad a is a straight line, and the lead is soldered.
  • the shape of the disk 021 is a circular shape. Therefore, if the direction perpendicular to the arrangement direction of the plurality of lead pads 021 and parallel to the back surface of the board main body is defined as the width direction M, two of the scratch pads 05 are along the width direction M.
  • the gap width between the end and end pin pads a is a first width b 1
  • the gap width between the middle portion of the stealth pad 05 along the width direction M and the end pin pad a is a second width b 2
  • the first width b 1 is greater than the second width b 2 , so that at the time of wave soldering, the force of the stray solder pad 05 applied to the end pin pad a along both ends of the width direction M is weak, and the The solder on the end pin pad a is effectively attracted to the scratch pad 05, resulting in more solder remaining on the end pin pad a, so the end pin pad a is adjacent to the same row. Solder adhesion still occurs between the pads and between the adjacent pads, and the printed circuit board is short-circuited. Sex remains high.
  • Embodiments of the present application provide a printed circuit board and a terminal capable of reducing end pin pads adjacent to the same row The possibility of solder adhesion between the pin pads and between the adjacent rows of the pad pads prevents short circuits on the printed circuit board.
  • the present application provides a printed circuit board including a circuit board body and a pad row disposed on a back surface of the circuit board body, the pad row including a scratch pad and a plurality of pin pads a plurality of the pin pads and the tin-plating pads are sequentially spaced apart along a first direction, the shape of the pin pads is circular, and the soldering pad is adjacent to the plurality of the lead pads.
  • the outline of one side edge of the disk is an arc that is recessed into the scratch pad.
  • the pin pads closest to the scratch pads in the plurality of pin pads are the end pin pads, and the definition is perpendicular to the first direction.
  • the direction parallel to the back surface of the board main body is the second direction.
  • the pad row since the pad row is disposed on the back surface of the circuit board body, the pad row includes a plurality of pin pads and a tin pad which are sequentially spaced apart in the first direction, and thus During wave soldering, the back side of the main body of the circuit board may be turned downward, and the main body of the drawing board is moved upward at an oblique angle of 6-8° in the opposite direction of the first direction and passes through the solder peak to make a plurality of pin pads, The stray tin pad passes through the solder wave crest, so that the scratch pad can attract the solder on the end pin pad to the scratch pad to prevent the solder from accumulating on the end pin pad.
  • the outline of one edge of the stray pad near the plurality of pin pads is a circle recessed into the scratch pad.
  • the two ends of the tin pad along the second direction and the end pin pad are stolen.
  • the gap between the two is small.
  • the force of the tip of the stud soldering pad applied to the end pin pad in the second direction is large, and the solder on the end pin pad can be effectively pulled to steal.
  • the solder pad which reduces the possibility of solder sticking between the end pin pad and the adjacent pin pad in the same row, and the pin pad of the adjacent row, avoiding the printed circuit board A short circuit is generated.
  • the center of the arc coincides with the center of the end pin pad, so that the gap width between each position of the scratch pad along the second direction and the end pin pad is equal, stealing The tin pad uniformly attracts the solder on the end pin pad, further reducing the need between the end pin pad and the adjacent row of the pad pad, and between the adjacent row of pin pads The possibility of solder sticking.
  • a minimum gap width between the scratch pad and the end pin pad is a first gap width
  • a minimum gap width between two adjacent pin pads is a second gap. Width, the first gap width is equal to the second gap width, such that the minimum gap width between the stud bump and the end pin pad is moderate, and the solder on the end pin pad can be attracted to Stealing the solder pad can prevent the solder from sticking due to the gap between the scratch pad and the end pin pad being too small.
  • a maximum width of the stray solder pad in the first direction is 2 to 4 times a maximum width of the pin pad in the first direction, so that the tin pad is in the The width in the first direction is moderate, which can effectively attract the solder on the end pin pad to the scratch pad, and can avoid the excessive width of the scratch pad in the first direction and increase the stealing tin.
  • the pad rows are arranged in a plurality of rows, and the plurality of rows of the pad rows are arranged side by side in the second direction, so that the tin-pads in the plurality of rows of pad rows respectively attract the rows of the plurality of rows of pads Solder on the end pin pads prevents solder sticking between the end pin pads in the adjacent two rows of pad rows.
  • the plurality of rows of the pad pads in the pad row are misaligned along the second direction, thus ensuring Under the premise that the minimum gap width between the lead pads in the adjacent two rows of pad rows is constant, the distance between the adjacent two rows of pad rows is facilitated, so as to reduce the number of rows of pads in the circuit.
  • the footprint on the back side of the board body which in turn reduces the size of the printed circuit board.
  • the rows of the tin-plated pads in the plurality of rows of pads are sequentially connected in the second direction and form an integrated stealing pad, so that the number of pads on the printed circuit board is small, and the structure is Simple and easy to make, and there is no gap between two adjacent tin-pads, which can more effectively attract the solder on the adjacent two end-on-pin pads to the scratch pad to avoid adjacent two Solder adhesion occurs between the end pin pads.
  • the start edge of the pin pad in the first row of the pad row is a first edge
  • the last row of the pin in the pad row The end edge of the pad is a second edge
  • the gap width between the first edge and the second edge is a third gap width
  • the width of the integrated tin-plated pad in the second direction is The width of the third gap is equal, so that the width of the integrated tin-plated pad in the second direction is moderate, and the width of the integrated tin-pad can be prevented from being too large in the second direction to make the tin-pad
  • the occupied space is too large, and at the same time, it can effectively attract the solder on the end pin pads in the rows of pad rows, so as to effectively avoid solder sticking between the plurality of end pin pads and cause short circuit.
  • the rows of the tin-plating pads in the plurality of rows of the pad rows are flush with the side edges of the pin pads, so that the rows of the rows of the plurality of rows of pads are flush along the trailing edge of the first direction. It facilitates the layout of the rows of pads on the back side of the board body.
  • the present application provides a terminal, including a printed circuit board, which is a printed circuit board according to any of the above technical solutions.
  • the terminal provided by the embodiment of the present application since the terminal includes a printed circuit board, and the printed circuit board is the printed circuit board according to any of the above technical solutions, the two can solve the same technical problem and achieve the same expected result.
  • FIG. 1 is a schematic structural view of a printed circuit board in the prior art
  • FIG. 2 is a schematic structural view of the printed circuit board shown in FIG. 1 during wave soldering;
  • FIG. 3 is a schematic structural view of the printed circuit board shown in FIG. 1 after wave soldering;
  • FIG. 4 is another schematic structural view of the printed circuit board shown in FIG. 1 after wave soldering;
  • FIG. 6 is a schematic diagram of a first structure of a printed circuit board according to an embodiment of the present application.
  • FIG. 7 is a second schematic structural diagram of a printed circuit board according to an embodiment of the present application.
  • FIG. 8 is a schematic diagram of a third structure of a printed circuit board according to an embodiment of the present application.
  • FIG. 9 is a schematic diagram of a fourth structure of a printed circuit board according to an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of a fifth type of printed circuit board according to an embodiment of the present application.
  • FIG. 11 is a schematic structural diagram of a sixth type of printed circuit board according to an embodiment of the present application.
  • FIG. 12 is a schematic structural diagram of a seventh structure of a printed circuit board according to an embodiment of the present application.
  • the printed circuit board provided in this embodiment includes a circuit board main body 1 and a pad row 2 disposed on the back surface of the circuit board main body 1.
  • the pad 2 comprises a row of pads steal tin pads 4 and the plurality of pins 3, the plurality of pin pads 3, the stealing tin pads 4 along the first direction K 1 are sequentially spaced apart, the
  • the shape of the lead pad 3 is circular, and the outline of the side edge 5 of the tin-plating pad 4 adjacent to the plurality of the lead pads 3 is a circle recessed into the scratch-pad 4. arc.
  • the pin pads closest to the stray pad 4 in the plurality of pin pads 3 are defined as the end pin pad A, and are defined and first.
  • the direction in which the direction K 1 is perpendicular and parallel to the back surface of the board main body 1 is the second direction K 2 .
  • a printed circuit board provided in the present application embodiment since the upper side of the board main body 1 is provided with two rows of pads, pad 2 comprises a row of pads K 1 a plurality of pins 3 are sequentially spaced along a first direction, steal tin pad 4, and therefore the flow soldering, the circuit board can body 1 downward back surface, and pulling the circuit board main body 1 in the reverse direction K 1 in a first direction at an inclination angle of 6 ⁇ 8 ° and is moved upward by soldering
  • the peaks are such that the plurality of pin pads 3 and the stray solder pads 4 pass through the solder peaks in sequence, so that the solder pad 4 can attract the solder on the end lead pads A to the scratch pad 4 Avoid solder build-up on this end pin pad A.
  • the tin pad 4 is in the second direction K
  • the two ends of the 2 are applied to the end pin pad A with a large force, and the solder on the end pin pad A can be effectively attracted to the stray pad 4, thereby reducing the end pin pad A and The possibility of solder sticking between the adjacent pin pads in the same row and the pin pads in the adjacent row prevents short circuit of the printed circuit board.
  • the steal tin pads 4 K h maximum width in the second direction on the pin pads 21 may be less than the maximum width h 3 K 2 in the second direction 2, pin pads may be equal to 3 K 2 h in the maximum width in the second direction 2, can also be greater than the maximum width of the pin pads 3 K 2 h 2 in the second direction, which is not particularly limited.
  • the first direction K 1 and the second direction K 2 may be any direction parallel to the back surface of the circuit board main body 1 , and is not specifically limited herein, as long as the first direction K 1 and the second direction K 2 are perpendicular to each other. .
  • the number of the lead pads 3 included in the pad row 2 may be two, three, four, etc., and is not specifically limited herein.
  • center of the arc may be located on the side of the end pin pad A near the stealing pad 4, or on the side of the end pin pad A away from the stray pad 4, and also with the end pin.
  • the centers of the pads A overlap, and are not specifically limited herein.
  • the center of the arc coincides with the center of the end pin pad A, so that the stray pad 4 is located between the respective positions of the second direction K 2 and the end pin pad A.
  • the gap widths are equal, and the scratch pad 4 can uniformly attract the solder on the end pin pad A, thereby further reducing the end pin pad A and the adjacent row of the pad pad, and the phase There is a possibility of solder sticking between the lead pads of the adjacent rows.
  • the minimum gap width between the scratch pad 4 and the end pin pad A is defined as the first gap width d 1
  • the minimum gap width is the second gap width d 2
  • the first gap width d 1 may be greater than the second gap width d 2 , or may be smaller than the second gap width d 2 , and may also be equal to the second gap width d 2 .
  • the first gap width d 1 is equal to the second gap width d 2 , so that the minimum gap width between the scratch pad 4 and the end pin pad A is moderate, and the end pin pad A can be
  • the solder on the solder is effectively attracted to the scratch pad 4, and the solder paste is prevented from being too small due to the gap width between the scratch pad 4 and the end pin pad A, thereby reducing the end pin pad A.
  • the possibility of a short circuit is possible.
  • the pad 4 K steal tin on the maximum width w of 11 3 K can be on the maximum width w 1 in a first direction a pin pads 2 times in a first direction, 1.5 times, 2 times, 3 times, etc., and are not specifically limited herein.
  • the maximum width w 1 of the tin-plating pad 4 in the first direction K 1 is 2 to 4 times the maximum width w 2 of the pin pad 3 in the first direction K 1 , so that the stealing The width w 1 of the tin pad 4 in the first direction K 1 is moderate, and the solder on the end pin pad A can be effectively attracted to the scratch pad 4, and the scratch pad 4 can be prevented from being first.
  • the maximum width in the direction K 1 is too large to increase the footprint of the scratch pad 4 and the volume of the printed circuit board.
  • the number of the pad rows 2 may be one row or multiple rows, which is not specifically limited herein. And when the number of the pad rows 2 is a plurality of rows, the plurality of rows of pad rows 2 may be arranged along the first direction K 1 (as shown in FIG. 10 ) or may be arranged along the second direction K 2 (as shown in FIG. 8 or FIG. 9)), there is no specific limit here. Wherein, when the number of the pad rows 2 is a plurality of rows, specifically, the number of the pad rows 2 may be two rows as shown in FIG. 8, FIG. 9, FIG. 10, FIG. 11 and FIG. 12, or three rows. Or four rows, etc., and are not specifically limited herein.
  • the pad row 2 is a plurality of rows, and the plurality of rows of the pad rows 2 are arranged side by side in the second direction K 2 , so that the rows of the rows of pads 2 are The scratched tin pads 4 respectively attract the solder on the end pin pads A of the plurality of rows of pad rows 2, thereby avoiding solder sticking between the end pin pads A of the adjacent rows of pad rows 2.
  • the pin pads in the plurality of rows of pad rows 2 may be aligned in the second direction K 2 (as shown in FIG. 8 ) or in the second direction K 2 .
  • the misalignment arrangement (as shown in FIG. 9) is not specifically limited herein.
  • the pin pads 3 of the plurality of rows of pad rows 2 are misaligned along the second direction K 2 , so that the pin pads in the adjacent two rows of pad rows 2 are ensured.
  • the minimum gap width is constant, it is advantageous to reduce the distance between the adjacent rows 2 of the pad rows 2, so as to reduce the occupied area of the plurality of rows of pad rows 2 on the back surface of the circuit board main body 1. Reduce the size of the printed circuit board.
  • the tin-plating pads 4 in the plurality of rows of pad rows 2 may be spaced apart from each other, or may be sequentially connected in the second direction K 2 and form an integrated structure. No specific restrictions.
  • the tin-plating pads in the plurality of rows of pad rows 2 are sequentially connected in the second direction and form an integrated stealing pad 6, so that the printed circuit board
  • the number of pads on the substrate is small, the structure is simple, and the fabrication is convenient, and there is no gap between the adjacent two scratch pads, which can more effectively attract the solder on the adjacent two end pin pads to steal tin. On the pad to avoid solder sticking between adjacent two end pin pads.
  • the starting edge of the lead pad 3 in the first row of pad rows 2 is the first edge a 1
  • the last row The end edge of the lead pad 3 in the pad row 2 is the second edge a 2
  • the gap width between the first edge and the second edge is the third gap width d 3
  • the integrated stealing pad 6 is The width H of the second direction K 2 may be greater than the third gap width d 3 , and may be smaller than the third gap width d 3 , and may be equal to the third gap width d 3 , which is not specifically limited herein.
  • the width H of the integrated tin-plating pad 6 in the second direction K 2 is equal to the third gap width d 3 , such that the width H of the integrated stealing pad 6 in the second direction K 2 is moderate.
  • the width of the integrated tin-plating pad 6 in the second direction K 2 is too large, so that the occupied space of the scratch-proof pad is too large, and at the same time, the end pin welding in the plurality of rows of pad rows 2 can be effectively attracted. Solder on the disk to effectively prevent solder sticking between the multiple end pin pads and cause a short circuit.
  • the side edges of the plurality of rows of pad rows that are away from the pin pads 3 may be flush or may not be flush. , there is no specific limit here.
  • the stray tin pads in the plurality of rows of pad rows are disposed flush with one side edge of the pin pad 3, so that the plurality of rows of pad rows are along the first direction. The trailing edge is flush, which facilitates the layout of the rows of pad rows on the back side of the circuit board body 1.
  • the present application also provides a terminal comprising a printed circuit board, which is a printed circuit board as described in any of the above aspects.
  • the terminal provided by the embodiment of the present application since the terminal includes a printed circuit board, and the printed circuit board is the printed circuit board according to any of the above technical solutions, the two can solve the same technical problem and achieve the same expected result.
  • the terminal may be a mobile phone, a tablet, a watch, a camera, etc., and is not specifically limited herein.
  • Other configurations and the like of the terminal of the embodiment of the present application are well known to those skilled in the art, and will not be described in detail herein.

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Abstract

一种印制电路板和终端，涉及终端技术领域。一种印制电路板，包括电路板主体（1）和设置于电路板主体（1）背面上的焊盘排（2），焊盘排（2）包括偷锡焊盘（4）和多个引脚焊盘（3），多个引脚焊盘（3）、偷锡焊盘（4）沿第一方向（K 1）依次间隔设置，引脚焊盘（3）的形状为圆形，偷锡焊盘（4）靠近多个引脚焊盘（3）的一侧边沿（5）的轮廓线为向偷锡焊盘（4）内凹陷的圆弧。从而，在保持偷锡焊盘（4）沿第二方向（K 2）的中部与末端引脚焊盘（A）之间的间隙宽度（D 1）不变的前提下，减小了偷锡焊盘（4）沿第二方向（K 2）的两端与末端引脚焊盘（A）之间的间隙，以使偷锡焊盘（4）能够有效吸引末端引脚焊盘（A）上的焊锡，从而降低了末端引脚焊盘（A）与同排相邻的引脚焊盘（3）之间，以及与相邻排的引脚焊盘（3）之间产生焊锡粘连的可能性，避免印制电路板产生短路。

Description

一种印制电路板和终端 技术领域
本申请涉及终端技术领域，尤其涉及一种印制电路板和终端。
背景技术
波峰焊技术是指将熔化的软钎焊料喷流成设计要求的焊料波峰，并使预先装有元器件的印制电路板通过此焊料波峰，以实现元器件的引脚与印制电路板上的焊盘之间的焊接的技术。
图1所示为现有技术中的一种印制电路板，印制电路板包括电路板主体01和设置于电路板主体01背面上的引脚焊盘排02，引脚焊盘排02包括沿直线排列的多个引脚焊盘021，如图2所示，在采用波峰焊技术将多个元器件引脚03分别焊接于此多个引脚焊盘021上时，可以将熔化的焊锡喷流成设计要求的焊锡波峰04，并使电路板主体01沿引脚焊盘排02的延伸方向以6～8°的倾斜角度向上(也即是图2所示的N方向)移动并通过焊锡波峰04，这样，引脚焊盘排02中的多个引脚焊盘021依次进入焊锡波峰04，后一个引脚焊盘021会给前一个引脚焊盘021上的焊锡一个与移动方向相反的作用力，以防止焊锡在此前一个引脚焊盘021上产生堆积，若定义多个引脚焊盘021中最后一个进入焊锡波峰04的引脚焊盘021为末端引脚焊盘a，则末端引脚焊盘a不存此作用力，因此，焊锡容易在此末端引脚焊盘a上产生堆积，这样，末端引脚焊盘a与同排相邻的引脚焊盘之间，以及与相邻排的引脚焊盘之间容易产生焊锡粘连(如图3和图4所示)，从而导致了短路。
为了避免此问题，现有技术中，如图5所示，通常在电路板上、引脚焊盘排02沿波峰焊过板方向N的尾部设置偷锡焊盘05，通过偷锡焊盘05给末端引脚焊盘a上的焊锡一个与波峰焊过板方向N相反的作用力，以避免焊锡在此末端引脚焊盘a上产生堆积，从而降低了末端引脚焊盘a与同排相邻的引脚焊盘之间，以及与相邻排的引脚焊盘之间产生焊锡粘连的可能性，进而避免了印制电路板产生短路。
但是，在图5所示的印制电路板中，偷锡焊盘05的形状为矩形，偷锡焊盘05靠近末端引脚焊盘a的一侧边沿的轮廓线为直线，而引脚焊盘021的形状为圆形，因此若定义与多个引脚焊盘021的排列方向垂直并与电路板主体的背面平行的方向为宽度方向M，偷锡焊盘05沿此宽度方向M的两端与末端引脚焊盘a之间的间隙宽度为第一宽度b1，偷锡焊盘05沿此宽度方向M的中部与末端引脚焊盘a之间的间隙宽度为第二宽度b2，则第一宽度b1大于第二宽度b2，因此在波峰焊时，偷锡焊盘05沿此宽度方向M的两端施加于末端引脚焊盘a上的作用力较弱，不能将末端引脚焊盘a上的焊锡有效吸引至偷锡焊盘05上，导致末端引脚焊盘a上仍然残留有较多的焊锡，因此末端引脚焊盘a与同排相邻的引脚焊盘之间，以及与相邻排的引脚焊盘之间仍然会产生焊锡粘连，印制电路板产生短路的可能性仍然较高。
发明内容
本申请的实施例提供一种印制电路板和终端，能够降低末端引脚焊盘与同排相邻 的引脚焊盘之间，以及与相邻排的引脚焊盘之间出现焊锡粘连的可能性，避免印制电路板产生短路。
为达到上述目的，本申请的实施例采用如下技术方案：
第一方面，本申请提供一种印制电路板，包括电路板主体和设置于所述电路板主体背面上的焊盘排，所述焊盘排包括偷锡焊盘和多个引脚焊盘，多个所述引脚焊盘、所述偷锡焊盘沿第一方向依次间隔设置，所述引脚焊盘的形状为圆形，所述偷锡焊盘靠近多个所述引脚焊盘的一侧边沿的轮廓线为向所述偷锡焊盘内凹陷的圆弧。
其中，需要说明的是，为了便于下文的分析和描述，定义多个引脚焊盘中与偷锡焊盘距离最近的引脚焊盘为末端引脚焊盘，同时定义与第一方向垂直并与电路板主体的背面平行的方向为第二方向。
本申请实施例提供的印制电路板，由于电路板主体的背面上设有焊盘排，焊盘排包括沿第一方向依次间隔设置的多个引脚焊盘、偷锡焊盘，因此在波峰焊时，可使电路板主体的背面朝下，并牵引电路板主体沿第一方向的反方向以6～8°的倾斜角度向上移动并通过焊锡波峰，以使多个引脚焊盘、偷锡焊盘先后通过焊锡波峰，这样，偷锡焊盘可将末端引脚焊盘上的焊锡吸引至偷锡焊盘上，以避免焊锡在此末端引脚焊盘上产生堆积。与现有技术相比，在引脚焊盘的形状为圆形的前提下，由于偷锡焊盘靠近多个引脚焊盘的一侧边沿的轮廓线为向偷锡焊盘内凹陷的圆弧，因此在保持偷锡焊盘沿第二方向的中部与末端引脚焊盘之间的间隙宽度不变的前提下，偷锡焊盘沿第二方向的两端与末端引脚焊盘之间的间隙较小，在波峰焊时，偷锡焊盘沿第二方向的两端施加于末端引脚焊盘上的作用力较大，能够将末端引脚焊盘上的焊锡有效牵引至偷锡焊盘上，从而降低了末端引脚焊盘与同排相邻的引脚焊盘之间，以及与相邻排的引脚焊盘之间产生焊锡粘连的可能性，避免印制电路板产生短路。
可选的，所述圆弧的圆心与所述末端引脚焊盘的中心重合，这样，偷锡焊盘沿第二方向的各个位置与末端引脚焊盘之间的间隙宽度均相等，偷锡焊盘能够均匀吸引末端引脚焊盘上的焊锡，从而进一步降低了末端引脚焊盘与同排相邻的引脚焊盘之间，以及与相邻排的引脚焊盘之间产生焊锡粘连的可能性。
可选的，所述偷锡焊盘与所述末端引脚焊盘之间的最小间隙宽度为第一间隙宽度，相邻两个所述引脚焊盘之间的最小间隙宽度为第二间隙宽度，所述第一间隙宽度与所述第二间隙宽度相等，这样，偷锡焊盘与末端引脚焊盘之间的最小间隙宽度适中，既能够将末端引脚焊盘上的焊锡吸引至偷锡焊盘上，又能够避免偷锡焊盘与末端引脚焊盘之间因间隙过小而导致焊锡粘连。
可选的，所述偷锡焊盘在所述第一方向上的最大宽度为所述引脚焊盘在所述第一方向上的最大宽度的2～4倍，这样，偷锡焊盘在第一方向上的宽度适中，既能够将末端引脚焊盘上的焊锡有效吸引至偷锡焊盘上，又能够避免偷锡焊盘在第一方向上的宽度过大而增大了偷锡焊盘的占用面积和印制电路板的体积。
可选的，所述焊盘排为多排，多排所述焊盘排沿第二方向并排设置，这样，通过多排焊盘排中的偷锡焊盘分别吸引多排焊盘排中的末端引脚焊盘上的焊锡，可避免相邻两排焊盘排中的末端引脚焊盘之间产生焊锡粘连。
可选的，多排所述焊盘排中的引脚焊盘沿所述第二方向错位排列，这样，在保证 相邻两排焊盘排中的引脚焊盘之间的最小间隙宽度不变的前提下，有利于缩小相邻两排焊盘排之间的距离，以利于缩小多排焊盘排在电路板主体的背面上的占用面积，进而缩小印制电路板的体积。
可选的，多排所述焊盘排中的偷锡焊盘沿所述第二方向依次相接并形成一体式偷锡焊盘，这样，印制电路板上的焊盘数量较少，结构简单，方便制作，且相邻两个偷锡焊盘之间不存在空隙，能够更有效地将相邻两个末端引脚焊盘上的焊锡吸引至偷锡焊盘上，以避免相邻两个末端引脚焊盘之间产生焊锡粘连。
可选的，沿所述第二方向，第一排所述焊盘排中的所述引脚焊盘的起始端边沿为第一边沿，最后一排所述焊盘排中的所述引脚焊盘的末端边沿为第二边沿，所述第一边沿与所述第二边沿之间的间隙宽度为第三间隙宽度，所述一体式偷锡焊盘在所述第二方向上的宽度与所述第三间隙宽度相等，这样，一体式偷锡焊盘在第二方向上的宽度适中，既能够避免一体式偷锡焊盘在第二方向上的宽度过大而使偷锡焊盘的占用空间过大，同时又能够有效吸引多排焊盘排中的末端引脚焊盘上的焊锡，以有效避免多个末端引脚焊盘之间产生焊锡粘连而导致短路。
可选的，多排所述焊盘排中的偷锡焊盘远离所述引脚焊盘的一侧边沿平齐设置，这样，多排焊盘排沿第一方向的尾端边沿平齐，有利于多排焊盘排在电路板主体的背面上进行布局。
第二方面，本申请提供一种终端，包括印制电路板，所述印制电路板为如上任一技术方案所述的印制电路板。
本申请实施例提供的终端，由于终端包括印制电路板，且此印制电路板为如上任一技术方案所述的印制电路板，因此二者能够解决相同的技术问题，并达到相同的预期效果。
附图说明
图1为现有技术中的一种印制电路板的结构示意图；
图2为图1所示印制电路板在波峰焊时的结构示意图；
图3为图1所示印制电路板在波峰焊后的一种结构示意图；
图4为图1所示印制电路板在波峰焊后的另一种结构示意图；
图5为现有技术中的另一种印制电路板的结构示意图；
图6为本申请实施例提供的印制电路板的第一种结构示意图；
图7为本申请实施例提供的印制电路板的第二种结构示意图；
图8为本申请实施例提供的印制电路板的第三种结构示意图；
图9为本申请实施例提供的印制电路板的第四种结构示意图；
图10为本申请实施例提供的印制电路板的第五种结构示意图；
图11为本申请实施例提供的印制电路板的第六种结构示意图；
图12为本申请实施例提供的印制电路板的第七种结构示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述。
图6为本申请实施例提供的一种印制电路板，参照图6，本实施例提供的印制电路板包括电路板主体1和设置于所述电路板主体1背面上的焊盘排2，所述焊盘排2 包括偷锡焊盘4和多个引脚焊盘3，多个所述引脚焊盘3、所述偷锡焊盘4沿第一方向K1依次间隔设置，所述引脚焊盘3的形状为圆形，所述偷锡焊盘4靠近多个所述引脚焊盘3的一侧边沿5的轮廓线为向所述偷锡焊盘4内凹陷的圆弧。
其中，需要说明的是，为了便于下文的分析和描述，定义多个引脚焊盘3中与偷锡焊盘4距离最近的引脚焊盘为末端引脚焊盘A，同时定义与第一方向K1垂直并与电路板主体1的背面平行的方向为第二方向K2。
本申请实施例提供的印制电路板，由于电路板主体1的背面上设有焊盘排2，焊盘排2包括沿第一方向K1依次间隔设置的多个引脚焊盘3、偷锡焊盘4，因此在波峰焊时，可使电路板主体1的背面朝下，并牵引电路板主体1沿第一方向K1的反方向以6～8°的倾斜角度向上移动并通过焊锡波峰，以使多个引脚焊盘3、偷锡焊盘4依次通过焊锡波峰，这样，偷锡焊盘4可将末端引脚焊盘A上的焊锡吸引至偷锡焊盘4上，以避免焊锡在此末端引脚焊盘A上产生堆积。
与现有技术相比，在引脚焊盘3的形状为圆形的前提下，由于偷锡焊盘4靠近多个引脚焊盘3的一侧边沿5的轮廓线为向偷锡焊盘4内凹陷的圆弧，因此在保持偷锡焊盘4沿第二方向K2的中部与末端引脚焊盘A之间的间隙宽度D1与图5中的b2相等的前提下，偷锡焊盘4沿第二方向K2的两端与末端引脚焊盘A之间的间隙宽度D2小于图5中的b1，在波峰焊时，偷锡焊盘4沿第二方向K2的两端施加于末端引脚焊盘A上的作用力较大，能够将末端引脚焊盘A上的焊锡有效吸引至偷锡焊盘4上，从而降低了末端引脚焊盘A与同排相邻的引脚焊盘之间，以及与相邻排的引脚焊盘之间产生焊锡粘连的可能性，避免印制电路板产生短路。
在上述实施例中，偷锡焊盘4沿第二方向K2上的最大宽度h1可以小于引脚焊盘3在第二方向K2上的最大宽度h2，也可以等于引脚焊盘3在第二方向K2上的最大宽度h2，还可以大于引脚焊盘3在第二方向K2上的最大宽度h2，在此不做具体限定。示例的，如图7所示，偷锡焊盘4沿第二方向K2上的最大宽度h1大于引脚焊盘3在第二方向K2上的最大宽度h2。
其中，第一方向K1和第二方向K2可以为平行于电路板主体1背面的任意方向，在此不做具体限定，只要保持第一方向K1与第二方向K2相互垂直即可。
另外，焊盘排2包括的引脚焊盘3的数量可以为两个、三个、四个等等，在此不做具体限定。
再者，圆弧的圆心可以位于末端引脚焊盘A靠近偷锡焊盘4的一侧，也可以位于末端引脚焊盘A远离偷锡焊盘4的一侧，还可以与末端引脚焊盘A的中心重合，在此不做具体限定。
可选的，如图6所示，圆弧的圆心与末端引脚焊盘A的中心重合，这样，偷锡焊盘4沿第二方向K2的各个位置与末端引脚焊盘A之间的间隙宽度均相等，偷锡焊盘4能够均匀吸引末端引脚焊盘A上的焊锡，从而进一步降低了末端引脚焊盘A与同排相邻的引脚焊盘之间，以及与相邻排的引脚焊盘之间产生焊锡粘连的可能性。
在图7所示的实施例中，若定义偷锡焊盘4与末端引脚焊盘A之间的最小间隙宽度为第一间隙宽度d1，相邻两个引脚焊盘3之间的最小间隙宽度为第二间隙宽度d2，则第一间隙宽度d1可以大于第二间隙宽度d2，也可以小于第二间隙宽度d2，还可以等 于第二间隙宽度d2，在此不做具体限定。
可选的，第一间隙宽度d1与第二间隙宽度d2相等，这样，偷锡焊盘4与末端引脚焊盘A之间的最小间隙宽度适中，既能够将末端引脚焊盘A上的焊锡有效吸引至偷锡焊盘4上，又能够避免偷锡焊盘4与末端引脚焊盘A之间因间隙宽度过小而导致焊锡粘连，从而降低了末端引脚焊盘A处产生短路的可能性。
在图6所示的实施例中，偷锡焊盘4在第一方向K1上的最大宽度w1可以为引脚焊盘3在第一方向K1上的最大宽度w2的1倍、1.5倍、2倍、3倍等等，在此不做具体限定。可选的，所述偷锡焊盘4在第一方向K1上的最大宽度w1为引脚焊盘3在第一方向K1上的最大宽度w2的2～4倍，这样，偷锡焊盘4在第一方向K1上的宽度w1适中，既能够将末端引脚焊盘A上的焊锡有效吸引至偷锡焊盘4上，又能够避免偷锡焊盘4在第一方向K1上的最大宽度过大而增大了偷锡焊盘4的占用面积和印制电路板的体积。
在图6所示的实施例中，焊盘排2的数量可以为一排，也可以为多排，在此不做具体限定。且当焊盘排2的数量为多排时，多排焊盘排2可以沿第一方向K1排列(如图10所示)，也可以沿第二方向K2排列(如图8或图9所示)，在此不做具体限定。其中，当焊盘排2的数量为多排时，具体的，焊盘排2的数量可以为图8、图9、图10、图11和图12所示的两排，也可以为三排或四排等等，在此不做具体限定。
可选的，如图8或图9所示，所述焊盘排2为多排，多排所述焊盘排2沿第二方向K2并排设置，这样，通过多排焊盘排2中的偷锡焊盘4分别吸引多排焊盘排2中的末端引脚焊盘A上的焊锡，可避免相邻两排焊盘排2中的末端引脚焊盘A之间产生焊锡粘连。
在图8或图9所示的实施例中，多排焊盘排2中的引脚焊盘可以沿第二方向K2对齐排列(如图8所示)，也可以沿第二方向K2错位排列(如图9所示)，在此不做具体限定。
可选的，如图9所示，多排焊盘排2中的引脚焊盘3沿第二方向K2错位排列，这样，在保证相邻两排焊盘排2中的引脚焊盘之间的最小间隙宽度不变的前提下，有利于缩小相邻两排焊盘排2之间的距离，以利于缩小多排焊盘排2在电路板主体1的背面上的占用面积，进而缩小印制电路板的体积。
在图8或图9所示的实施例中，多排焊盘排2中的偷锡焊盘4可以彼此间隔设置，也可以沿第二方向K2依次相接并形成一体式结构，在此不做具体限定。
可选的，如图11或图12所示，多排焊盘排2中的偷锡焊盘沿所述第二方向依次相接并形成一体式偷锡焊盘6，这样，印制电路板上的焊盘数量较少，结构简单，方便制作，且相邻两个偷锡焊盘之间不存在空隙，能够更有效地将相邻两个末端引脚焊盘上的焊锡吸引至偷锡焊盘上，以避免相邻两个末端引脚焊盘之间产生焊锡粘连。
在图11或图12所示的实施例中，若定义沿第二方向K2，第一排焊盘排2中的引脚焊盘3的起始端边沿为第一边沿a1，最后一排焊盘排2中的引脚焊盘3的末端边沿为第二边沿a2，第一边沿与第二边沿之间的间隙宽度为第三间隙宽度d3，则一体式偷锡焊盘6在第二方向K2上的宽度H可以大于此第三间隙宽度d3，也可以小于此第三间隙宽度d3，还可以等于此第三间隙宽度d3，在此不做具体限定。
可选的，一体式偷锡焊盘6在第二方向K2上的宽度H等于第三间隙宽度d3，这样，一体式偷锡焊盘6在第二方向K2上的宽度H适中，既能够避免一体式偷锡焊盘6在第二方向K2上的宽度过大而使偷锡焊盘的占用空间过大，同时又能够有效吸引多排焊盘排2中的末端引脚焊盘上的焊锡，以有效避免多个末端引脚焊盘之间产生焊锡粘连而导致短路。
在图8、图9、图11或图12所示的实施例中，多排焊盘排中的偷锡焊盘远离引脚焊盘3的一侧边沿可以平齐设置，也可以不平齐设置，在此不做具体限定。可选的，如图11或图12所示，多排焊盘排中的偷锡焊盘远离引脚焊盘3的一侧边沿平齐设置，这样，多排焊盘排沿第一方向的尾端边沿平齐，有利于多排焊盘排在电路板主体1的背面上进行布局。
本申请还提供了一种终端，包括印制电路板，所述印制电路板为如上任一技术方案所述的印制电路板。
本申请实施例提供的终端，由于终端包括印制电路板，且此印制电路板为如上任一技术方案所述的印制电路板，因此二者能够解决相同的技术问题，并达到相同的预期效果。
在上述实施例中，终端可以为手机、平板、手表、相机等，在此不做具体限定。且关于本申请实施例的终端的其他构成等已为本领域的技术人员所熟知，在此不再详细说明。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。

Claims (10)

  1. 一种印制电路板，包括电路板主体和设置于所述电路板主体背面上的焊盘排，
    所述焊盘排包括偷锡焊盘和多个引脚焊盘，多个所述引脚焊盘、所述偷锡焊盘沿第一方向依次间隔设置，所述引脚焊盘的形状为圆形，其特征在于，所述偷锡焊盘靠近多个所述引脚焊盘的一侧边沿的轮廓线为向所述偷锡焊盘内凹陷的圆弧。
  2. 根据权利要求1所述的印制电路板，其特征在于，多个所述引脚焊盘中与所述偷锡焊盘距离最近的所述引脚焊盘为末端引脚焊盘，所述圆弧的圆心与所述末端引脚焊盘的中心重合。
  3. 根据权利要求1或2所述的印制电路板，其特征在于，所述偷锡焊盘与所述末端引脚焊盘之间的最小间隙宽度为第一间隙宽度，相邻两个所述引脚焊盘之间的最小间隙宽度为第二间隙宽度，所述第一间隙宽度与所述第二间隙宽度相等。
  4. 根据权利要求1～3中任一项所述的印制电路板，其特征在于，所述偷锡焊盘在所述第一方向上的最大宽度为所述引脚焊盘在所述第一方向上的最大宽度的2～4倍。
  5. 根据权利要求1～4中任一项所述的印制电路板，其特征在于，所述焊盘排为多排，多排所述焊盘排沿第二方向并排设置，且所述第二方向与所述第一方向垂直。
  6. 根据权利要求5所述的印制电路板，其特征在于，多排所述焊盘排中的引脚焊盘沿所述第二方向错位排列。
  7. 根据权利要求5或6所述的印制电路板，其特征在于，多排所述焊盘排中的偷锡焊盘沿所述第二方向依次相接并形成一体式偷锡焊盘。
  8. 根据权利要求7所述的印制电路板，其特征在于，沿所述第二方向，第一排所述焊盘排中的所述引脚焊盘的起始端边沿为第一边沿，最后一排所述焊盘排中的所述引脚焊盘的末端边沿为第二边沿，所述第一边沿与所述第二边沿之间的间隙宽度为第三间隙宽度，所述一体式偷锡焊盘在所述第二方向上的宽度与所述第三间隙宽度相等。
  9. 根据权利要求5～8中任一项所述的印制电路板，其特征在于，多排所述焊盘排中的偷锡焊盘远离所述引脚焊盘的一侧边沿平齐设置。
  10. 一种终端，其特征在于，包括印制电路板，所述印制电路板为权利要求1～9中任一项所述的印制电路板。
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