WO2019024442A1 - 一种扫描驱动电路及装置 - Google Patents

一种扫描驱动电路及装置 Download PDF

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Publication number
WO2019024442A1
WO2019024442A1 PCT/CN2018/071911 CN2018071911W WO2019024442A1 WO 2019024442 A1 WO2019024442 A1 WO 2019024442A1 CN 2018071911 W CN2018071911 W CN 2018071911W WO 2019024442 A1 WO2019024442 A1 WO 2019024442A1
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Prior art keywords
switch
electrically connected
switch tube
unit
capacitor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2018/071911
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English (en)
French (fr)
Inventor
陈彩琴
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Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Priority to US15/754,167 priority Critical patent/US10553170B2/en
Publication of WO2019024442A1 publication Critical patent/WO2019024442A1/zh
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0291—Details of output amplifiers or buffers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a scan driving circuit and device.
  • the Gate Driver On Array (GOA) circuit is a driving method in which a scan driving circuit is formed on an array substrate of a conventional thin film transistor liquid crystal display to realize progressive scanning of a scanning line.
  • FIG. 1 is a circuit diagram of a prior art scan driving circuit.
  • FIG. 2 is a circuit timing diagram corresponding to the scan driving circuit.
  • the scan driving circuit uses a P-type thin film transistor (TFT), and by analyzing the circuit shown in FIG. 1, it can be seen that
  • the clock signal XCK is low and the capacitor C3 is charged, so that in the T1 phase, the capacitor C3 maintains the gate low of the transistor M4, and the transistor M4 is turned on. Since the clock signal CK is low during the T1 phase, the transistor M5 is turned on, the level of the scan signal of the previous stage is turned on, and the transistor M6 is also turned on, and the point of the point A is divided by the three TFTs to obtain a higher threshold value than the TFT. The level is such that transistor M2 and transistor M9 are turned off.
  • the level of the A point obtained by connecting a plurality of TFTs in series is unstable, which may cause the transistor M2 or the transistor M9 to be turned on, pulling up the level of the Q point, thereby causing an erroneous scan signal to be output.
  • the embodiment of the invention provides a scan driving circuit and device, which can avoid the instability of the control point caused by the series connection of the plurality of TFTs during the working process, and improve the correctness of the scan line output scan signal.
  • an embodiment of the present invention provides a scan driving circuit, including a plurality of scan drive units that are cascaded; and the Nth scan drive unit includes at least:
  • a first control module configured to receive an N-1th scan signal, and control a point at the first node according to the N-1 scan signal;
  • a second control module configured to control a point at the second node according to the N-1th scan signal, the N-2th scan signal, the first clock signal, the second clock signal, and the first constant voltage signal;
  • An output module configured to output an Nth-level scan signal according to a level at the first node and a level of the second node;
  • the second control module includes a first switch unit, a second switch unit, a potential maintaining unit, and a first switch control unit; the first control end of the first switch unit and the first end electrically connect the first clock signal The second control end of the first switch unit is electrically connected to the first switch control unit; the second end of the first switch unit is connected to the first end of the second switch unit, and the second switch unit The second end is connected to the first constant voltage signal; the second node is connected to the common end of the first switch unit and the second switch unit;
  • the potential maintaining unit is configured to maintain a level of the second node
  • the N-1th scan signal is electrically connected to the control end of the second switch unit, and the first switch control unit is configured to perform, according to the second clock signal, the N-1th scan signal,
  • the N-2th scanning signal and the first constant voltage signal are controlled by the second control end of the first switching unit, so that the first switching unit is different from the second switching unit through.
  • an embodiment of the present invention further provides an array substrate, wherein the array substrate comprises any one of the scan driving circuits according to the first aspect.
  • an embodiment of the present invention further provides a display panel, the display panel comprising an array substrate, wherein the array substrate comprises any one of the scan driving circuits according to the first aspect.
  • the scan driving circuit includes a plurality of scan drive units that are cascaded;
  • the Nth scan drive unit includes at least: a first control module, a second control module, and an output module
  • the second control module includes the first a switching unit, a second switching unit, a potential maintaining unit, and a first switching control unit
  • the N-1th scanning signal is electrically connected to a control end of the second switching unit
  • the first switching control unit is used to Controlling, by the second control end of the first switching unit, the second clock signal, the N-1th scan signal, the N-2th scan signal, and the first constant voltage signal
  • the first switching unit is configured such that the first switching unit and the second switching unit are not turned on at the same time, thereby preventing the potential of the control point caused by the series connection of the plurality of TFTs during the operation of the scanning circuit from being unstable, and improving the scanning line output scanning signal The correctness.
  • FIG. 1 is a schematic circuit diagram of a scan driving circuit provided by the prior art
  • FIG. 2 is a schematic diagram of a circuit structure of a scan driving unit provided by the prior art
  • FIG. 3 is a schematic structural diagram of a circuit of a scan driving circuit according to an embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of a circuit of a scan driving unit according to an embodiment of the present invention.
  • FIG. 5 is a schematic diagram of a first circuit of a first control module according to an embodiment of the present invention.
  • FIG. 6 is a first circuit diagram of another first control module according to an embodiment of the present invention.
  • FIG. 7 is a schematic diagram of a first circuit of a first switching unit according to an embodiment of the present invention.
  • FIG. 8 is a schematic diagram of a first circuit of a potential maintaining unit according to an embodiment of the present invention.
  • FIG. 9 is a schematic circuit diagram of a first switch control unit according to an embodiment of the present invention.
  • FIG. 10 is a schematic circuit diagram of an output module according to an embodiment of the present invention.
  • FIG. 11 is a circuit diagram of another scan driving circuit according to an embodiment of the present invention.
  • FIG. 12 is a circuit timing diagram of a scan driving circuit according to an embodiment of the present invention.
  • FIG. 3 is a schematic diagram of a circuit structure of a scan driving circuit according to an embodiment of the present invention.
  • the GOA circuit includes a display panel.
  • the GOA circuit includes a plurality of cascaded GOA units, setting N to be a positive integer, and the Nth stage GOA unit includes an Nth-stage scan driving circuit for driving the Nth-th scan line G(N) of the display region.
  • FIG. 4 is a schematic structural diagram of a circuit of a scan driving unit according to an embodiment of the present invention.
  • the scan driving unit includes at least:
  • the first control module 410 is configured to receive the N-1th scan signal G(N-1), and control a point at the first node Q(N) according to the N-1 scan signal;
  • the second control module 420 is configured to: according to the (N-1)th scan signal G(N-1), the N-2th scan signal G(N-2), the first clock signal CK1, and the second clock signal CK2 And the first constant voltage signal VGH controls a point at the second node P(N);
  • the output module 430 is configured to output an Nth-th scan signal G(N) according to a level at the first node Q(N) and a level of the second node P(N); wherein
  • the second control module 420 includes a first switch unit 421, a second switch unit 422, a potential maintaining unit 423, and a first switch control unit 424.
  • the first control end of the first switch unit 421 and the first end are electrically connected.
  • the first clock signal CK1 the second control end of the first switch unit 421 is electrically connected to the first switch control unit 424;
  • the second end of the first switch unit 421 is connected to the second switch unit 422
  • the first end of the second switch unit 422 is connected to the first constant voltage signal VGH;
  • the second node P(N) is connected to the first switch unit 421 and the second switch unit
  • the potential maintaining unit 423 is configured to maintain a level of the second node P(N);
  • the N-1th scan signal G(N-1) is electrically connected to the control end of the second switch unit 422, and the first switch control unit 424 is configured to use the second clock signal CK2 according to the second The N-1 stage scan signal G(N-1), the N-2th stage scan signal G(N-2), and the first constant voltage signal VGH pass through the second control end of the first switching unit 421
  • the first switching unit 421 is controlled such that the first switching unit 421 and the second switching unit 422 are not turned on at the same time.
  • the scan driving circuit includes a plurality of cascaded scan driving units; the Nth-level scan driving unit includes at least: a first control module 410, a second control module 420, and an output module 430, and a second control module.
  • the 420 includes a first switching unit 421, a second switching unit 422, a potential maintaining unit 423, and a first switching control unit 424, wherein the N-1th scanning signal G(N-1) is electrically connected to the second switch a control end of the unit 422, the first switch control unit 424 is configured to perform, according to the second clock signal CK2, the N-1th scan signal G(N-1), the N-2th scan signal G (N-2) and the first constant voltage signal VGH are controlled by the second control end of the first switching unit 421 to the first switching unit 421 such that the first switching unit 421 and the second switching unit 422 is not turned on at the same time, thereby preventing the potential of the control point caused by the series connection of the plurality of TFTs during the operation of the scan circuit from being unstable, and improving the correctness of the scan signal output by the scan line.
  • FIG. 5 is a schematic circuit diagram of a first control module according to an embodiment of the present invention.
  • the first control module 500 includes a first switch tube T1 and a second switch tube T2. And a first capacitor C1, wherein
  • the source and the gate of the first switch T1 are electrically connected to the N-1th scan signal G(N-1); the drain of the first switch T1 is electrically connected to the first capacitor C1.
  • the first end of the first capacitor C1 is electrically connected to the output end of the output module 430; the first node Q(N) is the first end of the first capacitor C1;
  • the source of the switch T2 is electrically connected to the drain of the first switch T1, the drain of the second switch T2 is electrically connected to the first constant voltage signal VGH; the gate of the third switch T3
  • the second node P(N) is electrically connected.
  • FIG. 6 is a schematic circuit diagram of another first control module according to an embodiment of the present invention.
  • the first control module 600 includes a first switch tube T1 and a second switch tube. T2, a third switch tube T3, and a first capacitor C1; wherein
  • the drain of the first switch T1 is electrically connected to the source of the third switch T3, and the drain of the third switch T3 is electrically connected to the first end of the first capacitor C1;
  • the second segment of the capacitor C1 is electrically connected to the output end of the output module 430;
  • the first node Q(N) is the first end of the first capacitor C1;
  • the gate of the third switch transistor T3 is electrically connected a second constant voltage signal VGL;
  • the second constant voltage signal VGL controls the conduction of the third switching tube T3;
  • the source of the second switching tube T2 is electrically connected to the first switching tube T1 and the first a common end of the three switch tubes T3, the drain of the second switch tube T2 is electrically connected to the first constant voltage signal VGH;
  • the gate of the third switch tube T3 is electrically connected to the second node P(N) .
  • FIG. 7 is a schematic diagram of a first circuit of a first switch unit according to an embodiment of the present invention.
  • the first switch unit 700 includes a fourth switch tube T4 and a fifth. Switch tube T5; among them,
  • the first clock signal CK1 is electrically connected to the source of the fourth switch tube T4, the drain of the fourth switch tube T4 is electrically connected to the source of the fifth switch tube T5; the fifth switch tube T5 The drain is electrically connected to the second node P(N); the gate of the fourth switch T4 is the second control end of the first switch T1, and is electrically connected to the first switch control unit 424; The gate of the fifth switch T5 is the first control end of the first switch T1, and is electrically connected to the first clock signal CK1.
  • the second switch unit 422 includes a sixth switch tube T6, the second switch unit 422 includes a sixth switch tube T6, and the source of the sixth switch tube T6 is electrically connected to the first a second end of the switch unit 421; a drain of the sixth switch T6 is electrically connected to the first constant voltage signal VGH; and a gate of the sixth switch T6 is electrically connected to the N-1th scan Signal G(N-1).
  • the potential maintaining unit 423 includes a second capacitor C2.
  • the first end of the second capacitor C2 is connected to the second node P(N), and the second capacitor C2 is The two ends are electrically connected to the first constant voltage power source.
  • FIG. 8 is a schematic diagram of a first circuit of a potential maintaining unit according to an embodiment of the present invention.
  • the potential maintaining unit 800 includes a seventh switching tube T7 and a second capacitor C2. ;among them,
  • the gate of the seventh switch tube T7 is electrically connected to the N-2th scan signal G(N-2), and the source of the seventh switch tube T7 is electrically connected to the first constant voltage signal VGH;
  • the drain of the seventh switch tube T7 is electrically connected to the first end of the second capacitor C2, the second end of the second capacitor C2 is electrically connected to the first constant voltage power source;
  • the seventh switch tube T7 is The common end of the second capacitor C2 is electrically connected to the second node P(N).
  • FIG. 9 is a schematic circuit diagram of a first switch control unit according to an embodiment of the present invention.
  • the first switch control unit 900 includes an eighth switch tube T8 and a ninth switch. a tube T9 and a third capacitor C3; wherein
  • the source and the gate of the eighth switch T8 are electrically connected to the second clock signal CK2; the drain of the eighth switch T8 is electrically connected to the second control end of the first switch unit 421 and the a first end of the third capacitor C3; a second end of the third capacitor C3 is electrically connected to the N-2th scan signal G(N-2); and a source of the ninth switch T9 is electrically connected a common end of the eighth switch tube T8 and the third capacitor C3; a drain of the ninth switch tube T9 is electrically connected to the first constant voltage signal VGH; and a gate of the ninth switch tube T9 is electrically connected The N-1th stage scan signal G(N-1).
  • FIG. 10 is a circuit diagram of an output module according to an embodiment of the present invention.
  • the output module 1000 includes a tenth switch tube T10 and an eleventh switch tube T11.
  • the source of the tenth switch tube T10 is electrically connected to the second clock signal CK2, and the drain of the tenth switch tube T10 is electrically connected to the source of the eleventh switch tube T11, the eleventh switch
  • the drain of the transistor T11 is electrically connected to the first constant voltage signal VGH;
  • the gate of the tenth switch transistor T10 is electrically connected to the first node Q(N);
  • the gate of the eleventh switch transistor T11 is electrically The second node P(N) is connected;
  • the common end of the tenth switch tube T10 and the eleventh switch tube T11 is an output end of the Nth stage scan signal G(N).
  • FIG. 11 is a schematic circuit diagram of a scan driving circuit according to an embodiment of the present invention.
  • the switching transistors shown in FIG. 5 to FIG. 11 are all P-type transistors (the source and the drain are turned on when the gate is at a low level), but in other embodiments of the present invention, an N-type transistor can be used. In place of some or all of the transistors in the figure, the source and the drain are turned on when the gate is at a high level, which is not limited in the present invention. Moreover, the connection mode of the source and the drain of each transistor can be determined according to the type of the transistor selected, and when the transistor has a structure in which the source and the drain are symmetric, the source and the drain can be regarded as two which are not particularly distinguished. Electrodes, which are well known to those skilled in the art, are not described herein.
  • first clock signal CK1, the second clock signal CK2, the first constant voltage signal VGH, the second constant voltage signal VGL, and the initial scan signal and the switch tube in the scan driving circuit when the switch tube is a P-type transistor The first clock signal CK1, the second clock signal CK2, the first constant voltage signal VGH, the second constant voltage signal VGL, and the initial scan signal are opposite in polarity in the scan driving circuit in the case of the N-type transistor.
  • FIG. 12 is a circuit timing diagram for the scan driving circuit shown in FIG. In each action phase, the first constant voltage signal VGH is always at a high level; the second constant voltage signal VGL is always at a low level, and the third switching transistor T3 is always in an on state.
  • the N-1th scanning signal G(N-1) is at a low level, and the first switching transistor T1T1, the sixth switching transistor T6T6, and the ninth switching transistor T9T9 are turned on.
  • the first switch tube T1 and the third switch tube T3 are turned on, and the low level of the N-1th scan signal G(N-1) is input to the first node Q(N), and the first node Q(N) is pulled down. Level, the tenth switch tube T10 is turned on, the Nth scan line is input to the high level of the second clock signal CK2, and the first capacitor C1 is charged.
  • the second clock signal CK2 is at a high level, and the eighth switch tube T8 is turned off; the first clock signal CK1 is at a low level, and the fifth switch tube T5 is turned on. Since the N-2th scanning signal G(N-2) is at a low level, the second clock signal CK2 is at a low level, the eighth switching transistor T8 is turned on, and the third capacitor C3 is in an initial active phase (t0).
  • the N-2th scanning signal G(N-2) transitions to a high level
  • the second clock signal CK2 is at a high level
  • the eighth switching transistor T8 is turned off
  • the N-2th scanning signal G(N-2) transitions from the low level of the t0 phase to the high level
  • the first constant voltage signal VGH is due to the action of the third capacitor C3 and the conduction of the ninth switching transistor T9.
  • the high level is input to the gate of the fourth switching transistor T4, at which time the fourth switching transistor T4 is turned off, preventing the high level input of the first clock signal CK1 from being input to the second node P(N), and the fourth switch being avoided.
  • the tube T4, the fifth switching tube T5, and the sixth switching tube T6 are simultaneously turned on, and the partial pressure of the second node P(N) is caused.
  • the high level of the first constant voltage signal VGH, the seventh switch tube T7 is turned off; since the sixth switch tube T6 is turned on, the high level of the first constant voltage signal VGH is input to the second node P(N), the second The switch tube T2 and the eleventh switch tube T11 are turned off.
  • the N-1th scanning signal G(N-1) is at a high level, and the first switching transistor T1T1, the sixth switching transistor T6T6, and the ninth switching transistor T9T9 are both turned off.
  • the level at the first node Q(N) is maintained at a low level due to the action of the first capacitor C1, the tenth switch tube T10 is turned on, and the Nth-th scan line is input at a low level of the second clock signal CK2 at this time.
  • the second clock signal CK2 is at a low level, and the eighth switch tube T8 and the fourth switch tube T4 are turned on.
  • the first clock signal CK1 is at a low level
  • the fifth switch tube T5 is turned off
  • the first clock signal CK1 is turned on.
  • the flat switch cannot be input to the second node P(N); the sixth switch tube T6 is turned off, and the first constant voltage signal VGH cannot be input to the second node P(N). Since the second node P(N) is at a high level in the first action phase (t1), the second node P(N) is kept at a low level by the second capacitor C2, and the second opening, the eleventh switch Tube T11 is cut off.
  • the N-1th scanning signal G(N-1) is at a high level, and the first switching transistor T1T1, the sixth switching transistor T6T6, and the ninth switching transistor T9T9 are both turned off.
  • the second clock signal CK2 is at a high level, and the eighth switch tube T8 is turned off; since the third capacitor C3 is charged in the upper stage, the third capacitor C3 maintains the gate of the fourth switch tube T4 at a low level, and the fourth switch tube T4 Turning on; the first clock signal CK1 is low level, and the fifth switch tube T5 is turned on, so that the low level of the first clock signal CK1 is input to the second node P(N), and the power of the second node P(N) is pulled down. In the flat state, the second switching transistor T2 and the eleventh switching transistor T11 are both turned on, and the Nth scanning line inputs the high level of the first constant voltage signal VGH at this time.
  • the N-2th scanning signal G(N-2) is at a high level, the seventh switching transistor T7 is turned off, and the second capacitor C2 is charged.
  • the second switch tube T2 is turned on, the high level of the first constant voltage signal VGH is input to the first node Q(N), the level of the first node Q(N) is pulled up, and the tenth switch tube T10 is turned off, the first Capacitor C1 is discharged.
  • the N-1th scanning signal G(N-1) is at a high level, and the first switching transistor T1T1, the sixth switching transistor T6T6, and the ninth switching transistor T9T9 are both turned off.
  • the second capacitor C2 is charged, maintaining the low level of the second node P(N), and the second switching tube T2 and the eleventh switching tube T11 are both turned on, and the Nth scanning line is input at this time.
  • the second switching transistor T2 is turned on, the high level of the first constant voltage signal VGH is input to the level of the first pull-up first node Q(N), the tenth switching tube T10 is turned off, and the first capacitor C1 is discharged.
  • the second clock signal CK2 is at a low level, and the eighth switch tube T8 and the fourth switch tube T4 are both turned on, the first clock signal CK1 is at a high level, and the fifth switch tube T5 is turned off.
  • the N-2th scanning signal G(N-2) is at a high level, and the third capacitor C3 is charged.
  • high level and low level in this document refer to two logic states represented by the level height range at a certain circuit node position, respectively. It can be understood that the specific level height range can be set as needed in a specific application scenario, and the present invention does not limit this.
  • pulse-up in this context refers to raising the level at the corresponding circuit node to a high level.
  • pulse-down refers to lowering the level at the corresponding circuit node to a low level. Level. It can be understood that the above-mentioned “pull-up” and “pull-down” can be realized by the directional movement of the electric charge, and thus can be realized by an electronic component having a corresponding function or a combination thereof, which is not limited by the present invention.
  • an embodiment of the present invention provides an array substrate including the scan driving circuit of any of the above. It will be appreciated that the scan drive circuit can be disposed outside of the display area to form a GOA circuit structure and has the advantages of any of the scan drive circuits described above.
  • an embodiment of the present invention provides a display device including the array substrate of any of the above, and thus has the advantages of any of the above array substrates.
  • the display device in this embodiment may be any product or component having a display function, such as a display, a mobile phone, a tablet computer, a television, a notebook computer, a digital photo frame, a navigator, and the like.
  • the terms “mounted,” “connected,” and “connected” are used in a broad sense, and may be, for example, a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection, It can also be an electrical connection; it can be directly connected, or it can be connected indirectly through an intermediate medium, which can be the internal connection of two components.
  • the specific meanings of the above terms in the present invention can be understood on a case-by-case basis.

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Abstract

一种扫描驱动电路及装置。扫描驱动电路包括多级联的多个扫描驱动单元；第N级扫描驱动单元至少包括：第一控制模块（410）、第二控制模块（420）以及输出模块（430），第二控制模块（420）包括第一开关单元（421）、第二开关单元（422）、电位维持单元（423）以及第一开关控制单元（424），其中，第N-1级扫描信号（G(N-1)）电连接第二开关单元（422）的控制端，第一开关控制单元（424）用于根据第二时钟信号（CK2）、第N-1级扫描信号（G(N-1)）、第N-2级扫描信号（G(N-2)）以及第一恒压信号（VGH）通过第一开关单元（421）的第二控制端控制第一开关单元（421），使得第一开关单元（421）与第二开关单元（422）不同时导通，进而避免扫描电路在工作过程中多个TFT的串联引起的控制点的电位不稳定，提高扫描线输出扫描信号的正确性。

Description

一种扫描驱动电路及装置 技术领域
本发明涉及显示技术领域，尤其涉及一种扫描驱动电路及装置。
背景技术
阵列基板行驱动(Gate Driver On Array，简称GOA)电路是在现有薄膜晶体管液晶显示器的阵列基板上制作扫描驱动电路，实现对扫描线逐行扫描的驱动方式。
请参阅图1，图1是现有技术中扫描驱动电路的电路图，请参阅图2，图2图1所示的扫描驱动电路对应的电路时序图。该扫描驱动电路采用P型薄膜晶体管(Thin Film Transistor，TFT)，通过分析图1所示的电路，可见，
在T0阶段时，时钟信号XCK低电平，电容C3充电，使得在T1阶段时，电容C3维持晶体管M4栅极低电平，晶体管M4导通。由于在T1阶段时，时钟信号CK低电平，晶体管M5导通，上一级扫描信号电平，晶体管M6也导通，A点的点位通过三个TFT分压，得到较TFT阈值较高的电平，使得晶体管M2和晶体管M9关闭。然而，多个TFT串联得到的A点的电平不稳定，可能会造成晶体管M2或晶体管M9的导通，拉升Q点的电平，从而导致输出错误的扫描信号。
发明内容
本发明实施例提供了一种扫描驱动电路及装置，能够避免扫描电路在工作过程中多个TFT的串联引起的控制点的电位不稳定，提高扫描线输出扫描信号的正确性。
第一方面，本发明实施例提供了一种扫描驱动电路，包括多级联的多个扫描驱动单元；第N级扫描驱动单元至少包括：
第一控制模块，用于接收第N-1级扫描信号，并根据所述N-1扫描信号控制第一节点处的点位；
第二控制模块，用于根据所述第N-1级扫描信号、第N-2级扫描信号、第一时钟信号、第二时钟信号以及第一恒压信号控制第二节点处的点位；
输出模块，用于根据所述第一节点处的电平以及所述第二节点的电平输出第N级扫描信号；其中，
所述第二控制模块包括第一开关单元、第二开关单元、电位维持单元以及第一开关控制单元；所述第一开关单元的第一控制端以及第一端电连接所述第一时钟信号，所述第一开关单元的第二控制端电连接所述第一开关控制单元；所述第一开关单元的第二端连接所述第二开关单元的第一端，所述第二开关单元的第二端连接所述第一恒压信号；所述第二节点连接所述第一开关单元与所述第二开关单元的公共端；
所述电位维持单元用于维持所述第二节点的电平；
所述第N-1级扫描信号电连接所述第二开关单元的控制端，所述第一开关控制单元用于根据所述第二时钟信号、所述第N-1级扫描信号、所述第N-2级扫描信号以及所述第一恒压信号通过所述第一开关单元的第二控制端控制所述第一开关单元，使得所述第一开关单元与第二开关单元不同时导通。
第二方面，本发明实施例还提供了一种阵列基板，所述阵列基板包括如第一方面所述的任一扫描驱动电路。
第三方面，本发明实施例还提供了一种显示面板，所述显示面板包括阵列基板，所述阵列基板包括如第一方面所述的任一扫描驱动电路。
本发明实施例中，该扫描驱动电路包括多级联的多个扫描驱动单元；第N级扫描驱动单元至少包括：第一控制模块、第二控制模块以及输出模块，第二控制模块包括第一开关单元、第二开关单元、电位维持单元以及第一开关控制单元，其中，所述第N-1级扫描信号电连接所述第二开关单元的控制端，所述第一开关控制单元用于根据所述第二时钟信号、所述第N-1级扫描信号、所述第N-2级扫描信号以及所述第一恒压信号通过所述第一开关单元的第二控制端控制所述第一开关单元，使得所述第一开关单元与第二开关单元不同时导通，进而避免扫描电路在工作过程中多个TFT的串联引起的控制点的电位不稳定，提高扫描线输出扫描信号的正确性。
附图说明
为了更清楚地说明本发明实施例技术方案，下面将对实施例描述中所需要 使用的附图作简单地介绍。
图1是现有技术提供的一种扫描驱动电路的电路示意图；
图2是现有技术提供的一种扫描驱动单元的电路结构示意图；
图3是本发明实施例提供的一种扫描驱动电路的电路结构示意图；
图4是本发明实施例提供的一种扫描驱动单元的电路结构示意图；
图5是本发明实施例提供的一种第一控制模块的第一种电路示意图；
图6是本发明实施例提供的另一种第一控制模块的第一种电路示意图；
图7是本发明实施例提供的一种第一开关单元的第一种电路示意图；
图8是本发明实施例提供的一种电位维持单元的第一种电路示意图；
图9是本发明实施例提供的一种第一开关控制单元的电路示意图；
图10是本发明实施例提供的一种输出模块的电路示意图；
图11是本发明实施例提供的另一种扫描驱动电路的电路示意图；
图12是本发明实施例提供的一种扫描驱动电路的电路时序图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行描述。
请参阅图3，图3是本发明实施例提供的一种扫描驱动电路的电路结构示意图，该GOA电路包括可应用于显示面板。该GOA电路包括多个级联的GOA单元，设定N为正整数，第N级GOA单元包括第N级扫描驱动电路，用于驱动显示区域的第N级扫描线G(N)。
请参阅图4，图4是本发明实施例提供的一种扫描驱动单元的电路结构示意图，该扫描驱动单元至少包括：
第一控制模块410，用于接收第N-1级扫描信号G(N-1)，并根据所述N-1扫描信号控制第一节点Q(N)处的点位；
第二控制模块420，用于根据所述第N-1级扫描信号G(N-1)、第N-2级扫描信号G(N-2)、第一时钟信号CK1、第二时钟信号CK2以及第一恒压信号VGH控制第二节点P(N)处的点位；
输出模块430，用于根据所述第一节点Q(N)处的电平以及所述第二节点 P(N)的电平输出第N级扫描信号G(N)；其中，
所述第二控制模块420包括第一开关单元421、第二开关单元422、电位维持单元423以及第一开关控制单元424；所述第一开关单元421的第一控制端以及第一端电连接所述第一时钟信号CK1，所述第一开关单元421的第二控制端电连接所述第一开关控制单元424；所述第一开关单元421的第二端连接所述第二开关单元422的第一端，所述第二开关单元422的第二端连接所述第一恒压信号VGH；所述第二节点P(N)连接所述第一开关单元421与所述第二开关单元422的公共端；
所述电位维持单元423用于维持所述第二节点P(N)的电平；
所述第N-1级扫描信号G(N-1)电连接所述第二开关单元422的控制端，所述第一开关控制单元424用于根据所述第二时钟信号CK2、所述第N-1级扫描信号G(N-1)、所述第N-2级扫描信号G(N-2)以及所述第一恒压信号VGH通过所述第一开关单元421的第二控制端控制所述第一开关单元421，使得所述第一开关单元421与第二开关单元422不同时导通。
本发明实施例中，该扫描驱动电路包括多级联的多个扫描驱动单元；第N级扫描驱动单元至少包括：第一控制模块410、第二控制模块420以及输出模块430，第二控制模块420包括第一开关单元421、第二开关单元422、电位维持单元423以及第一开关控制单元424，其中，所述第N-1级扫描信号G(N-1)电连接所述第二开关单元422的控制端，所述第一开关控制单元424用于根据所述第二时钟信号CK2、所述第N-1级扫描信号G(N-1)、所述第N-2级扫描信号G(N-2)以及所述第一恒压信号VGH通过所述第一开关单元421的第二控制端控制所述第一开关单元421，使得所述第一开关单元421与第二开关单元422不同时导通，进而避免扫描电路在工作过程中多个TFT的串联引起的控制点的电位不稳定，提高扫描线输出扫描信号的正确性。
本发明一实施例中，请参阅图5，图5是本发明实施例提供的一种第一控制模块的电路示意图，所述第一控制模块500包括第一开关管T1、第二开关管T2和第一电容C1，其中，
所述第一开关管T1的源极和栅极电连接所述第N-1级扫描信号G(N-1)；所述第一开关管T1的漏极电连接所述第一电容C1的第一端，所述第一电容 C1的第二段电连接所述输出模块430的输出端；所述第一节点Q(N)为所述第一电容C1的第一端；所述第二开关管T2的源极电连接所述第一开关管T1的漏极，所述第二开关管T2的漏极电连接所述第一恒压信号VGH；所述第三开关管T3的栅极电连接所述第二节点P(N)。
本发明一实施例中，请参阅图6，图6是本发明实施例提供的另一种第一控制模块的电路示意图，所述第一控制模块600包括第一开关管T1、第二开关管T2、第三开关管T3以及第一电容C1；其中，
所述第一开关管T1的漏极电连接所述第三开关管T3的源极，所述第三开关管T3的漏极电连接所述第一电容C1的第一端；所述第一电容C1的第二段电连接所述输出模块430的输出端；所述第一节点Q(N)为所述第一电容C1的第一端；所述第三开关管T3的栅极电连接第二恒压信号VGL；所述第二恒压信号VGL控制所述第三开关管T3的导通；所述第二开关管T2的源极电连接所述第一开关管T1与所述第三开关管T3的公共端，所述第二开关管T2的漏极电连接所述第一恒压信号VGH；所述第三开关管T3的栅极电连接所述第二节点P(N)。
本发明一实施例中，请参阅图7，图7是本发明实施例提供的一种第一开关单元的第一种电路示意图，所述第一开关单元700包括第四开关管T4和第五开关管T5；其中，
所述第一时钟信号CK1电连接所述第四开关管T4的源极，所述第四开关管T4的漏极电连接所述第五开关管T5的源极；所述第五开关管T5的漏极电连接所述第二节点P(N)；所述第四开关管T4的栅极为所述第一开关管T1的第二控制端，电连接所述第一开关控制单元424；所述第五开关管T5的栅极为所述第一开关管T1的第一控制端，电连接所述第一时钟信号CK1。
本发明一实施例中，所述第二开关单元422包括第六开关管T6，所述第二开关单元422包括第六开关管T6，所述第六开关管T6的源极电连接所述第一开关单元421的第二端；所述第六开关管T6的漏极电连接所述第一恒压信号VGH；所述第六开关管T6的栅极电连接所述第N-1级扫描信号G(N-1)。
本发明一实施例中，所述电位维持单元423包括第二电容C2；其中，所述第二电容C2的第一端连接所述第二节点P(N)，所述第二电容C2的第二端 电连接所述第一恒压电源。
本发明一实施例中，请参阅图8，图8是本发明实施例提供的一种电位维持单元的第一种电路示意图，所述电位维持单元800包括第七开关管T7和第二电容C2；其中，
所述第七开关管T7的栅极电连接所述第N-2级扫描信号G(N-2)，所述第七开关管T7的源极电连接所述第一恒压信号VGH；所述第七开关管T7的漏极电连接所述第二电容C2的第一端，所述第二电容C2的第二端电连接所述第一恒压电源；所述第七开关管T7与所述第二电容C2的公共端电连接所述第二节点P(N)。
本发明一实施例中，请参阅图9，图9是本发明实施例提供的一种第一开关控制单元的电路示意图，所述第一开关控制单元900包括第八开关管T8、第九开关管T9和第三电容C3；其中，
所述第八开关管T8的源极和栅极电连接所述第二时钟信号CK2；所述第八开关管T8的漏极电连接所述第一开关单元421的第二控制端以及所述第三电容C3的第一端；所述第三电容C3的第二端电连接所述第N-2级扫描信号G(N-2)；所述第九开关管T9的源极电连接所述第八开关管T8与所述第三电容C3的公共端；所述第九开关管T9的漏极电连接所述第一恒压信号VGH；所述第九开关管T9的栅极电连接所述第N-1级扫描信号G(N-1)。
本发明一实施例中，请参阅图10，图10是本发明实施例提供的一种输出模块的电路示意图，所述输出模块1000包括第十开关管T10和第十一开关管T11；其中，
所述第十开关管T10的源极电连接所述第二时钟信号CK2，所述第十开关管T10的漏极电连接所述第十一开关管T11的源极，所述第十一开关管T11的漏极电连接所述第一恒压信号VGH；所述第十开关管T10的栅极电连接所述第一节点Q(N)；所述第十一开关管T11的栅极电连接所述第二节点P(N)；所述第十开关管T10与所述第十一开关管T11的公共端为所述第N级扫描信号G(N)的输出端。
请参阅图11，图11是本发明实施例提供的一种扫描驱动电路的电路示意图。
需要说明的是，上述图5-图11所示的开关管均为P型晶体管(栅极为低电平时源极与漏极导通)，但在本发明的其他实施例中可以用N型晶体管(栅极为高电平时源极与漏极导通)来代替图中的部分或全部晶体管，本发明对此不作限制。而且，每一晶体管源极与漏极的连接方式可以根据所选用的晶体管的类型进行确定，而在晶体管具有源极与漏极对称的结构时源极与漏极可以视为不作特别区分的两个电极，其是本领域技术人员所熟知的，在此不再赘述。
需要说明的是，开关管都为P型晶体管时的扫描驱动电路中第一时钟信号CK1、第二时钟信号CK2、第一恒压信号VGH、第二恒压信号VGL和初始扫描信号与开关管都为N型晶体管时的扫描驱动电路中对应的第一时钟信号CK1、第二时钟信号CK2、第一恒压信号VGH、第二恒压信号VGL和初始扫描信号极性相反。
下面以电路中开关管为PMOS型开关管为例，对本电路的实施方式进行具体说明：
请参阅图12，图12是针对图11所示的扫描驱动电路的电路时序图。在各个作用阶段，第一恒压信号VGH恒为高电平；第二恒压信号VGL恒为低电平，第三开关管T3恒为导通状态。
在第一作用阶段(t1)，第N-1级扫描信号G(N-1)为低电平，导通第一开关管T1T1、第六开关管T6T6以及第九开关管T9T9。
第一开关管T1、第三开关管T3导通，第N-1级扫描信号G(N-1)的低电平输入到第一节点Q(N)，下拉第一节点Q(N)的电平，导通第十开关管T10，第N级扫描线输入此时第二时钟信号CK2的高电平，第一电容C1充电。
第二时钟信号CK2为高电平，第八开关管T8截止；第一时钟信号CK1为低电平，第五开关管T5导通。由于在初始作用阶段(t0)时，第N-2级扫描信号G(N-2)为低电平，第二时钟信号CK2为低电平，第八开关管T8导通，第三电容C3放电，因此在第一作用阶段(t1)时，第N-2级扫描信号G(N-2)转变为高电平，第二时钟信号CK2为高电平，第八开关管T8截止；而且在第N-2级扫描信号G(N-2)从t0阶段的低电平转变为高电平时，由于第三电容C3的作用以及第九开关管T9的导通，第一恒压信号VGH的高电平输入到第四 开关管T4的栅极，此时第四开关管T4截止，阻止第一时钟信号CK1的高电平输入到第二节点P(N)，且避免的第四开关管T4、第五开关管T5、第六开关管T6的同时导通，引起的第二节点P(N)的分压。
第一恒压信号VGH的高电平，第七开关管T7截止；由于第六开关管T6导通，第一恒压信号VGH的高电平，输入到第二节点P(N)，第二开关管T2、第十一开关管T11截止。
在第二作用阶段(t2)，第N-1级扫描信号G(N-1)为高电平，第一开关管T1T1、第六开关管T6T6以及第九开关管T9T9都截止。第一节点Q(N)处的电平由于第一电容C1的作用维持低电平，第十开关管T10导通，第N级扫描线输入此时第二时钟信号CK2的低电平。
第二时钟信号CK2处于低电平，第八开关管T8和第四开关管T4导通，然而第一时钟信号CK1为低电平，第五开关管T5截止，第一时钟信号CK1的高电平不能输入到第二节点P(N)；第六开关管T6截止，第一恒压信号VGH也不能输入到第二节点P(N)。由于在第一作用阶段(t1)第二节点P(N)为高电平，在第二电容C2的作用下，第二节点P(N)保持低电平，第二开光、第十一开关管T11截止。
在第三作用阶段(t3)，第N-1级扫描信号G(N-1)为高电平，第一开关管T1T1、第六开关管T6T6以及第九开关管T9T9都截止。
第二时钟信号CK2处于高电平，第八开关管T8截止；由于第三电容C3在上阶段充电，第三电容C3维持第四开关管T4的栅极处于低电平，第四开关管T4导通；第一时钟信号CK1低电平，第五开关管T5导通，使得第一时钟信号CK1的低电平输入到第二节点P(N)，下拉第二节点P(N)的电平，第二开关管T2和第十一开关管T11都导通，第N级扫描线输入此时第一恒压信号VGH的高电平。
第N-2级扫描信号G(N-2)为高电平，第七开关管T7截止，第二电容C2冲电。
第二开关管T2打开，第一恒压信号VGH的高电平输入到第一节点Q(N) 处，上拉第一节点Q(N)的电平，第十开关管T10截止，第一电容C1放电。
在第四作用阶段(t4)，第N-1级扫描信号G(N-1)为高电平，第一开关管T1T1、第六开关管T6T6以及第九开关管T9T9都截止。
此时，在上阶段第二电容C2充电，维持第二节点P(N)的低电平，第二开关管T2和第十一开关管T11都导通，第N级扫描线输入此时第一恒压信号VGH的高电平。
第二开关管T2打开，第一恒压信号VGH的高电平输入到第一上拉第一节点Q(N)的电平处，第十开关管T10截止，第一电容C1放电。
第二时钟信号CK2为低电平，第八开关管T8和第四开关管T4都导通，第一时钟信号CK1为高电平，第五开关管T5截止。第N-2级扫描信号G(N-2)为高电平，第三电容C3充电。
需要说明的是，本文中的“高电平”和“低电平”分别指的是某一电路节点位置处由电平高度范围代表的两种逻辑状态。可以理解的是，具体的电平高度范围可以在具体应用场景下根据需要进行设置，本发明对此不做限制。
与之对应的，本文中的“上拉”指的是使相应的电路节点处的电平上升至高电平，本文中的“下拉”指的是使相应的电路节点处的电平下降至低电平。可以理解的是，上述“上拉”与“下拉”均可以通过电荷的定向移动实现，因此可以具体由具有相应功能的电子元器件或其组合实现，本发明对此不做限制。
基于同样的发明构思，本发明实施例提供一种阵列基板，该阵列基板包括上述任意一种的扫描驱动电路。可以理解的是，该扫描驱动电路可以设置在显示区之外，以形成GOA电路结构，并具有上述任意一种扫描驱动电路所具有的优点。
基于同样的发明构思，本发明实施例提供了一种显示装置，该显示装置包括上述任意一种的阵列基板，因而具有上述任意一种阵列基板所具有的优点。需要说明的是，本实施例中的显示装置可以为：显示器、手机、平板电脑、电视机、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
在本发明的描述中需要说明的是，术语“上”、“下”等指示的方位或位置关 系为基于附图所示的方位或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本发明中的具体含义。
应该注意的是上述实施例对本发明进行说明而不是对本发明进行限制，并且本领域技术人员在不脱离所附权利要求的范围的情况下可设计出替换实施例。在权利要求中，不应将位于括号之间的任何参考符号构造成对权利要求的限制。单词“包括”不排除存在未列在权利要求中的元件或步骤。位于元件之前的单词“一”或“一个”不排除存在多个这样的元件。本发明可以借助于包括有若干不同元件的硬件以及借助于适当编程的计算机来实现。在列举了若干装置的单元权利要求中，这些装置中的若干个可以是通过同一个硬件项来具体体现。单词第一、第二、以及第三等的使用不表示任何顺序。可将这些单词解释为名称。
以上各实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述各实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的范围，其均应涵盖在本发明的权利要求和说明书的范围当中。

Claims (11)

  1. 一种扫描驱动电路，其中，包括多级联的多个扫描驱动单元；第N级扫描驱动单元至少包括：
    第一控制模块，用于接收第N-1级扫描信号，并根据所述N-1扫描信号控制第一节点处的点位；
    第二控制模块，用于根据所述第N-1级扫描信号、第N-2级扫描信号、第一时钟信号、第二时钟信号以及第一恒压信号控制第二节点处的点位；
    输出模块，用于根据所述第一节点处的电平以及所述第二节点的电平输出第N级扫描信号；其中，
    所述第二控制模块包括第一开关单元、第二开关单元、电位维持单元以及第一开关控制单元；所述第一开关单元的第一控制端以及第一端电连接所述第一时钟信号，所述第一开关单元的第二控制端电连接所述第一开关控制单元；所述第一开关单元的第二端连接所述第二开关单元的第一端，所述第二开关单元的第二端连接所述第一恒压信号；所述第二节点连接所述第一开关单元与所述第二开关单元的公共端；
    所述电位维持单元用于维持所述第二节点的电平；
    所述第N-1级扫描信号电连接所述第二开关单元的控制端，所述第一开关控制单元用于根据所述第二时钟信号、所述第N-1级扫描信号、所述第N-2级扫描信号以及所述第一恒压信号通过所述第一开关单元的第二控制端控制所述第一开关单元，使得所述第一开关单元与第二开关单元不同时导通。
  2. 根据权利要求1所述的扫描驱动电路，其中，所述第一控制模块包括第一开关管、第二开关管和第一电容，其中，
    所述第一开关管的源极和栅极电连接所述第N-1级扫描信号；所述第一开关管的漏极电连接所述第一电容的第一端，所述第一电容的第二段电连接所述输出模块的输出端；所述第一节点为所述第一电容的第一端；所述第二开关管的源极电连接所述第一开关管的漏极，所述第二开关管的漏极电连接所述第一恒压信号；所述第三开关管的栅极电连接所述第二节点。
  3. 根据权利要求1所述的扫描驱动电路，其中，所述第一控制模块包括 第一开关管、第二开关管、第三开关管以及第一电容；其中，
    所述第一开关管的漏极电连接所述第三开关管的源极，所述第三开关管的漏极电连接所述第一电容的第一端；所述第一电容的第二段电连接所述输出模块的输出端；所述第一节点为所述第一电容的第一端；所述第三开关管的栅极电连接第二恒压信号；所述第二恒压信号控制所述第三开关管的导通；所述第二开关管的源极电连接所述第一开关管与所述第三开关管的公共端，所述第二开关管的漏极电连接所述第一恒压信号；所述第三开关管的栅极电连接所述第二节点。
  4. 根据权利要求1所述的扫描驱动电路，其中，所述第一开关单元包括第四开关管和第五开关管；其中，
    所述第一时钟信号电连接所述第四开关管的源极，所述第四开关管的漏极电连接所述第五开关管的源极；所述第五开关管的漏极电连接所述第二节点；所述第四开关管的栅极为所述第一开关管的第二控制端，电连接所述第一开关控制单元；所述第五开关管的栅极为所述第一开关管的第一控制端，电连接所述第一时钟信号。
  5. 根据权利要求1所述的扫描驱动电路，其中，所述第二开关单元包括第六开关管，所述第六开关管的源极电连接所述第一开关单元的第二端；所述第六开关管的漏极电连接所述第一恒压信号；所述第六开关管的栅极电连接所述第N-1级扫描信号。
  6. 根据权利要求1所述的方法，其中，所述电位维持单元包括第二电容；其中，所述第二电容的第一端连接所述第二节点，所述第二电容的第二端电连接所述第一恒压电源。
  7. 根据权利要求1所述的方法，其中，所述电位维持单元包括第七开关管和第二电容；其中，
    所述第七开关管的栅极电连接所述第N-2级扫描信号，所述第七开关管的源极电连接所述第一恒压信号；所述第七开关管的漏极电连接所述第二电容的第一端，所述第二电容的第二端电连接所述第一恒压电源；所述第七开关管与所述第二电容的公共端电连接所述第二节点。
  8. 根据权利要求1所述的方法，其中，所述第一开关控制单元包括第八 开关管、第九开关管和第三电容；其中，
    所述第八开关管的源极和栅极电连接所述第二时钟信号；所述第八开关管的漏极电连接所述第一开关单元的第二控制端以及所述第三电容的第一端；所述第三电容的第二端电连接所述第N-2级扫描信号；所述第九开关管的源极电连接所述第八开关管与所述第三电容的公共端；所述第九开关管的漏极电连接所述第一恒压信号；所述第九开关管的栅极电连接所述第N-1级扫描信号。
  9. 根据权利要求1所述的方法，其中，所述输出模块包括第十开关管和第十一开关管；其中，
    所述第十开关管的源极电连接所述第二时钟信号，所述第十开关管的漏极电连接所述第十一开关管的源极，所述第十一开关管的漏极电连接所述第一恒压信号；所述第十开关管的栅极电连接所述第一节点；所述第十一开关管的栅极电连接所述第二节点；所述第十开关管与所述第十一开关管的公共端为所述第N级扫描信号的输出端。
  10. 一种阵列基板，其中，所述阵列基板包括如权利要求1所述的扫描驱动电路。
  11. 一种显示面板，其中，所述显示面板包括阵列基板，所述阵列基板如权利要求1所述的扫描驱动电路。
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