WO2019019438A1 - 一种阵列基板、显示面板及该阵列基板的制备方法 - Google Patents

一种阵列基板、显示面板及该阵列基板的制备方法 Download PDF

Info

Publication number
WO2019019438A1
WO2019019438A1 PCT/CN2017/107149 CN2017107149W WO2019019438A1 WO 2019019438 A1 WO2019019438 A1 WO 2019019438A1 CN 2017107149 W CN2017107149 W CN 2017107149W WO 2019019438 A1 WO2019019438 A1 WO 2019019438A1
Authority
WO
WIPO (PCT)
Prior art keywords
passivation layer
thin film
film transistor
pixel electrode
gate line
Prior art date
Application number
PCT/CN2017/107149
Other languages
English (en)
French (fr)
Inventor
陈辰
Original Assignee
武汉华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 武汉华星光电技术有限公司 filed Critical 武汉华星光电技术有限公司
Priority to US15/744,298 priority Critical patent/US20200027899A1/en
Publication of WO2019019438A1 publication Critical patent/WO2019019438A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133371—Cells with varying thickness of the liquid crystal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1337—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
    • G02F1/133707—Structures for producing distorted electric fields, e.g. bumps, protrusions, recesses, slits in pixel electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods

Definitions

  • the present invention relates to the field of display technologies, and in particular, to an array substrate, a display panel, and a method of fabricating the array substrate.
  • the liquid crystal display panel has the advantages of low voltage, micro power consumption, large display information, easy colorization, etc., and has occupied a dominant position in the current display market, and has been widely used in electronic computers, electronic notebooks, mobile phones, video cameras, Electronic devices such as high-definition televisions.
  • the inventors of the present application found that the display screen of the existing display panel is uneven, and in some places, the screen display is brighter, and in some places, the screen display is dark.
  • the technical problem to be solved by the present invention is to provide an array substrate, a display panel, and a method for preparing the array substrate, which can improve the uniformity of the display screen.
  • a technical solution adopted by the present invention is to provide an array substrate, including: a gate line, a thin film transistor, a passivation layer, and a pixel electrode; wherein the gate line and the thin film transistor are The gate electrode is electrically connected, the pixel electrode is electrically connected to a drain of the thin film transistor, and the passivation layer is located between a layer where the thin film transistor is located and a layer where the pixel electrode is located, and extends along the gate line In the direction, the thickness of the passivation layer is gradually reduced, and the material of the passivation layer is at least one of silicon nitride and silicon oxide.
  • a display panel including an array substrate, the array substrate including: a gate line, a thin film transistor, a passivation layer, and a pixel electrode; wherein a gate line electrically connected to a gate of the thin film transistor, the pixel electrode being electrically connected to a drain of the thin film transistor, the passivation layer being located between a layer where the thin film transistor is located and a layer where the pixel electrode is located The thickness of the passivation layer gradually changes along the direction in which the gate line outputs a signal.
  • another technical solution adopted by the present invention is to provide a method for preparing an array substrate, including:
  • the gate line is electrically connected to a gate of the thin film transistor
  • the pixel electrode is electrically connected to a drain of the thin film transistor
  • the passivation layer is located at a layer where the thin film transistor is located and the pixel electrode
  • the invention has the beneficial effects that the present invention can be improved by setting the passivation layer between the layer where the thin film transistor is located and the layer where the pixel electrode is located to gradually change in thickness along the extending direction of the gate line, which is different from the prior art. Shows the uniformity of the picture.
  • FIG. 1 is a schematic plan view showing a plan view of an embodiment of an array substrate of the present invention
  • FIG. 2 is a partial cross-sectional structural view of the array substrate of FIG. 1 taken along the A-B direction;
  • FIG. 3 is a schematic structural view of an embodiment of a display panel of the present invention.
  • FIG. 4 is a schematic flow chart of an embodiment of a method for preparing an array substrate of the present invention.
  • FIG. 5 is a partial flow chart showing another embodiment of a method for preparing an array substrate of the present invention.
  • FIG. 6 is a schematic structural view of the array substrate corresponding to steps S4021 to S4024 in FIG. 5.
  • FIG. 1 is a schematic view showing a structure of a plan view of an embodiment of an array substrate of the present invention.
  • 2 is a partial cross-sectional structural view of the array substrate in FIG. 1 along the A-B direction.
  • the array substrate includes a gate line 101, a thin film transistor 102, a passivation layer 103, and a pixel electrode 104.
  • the array substrate further includes a data line 106.
  • the thin film transistor 102 includes a gate 1021, a source 1022, and a drain 1023.
  • the gate line 101 and the gate 1021 are made of the same layer of metal, the gate line 101 is electrically connected to the gate 1021, and the pixel electrode 104 is electrically connected to the drain 1023.
  • the gate line 101 inputs a scan signal to the gate 1021 to turn on the thin film transistor 102, and then the data line 106 inputs a data signal to the source 1022 and is input to the pixel electrode 104 through the drain 1023.
  • the passivation layer 103 is located between the layer where the thin film transistor 102 is located and the layer where the pixel electrode 104 is located.
  • the thickness of the passivation layer 103 gradually changes along the extending direction of the gate line 101, that is, for the passivation layer 103, at different positions. The thickness is not exactly the same.
  • the voltage drop value is also gradually changed, specifically, when the thickness of the passivation layer 103 becomes large, the voltage drop value becomes large, when When the thickness of the passivation layer 103 becomes small, the voltage drop value becomes small, that is, the thickness of the passivation layer 103 is proportional to the voltage drop value.
  • the thickness of the passivation layer 103 is gradually changed along the extending direction of the gate line 101, that is, the voltage drop value can be adjusted by adjusting the thickness of the passivation layer 103, for example, when the edge When the voltage drop value is too high and the display screen is dark, the voltage drop value can be lowered by reducing the thickness of the passivation layer 103, thereby improving the uniformity of display of the display panel.
  • the uniformity of the display screen can be improved.
  • the thickness of the passivation layer 103 gradually decreases along the extending direction of the gate line 101, that is, the distance from the input signal terminal of the gate line 101 is further.
  • the thickness of the passivation layer 103 is smaller.
  • the transmission distance of the gate line 103 increases, the signal is gradually weakened. As the transmission distance is from near to far, the voltage drop value is gradually increased, and the picture is gradually darkened. Therefore, in this application scenario In the extending direction of the gate line 101, the thickness of the passivation layer 103 is gradually decreased, and as the thickness of the passivation layer 103 is gradually decreased, the voltage drop value is gradually decreased to ensure that the picture does not follow the gate.
  • the direction in which the polar line 103 extends is darkened, improving the uniformity of the screen display.
  • the passivation layer 103 is provided with a via hole (not shown), and the pixel electrode 104 is electrically connected to the drain electrode 1023 through the via hole.
  • the material of the passivation layer 103 is at least one of silicon nitride and silicon oxide.
  • the material of the passivation layer 103 may be other organic or inorganic materials. Material.
  • the array substrate further includes a base substrate 105 having excellent optical properties, high transparency, and low reflectivity, for example, may be made of a glass material.
  • FIG. 3 is a schematic structural diagram of an embodiment of a display panel according to the present invention.
  • the display panel 300 includes an array substrate 301.
  • the array substrate 301 is an array substrate according to any of the above embodiments. No longer.
  • FIG. 4 is a schematic flow chart of an embodiment of a method for fabricating an array substrate according to the present invention.
  • the method is described in detail below with reference to FIG. 1 and FIG. 2, and the method includes:
  • the base substrate 105 has excellent optical properties, high transparency, and low reflectance, and for example, can be made of a glass material.
  • S402 sequentially forming a gate line 101, a thin film transistor 102, a passivation layer 103 and a pixel electrode 104 on the base substrate 105; wherein the gate line 101 is electrically connected to the gate 1021 of the thin film transistor 102, and the pixel electrode 104 and the film
  • the drain 1023 of the transistor 102 is electrically connected, and the passivation layer 103 is located between the layer where the thin film transistor 102 is located and the layer where the pixel electrode 104 is located, and the thickness of the passivation layer 103 gradually changes along the extending direction of the gate line 101.
  • the thickness of the passivation layer 103 is gradually changed along the extending direction of the gate line 101, that is, the voltage drop value can be adjusted by adjusting the thickness of the passivation layer 103, and when the screen display is bright, it is required.
  • the thickness of the passivation layer 101 at the position is increased to increase the voltage drop value.
  • the thickness of the passivation layer 101 at the position is reduced to lower the voltage drop value.
  • FIG. 5 is a schematic diagram of a specific process of step S402 in another embodiment of the method for fabricating the array substrate of the present invention
  • FIG. 6 is a schematic structural diagram of the array substrate corresponding to steps S4021 to S4024 in FIG. 5 .
  • step S402 specifically includes:
  • S4021 sequentially forming a gate line 101, a thin film transistor 102, a passivation layer 103, and a photoresist layer 106 on the base substrate 105, wherein the photoresist layer 106 is located on a side of the passivation layer 103 away from the thin film transistor 102, that is, light
  • the resist layer 106 covers the passivation layer 103.
  • S4022 providing a mask 107 for exposing and developing the photoresist layer 106, wherein the amount of light 108 irradiated on the photoresist layer 106 through the mask 107 is gradually changed along the extending direction of the gate line 101 so that the edge The extending direction of the gate line 101 gradually changes the thickness of the developed photoresist layer 106.
  • the light transmittance of the mask 107 may gradually change along the extending direction of the gate line 101, so that the amount of light 108 irradiated to the photoresist layer 106 through the mask 107 is gradually changed.
  • the transmittance of the mask 107 may not gradually change along the extending direction of the gate line 101, that is, the transmittance of the mask 107 is ensured to be uniform, but the illumination is changed by changing the mask.
  • the amount of light of the plate 107 is such that the amount of light 108 transmitted through the mask 107 is gradually changed.
  • the remaining photoresist layer 106 is etched, but in a corresponding time, the thinner photoresist region is preferentially etched, so that the corresponding passivation layer 103 of the region is etched, and the photoresist is thicker. Since the photoresist is not etched, the corresponding passivation layer 103 is not etched, so that the thickness of the passivation layer 103 gradually changes after the etching is completed.
  • a pixel electrode 104 is formed on a side of the passivation layer 103 away from the thin film transistor 102.
  • the pixel electrode 104 is formed on the side of the passivation layer 103 away from the thin film transistor 102, that is, the pixel electrode 104 covers the passivation layer 103.
  • the material of the pixel electrode 104 is indium tin oxide.
  • the thickness of the passivation layer 103 is gradually decreased along the extending direction of the gate line 101 to ensure that the screen does not follow the extending direction of the gate line 103. Darken to improve the uniformity of the screen display.
  • the array substrate prepared by using the method for preparing the array substrate described above is the array substrate in any of the above embodiments.
  • the structure of the specific array substrate reference may be made to the above, and details are not described herein again.

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Nonlinear Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Chemical & Material Sciences (AREA)
  • Mathematical Physics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Thin Film Transistor (AREA)

Abstract

一种阵列基板（301）、显示面板（300）及阵列基板（301）的制备方法，阵列基板（301）包括：栅极线（101）、薄膜晶体管（102）、钝化层（103）与像素电极（104）；其中，栅极线（101）与薄膜晶体管（102）的栅极（1021）电连接，像素电极（104）与薄膜晶体管（102）的漏极（1023）电连接，钝化层（103）位于薄膜晶体管（102）所在层与像素电极（104）所在层之间，沿栅极线（101）的延伸方向，钝化层（103）的厚度逐渐改变，从而能够改善画面显示的均一性。

Description

一种阵列基板、显示面板及该阵列基板的制备方法 【技术领域】
本发明涉及显示技术领域，特别是涉及一种阵列基板、显示面板及该阵列基板的制备方法。
【背景技术】
液晶显示面板具有低电压、微功耗、显示信息量大、易于彩色化等优点，在当前的显示器市场占据了主导地位，其已被广泛应用于电子计算机、电子记事本、移动电话、摄像机、高清电视机等电子设备。
在液晶显示面板显示时，每帧画面的切换都是通过栅极线扫描的方式实现的。
本申请的发明人在长期的研究中发现，现有显示面板画面显示不均匀，有的地方画面显示较亮，有的地方画面显示较暗。
【发明内容】
本发明主要解决的技术问题是提供一种阵列基板、显示面板及该阵列基板的制备方法，能够提高显示画面的均一性。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种阵列基板，包括：栅极线、薄膜晶体管、钝化层与像素电极；其中，所述栅极线与所述薄膜晶体管的栅极电连接，所述像素电极与所述薄膜晶体管的漏极电连接，所述钝化层位于所述薄膜晶体管所在层与所述像素电极所在层之间，沿所述栅极线的延伸方向，所述钝化层的厚度逐渐减小，所述钝化层的材料为氮化硅、氧化硅中的至少一种。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种显示面板，包括阵列基板，所述阵列基板包括：栅极线、薄膜晶体管、钝化层与像素电极；其中，所述栅极线与所述薄膜晶体管的栅极电连接，所述像素电极与所述薄膜晶体管的漏极电连接，所述钝化层位于所述薄膜晶体管所在层与所述像素电极所在层之间，沿所述栅极线输出信号的方向，所述钝化层的厚度逐渐改变。
为解决上述技术问题，本发明采用的又一个技术方案是：提供一种阵列基板的制备方法，包括：
提供一衬底基板；
在所述衬底基板上依次形成栅极线、薄膜晶体管、钝化层与像素电极；
其中，所述栅极线与所述薄膜晶体管的栅极电连接，所述像素电极与所述薄膜晶体管的漏极电连接，所述钝化层位于所述薄膜晶体管所在层与所述像素电极所在层之间，且沿所述栅极线的延伸方向，所述钝化层的厚度逐渐改变。
本发明的有益效果是：区别于现有技术的情况，本发明通过将薄膜晶体管所在层与像素电极所在层之间的钝化层设置为沿栅极线的延伸方向上厚度逐渐改变，能够改善显示画面的均一性。
【附图说明】
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。其中：
图1是本发明阵列基板一实施方式的俯面结构示意图；
图2是图1中阵列基板沿A-B方向的部分剖面结构示意图；
图3是本发明显示面板一实施方式的结构示意图；
图4是本发明阵列基板的制备方法一实施方式的流程示意图；
图5是本发明阵列基板的制备方法另一实施方式的部分流程示意图；
图6是图5中步骤S4021至S4024对应的阵列基板的结构示意图。
【具体实施方式】
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性的劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
参阅图1和图2，图1是本发明阵列基板一实施方式的俯面结构示意图，图 2是图1中阵列基板沿A-B方向的部分剖面结构示意图。
该阵列基板包括：栅极线101、薄膜晶体管102、钝化层103与像素电极104，可选的，该阵列基板还包括数据线106。
其中，薄膜晶体管102包括栅极1021、源极1022以及漏极1023。可选的，栅极线101与栅极1021由同一层金属制成，栅极线101与栅极1021电连接，像素电极104与漏极1023电连接。当需要显示画面时，栅极线101输入扫描信号至栅极1021以打开薄膜晶体管102，然后数据线106输入数据信号至源极1022，并经过漏极1023输入像素电极104。
钝化层103位于薄膜晶体管102所在层与像素电极104所在层之间，沿栅极线101的延伸方向，钝化层103的厚度逐渐改变，即，对于钝化层103来说，不同位置处的厚度不完全相同。由电容的计算公式：
Figure PCTCN2017107149-appb-000001
(d为极板间的距离)可知，沿栅极线101的延伸方向，当钝化层103的厚度逐渐改变时，储存电容Cs的大小也在逐渐改变，具体为：当钝化层103的厚度变大时，储存电容变小，当钝化层103的厚度变小时，储存电容变大。
又由压降公式：
Figure PCTCN2017107149-appb-000002
(ΔVp为压降值，Cs为储存电容)可知，随着储存电容的逐渐改变，压降值也在逐渐改变，具体为：当储存电容变大时，压降值变小，当储存电容变小时，压降值变大。
因此沿栅极线101的延伸方向，当钝化层103的厚度逐渐改变时，压降值也在逐渐改变，具体为：当钝化层103的厚度变大时，压降值变大，当钝化层103的厚度变小时，压降值变小，即钝化层103的厚度与压降值成正比。
因此在本实施方式中，沿着栅极线101的延伸方向，将钝化层103的厚度设置为逐渐改变，即，可以通过调节钝化层103的厚度来调节压降值，例如：当沿着栅极线101的延伸方向，当压降值过高，显示画面较暗时，可通过降低钝化层103的厚度来降低压降值，从而改善显示面板显示的均一性。
上述实施方式中，通过将薄膜晶体管102所在层与像素电极104所在层之间的钝化层103设置为沿栅极线101的延伸方向厚度逐渐改变，能够改善显示画面的均一性。
如图2所示，在上述实施方式的一个应用场景中，沿栅极线101的延伸方向，钝化层103的厚度逐渐减小，即，距离栅极线101输入信号端距离越远， 钝化层103的厚度越小。
由于现有技术中，随着栅极线103传输距离的增加，信号会逐渐受到削弱，随着传输距离的由近到远，压降值会逐渐增强，画面逐渐变暗，因此在本应用场景中，沿栅极线101的延伸方向，钝化层103的厚度逐渐减小，而随着钝化层103的厚度逐渐减小，压降值也逐渐减小，以保证画面不会随着栅极线103的延伸方向而变暗，改善画面显示的均一性。
可选的，在本实施方式中，钝化层103上设置有过孔(图未示)，像素电极104通过过孔与漏极1023电连接。
可选的，在本实施方式中，钝化层103的材料为氮化硅、氧化硅中的至少一种，当然，在其他实施方式中，钝化层103的材料也可以为其他有机物或无机物材料。
可选的，在本实施方式中，阵列基板还包括衬底基板105，衬底基板105具有优良的光学性能，较高的透明度和较低的反射率，例如，可采用玻璃材料制成。
参阅图3，图3是本发明显示面板一实施方式的结构示意图，该显示面板300包括阵列基板301，阵列基板301为上述任一项实施方式中的阵列基板，具体结构可参见上述，在此不再赘述。
参阅图4，图4是本发明阵列基板的制备方法一实施方式的流程示意图。
下面结合图1和图2对该方法进行详细的说明，该方法包括：
S401：提供一衬底基板105。
衬底基板105具有优良的光学性能，较高的透明度和较低的反射率，例如，可采用玻璃材料制成。
S402：在衬底基板105上依次形成栅极线101、薄膜晶体管102、钝化层103与像素电极104；其中，栅极线101与薄膜晶体管102的栅极1021电连接，像素电极104与薄膜晶体管102的漏极1023电连接，钝化层103位于薄膜晶体管102所在层与像素电极104所在层之间，且沿栅极线101的延伸方向，钝化层103的厚度逐渐改变。
在本实施方式中，沿栅极线101的延伸方向，将钝化层103的厚度设置为逐渐改变，即，可通过调节钝化层103的厚度调节压降值，当画面显示较亮，需要降低亮度时，增大该位置处钝化层101的厚度，提高压降值，当画面显示较暗，需要提高亮度时，减小该位置处钝化层101的厚度，降低压降值。
请参阅图5和图6，图5是本发明阵列基板的制备方式另一实施方式中步骤S402的具体流程示意图，图6是图5中步骤S4021至S4024对应的阵列基板的结构示意图。
在本实施方式中，步骤S402具体包括：
S4021：在衬底基板105上依次形成栅极线101、薄膜晶体管102、钝化层103和光阻层106，其中，光阻层106位于钝化层103远离薄膜晶体管102的一侧，即，光阻层106覆盖钝化层103。
S4022：提供一掩膜板107，对光阻层106进行曝光显影，其中，沿栅极线101的延伸方向，透过掩膜板107照射在光阻层106的光量108逐渐改变，以使沿栅极线101的延伸方向，显影后的光阻层106的厚度逐渐改变。
可选的，在本实施方式中，掩膜板107的透光率可沿栅极线101的延伸方向逐渐改变，使得透过掩膜板107照射在光阻层106的光量108逐渐改变。当然，在其他实施方式中，掩膜板107的透光率也可不沿栅极线101的延伸方向逐渐改变，即，掩膜板107的透光率保证一致，而是通过改变照射在掩膜板107的光量使得透过掩膜板107的光量108逐渐改变。
S4023：对剩余的光阻层106进行蚀刻，以去除剩余的光阻层106并蚀刻掉钝化层103的部分，从而使得钝化层103的厚度逐渐改变。
在蚀刻过程中，剩余的光阻层106会被蚀刻，但在同等时间内，光阻较薄的区域优先被蚀刻，从而该区域对应的钝化层103会被蚀刻，而光阻较厚的区域由于光阻未被蚀刻导致对应的钝化层103未被蚀刻，从而在蚀刻完成后，钝化层103的厚度逐渐改变。
S4024：在钝化层103远离薄膜晶体管102的一侧，形成像素电极104。
在钝化层103远离薄膜晶体管102的一侧形成像素电极104，即，像素电极104覆盖钝化层103，可选的，像素电极104的材料为铟锡氧化物。
可选的，在上述阵列基板的制备方法任一实施方式中，沿栅极线101的延伸方向，钝化层103的厚度逐渐减小，保证画面不会随着栅极线103的延伸方向而变暗，改善画面显示的均一性。
采用上述任一项阵列基板的制备方法制备的阵列基板为上述任一项实施方式中的阵列基板，具体的阵列基板结构可参见上述，在此不再赘述。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接 运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (13)

  1. 一种阵列基板，其中，
    包括：栅极线、薄膜晶体管、钝化层与像素电极；
    其中，所述栅极线与所述薄膜晶体管的栅极电连接，所述像素电极与所述薄膜晶体管的漏极电连接，所述钝化层位于所述薄膜晶体管所在层与所述像素电极所在层之间，沿所述栅极线的延伸方向，所述钝化层的厚度逐渐减小，所述钝化层的材料为氮化硅、氧化硅中的至少一种。
  2. 根据权利要求1所述的阵列基板，其中，
    所述钝化层上设置有过孔，所述像素电极通过所述过孔与所述薄膜晶体管的漏极电连接。
  3. 根据权利要求1所述的阵列基板，其中，
    所述像素电极的材料为铟锡氧化物。
  4. 一种显示面板，包括阵列基板，其中，
    所述阵列基板包括：栅极线、薄膜晶体管、钝化层与像素电极；
    其中，所述栅极线与所述薄膜晶体管的栅极电连接，所述像素电极与所述薄膜晶体管的漏极电连接，所述钝化层位于所述薄膜晶体管所在层与所述像素电极所在层之间，沿所述栅极线输出信号的方向，所述钝化层的厚度逐渐改变。
  5. 根据权利要求4所述的显示面板，其中，
    沿所述栅极线输出信号的方向，所述钝化层的厚度减小。
  6. 根据权利要求4所述的显示面板，其中，
    所述钝化层上设置有过孔，所述像素电极通过所述过孔与所述薄膜晶体管的漏极电连接。
  7. 根据权利要求4所述的显示面板，其中，
    所述钝化层的材料为氮化硅、氧化硅中的至少一种。
  8. 根据权利要求4所述的显示面板，其中，
    所述像素电极的材料为铟锡氧化物。
  9. 一种阵列基板的制备方法，其中，包括：
    提供一衬底基板；
    在所述衬底基板上依次形成栅极线、薄膜晶体管、钝化层与像素电极；
    其中，所述栅极线与所述薄膜晶体管的栅极电连接，所述像素电极与所述薄膜晶体管的漏极电连接，所述钝化层位于所述薄膜晶体管所在层与所述像素电极所在层之间，且沿所述栅极线的延伸方向，所述钝化层的厚度逐渐改变。
  10. 根据权利要求9所述的方法，其中，所述在所述衬底基板上依次形成栅极线、薄膜晶体管、钝化层与像素电极的步骤，包括：
    在所述衬底基板上依次形成栅极线、薄膜晶体管、钝化层和光阻层，其中，所述光阻层位于所述钝化层远离所述薄膜晶体管的一侧；
    提供一掩膜板，对所述光阻层进行曝光显影，其中，沿所述栅极线的延伸方向，透过所述掩膜板照射在所述光阻层的光量逐渐改变，以使沿所述栅极线的延伸方向，显影后的所述光阻层的厚度逐渐改变；
    对剩余的光阻层进行蚀刻，以去除剩余的光阻层并蚀刻掉所述钝化层的部分，从而使得所述钝化层的厚度逐渐改变；
    在所述钝化层远离所述薄膜晶体管的一侧，形成所述像素电极。
  11. 根据权利要求9所述的方法，其中，
    沿所述栅极线的延伸方向，所述钝化层的厚度逐渐减小。
  12. 根据权利要求9所述的方法，其中，
    所述钝化层的材料为氮化硅、氧化硅中的至少一种。
  13. 根据权利要求9所述的方法，其中，
    所述像素电极的材料为铟锡氧化物。
PCT/CN2017/107149 2017-07-25 2017-10-20 一种阵列基板、显示面板及该阵列基板的制备方法 WO2019019438A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US15/744,298 US20200027899A1 (en) 2017-07-25 2017-10-20 Array substrate, display panel and manufacturing method of the array substrate

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201710613991.4A CN107272291A (zh) 2017-07-25 2017-07-25 一种阵列基板、显示面板及该阵列基板的制备方法
CN201710613991.4 2017-07-25

Publications (1)

Publication Number Publication Date
WO2019019438A1 true WO2019019438A1 (zh) 2019-01-31

Family

ID=60079551

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/107149 WO2019019438A1 (zh) 2017-07-25 2017-10-20 一种阵列基板、显示面板及该阵列基板的制备方法

Country Status (3)

Country Link
US (1) US20200027899A1 (zh)
CN (1) CN107272291A (zh)
WO (1) WO2019019438A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108628045B (zh) * 2017-03-21 2022-01-25 京东方科技集团股份有限公司 阵列基板、显示面板和显示装置

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1904680A (zh) * 2005-07-29 2007-01-31 Nec液晶技术株式会社 面内转换模式的液晶显示器件
US20090073367A1 (en) * 2007-09-13 2009-03-19 Hwa-Sung Woo Array substrate and display panel having the same
CN102419500A (zh) * 2010-09-27 2012-04-18 三星电子株式会社 液晶显示器
CN103064224A (zh) * 2013-01-28 2013-04-24 京东方科技集团股份有限公司 阵列基板及显示装置
CN202995188U (zh) * 2012-12-28 2013-06-12 南京中电熊猫液晶显示科技有限公司 用于液晶显示器的存储电容
CN103915431A (zh) * 2013-06-17 2014-07-09 上海天马微电子有限公司 一种tft阵列基板、显示装置及阵列基板制作方法
CN105045002A (zh) * 2015-09-09 2015-11-11 深圳市华星光电技术有限公司 Psva型液晶显示面板及其制作方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6124911A (en) * 1994-07-29 2000-09-26 Kabushiki Kaisha Toshiba Reflection LCD with a counter substrate having a plurality of curved areas
JP2001075127A (ja) * 1999-09-03 2001-03-23 Matsushita Electric Ind Co Ltd アクティブマトッリクス型液晶表示素子及びその製造方法
KR20070003412A (ko) * 2005-07-01 2007-01-05 삼성전자주식회사 액정 표시 장치 및 이의 제조 방법
CN1971910B (zh) * 2005-11-22 2010-12-29 奇美电子股份有限公司 液晶显示装置、像素阵列基板及防止显示面板闪烁的方法
KR101359915B1 (ko) * 2006-09-08 2014-02-07 삼성디스플레이 주식회사 액정표시장치
JP4345811B2 (ja) * 2006-12-27 2009-10-14 セイコーエプソン株式会社 光学素子、転写型及び撮像装置
CN101004527A (zh) * 2007-01-16 2007-07-25 友达光电股份有限公司 一种液晶显示面板与主动式阵列基板
CN104102058A (zh) * 2014-07-02 2014-10-15 京东方科技集团股份有限公司 阵列基板、显示面板及显示装置

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1904680A (zh) * 2005-07-29 2007-01-31 Nec液晶技术株式会社 面内转换模式的液晶显示器件
US20090073367A1 (en) * 2007-09-13 2009-03-19 Hwa-Sung Woo Array substrate and display panel having the same
CN102419500A (zh) * 2010-09-27 2012-04-18 三星电子株式会社 液晶显示器
CN202995188U (zh) * 2012-12-28 2013-06-12 南京中电熊猫液晶显示科技有限公司 用于液晶显示器的存储电容
CN103064224A (zh) * 2013-01-28 2013-04-24 京东方科技集团股份有限公司 阵列基板及显示装置
CN103915431A (zh) * 2013-06-17 2014-07-09 上海天马微电子有限公司 一种tft阵列基板、显示装置及阵列基板制作方法
CN105045002A (zh) * 2015-09-09 2015-11-11 深圳市华星光电技术有限公司 Psva型液晶显示面板及其制作方法

Also Published As

Publication number Publication date
CN107272291A (zh) 2017-10-20
US20200027899A1 (en) 2020-01-23

Similar Documents

Publication Publication Date Title
US9823522B2 (en) COA type liquid crystal display panel and method for manufacturing the same
EP3214492B1 (en) Colour filter on array substrate and fabrication method thereof
WO2016086539A1 (zh) 液晶面板及其制作方法
TWI553837B (zh) 製作顯示面板之方法
WO2017147974A1 (zh) 阵列基板的制作方法及制得的阵列基板
WO2017101204A1 (zh) 液晶显示装置
US20180314093A1 (en) Array substrate, method of manufacturing the same and in cell touch control display panel
WO2017016014A1 (zh) Coa阵列基板及液晶面板
WO2017124673A1 (zh) 阵列基板的制作方法及液晶显示面板
WO2014190713A1 (zh) 阵列基板及其制造方法、显示装置
US20170200750A1 (en) Method for manufacturing array substrate
US9335587B2 (en) Liquid crystal cell and method for manufacturing the same
CN113359344A (zh) 阵列基板、液晶显示面板以及液晶显示装置
WO2020093442A1 (zh) 阵列基板的制作方法及阵列基板
TWI272424B (en) Liquid crystal display and fabricating the same
WO2017147973A1 (zh) 阵列基板的制作方法及制得的阵列基板
US20120025197A1 (en) Thin film transistor substrate of liquid crystal display panel
US10503034B2 (en) Manufacturing method of a TFT substrate and structure
US9477127B2 (en) Thin film transistor substrate, manufacture method thereof and liquid crystal display
WO2017143660A1 (zh) 阵列基板、显示面板以及液晶显示装置
US20180059494A1 (en) Liquid crystal display panel and manufacturing method for the same
WO2019019438A1 (zh) 一种阵列基板、显示面板及该阵列基板的制备方法
WO2019100496A1 (zh) Va型薄膜晶体管阵列基板及其制作方法
EP3547015A1 (en) Manufacturing method for coa type liquid crystal panel, and coa type liquid crystal panel
CN107479291B (zh) 液晶显示面板的制作方法及液晶显示面板

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17918910

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 17918910

Country of ref document: EP

Kind code of ref document: A1