WO2019019430A1 - 阵列基板测试电路 - Google Patents

阵列基板测试电路 Download PDF

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Publication number
WO2019019430A1
WO2019019430A1 PCT/CN2017/106869 CN2017106869W WO2019019430A1 WO 2019019430 A1 WO2019019430 A1 WO 2019019430A1 CN 2017106869 W CN2017106869 W CN 2017106869W WO 2019019430 A1 WO2019019430 A1 WO 2019019430A1
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measurement
control
signal input
input point
control signal
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PCT/CN2017/106869
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English (en)
French (fr)
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洪光辉
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武汉华星光电技术有限公司
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Priority to US15/571,004 priority Critical patent/US10497294B2/en
Publication of WO2019019430A1 publication Critical patent/WO2019019430A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays

Definitions

  • the present invention relates to the field of display technologies, and in particular, to an array substrate test circuit.
  • LCDs liquid crystal displays
  • Various consumer electronic products such as digital assistants, digital cameras, notebook computers, and desktop computers have become mainstream in display devices.
  • a liquid crystal display panel consists of a color filter substrate (CF), a thin film transistor substrate (TFT, Thin Film Transistor), a liquid crystal (LC) sandwiched between a color filter substrate and a thin film transistor substrate, and a sealant frame ( Sealant), the molding process generally includes: front array (Array) process (film, yellow, etching and stripping), middle cell (Cell) process (TFT substrate and CF substrate bonding) and rear module assembly Process (drive IC and printed circuit board is pressed).
  • Array array
  • Cell middle cell
  • rear module assembly Process drive IC and printed circuit board is pressed.
  • the front Array process mainly forms a TFT substrate to control the movement of liquid crystal molecules; the middle Cell process mainly adds liquid crystal between the TFT substrate and the CF substrate; the rear module assembly process is mainly to drive the IC to press and print the circuit.
  • the integration of the plates drives the liquid crystal molecules to rotate and display images.
  • the Array Test circuit is a circuit used to test the electrical side of the array substrate in the Array process of the liquid crystal display panel, and plays an important role in improving the yield of the product.
  • the Array Test circuit is usually located at an upper portion of the panel display area, and includes: a plurality of driving units, each of which includes: a plurality of Array Test Pads 100, and the plurality of Array test point 100 electrically coupled multiplexing circuit (DEMUX) 200, and test enable circuit 300, wherein said multiplexing circuit 200 includes: a first multiplexing module 201, and four a second multiplexing module 202; the first multiplexing module 201 includes four first thin film transistors T1, each of the second multiplexing modules 202 including six second thin film transistors T2,
  • the test enable circuit 300 includes twenty-four third thin film transistors T3; the gates of the four first thin film transistors T1 are electrically connected to the first, second, third, and fourth control signals ATC1 to ATC4, respectively.
  • the sources of the four first thin film transistors T1 are respectively connected to the data signal Data, and the drains of the four first thin film transistors T1 are electrically connected to a second multiplexing module 202;
  • the gates of the second thin film transistors T2 are electrically connected Fifth, sixth, seventh, eighth, ninth, and tenth control signals ATC5 to ATC10, said six
  • the sources of the second thin film transistors T2 are electrically connected to the drains of a first thin film transistor T1 corresponding to the second multiplexing module 202, and the drain electrical properties of the six second thin film transistors T2.
  • the gates of the twenty-four third thin film transistors T3 are connected to the test enable signal ATEN, and the sources of the twenty-four third thin film transistors T3 are electrically connected to each other.
  • the drains of the two thin film transistors T2, the drains of the twenty-four third thin film transistors T3 are electrically connected to a data line, respectively, as shown in FIG. 2, when the array is tested, the first to tenth control signals ATC1 ⁇ ATC10, test enable signal ATEN, and data signal Data are input to the corresponding thin film transistor through the corresponding array test point 100, but after the test is completed, when the panel is working normally, there is no signal input on the array test point.
  • the circuit does not work, and the first to tenth control signals ATC1 to ATC10 are in a floating state, causing each thin film transistor in the multiplexer 100 to be in a blank state, causing the panel to be in an unknown state.
  • the status causes uncertainty in the display of the panel and affects the stability of the panel display.
  • the present invention provides an array substrate test circuit comprising: at least one first multiplexing module, an enable signal input point, a plurality of measurement and control signal input points, a plurality of data lines, and a plurality of a switching element, a plurality of anti-empty switching elements, and an inverter;
  • Each of the first measurement and control switching elements corresponds to an enabling switching element, and each of the control ends of the first measuring and controlling switching element is electrically connected to a measurement and control signal input point, and the input end is connected to the data signal, and the output end is electrically connected to the corresponding one.
  • the input of the enabling switching element
  • Each of the enabling switching elements corresponds to a data line, and each of the control terminals of the enabling switching element is electrically connected to the enabling signal input point, and the output end is electrically connected to a corresponding data line;
  • Each anti-empty switching element corresponds to a measurement and control signal input point, and the control end of each anti-empty switching element is electrically connected to the output end of the inverter, and the input end is connected to the measurement and control switch off signal, and the output end is Electrically connected to a corresponding measurement and control signal input point;
  • the enable signal input point is configured to receive a high potential enable signal when the array substrate is tested, such that the enable switch element is turned on and the anti-shunt switch element is turned off, and receiving a low potential when the liquid crystal display panel is normally displayed.
  • An enable signal such that the enable switch element is turned off and the anti-slot switch element is turned on;
  • the measurement and control signal input point is configured to receive a measurement and control signal when the array substrate is tested, so that the first measurement and control switch element is turned on, and the measurement and control switch is closed when the liquid crystal display panel is normally displayed. No. such that the first measurement and control switching element is turned off.
  • the anti-slot switching element is a thin film transistor
  • the gate of the thin film transistor is a control end of the anti-slot switching element
  • the source is an input end of the anti-empty switching element
  • the drain is the anti-empty switch The output of the component.
  • the anti-slot switching element is a transmission gate, the high-potential control end of the transmission gate is a control end of the anti-slot switching element, the input end is an input end of the anti-snull switching element, and the output end is a
  • the output terminal of the anti-empty switching element is electrically connected to the enable signal input point of the low potential control terminal of the transmission gate.
  • the plurality of measurement and control signal input points include: a first measurement and control signal input point, a second measurement and control signal input point, a third measurement and control signal input point, a fourth measurement and control signal input point, a fifth measurement and control signal input point, and a sixth measurement and control signal input. point;
  • the number of the first multiplexing modules is four, and each of the first multiplexing modules includes six first measurement and control switching elements, and six measurement and control switching elements in the same first multiplexing module.
  • the control end respectively accesses the first measurement and control signal input point, the second measurement and control signal input point, the third measurement and control signal input point, the fourth measurement and control signal input point, the fifth measurement and control signal input point, and the sixth measurement and control signal input point.
  • the array substrate test circuit further includes: a second multiplexing module, a seventh measurement and control signal input point, an eighth measurement and control signal input point, a ninth measurement and control signal input point, and a tenth measurement and control signal input point, wherein the a multiplexing module acquiring a data signal from the second multiplexing module;
  • the second multiplexing module includes: four second measurement and control switching elements, each of the second measurement and control switching elements corresponding to a first multiplexing module, and the output ends of each of the second measurement and control switching elements are corresponding thereto
  • the input ends of the first measurement and control switching elements of the first multiplexing control module are electrically connected; the control ends of the four second measurement and control switching elements are electrically connected to the seventh measurement and control signal input point and the eighth measurement and control signal input respectively
  • the point, the ninth measurement and control signal input point, and the tenth measurement and control signal input point, the input ends of the four second measurement and control switching elements are all connected to the data signal.
  • the array substrate test circuit further includes: a data signal input point for providing a data signal to the second multiplexing module.
  • the enable switch element is a thin film transistor, the gate of the thin film transistor is a control end of the enable switch element, the source is an input end of the enable switch element, and the drain is an output end of the enable switch element .
  • the first measurement and control switching element is a thin film transistor
  • the gate of the thin film transistor is a control end of the first measurement and control switching element
  • the source is an input end of the first measurement and control switching element
  • the drain is the first measurement and control switch The output of the component.
  • the invention also provides an array substrate testing circuit comprising: at least one first multiplexing a module, an enable signal input point, a plurality of measurement and control signal input points, a plurality of data lines, a plurality of enable switching elements, a plurality of anti-slot switching elements, and an inverter;
  • Each of the first multiplexing modules includes: a plurality of first measurement and control switching elements
  • Each of the first measurement and control switching elements corresponds to an enabling switching element, and each of the control ends of the first measuring and controlling switching element is electrically connected to a measurement and control signal input point, and the input end is connected to the data signal, and the output end is electrically connected to the corresponding one.
  • the input of the enabling switching element
  • Each of the enabling switching elements corresponds to a data line, and each of the control terminals of the enabling switching element is electrically connected to the enabling signal input point, and the output end is electrically connected to a corresponding data line;
  • Each anti-empty switching element corresponds to a measurement and control signal input point, and the control end of each anti-empty switching element is electrically connected to the output end of the inverter, and the input end is connected to the measurement and control switch off signal, and the output end is Electrically connected to a corresponding measurement and control signal input point;
  • the enable signal input point is configured to receive a high potential enable signal when the array substrate is tested, such that the enable switch element is turned on and the anti-shunt switch element is turned off, and receiving a low potential when the liquid crystal display panel is normally displayed.
  • An enable signal such that the enable switch element is turned off and the anti-slot switch element is turned on;
  • the measurement and control signal input point is configured to receive the measurement and control signal when the array substrate is tested, so that the first measurement and control switch element is turned on, and the measurement and control switch off signal is received when the liquid crystal display panel is normally displayed, so that the first measurement and control switch element is turned off;
  • the plurality of measurement and control signal input points include: a first measurement and control signal input point, a second measurement and control signal input point, a third measurement and control signal input point, a fourth measurement and control signal input point, a fifth measurement and control signal input point, and a sixth measurement and control Signal input point;
  • the number of the first multiplexing modules is four, and each of the first multiplexing modules includes six first measurement and control switching elements, and six measurement and control switching elements in the same first multiplexing module.
  • the control end respectively accesses the first measurement and control signal input point, the second measurement and control signal input point, the third measurement and control signal input point, the fourth measurement and control signal input point, the fifth measurement and control signal input point, and the sixth measurement and control signal input point;
  • the method further includes: a second multiplexing module, a seventh measurement and control signal input point, an eighth measurement and control signal input point, a ninth measurement and control signal input point, and a tenth measurement and control signal input point, the first multiplexing module Acquiring a data signal from the second multiplexing module;
  • the second multiplexing module includes: four second measurement and control switching elements, each of the second measurement and control switching elements corresponding to a first multiplexing module, and the output ends of each of the second measurement and control switching elements are corresponding thereto
  • the input ends of the first measurement and control switching elements of the first multiplexing control module are electrically connected;
  • the control ends of the four second measurement and control switching elements are electrically connected to the seventh measurement and control signal input point and the eighth measurement and control signal input respectively Point, ninth measurement and control signal input point, tenth measurement and control signal input Point, the input ends of the four second measurement and control switching elements are all connected to the data signal;
  • the method further includes: a data signal input point, wherein the data signal input point is used to provide a data signal to the second multiplexing module;
  • the enabling switching element is a thin film transistor
  • a gate of the thin film transistor is a control end of the enabling switching element
  • a source is an input end of the enabling switching element
  • a drain is the enabling switching element Output.
  • the present invention provides an array substrate test circuit including: at least one first multiplexing module, an enable signal input point, a plurality of measurement and control signal input points, a plurality of data lines, and a plurality of The switch element, the plurality of anti-empty switch elements, and an inverter; the control end of each of the first measurement and control switch elements is electrically connected to a measurement and control signal input point, the input end is connected to the data signal, and the output end is electrically connected The input terminal of the corresponding one of the enable switch elements; the control end of each of the enable switch elements is electrically connected to the enable signal input point, and the output end is electrically connected to a corresponding data line; each of the protection The control end of the empty switching element is electrically connected to the output end of the inverter, and the input end is connected to the measurement and control switch closing signal, and the output end is electrically connected to a corresponding measurement and control signal input point; through the liquid crystal display panel Opening the anti-empty switching element, inputting
  • 1 is a circuit diagram of a conventional array substrate test circuit
  • FIG. 2 is a schematic view of an array test point of a conventional array substrate test circuit
  • FIG. 3 is a circuit diagram of a first embodiment of an array substrate test circuit of the present invention.
  • FIG 4 is a partially enlarged view of the anti-vacancy switching element in the second embodiment of the array substrate test circuit of the present invention.
  • the present invention provides an array substrate testing circuit, including: at least one first Multiplex module 1, an enable signal input point 2, a plurality of measurement and control signal input points 3, a plurality of data lines 4, a plurality of enable switching elements 5, a plurality of anti-empty switching elements 6, and an inversion 7
  • Each of the first measurement and control switching elements 11 corresponds to an enabling switching element 5, and the control terminals of each of the first measurement and control switching elements 11 are electrically connected to a measurement and control signal input point 3, and the input terminals are all connected to the data signal Data, and the output ends are respectively connected. Electrically connecting the input end of the corresponding enable switching element 5;
  • Each of the enabling switching elements 5 corresponds to a data line 4, each of the control terminals of the enabling switching element 5 is electrically connected to the enable signal input point 2, and the output terminals are electrically connected to a corresponding data line 4;
  • Each of the anti-empty switching elements 6 corresponds to a measurement and control signal input point 3, and the control end of each of the anti-empty switching elements 6 is electrically connected to the output end of the inverter 7, and the input end is connected to the measurement and control switch to close the signal.
  • VGL the output terminal is electrically connected to a corresponding measurement and control signal input point 3;
  • the enable signal input point 2 is configured to receive a high potential enable signal ATEN during the array substrate test, such that the enable switch element 5 is turned on and the anti-slot switch element 6 is turned off, and the liquid crystal display panel is normally displayed. Receiving a low potential enable signal ATEN such that the enable switching element 5 is turned off and the anti-slot switching element 6 is turned on;
  • the measurement and control signal input point 3 is configured to receive the measurement and control signal ATC when the array substrate is tested, so that the first measurement and control switching element 11 is turned on, and the measurement and control switch off signal VGL is received when the liquid crystal display panel is normally displayed, so that the first measurement and control The switching element 11 is turned off.
  • the anti-slot switching element 6 is a thin film transistor, and the gate of the thin film transistor is a control end of the anti-slot switching element 6,
  • the source is the input terminal of the anti-slot switching element 6, and the drain is the output terminal of the anti-slot switching element 6.
  • the anti-slot switching element 6 is a transmission gate, and the high potential control end of the transmission gate is the anti-slot switching element 6. a control terminal, the input end is an input end of the anti-slot switching element 6, the output end is an output end of the anti-slot switching element 6, and the low potential control end of the transmission gate is electrically connected to the enable signal Enter point 2.
  • the potential of the low potential enable signal ATEN is -7V
  • the potential of the measurement switch off signal VGL is -7V.
  • the plurality of measurement and control signal input points 3 may be selected to include: a first measurement and control signal input point 31, a second measurement and control signal input point 32, a third measurement and control signal input point 33, and a fourth measurement and control Signal input point 34, fifth measurement and control signal input point 35, sixth measurement and control signal input point 36;
  • the number of the first multiplexing modules 1 is four, and each of the first multiplexing modules 1 includes six first measurement and control switching elements 11 and six in the same first multiplexing module 1. Test The control end of the control switching element 11 is respectively connected to the first measurement and control signal input point 31, the second measurement and control signal input point 32, the third measurement and control signal input point 33, the fourth measurement and control signal input point 34, the fifth measurement and control signal input point 35, The sixth measurement and control signal is input to point 36.
  • the array substrate test circuit may further include: a second multiplexing module 8, a seventh measurement and control signal input point 37, an eighth measurement and control signal input point 38, and a ninth The measurement and control signal input point 39 and the tenth measurement and control signal input point 310, the first multiplexing module 1 acquires the data signal Data from the second multiplexing module 8.
  • the second multiplexing module 8 includes four second measurement and control switching elements 81, and each of the second measurement and control switching elements 81 corresponds to a first multiplexing module 1, and the output of each of the second measurement and control switching elements 81
  • the terminals are electrically connected to the input ends of the first measurement and control switching elements 11 of the corresponding first multiplexing module 1; the control terminals of the four second measurement and control switching elements 81 are electrically connected to the seventh measurement and control signals respectively.
  • the input point 37, the eighth measurement and control signal input point 38, the ninth measurement and control signal input point 39, and the tenth measurement and control signal input point 310, and the input ends of the four second measurement and control switching elements 81 are all connected to the data signal.
  • the array substrate test circuit may further include: a data signal input point 9 for providing a data signal to the second multiplexing module 8 .
  • the enabling switching element 5 is a thin film transistor
  • the gate of the thin film transistor is a control end of the enabling switching element 5
  • the source is the input end of the enabling switching element 5
  • the drain is the The output of the switching element 5 can be switched.
  • the first measurement and control switching element 11 is a thin film transistor
  • the gate of the thin film transistor is a control end of the first measurement and control switching element 11
  • the source is an input end of the first measurement and control switching element 11
  • the drain is the The output of the switching element 11 is measured and controlled.
  • the working process of the array substrate testing circuit of the present invention includes: performing array substrate testing, and each of the measurement and control signal input points 3 respectively receives different measurement and control signals ATC, so that the first measurement and control switching element 11 and the second measurement and control switch
  • the element 81 is turned on, the data signal Data is output from the multiplexing module, the enable signal input point 2 receives a high potential enable signal ATEN, and the enable switch element 5 is turned on, the data
  • the signal Data is written into the data line 4 for the array substrate test, and the high potential enable signal ATEN is turned to a low potential after being inverted, the anti-shunt switching element 6 is turned off, and the measurement and control switch off signal VGL cannot be written into the measurement and control.
  • the signal input point 3 avoids the influence on the array substrate test. After the array substrate test is finished, the liquid crystal display panel is normally displayed, and the respective measurement and control signal input points 3 no longer receive the measurement and control signal ATC, and the enable signal input point 2 receives the low potential.
  • the enable signal ATEN, the enable switching element 5 is turned off, and the low potential enable signal ATEN is turned to a high potential after being inverted.
  • Set The empty switching element 6 is turned on, and the measurement and control switch off signal VGL is written into the measurement and control signal input point 3, so that the first measurement and control switching element 11 and the second measurement and control switching element 81 are both turned off, compared with the prior art liquid crystal display panel.
  • the array substrate testing circuit of the present invention can ensure that the switching element in the multiplexer is normally turned off in the liquid crystal display panel when the liquid crystal display panel is normally displayed. To improve the working stability of the liquid crystal display panel.
  • the present invention provides an array substrate test circuit, including: at least one first multiplexing module, one enable signal input point, multiple measurement and control signal input points, multiple data lines, and multiple enable a switching element, a plurality of anti-empty switching elements, and an inverter; each of the control ends of the first measurement and control switching element is electrically connected to a measurement and control signal input point, the input end is connected to the data signal, and the output end is electrically connected An input end of an enable switch element corresponding thereto is connected; a control end of each enable switch element is electrically connected to an enable signal input point, and the output end is electrically connected to a corresponding data line; each anti-empty The control end of the switching element is electrically connected to the output end of the inverter, and the input end is connected to the measurement and control switch closing signal, and the output end is electrically connected to a corresponding measurement and control signal input point; when displayed on the liquid crystal display panel Turning on the anti-empty switching component, inputting the measurement and control switch off signal into the

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Abstract

一种阵列基板测试电路，包括：至少一个第一多路复用模块（1）、一使能信号输入点（2）、多个测控信号输入点（3）、多条数据线（4）、多个使能开关元件（5）、多个防置空开关元件（6）、以及一反相器（7）；每一个防置空开关元件（6）的控制端均接入反相后的使能信号（ATEN），输入端均接入测控开关关闭信号（VGL），输出端电性连接与其对应的一个测控信号输入点（3）；能够在液晶显示面板显示时打开防置空开关元件（6），将测控开关关闭信号（VGL）输入测控信号输入点（3），以保证多路复用模块（1，8）中的开关元件（11，81）在液晶显示面板正常显示保持关闭状态，避免多路复用模块（1，8）中的开关元件（11，81）处于置空状态，提升液晶显示面板的工作稳定性。

Description

阵列基板测试电路 技术领域
本发明涉及显示技术领域，尤其涉及一种阵列基板测试电路。
背景技术
随着显示技术的发展，液晶显示器(Liquid Crystal Display，LCD)等平面显示装置因具有高画质、省电、机身薄及应用范围广等优点，而被广泛的应用于手机、电视、个人数字助理、数字相机、笔记本电脑、台式计算机等各种消费性电子产品，成为显示装置中的主流。
通常液晶显示面板由彩膜基板(CF，Color Filter)、薄膜晶体管基板(TFT，Thin Film Transistor)、夹于彩膜基板与薄膜晶体管基板之间的液晶(LC，Liquid Crystal)及密封胶框(Sealant)组成，其成型工艺一般包括：前段阵列(Array)制程(薄膜、黄光、蚀刻及剥膜)、中段成盒(Cell)制程(TFT基板与CF基板贴合)及后段模组组装制程(驱动IC与印刷电路板压合)。其中，前段Array制程主要是形成TFT基板，以便于控制液晶分子的运动；中段Cell制程主要是在TFT基板与CF基板之间添加液晶；后段模组组装制程主要是驱动IC压合与印刷电路板的整合，进而驱动液晶分子转动，显示图像。
阵列基板测试(Array Test)电路，是用于液晶显示面板Array制程中用来测试阵列基板侧电性情况的电路，对于产品良率的提升具有很重要的作用。如图1及图2所示，Array Test电路通常位于面板显示区的上部，包括：多个驱动单元，每一个驱动单元均包括：多个阵列测试点(Array Test pad)100、与所述多个阵列测试点100电性连接的多路复用电路(DEMUX)200、以及测试使能电路300，其中所述多路复用电路200包括：一个第一多路复用模块201、以及四个第二多路复用模块202；所述第一多路复用模块201包括四个第一薄膜晶体管T1，所述每一个第二多路复用模块202包括六个第二薄膜晶体管T2，所述测试使能电路300包括二十四个第三薄膜晶体管T3；所述四个第一薄膜晶体管T1的栅极分别电性连接第一、第二、第三、及第四控制信号ATC1～ATC4，所述四个第一薄膜晶体管T1的源极均接入数据信号Data，所述四个第一薄膜晶体管T1的漏极分别对应电性连接一个第二多路复用模块202；所述六个第二薄膜晶体管T2的栅极分别电性连接第五、第六、第七、第八、第九、及第十控制信号ATC5～ATC10，所述六 个第二薄膜晶体管T2的源极均电性连接其所在的第二多路复用模块202对应的一个第一薄膜晶体管T1的漏极，所述六个第二薄膜晶体管T2的漏极电性连接测试使能电路300，所述二十四个第三薄膜晶体管T3的栅极均接入测试使能信号ATEN，所述二十四个第三薄膜晶体管T3的源极分别电性连接一个第二薄膜晶体管T2的漏极，所述二十四个第三薄膜晶体管T3的漏极分别电性连接一条数据线，如图2所示，阵列测试时，所述第一至第十控制信号ATC1～ATC10、测试使能信号ATEN、及数据信号Data均通过对应的阵列测试点100输入到相应到薄膜晶体管中，但是测试完成之后，在面板正常工作时，阵列测试点上不再有信号输入，电路不工作，第一至第十控制信号ATC1～ATC10处于置空(Floating)状态，导致所述多路复用器100中的各个薄膜晶体管也处于置空的状态，导致面板处于一种未知的状态，对面板的显示造成不确定性，影响面板显示的稳定性。
发明内容
本发明的目的在于提供一种阵列基板测试电路，能够保证多路复用器中的开关元件在液晶显示面板正常显示保持关闭状态，避免多路复用器中的开关元件处于置空状态，提升液晶显示面板的工作稳定性。
为实现上述目的，本发明提供了一种阵列基板测试电路，包括：至少一个第一多路复用模块、一使能信号输入点、多个测控信号输入点、多条数据线、多个使能开关元件、多个防置空开关元件、以及一反相器；
每一个第一测控开关元件对应一个使能开关元件，每一个第一测控开关元件的控制端均电性连接一个测控信号输入点，输入端均接入数据信号，输出端均电性连接与其对应的使能开关元件的输入端；
每一个使能开关元件对应一条数据线，每一个使能开关元件的控制端均电性连接使能信号输入点，输出端均电性连接与其对应的一数据线；
每一个防置空开关元件对应一个测控信号输入点，每一个防置空开关元件的控制端均电性连接所述反相器的输出端，输入端均接入测控开关关闭信号，输出端均电性连接与其对应的一个测控信号输入点；
所述使能信号输入点用于在阵列基板测试时接收高电位的使能信号，使得所述使能开关元件打开且所述防置空开关元件关闭，在液晶显示面板正常显示时接收低电位的使能信号，使得所述使能开关元件关闭且所述防置空开关元件打开；
所述测控信号输入点用于在阵列基板测试时接收测控信号，使得所述第一测控开关元件打开，在液晶显示面板正常显示时接收测控开关关闭信 号，使得所述第一测控开关元件关闭。
所述防置空开关元件为薄膜晶体管，所述薄膜晶体管的栅极为所述防置空开关元件的控制端，源极为所述防置空开关元件的输入端，漏极为所述防置空开关元件的输出端。
所述防置空开关元件为传输门，所述传输门的高电位控制端为所述防置空开关元件的控制端，输入端为所述防置空开关元件的输入端，输出端为所述防置空开关元件的输出端，所述传输门的低电位控制端电性连接所述使能信号输入点。
所述多个测控信号输入点包括：第一测控信号输入点、第二测控信号输入点、第三测控信号输入点、第四测控信号输入点、第五测控信号输入点、第六测控信号输入点；
所述第一多路复用模块的数量为四个，每一个第一多路复用模块均包括六个第一测控开关元件，同一个第一多路复用模块中的六个测控开关元件的控制端分别接入第一测控信号输入点、第二测控信号输入点、第三测控信号输入点、第四测控信号输入点、第五测控信号输入点、第六测控信号输入点。
所述阵列基板测试电路还包括：一第二多路复用模块、第七测控信号输入点、第八测控信号输入点、第九测控信号输入点、及第十测控信号输入点，所述第一多路复用模块从第二多路复用模块获取数据信号；
所述第二多路复用模块包括：四个第二测控开关元件，每一个第二测控开关元件对应一个第一多路复用模块，每一个第二测控开关元件的输出端均与其对应的第一多路复用模块中的各个第一测控开关元件的输入端电性连接；所述四个第二测控开关元件的控制端分别电性连接第七测控信号输入点、第八测控信号输入点、第九测控信号输入点、第十测控信号输入点，所述四个第二测控开关元件的输入端均接入数据信号。
所述阵列基板测试电路还包括：一数据信号输入点，所述数据信号输入点用于向所述第二多路复用模块提供数据信号。
所述使能开关元件为薄膜晶体管，所述薄膜晶体管的栅极为所述使能开关元件的控制端，源极为所述使能开关元件的输入端，漏极为所述使能开关元件的输出端。
所述第一测控开关元件为薄膜晶体管，所述薄膜晶体管的栅极为所述第一测控开关元件的控制端，源极为所述第一测控开关元件的输入端，漏极为所述第一测控开关元件的输出端。
本发明还提供一种阵列基板测试电路，包括：至少一个第一多路复用 模块、一使能信号输入点、多个测控信号输入点、多条数据线、多个使能开关元件、多个防置空开关元件、以及一反相器；
每一个第一多路复用模块均包括：多个第一测控开关元件；
每一个第一测控开关元件对应一个使能开关元件，每一个第一测控开关元件的控制端均电性连接一个测控信号输入点，输入端均接入数据信号，输出端均电性连接与其对应的使能开关元件的输入端；
每一个使能开关元件对应一条数据线，每一个使能开关元件的控制端均电性连接使能信号输入点，输出端均电性连接与其对应的一数据线；
每一个防置空开关元件对应一个测控信号输入点，每一个防置空开关元件的控制端均电性连接所述反相器的输出端，输入端均接入测控开关关闭信号，输出端均电性连接与其对应的一个测控信号输入点；
所述使能信号输入点用于在阵列基板测试时接收高电位的使能信号，使得所述使能开关元件打开且所述防置空开关元件关闭，在液晶显示面板正常显示时接收低电位的使能信号，使得所述使能开关元件关闭且所述防置空开关元件打开；
所述测控信号输入点用于在阵列基板测试时接收测控信号，使得所述第一测控开关元件打开，在液晶显示面板正常显示时接收测控开关关闭信号，使得所述第一测控开关元件关闭；
其中，所述多个测控信号输入点包括：第一测控信号输入点、第二测控信号输入点、第三测控信号输入点、第四测控信号输入点、第五测控信号输入点、第六测控信号输入点；
所述第一多路复用模块的数量为四个，每一个第一多路复用模块均包括六个第一测控开关元件，同一个第一多路复用模块中的六个测控开关元件的控制端分别接入第一测控信号输入点、第二测控信号输入点、第三测控信号输入点、第四测控信号输入点、第五测控信号输入点、第六测控信号输入点；
还包括：一第二多路复用模块、第七测控信号输入点、第八测控信号输入点、第九测控信号输入点、及第十测控信号输入点，所述第一多路复用模块从第二多路复用模块获取数据信号；
所述第二多路复用模块包括：四个第二测控开关元件，每一个第二测控开关元件对应一个第一多路复用模块，每一个第二测控开关元件的输出端均与其对应的第一多路复用模块中的各个第一测控开关元件的输入端电性连接；所述四个第二测控开关元件的控制端分别电性连接第七测控信号输入点、第八测控信号输入点、第九测控信号输入点、第十测控信号输入 点，所述四个第二测控开关元件的输入端均接入数据信号；
还包括：一数据信号输入点，所述数据信号输入点用于向所述第二多路复用模块提供数据信号；
其中，所述使能开关元件为薄膜晶体管，所述薄膜晶体管的栅极为所述使能开关元件的控制端，源极为所述使能开关元件的输入端，漏极为所述使能开关元件的输出端。
本发明的有益效果：本发明提供一种阵列基板测试电路，包括：至少一个第一多路复用模块、一使能信号输入点、多个测控信号输入点、多条数据线、多个使能开关元件、多个防置空开关元件、以及一反相器；每一个第一测控开关元件的控制端均电性连接一个测控信号输入点，输入端均接入数据信号，输出端均电性连接与其对应的一使能开关元件的输入端；每一个使能开关元件的控制端均电性连接使能信号输入点，输出端均电性连接与其对应的一数据线；每一个防置空开关元件的控制端均电性连接所述反相器的输出端，输入端均接入测控开关关闭信号，输出端均电性连接与其对应的一个测控信号输入点；通过在液晶显示面板显示时打开所述防置空开关元件，将所述测控开关关闭信号输入测控信号输入点，可保证多路复用器中的开关元件在液晶显示面板正常显示保持关闭状态，避免多路复用器中的开关元件处于置空状态，提升液晶显示面板的工作稳定性。
附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为现有的阵列基板测试电路的电路图；
图2为现有的阵列基板测试电路的阵列测试点处的示意图；
图3为本发明的阵列基板测试电路的第一实施例的电路图；
图4为本发明的阵列基板测试电路的第二实施例中防置空开关元件处的局部放大图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图3，本发明提供一种阵列基板测试电路，包括：至少一个第一 多路复用模块1、一使能信号输入点2、多个测控信号输入点3、多条数据线4、多个使能开关元件5、多个防置空开关元件6、以及一反相器7；
每一个第一测控开关元件11对应一个使能开关元件5，每一个第一测控开关元件11的控制端均电性连接一个测控信号输入点3，输入端均接入数据信号Data，输出端均电性连接与其对应的使能开关元件5的输入端；
每一个使能开关元件5对应一条数据线4，每一个使能开关元件5的控制端均电性连接使能信号输入点2，输出端均电性连接与其对应的一数据线4；
每一个防置空开关元件6对应一个测控信号输入点3，每一个防置空开关元件6的控制端均电性连接所述反相器7的输出端，输入端均接入测控开关关闭信号VGL，输出端均电性连接与其对应的一个测控信号输入点3；
所述使能信号输入点2用于在阵列基板测试时接收高电位的使能信号ATEN，使得所述使能开关元件5打开且所述防置空开关元件6关闭，在液晶显示面板正常显示时接收低电位的使能信号ATEN，使得所述使能开关元件5关闭且所述防置空开关元件6打开；
所述测控信号输入点3用于在阵列基板测试时接收测控信号ATC，使得所述第一测控开关元件11打开，在液晶显示面板正常显示时接收测控开关关闭信号VGL，使得所述第一测控开关元件11关闭。
具体地，如图3所示，在本发明的第一实施例中，所述防置空开关元件6为薄膜晶体管，所述薄膜晶体管的栅极为所述防置空开关元件6的控制端，源极为所述防置空开关元件6的输入端，漏极为所述防置空开关元件6的输出端。
具体地，如图4所示，在本发明的第二实施例中，所述防置空开关元件6为传输门，所述传输门的高电位控制端为所述防置空开关元件6的控制端，输入端为所述防置空开关元件6的输入端，输出端为所述防置空开关元件6的输出端，所述传输门的低电位控制端电性连接所述使能信号输入点2。
优选地，所述低电位的使能信号ATEN的电位为-7V，所述测控开关关闭信号VGL的电位为-7V。
具体实施时，如图3所示，可选择所述多个测控信号输入点3包括：第一测控信号输入点31、第二测控信号输入点32、第三测控信号输入点33、第四测控信号输入点34、第五测控信号输入点35、第六测控信号输入点36；
所述第一多路复用模块1的数量为四个，每一个第一多路复用模块1均包括六个第一测控开关元件11，同一个第一多路复用模块1中的六个测 控开关元件11的控制端分别接入第一测控信号输入点31、第二测控信号输入点32、第三测控信号输入点33、第四测控信号输入点34、第五测控信号输入点35、第六测控信号输入点36。
具体实施时，如图3所示，所述阵列基板测试电路还可以进一步的包括：一第二多路复用模块8、第七测控信号输入点37、第八测控信号输入点38、第九测控信号输入点39、及第十测控信号输入点310，所述第一多路复用模块1从第二多路复用模块8获取数据信号Data。
所述第二多路复用模块8包括：四个第二测控开关元件81，每一个第二测控开关元件81对应一个第一多路复用模块1，每一个第二测控开关元件81的输出端均与其对应的第一多路复用模块1中的各个第一测控开关元件11的输入端电性连接；所述四个第二测控开关元件81的控制端分别电性连接第七测控信号输入点37、第八测控信号输入点38、第九测控信号输入点39、第十测控信号输入点310，所述四个第二测控开关元件81的输入端均接入数据信号。
具体地，上述的实施方案中，所述阵列基板测试电路还可以包括：一数据信号输入点9，所述数据信号输入点9用于向所述第二多路复用模块8提供数据信号Data。
优选地，所述使能开关元件5为薄膜晶体管，所述薄膜晶体管的栅极为所述使能开关元件5的控制端，源极为所述使能开关元件5的输入端，漏极为所述使能开关元件5的输出端。所述第一测控开关元件11为薄膜晶体管，所述薄膜晶体管的栅极为所述第一测控开关元件11的控制端，源极为所述第一测控开关元件11的输入端，漏极为所述第一测控开关元件11的输出端。
需要说明的是，本发明的阵列基板测试电路的工作过程包括：进行阵列基板测试，各个测控信号输入点3分别接收不同的测控信号ATC，使得所述第一测控开关元件11和第二测控开关元件81打开，所述数据信号Data从所述多路复用模块中输出，所述使能信号输入点2接收高电位的使能信号ATEN，所述使能开关元件5均打开，所述数据信号Data写入数据线4进行阵列基板测试，同时高电位的使能信号ATEN经过反相后变为低电位，所述防置空开关元件6关闭，所述测控开关关闭信号VGL无法写入测控信号输入点3，避免对阵列基板测试造成影响，阵列基板测试结束后，液晶显示面板正常显示，各个测控信号输入点3分别不再接收测控信号ATC，所述使能信号输入点2接收低电位的使能信号ATEN，所述使能开关元件5均关闭，同时低电位的使能信号ATEN经过反相后变为高电位，所述防置 空开关元件6打开，所述测控开关关闭信号VGL写入测控信号输入点3，使得所述第一测控开关元件11和第二测控开关元件81均关闭，相比现有技术液晶显示面板正常显示时多路复用器中的开关元件处于置空状态，本发明的阵列基板测试电路能够保证液晶显示面板正常显示时，多路复用器中的开关元件在液晶显示面板正常显示保持关闭状态，以提升液晶显示面板的工作稳定性。
综上所述，本发明提供一种阵列基板测试电路，包括：至少一个第一多路复用模块、一使能信号输入点、多个测控信号输入点、多条数据线、多个使能开关元件、多个防置空开关元件、以及一反相器；每一个第一测控开关元件的控制端均电性连接一个测控信号输入点，输入端均接入数据信号，输出端均电性连接与其对应的一使能开关元件的输入端；每一个使能开关元件的控制端均电性连接使能信号输入点，输出端均电性连接与其对应的一数据线；每一个防置空开关元件的控制端均电性连接所述反相器的输出端，输入端均接入测控开关关闭信号，输出端均电性连接与其对应的一个测控信号输入点；通过在液晶显示面板显示时打开所述防置空开关元件，将所述测控开关关闭信号输入测控信号输入点，可保证多路复用器中的开关元件在液晶显示面板正常显示保持关闭状态，避免多路复用器中的开关元件处于置空状态，提升液晶显示面板的工作稳定性。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (12)

  1. 一种阵列基板测试电路，包括：至少一个第一多路复用模块、一使能信号输入点、多个测控信号输入点、多条数据线、多个使能开关元件、多个防置空开关元件、以及一反相器；
    每一个第一多路复用模块均包括：多个第一测控开关元件；
    每一个第一测控开关元件对应一个使能开关元件，每一个第一测控开关元件的控制端均电性连接一个测控信号输入点，输入端均接入数据信号，输出端均电性连接与其对应的使能开关元件的输入端；
    每一个使能开关元件对应一条数据线，每一个使能开关元件的控制端均电性连接使能信号输入点，输出端均电性连接与其对应的一数据线；
    每一个防置空开关元件对应一个测控信号输入点，每一个防置空开关元件的控制端均电性连接所述反相器的输出端，输入端均接入测控开关关闭信号，输出端均电性连接与其对应的一个测控信号输入点；
    所述使能信号输入点用于在阵列基板测试时接收高电位的使能信号，使得所述使能开关元件打开且所述防置空开关元件关闭，在液晶显示面板正常显示时接收低电位的使能信号，使得所述使能开关元件关闭且所述防置空开关元件打开；
    所述测控信号输入点用于在阵列基板测试时接收测控信号，使得所述第一测控开关元件打开，在液晶显示面板正常显示时接收测控开关关闭信号，使得所述第一测控开关元件关闭。
  2. 如权利要求1所述的阵列基板测试电路，其中，所述防置空开关元件为薄膜晶体管，所述薄膜晶体管的栅极为所述防置空开关元件的控制端，源极为所述防置空开关元件的输入端，漏极为所述防置空开关元件的输出端。
  3. 如权利要求1所述的阵列基板测试电路，其中，所述防置空开关元件为传输门，所述传输门的高电位控制端为所述防置空开关元件的控制端，输入端为所述防置空开关元件的输入端，输出端为所述防置空开关元件的输出端，所述传输门的低电位控制端电性连接所述使能信号输入点。
  4. 如权利要求1所述的阵列基板测试电路，其中，所述多个测控信号输入点包括：第一测控信号输入点、第二测控信号输入点、第三测控信号输入点、第四测控信号输入点、第五测控信号输入点、第六测控信号输入点；
    所述第一多路复用模块的数量为四个，每一个第一多路复用模块均包括六个第一测控开关元件，同一个第一多路复用模块中的六个测控开关元件的控制端分别接入第一测控信号输入点、第二测控信号输入点、第三测控信号输入点、第四测控信号输入点、第五测控信号输入点、第六测控信号输入点。
  5. 如权利要求4所述的阵列基板测试电路，还包括：一第二多路复用模块、第七测控信号输入点、第八测控信号输入点、第九测控信号输入点、及第十测控信号输入点，所述第一多路复用模块从第二多路复用模块获取数据信号；
    所述第二多路复用模块包括：四个第二测控开关元件，每一个第二测控开关元件对应一个第一多路复用模块，每一个第二测控开关元件的输出端均与其对应的第一多路复用模块中的各个第一测控开关元件的输入端电性连接；所述四个第二测控开关元件的控制端分别电性连接第七测控信号输入点、第八测控信号输入点、第九测控信号输入点、第十测控信号输入点，所述四个第二测控开关元件的输入端均接入数据信号。
  6. 如权利要求5所述的阵列基板测试电路，还包括：一数据信号输入点，所述数据信号输入点用于向所述第二多路复用模块提供数据信号。
  7. 如权利要求1所述的阵列基板测试电路，其中，所述使能开关元件为薄膜晶体管，所述薄膜晶体管的栅极为所述使能开关元件的控制端，源极为所述使能开关元件的输入端，漏极为所述使能开关元件的输出端。
  8. 如权利要求1所述的阵列基板测试电路，其中，所述第一测控开关元件为薄膜晶体管，所述薄膜晶体管的栅极为所述第一测控开关元件的控制端，源极为所述第一测控开关元件的输入端，漏极为所述第一测控开关元件的输出端。
  9. 一种阵列基板测试电路，包括：至少一个第一多路复用模块、一使能信号输入点、多个测控信号输入点、多条数据线、多个使能开关元件、多个防置空开关元件、以及一反相器；
    每一个第一多路复用模块均包括：多个第一测控开关元件；
    每一个第一测控开关元件对应一个使能开关元件，每一个第一测控开关元件的控制端均电性连接一个测控信号输入点，输入端均接入数据信号，输出端均电性连接与其对应的使能开关元件的输入端；
    每一个使能开关元件对应一条数据线，每一个使能开关元件的控制端均电性连接使能信号输入点，输出端均电性连接与其对应的一数据线；
    每一个防置空开关元件对应一个测控信号输入点，每一个防置空开关 元件的控制端均电性连接所述反相器的输出端，输入端均接入测控开关关闭信号，输出端均电性连接与其对应的一个测控信号输入点；
    所述使能信号输入点用于在阵列基板测试时接收高电位的使能信号，使得所述使能开关元件打开且所述防置空开关元件关闭，在液晶显示面板正常显示时接收低电位的使能信号，使得所述使能开关元件关闭且所述防置空开关元件打开；
    所述测控信号输入点用于在阵列基板测试时接收测控信号，使得所述第一测控开关元件打开，在液晶显示面板正常显示时接收测控开关关闭信号，使得所述第一测控开关元件关闭；
    其中，所述多个测控信号输入点包括：第一测控信号输入点、第二测控信号输入点、第三测控信号输入点、第四测控信号输入点、第五测控信号输入点、第六测控信号输入点；
    所述第一多路复用模块的数量为四个，每一个第一多路复用模块均包括六个第一测控开关元件，同一个第一多路复用模块中的六个测控开关元件的控制端分别接入第一测控信号输入点、第二测控信号输入点、第三测控信号输入点、第四测控信号输入点、第五测控信号输入点、第六测控信号输入点；
    还包括：一第二多路复用模块、第七测控信号输入点、第八测控信号输入点、第九测控信号输入点、及第十测控信号输入点，所述第一多路复用模块从第二多路复用模块获取数据信号；
    所述第二多路复用模块包括：四个第二测控开关元件，每一个第二测控开关元件对应一个第一多路复用模块，每一个第二测控开关元件的输出端均与其对应的第一多路复用模块中的各个第一测控开关元件的输入端电性连接；所述四个第二测控开关元件的控制端分别电性连接第七测控信号输入点、第八测控信号输入点、第九测控信号输入点、第十测控信号输入点，所述四个第二测控开关元件的输入端均接入数据信号；
    还包括：一数据信号输入点，所述数据信号输入点用于向所述第二多路复用模块提供数据信号；
    其中，所述使能开关元件为薄膜晶体管，所述薄膜晶体管的栅极为所述使能开关元件的控制端，源极为所述使能开关元件的输入端，漏极为所述使能开关元件的输出端。
  10. 如权利要求9所述的阵列基板测试电路，其中，所述防置空开关元件为薄膜晶体管，所述薄膜晶体管的栅极为所述防置空开关元件的控制端，源极为所述防置空开关元件的输入端，漏极为所述防置空开关元件的 输出端。
  11. 如权利要求9所述的阵列基板测试电路，其中，所述防置空开关元件为传输门，所述传输门的高电位控制端为所述防置空开关元件的控制端，输入端为所述防置空开关元件的输入端，输出端为所述防置空开关元件的输出端，所述传输门的低电位控制端电性连接所述使能信号输入点。
  12. 如权利要求9所述的阵列基板测试电路，其中，所述第一测控开关元件为薄膜晶体管，所述薄膜晶体管的栅极为所述第一测控开关元件的控制端，源极为所述第一测控开关元件的输入端，漏极为所述第一测控开关元件的输出端。
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