WO2019019268A1 - 低温多晶硅薄膜晶体管及其制作方法、有机发光显示器 - Google Patents

低温多晶硅薄膜晶体管及其制作方法、有机发光显示器 Download PDF

Info

Publication number
WO2019019268A1
WO2019019268A1 PCT/CN2017/100585 CN2017100585W WO2019019268A1 WO 2019019268 A1 WO2019019268 A1 WO 2019019268A1 CN 2017100585 W CN2017100585 W CN 2017100585W WO 2019019268 A1 WO2019019268 A1 WO 2019019268A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
substrate
disposed
polysilicon
interlayer insulating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2017/100585
Other languages
English (en)
French (fr)
Inventor
李松杉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Original Assignee
Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd filed Critical Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority to US15/577,448 priority Critical patent/US10516059B1/en
Publication of WO2019019268A1 publication Critical patent/WO2019019268A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0314—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral top-gate TFTs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • H10D30/6715—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes characterised by the doping profiles, e.g. having lightly-doped source or drain extensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6731—Top-gate only TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6745—Polycrystalline or microcrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3404—Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
    • H10P14/3411—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3451—Structure
    • H10P14/3452—Microstructure
    • H10P14/3456—Polycrystalline
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/202—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials
    • H10P30/204—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/21—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically active species
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/411—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by materials, geometry or structure of the substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment

Definitions

  • the invention belongs to the technical field of thin film transistor fabrication, and in particular relates to a low temperature polysilicon thin film transistor and a manufacturing method thereof, and an organic light emitting display.
  • liquid crystal displays LCDs
  • organic light emitting diodes OLED
  • amorphous silicon thin film transistors are widely used as switching elements of LCD and OLED displays, but a-Si TFTs are thin, lightweight, high-definition, high-brightness, high-reliability, and low. Power consumption requirements are still limited.
  • Lower Temperature Polycrystal Silicon (LTPS) TFTs have significant advantages in meeting the above requirements compared to a-Si TFTs.
  • an object of the present invention is to provide a low-temperature polysilicon thin film transistor which forms a heavily doped layer and a lightly doped layer by using only one mask process and one ion implantation, and a method for fabricating the same, and organic light-emitting monitor.
  • a low temperature polysilicon thin film transistor comprising: a substrate; a polysilicon layer disposed on the substrate, the polysilicon layer including an undoped layer, respectively disposed on the undoped layer a heavily doped layer on both sides and a lightly doped layer disposed between the heavily doped layer and the undoped layer; a gate insulating layer disposed on the polysilicon layer, the gate insulating layer Including the undoped a first layer opposite the impurity layer, a second layer opposite the lightly doped layer, and a third layer opposite the heavily doped layer, the second layer having a thickness greater than a thickness of the first layer and a thickness of the third layer; a gate disposed on the first layer; an interlayer insulating layer disposed on the gate, the gate insulating layer, and the substrate; the first via and the first a second via hole penetrating through one of the interlayer insulating layer and the third layer, the second via hole penetrating through the other
  • the low temperature polysilicon thin film transistor further includes a buffer layer disposed between the substrate and the polysilicon layer and the interlayer insulating layer.
  • the lightly doped layer is an N-type lightly doped layer
  • the heavily doped layer is an N-type heavily doped layer
  • an organic light emitting display comprising: the above low temperature polysilicon thin film transistor; a flat layer disposed on the interlayer insulating layer, the source and the drain; a third via extending through the planar layer to expose the drain; a bottom electrode disposed on the planar layer and in contact with the drain through the third via; a pixel defining layer disposed on a fourth via, extending through the pixel defining layer to expose the bottom electrode; an organic electroluminescent device disposed on the bottom electrode; and a top electrode disposed on the bottom layer On the organic electroluminescent device.
  • the organic electroluminescent device sequentially includes a hole injection layer, a hole transport layer, an organic light emitting layer, an electron transport layer, and an electron injection layer from the bottom electrode to the top electrode.
  • one of the bottom electrode and the top electrode is transparent or translucent, and the other is opaque and reflects light.
  • a method for fabricating a low temperature polysilicon thin film transistor includes the steps of: providing a substrate; forming a polysilicon layer on the substrate; forming a gate insulating on the polysilicon layer a layer, the gate insulating layer includes: a first layer, a third layer respectively disposed on two sides of the first layer, and a second layer disposed between the first layer and the third layer, The thickness of the second layer is greater than the thickness of the first layer and the thickness of the third layer; forming a gate on the first layer; ion implantation of the polysilicon layer to form the same a layer of relative undoped a layer, a lightly doped layer opposite the second layer, and a heavily doped layer opposite to the third layer; forming interlayer insulation on the gate, the gate insulating layer, and the substrate a first via formed through one of the interlayer insulating layer and the third layer and a second through the interlayer insulating layer and the third layer are formed in the interlayer
  • the manufacturing method further comprises the steps of: forming a buffer layer on the substrate; and the step of "forming a polysilicon layer on the substrate” is replaced
  • the step of "forming a polysilicon layer on the buffer layer” is replaced by the step "in the gate An interlayer insulating layer is formed on the gate, the gate insulating layer, and the buffer layer.
  • a specific method of implementing the step of “forming a gate insulating layer on the polysilicon layer” includes: forming a layer of insulating material on the polysilicon layer and the substrate; using a halftone mask reticle Exposing a layer of insulating material; the halftone mask comprises: a first portion opposite the first layer, a second portion opposite the second layer, and a third opposite the third layer And a fourth portion opposite to the insulating material layer on the substrate, the fourth portion having a light transmittance greater than a transmittance of the first portion, the second portion, and the third portion The light transmittance of the first portion and the third portion is greater than the light transmittance of the second portion; and the exposed insulating material layer is developed and etched.
  • the lightly doped layer is an N-type lightly doped layer
  • the heavily doped layer is an N-type heavily doped layer
  • the invention has the beneficial effects that the invention completes the fabrication of the heavily doped layer and the lightly doped layer by only one mask and one ion implantation, the process flow is simplified, and the manufacturing cost is also reduced.
  • FIG. 1 is a schematic structural view of a low temperature polysilicon thin film transistor according to an embodiment of the present invention
  • FIG. 2 is a schematic structural view of an organic light emitting display according to an embodiment of the present invention.
  • 3A through 3I are process diagrams of a low temperature polysilicon thin film transistor in accordance with an embodiment of the present invention.
  • FIGS. 4A through 4C are process diagrams of a gate insulating layer in accordance with an embodiment of the present invention.
  • FIG. 1 is a schematic structural view of a low temperature polysilicon thin film transistor according to an embodiment of the present invention.
  • a low temperature polysilicon thin film transistor 10 includes a substrate 100, a buffer layer 200, a polysilicon layer 300, a gate insulating layer 400, a gate 500, an interlayer insulating layer 600, a source 700, and a drain. 800.
  • the substrate 100 may be, for example, a transparent glass substrate or a resin substrate, but the present invention is not limited thereto.
  • the buffer layer 200 is disposed on the substrate 100.
  • the buffer layer 200 may be, for example, a SiN x /SiO x structure, but the present invention is not limited thereto.
  • the buffer layer 200 may also be a single-layer SiN x structure or a SiO x structure.
  • the buffer layer 200 may not be present.
  • the polysilicon layer 300 is disposed on the buffer layer 200. Wherein, when the buffer layer 200 is not present, the polysilicon layer 300 is directly disposed on the substrate 100.
  • the polysilicon layer 300 includes an undoped layer 310, a heavily doped layer 330 disposed on both sides of the undoped layer 310, and a lightly doped layer 320 disposed between the heavily doped layer 330 and the undoped layer 310.
  • the lightly doped layer 320 is an N-type lightly doped layer
  • the heavily doped layer 330 is The N-type heavily doped layer is not limited thereto.
  • the lightly doped layer 320 may also be a P-type lightly doped layer
  • the heavily doped layer 330 may also be a P-type heavily doped layer.
  • the gate insulating layer 400 is disposed on the polysilicon layer 300.
  • the gate insulating layer 400 includes a first layer 410 opposite to the undoped layer 310, a second layer 420 opposite the lightly doped layer 320, and a third layer 430 opposite the heavily doped layer 330, wherein the second layer
  • the thickness of 420 is greater than the thickness of first layer 410 and the thickness of third layer 430.
  • the gate insulating layer 400 may be, for example, a SiN x /SiO x structure, but the present invention is not limited thereto.
  • the gate insulating layer 400 may also be a single-layer SiN x structure or a SiO x structure.
  • the gate 500 is disposed on the first layer 410.
  • the gate electrode 500 may be a molybdenum aluminum molybdenum (MoAlMo) structure or a titanium aluminum titanium (TiAlTi) structure, or may be a single layer molybdenum structure or a single layer aluminum structure, but the invention is not limited thereto.
  • the interlayer insulating layer 600 is disposed on the gate electrode 500, the gate insulating layer 400, and the buffer layer 200. When the buffer layer 200 is not present, the interlayer insulating layer 600 is disposed on the gate electrode 500, the gate insulating layer 400, and the substrate 100.
  • the interlayer insulating layer 600 may be, for example, a SiN x /SiO x structure, but the present invention is not limited thereto.
  • the interlayer insulating layer 600 may also be a single-layer SiN x structure or a SiO x structure.
  • a first via 610 and a second via 620 are disposed in the interlayer insulating layer 600, wherein the first via 610 penetrates one of the third layers 430, and the second via 620 penetrates the other of the third layer 430 to The heavily doped layer 330 is exposed separately.
  • the source 700 and the drain 800 are disposed on the interlayer insulating layer 600.
  • the source 700 fills the first via 610 to contact the corresponding heavily doped layer 330; the drain 800 fills the second via 620 to contact the corresponding heavily doped layer 330.
  • the source 700 and the drain 800 may be a molybdenum aluminum molybdenum (MoAlMo) structure or a titanium aluminum titanium (TiAlTi) structure, or may be a single layer molybdenum structure or a single layer aluminum structure, but the invention is not limited thereto.
  • the low temperature polysilicon thin film transistor 10 according to an embodiment of the present invention can be applied to a display such as a liquid crystal display or an organic light emitting display such as an OLED display.
  • a display such as a liquid crystal display or an organic light emitting display such as an OLED display.
  • OLED display organic light emitting display to which the low temperature polysilicon thin film transistor 10 according to the embodiment of the present invention is applied will be described in detail below.
  • FIG. 2 is a schematic structural view of an organic light emitting display according to an embodiment of the present invention.
  • an organic light emitting display includes: a low temperature polysilicon thin film transistor 10, a flat layer 20, a bottom electrode 30, a pixel defining layer 40, an organic electroluminescent device 50, and a top electrode 60 shown in FIG. 1. .
  • the flat layer 20 is disposed on the interlayer insulating layer 600, the source 700, and the drain 800.
  • the flat layer 20 has a third via 21 that exposes the drain 80.
  • the bottom electrode 30 is disposed on the flat layer, and the bottom electrode 30 fills the third via 21 to be in contact with the exposed drain 80.
  • the bottom electrode 30 is typically provided as an anode.
  • the bottom electrode 30 is also a mirror.
  • the bottom electrode 30 may be made of a reflective metal and should be thin enough to have a partial transmittance at the wavelength of the emitted light, which is said to be translucent.
  • the bottom electrode 30 may be made of a transparent metal oxide such as indium tin oxide or zinc tin oxide.
  • the bottom electrode 30 can be made of a reflective metal and should be thick enough to be substantially opaque and to be a full mirror.
  • the pixel defining layer 40 is disposed on the flat layer 20 and the bottom electrode 30.
  • the pixel defining layer 40 has a fourth via hole 41 therein, which exposes the bottom electrode 30.
  • the organic electroluminescent device 50 is disposed on the exposed bottom electrode 30.
  • the organic electroluminescent device 50 includes, in order from the bottom electrode 30 to the top electrode 60, a hole injection layer (HIL) 51, a hole transport layer (HTL) 52, an organic light emitting layer (EML) 53, and electron transport.
  • HIL hole injection layer
  • HTL hole transport layer
  • EML organic light emitting layer
  • ETL electron injection layer
  • the organic electroluminescent device 50 of the present invention is not limited to the structure herein.
  • the top electrode 60 is disposed on the organic electroluminescent device 50.
  • the top electrode 60 is typically provided as a cathode.
  • the top electrode 60 is also a mirror.
  • the top electrode 60 may be made of a reflective metal and should be thin enough to have a partial light transmittance at the wavelength of the emitted light, which is called translucent
  • the top electrode 60 may be made of a transparent metal oxide such as indium tin oxide or zinc tin oxide.
  • the top electrode 60 may be made of a reflective metal and should be thick enough to be substantially opaque and to be a full mirror.
  • 3A through 3I are process diagrams of a low temperature polysilicon thin film transistor in accordance with an embodiment of the present invention.
  • Step 1 Referring to FIG. 3A, a substrate 100 is provided.
  • the substrate 100 may be, for example, a transparent glass substrate or a resin substrate, but the present invention is not limited thereto.
  • Step 2 Referring to FIG. 3B, a buffer layer 200 is formed on the substrate 100.
  • the buffer layer 200 may be, for example, a SiN x /SiO x structure, but the present invention is not limited thereto.
  • the buffer layer 200 may also be a single-layer SiN x structure or a SiO x structure.
  • step two may be omitted.
  • Step 3 Referring to FIG. 3C, a polysilicon layer 300 is formed on the buffer layer 200.
  • the polysilicon layer 300 is directly formed on the substrate 100.
  • the polysilicon layer 300 is formed by specifically forming an amorphous silicon layer on the buffer layer 200 by plasma enhanced chemical vapor deposition (PECVD); then, recrystallizing the amorphous silicon layer by using excimer laser A polysilicon layer 300 is formed.
  • PECVD plasma enhanced chemical vapor deposition
  • Step 4 Referring to FIG. 3D, a gate insulating layer 400 is formed on the polysilicon layer 300.
  • the gate insulating layer 400 includes a first layer 410, a third layer 430 respectively disposed on two sides of the first layer 410, and a first layer 430.
  • the second layer 420 between the first layer 410 and the third layer 430 has a thickness greater than the thickness of the first layer 410 and the thickness of the third layer 430.
  • the gate insulating layer 400 may be, for example, a SiN x /SiO x structure, but the present invention is not limited thereto.
  • the gate insulating layer 400 may also be a single-layer SiN x structure or a SiO x structure.
  • FIGS. 4A through 4C are process diagrams of a gate insulating layer in accordance with an embodiment of the present invention.
  • an insulating material layer IL is formed on the polysilicon layer 300 and the buffer layer 200.
  • the insulating material layer IL may be, for example, a SiN x /SiO x structure, but the invention is not limited thereto, and for example, the insulating material layer IL may also be a single-layer SiN x structure or a SiO x structure.
  • the tone mask reticle 70 includes: a first portion 71 opposite to the first layer 410, a second portion 72 opposite to the second layer 420, a third portion 73 opposite to the third layer 430, and a buffer
  • the fourth portion 74 of the insulating material layer IL on the layer 200, the fourth portion 74 has a light transmittance greater than that of the first portion 71, the second portion 72, and the third portion 73, the first portion 71 and the third portion
  • the light transmittance of the portion 73 is greater than the light transmittance of the second portion 72.
  • the first portion 71 and the third portion 73 have the same light transmittance.
  • the exposed insulating material layer IL is developed and etched.
  • a gate 500 is formed on the first layer 410.
  • the gate electrode 500 may be a molybdenum aluminum molybdenum (MoAlMo) structure or a titanium aluminum titanium (TiAlTi) structure, or may be a single layer molybdenum structure or a single layer aluminum structure, but the invention is not limited thereto.
  • Step 6 Referring to FIG. 3F, the polysilicon layer 300 is ion implanted to form an undoped layer 310 opposite the first layer 410, a lightly doped layer 320 opposite the second layer 420, and opposite the third layer 430.
  • the layer 330 is heavily doped.
  • the ions implanted here may be, for example, phosphorus ions, but the present invention is not limited thereto, and may be, for example, boron ions or the like.
  • Step 7 Referring to FIG. 3G, an interlayer insulating layer 600 is formed on the gate electrode 500, the gate insulating layer 400, and the buffer layer 200.
  • the interlayer insulating layer 600 is formed on the gate electrode 500, the gate insulating layer 400, and the substrate 100.
  • the interlayer insulating layer 600 may be, for example, a SiN x /SiO x structure, but the present invention is not limited thereto.
  • the interlayer insulating layer 600 may also be a single-layer SiN x structure or a SiO x structure.
  • Step 8 Referring to FIG. 3H, a first via 610 forming one of the interlayer insulating layer 600 and the third layer 430 and another through the interlayer insulating layer 600 and the third layer 430 are formed in the interlayer insulating layer 600.
  • the second via 620 Referring to FIG. 3H, a first via 610 forming one of the interlayer insulating layer 600 and the third layer 430 and another through the interlayer insulating layer 600 and the third layer 430 are formed in the interlayer insulating layer 600.
  • the second via 620 Referring to FIG. 3H, a first via 610 forming one of the interlayer insulating layer 600 and the third layer 430 and another through the interlayer insulating layer 600 and the third layer 430 are formed in the interlayer insulating layer 600.
  • the second via 620 Referring to FIG. 3H, a first via 610 forming one of the interlayer insulating layer 600 and the third layer 430 and another through the interlayer insulating layer 600 and the third layer
  • Step 9 Referring to FIG. 3I, a source 700 filling the first via 610 in contact with the corresponding heavily doped layer 330 and filling the second via 620 and the corresponding heavily doped layer 330 are formed on the interlayer insulating layer 600.
  • Contact drain 800 The source 700 and the drain 800 may be a molybdenum aluminum molybdenum (MoAlMo) structure or a titanium aluminum titanium (TiAlTi) structure, or may be a single layer molybdenum structure or a single layer aluminum structure, but the invention is not limited thereto.
  • MoAlMo molybdenum aluminum molybdenum
  • TiAlTi titanium aluminum titanium

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Thin Film Transistor (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

一种低温多晶硅薄膜晶体管(10)，其包括：基板(100)；多晶硅层(300)，包括未掺杂层(310)、重掺杂层(330)及轻掺杂层(320)；栅极绝缘层(400)，设置于多晶硅层(300)上，且包括与未掺杂层(310)、轻掺杂层(320)和重掺杂层(330)分别相对的第一层(410)、第二层(420)和第三层(430)，第二层(420)的厚度大于第一层(410)和第三层(430)的厚度；栅极(500)，设置于第一层(410)上；层间绝缘层(600)，设置于栅极(500)、栅极绝缘层(400)和基板(100)上；第一过孔(610)，贯穿层间绝缘层(600)和第三层(430)之一；第二过孔(620)，贯穿层间绝缘层(600)和第三层(430)之另一；源极(700)和漏极(800)，设置于层间绝缘层(600)上，且分别通过第一过孔(610)和第二过孔(620)与对应的重掺杂层(330)接触。此外，还提供了一种低温多晶硅薄膜晶体管(10)的制作方法和有机发光显示器。该低温多晶硅薄膜晶体管(10)的制作工艺简单，且制作成本也较低。

Description

低温多晶硅薄膜晶体管及其制作方法、有机发光显示器 技术领域
本发明属于薄膜晶体管制作技术领域，具体地将，涉及一种低温多晶硅薄膜晶体管及其制作方法、有机发光显示器。
背景技术
随着光电与半导体技术的演进，也带动了平板显示器(Flat Panel Display)的蓬勃发展，而在诸多平板显示器中，液晶显示器(Liquid Crystal Display，简称LCD)和有机发光二极管(OLED)显示器因具有高空间利用效率、低消耗功率、无辐射以及低电磁干扰等诸多优越特性，已成为市场的主流。
目前，作为LCD和OLED显示器的开关元件而广泛采用的是非晶硅薄膜晶体管(a-Si TFT)，但a-Si TFT在满足薄型、轻量、高精细度、高亮度、高可靠性、低功耗等要求仍受到限制。低温多晶硅(Lower Temperature Polycrystal Silicon，LTPS)TFT与a-Si TFT相比，在满足上述要求方面，具有明显优势。
然而，在现有的低温多晶硅薄膜晶体管中，需要对多晶硅层进行两次光罩工艺来形成重掺杂区和轻掺杂区，再进行两次离子注入才能形成重掺杂层和轻掺杂层，工艺流程复杂，制作成本也比较高。
发明内容
为了解决上述现有技术存在的问题，本发明的目的在于提供一种仅利用一次光罩工艺和一次离子注入形成重掺杂层和轻掺杂层的低温多晶硅薄膜晶体管及其制作方法、有机发光显示器。
根据本发明的一方面，提供了一种低温多晶硅薄膜晶体管，其包括：基板；多晶硅层，设置于所述基板上，所述多晶硅层包括未掺杂层、分别设置于所述未掺杂层两侧的重掺杂层及设置于所述重掺杂层和所述未掺杂层之间的轻掺杂层；栅极绝缘层，设置于所述多晶硅层上，所述栅极绝缘层包括与所述未掺 杂层相对的第一层、与所述轻掺杂层相对的第二层以及与所述重掺杂层相对的第三层，所述第二层的厚度大于所述第一层的厚度和所述第三层的厚度；栅极，设置于所述第一层上；层间绝缘层，设置于所述栅极、所述栅极绝缘层和所述基板上；第一过孔和第二过孔，所述第一过孔贯穿所述层间绝缘层和所述第三层之一，所述第二过孔贯穿所述层间绝缘层和所述第三层之另一；源极和漏极，设置于所述层间绝缘层上，所述源极和所述漏极分别通过所述第一过孔和所述第二过孔与对应的所述重掺杂层接触。
进一步地，所述低温多晶硅薄膜晶体管还包括：缓冲层，设置于所述基板与所述多晶硅层和所述层间绝缘层之间。
进一步地，所述轻掺杂层为N型轻掺杂层，所述重掺杂层为N型重掺杂层。
根据本发明的另一方面，还提供了一种有机发光显示器，其包括：上述的低温多晶硅薄膜晶体管；平坦层，设置于所述层间绝缘层、所述源极和所述漏极上；第三过孔，贯穿所述平坦层，以将所述漏极暴露；底电极，设置于所述平坦层上且通过所述第三过孔与所述漏极接触；像素限定层，设置于所述平坦层和所述底电极上；第四过孔，贯穿所述像素限定层，以将所述底电极暴露；有机电致发光器件，设置于所述底电极上；顶电极，设置于所述有机电致发光器件上。
进一步地，所述有机电致发光器件从底电极到顶电极顺序包括：空穴注入层、空穴传输层、有机发光层、电子传输层及电子注入层。
进一步地，所述底电极和所述顶电极中的一个是透明的或半透明的，另一个是不透明的且反射光的。
根据本发明的又一方面，又提供了一种低温多晶硅薄膜晶体管的制作方法，其包括步骤：提供一基板；在所述基板上制作形成多晶硅层；在所述多晶硅层上制作形成栅极绝缘层，所述栅极绝缘层包括：第一层、分别设置于所述第一层两侧的第三层及设置于所述第一层和所述第三层之间的第二层，所述第二层的厚度大于所述第一层的厚度和所述第三层的厚度；在所述第一层上制作形成栅极；对所述多晶硅层进行离子注入，以形成与所述第一层相对的未掺杂 层、与所述第二层相对的轻掺杂层以及与所述第三层相对的重掺杂层；在所述栅极、所述栅极绝缘层和所述基板上制作形成层间绝缘层；在所述层间绝缘层中制作形成贯穿所述层间绝缘层和所述第三层之一的第一过孔和贯穿所述层间绝缘层和所述第三层之另一的第二过孔；在所述层间绝缘层上制作形成填充所述第一过孔与对应的所述重掺杂层接触的源极和填充所述第二过孔与对应的所述重掺杂层接触的漏极。
进一步地，在步骤“在所述基板上制作形成多晶硅层”之前，所述制作方法还包括步骤：在所述基板上制作形成缓冲层；步骤“在所述基板上制作形成多晶硅层”被替换为步骤“在所述缓冲层上制作形成多晶硅层”；步骤“在所述栅极、所述栅极绝缘层和所述基板上制作形成层间绝缘层”被替换为步骤“在所述栅极、所述栅极绝缘层和所述缓冲层上制作形成层间绝缘层”。
进一步地，实现步骤“在所述多晶硅层上制作形成栅极绝缘层”的具体方法包括：在所述多晶硅层和所述基板上制作形成绝缘材料层；利用半色调掩膜光罩对所述绝缘材料层进行曝光；所述半色调掩膜光罩包括：与所述第一层相对的第一部、与所述第二层相对的第二部、与所述第三层相对的第三部以及与所述基板上的绝缘材料层相对的第四部，所述第四部的透光率大于所述第一部、所述第二部和所述第三部的透光率，所述第一部和所述第三部的透光率大于所述第二部的透光率；对曝光后的绝缘材料层进行显影和刻蚀。
进一步地，所述轻掺杂层为N型轻掺杂层，所述重掺杂层为N型重掺杂层。
本发明的有益效果：本发明仅采用一道光罩和一次离子注入完成了重掺杂层和轻掺杂层的制作，工艺流程得到了简化，并且制作成本也被降低。
附图说明
通过结合附图进行的以下描述，本发明的实施例的上述和其它方面、特点和优点将变得更加清楚，附图中：
图1是根据本发明的实施例的低温多晶硅薄膜晶体管的结构示意图；
图2是根据本发明的实施例的有机发光显示器的结构示意图；
图3A至图3I是根据本发明的实施例的低温多晶硅薄膜晶体管的制程图；
图4A至图4C是根据本发明的实施例的栅极绝缘层的制程图。
具体实施方式
以下，将参照附图来详细描述本发明的实施例。然而，可以以许多不同的形式来实施本发明，并且本发明不应该被解释为限制于这里阐述的具体实施例。相反，提供这些实施例是为了解释本发明的原理及其实际应用，从而使本领域的其他技术人员能够理解本发明的各种实施例和适合于特定预期应用的各种修改。
在附图中，为了清楚器件，夸大了层和区域的厚度。相同的标号在整个说明书和附图中表示相同的元器件。
将理解的是，当诸如层、膜、区域或基板的元件被称作“在”另一元件“上”时，该元件可以直接在所述另一元件上，或者也可以存在中间元件。可选择地，当元件被称作“直接在”另一元件“上”时，不存在中间元件。
图1是根据本发明的实施例的低温多晶硅薄膜晶体管的结构示意图。
参照图1，根据本发明的实施例的低温多晶硅薄膜晶体管10包括基板100、缓冲层200、多晶硅层300、栅极绝缘层400、栅极500、层间绝缘层600、源极700和漏极800。
具体而言，在本实施例中，基板100可例如是透明的玻璃基板或者树脂基板，但本发明并不限制于此。
缓冲层200设置于基板100上。缓冲层200可例如是SiNx/SiOx结构，但本发明并不限制于此，例如缓冲层200也可以是单层的SiNx结构或SiOx结构。作为本发明的另一实施方式，也可以不存在缓冲层200。
多晶硅层300设置于缓冲层200上。其中，当不存在缓冲层200上时，多晶硅层300直接设置于基板100上。多晶硅层300包括未掺杂层310、分别设置于未掺杂层310两侧的重掺杂层330及设置于重掺杂层330和未掺杂层310之间的轻掺杂层320。这里，轻掺杂层320为N型轻掺杂层，重掺杂层330为 N型重掺杂层，单本发明并不限制于此，例如轻掺杂层320也可以为P型轻掺杂层，重掺杂层330也可以为P型重掺杂层。
栅极绝缘层400设置于多晶硅层300上。栅极绝缘层400包括与未掺杂层310相对的第一层410、与轻掺杂层320相对的第二层420以及与重掺杂层330相对的第三层430，其中，第二层420的厚度大于第一层410的厚度和第三层430的厚度。在本实施例中，为了简化制作工艺以及简化光罩的结构，优选地，第一层410的厚度和第三层430的厚度相同。这里，栅极绝缘层400可例如是SiNx/SiOx结构，但本发明并不限制于此，例如栅极绝缘层400也可以是单层的SiNx结构或SiOx结构。
栅极500设置于第一层410上。栅极500可以是钼铝钼(MoAlMo)结构或钛铝钛(TiAlTi)结构，也可以是单层的钼结构或者单层的铝结构，但本发明并不限制于此。
层间绝缘层600设置于栅极500、栅极绝缘层400和缓冲层200上。当不存在缓冲层200上时，层间绝缘层600设置于栅极500、栅极绝缘层400和基板100上。层间绝缘层600可例如是SiNx/SiOx结构，但本发明并不限制于此，例如层间绝缘层600也可以是单层的SiNx结构或SiOx结构。
层间绝缘层600中设置有第一过孔610和第二过孔620，其中，第一过孔610贯穿第三层430之一，第二过孔620贯穿第三层430之另一，以分别将重掺杂层330暴露。
源极700和漏极800设置于层间绝缘层600上。源极700填充第一过孔610以与对应的所述重掺杂层330接触；漏极800填充第二过孔620以与对应的所述重掺杂层330接触。源极700和漏极800可采用钼铝钼(MoAlMo)结构或钛铝钛(TiAlTi)结构，也可以是单层的钼结构或者单层的铝结构，但本发明并不限制于此。
根据本发明的实施例的低温多晶硅薄膜晶体管10可应用于显示器中，诸如液晶显示器或有机发光显示器(诸如OLED显示器)OLED中。以下将对应用了根据本发明的实施例的低温多晶硅薄膜晶体管10的有机发光显示器进行详细描述。
图2是根据本发明的实施例的有机发光显示器的结构示意图。
参照图2，根据本发明的实施例的有机发光显示器包括：图1所示的低温多晶硅薄膜晶体管10、平坦层20、底电极30、像素限定层40、有机电致发光器件50和顶电极60。
平坦层20设置于层间绝缘层600、源极700和漏极800上。平坦层20中具有第三过孔21，该第三过孔21将漏极80暴露。
底电极30设置于平坦层上，并且底电极30填充第三过孔21，以与暴露的漏极80接触。底电极30通常被设置为阳极。底电极30也是反光镜。当通过基板100观察有机电致发光器件50发光时，底电极30可以由反射性金属制成，并且应该足够薄以便在发射光的波长下具有部分透光率，这被称为是半透明的，或者底电极30可以由透明的金属氧化物制成，诸如氧化铟锡或氧化锌锡等。当通过顶电极60观察有机电致发光器件50发光时，底电极30可以由反射性金属制成，并且应该足够厚，以使其基本上是不透光的且是全反光镜。
像素限定层40设置于平坦层20和底电极30上。像素限定层40中具有第四过孔41，该第四过孔41将底电极30暴露。
有机电致发光器件50设置于暴露的底电极30上。在本实施例中，有机电致发光器件50从底电极30到顶电极60顺序包括：空穴注入层(HIL)51、空穴传输层(HTL)52、有机发光层(EML)53、电子传输层(ETL)54以及电子注入层(EIL)55；但本发明的有机电致发光器件50并不限制于这里的结构。
顶电极60设置于有机电致发光器件50上。顶电极60通常被设置为阴极。顶电极60也是反光镜。当通过顶电极60观察有机电致发光器件50发光时，顶电极60可以由反射性金属制成，并且应该足够薄以便在发射光的波长下具有部分透光率，这被称为是半透明的，或者顶电极60可以由透明的金属氧化物制成，诸如氧化铟锡或氧化锌锡等。当通过基板100观察有机电致发光器件50发光时，顶电极60可以由反射性金属制成，并且应该足够厚，以使其基本上是不透光的且是全反光镜。
以下将对根据本发明的实施例的低温多晶硅薄膜晶体管10的制作过程进 行详细描述。
图3A至图3I是根据本发明的实施例的低温多晶硅薄膜晶体管的制程图。
根据本发明的实施例的低温多晶硅薄膜晶体管的制作方法包括：
步骤一：参照图3A，提供一基板100。这里，基板100可例如是透明的玻璃基板或者树脂基板，但本发明并不限制于此。
步骤二：参照图3B，在基板100上制作形成缓冲层200。缓冲层200可例如是SiNx/SiOx结构，但本发明并不限制于此，例如缓冲层200也可以是单层的SiNx结构或SiOx结构。此外，作为本发明的另一实施方式，步骤二可以被省略。
步骤三：参照图3C，在缓冲层200上制作形成多晶硅层300。作为本发明的另一实施方式，当步骤二被省略时，在基板100上直接制作形成多晶硅层300。多晶硅层300的形成方式具体为：利用等离子体增强化学气相沉积法(PECVD)在缓冲层200上制作形成非晶硅层；接着，以利用准分子镭射使所述非晶硅层再结晶，从而生成多晶硅层300。
步骤四：参照图3D，在多晶硅层300上制作形成栅极绝缘层400，栅极绝缘层400包括：第一层410、分别设置于第一层410两侧的第三层430及设置于第一层410和第三层430之间的第二层420，第二层420的厚度大于第一层410的厚度和第三层430的厚度。在本实施例中，为了简化制作工艺以及简化光罩的结构，优选地，第一层410的厚度和第三层430的厚度相同。这里，栅极绝缘层400可例如是SiNx/SiOx结构，但本发明并不限制于此，例如栅极绝缘层400也可以是单层的SiNx结构或SiOx结构。
图4A至图4C是根据本发明的实施例的栅极绝缘层的制程图。
首先，参照图4A，在多晶硅层300和缓冲层200上制作形成绝缘材料层IL。绝缘材料层IL可例如是SiNx/SiOx结构，但本发明并不限制于此，例如绝缘材料层IL也可以是单层的SiNx结构或SiOx结构。
接着，参照图4B，利用半色调掩膜光罩70对绝缘材料层IL进行曝光。 其中，色调掩膜光罩70包括：与所述第一层410相对的第一部71、与第二层420相对的第二部72、与第三层430相对的第三部73以及与缓冲层200上的绝缘材料层IL相对的第四部74，第四部74的透光率大于第一部71、第二部72和第三部73的透光率，第一部71和第三部73的透光率大于第二部72的透光率。优选地，第一部71和第三部73的透光率相同。
接着，参照图4C，对曝光后的绝缘材料层IL进行显影和刻蚀。
步骤五：参照图3E，在第一层410上制作形成栅极500。这里，栅极500可以是钼铝钼(MoAlMo)结构或钛铝钛(TiAlTi)结构，也可以是单层的钼结构或者单层的铝结构，但本发明并不限制于此。
步骤六：参照图3F，对多晶硅层300进行离子注入，以形成与第一层410相对的未掺杂层310、与第二层420相对的轻掺杂层320以及与第三层430相对的重掺杂层330。这里注入的离子可例如是磷离子，但本发明并不限制于此，例如也可以是硼离子等。
步骤七：参照图3G，在栅极500、栅极绝缘层400和缓冲层200上制作形成层间绝缘层600。作为本发明的另一实施方式，当步骤二被省略时，在栅极500、栅极绝缘层400和基板100上制作形成层间绝缘层600。层间绝缘层600可例如是SiNx/SiOx结构，但本发明并不限制于此，例如层间绝缘层600也可以是单层的SiNx结构或SiOx结构。
步骤八：参照图3H，在层间绝缘层600中制作形成贯穿层间绝缘层600和第三层430之一的第一过孔610和贯穿层间绝缘层600和第三层430之另一的第二过孔620。
步骤九：参照图3I，在层间绝缘层600上制作形成填充第一过孔610与对应的重掺杂层330接触的源极700和填充第二过孔620与对应的重掺杂层330接触的漏极800。源极700和漏极800可采用钼铝钼(MoAlMo)结构或钛铝钛(TiAlTi)结构，也可以是单层的钼结构或者单层的铝结构，但本发明并不限制于此。
综上所述，根据本发明的实施例，仅采用一道光罩和一次离子注入完成了 重掺杂层和轻掺杂层的制作，工艺流程得到了简化，并且制作成本也被降低。
虽然已经参照特定实施例示出并描述了本发明，但是本领域的技术人员将理解：在不脱离由权利要求及其等同物限定的本发明的精神和范围的情况下，可在此进行形式和细节上的各种变化。

Claims (13)

  1. 一种低温多晶硅薄膜晶体管，其中，包括：
    基板；
    多晶硅层，设置于所述基板上，所述多晶硅层包括未掺杂层、分别设置于所述未掺杂层两侧的重掺杂层及设置于所述重掺杂层和所述未掺杂层之间的轻掺杂层；
    栅极绝缘层，设置于所述多晶硅层上，所述栅极绝缘层包括与所述未掺杂层相对的第一层、与所述轻掺杂层相对的第二层以及与所述重掺杂层相对的第三层，所述第二层的厚度大于所述第一层的厚度和所述第三层的厚度；
    栅极，设置于所述第一层上；
    层间绝缘层，设置于所述栅极、所述栅极绝缘层和所述基板上；
    第一过孔和第二过孔，所述第一过孔贯穿所述层间绝缘层和所述第三层之一，所述第二过孔贯穿所述层间绝缘层和所述第三层之另一；
    源极和漏极，设置于所述层间绝缘层上，所述源极和所述漏极分别通过所述第一过孔和所述第二过孔与对应的所述重掺杂层接触。
  2. 根据权利要求1所述的低温多晶硅薄膜晶体管，其中，还包括：缓冲层，设置于所述基板与所述多晶硅层和所述层间绝缘层之间。
  3. 根据权利要求1所述的低温多晶硅薄膜晶体管，其中，所述轻掺杂层为N型轻掺杂层，所述重掺杂层为N型重掺杂层。
  4. 一种有机发光显示器，其中，包括：
    基板；
    多晶硅层，设置于所述基板上，所述多晶硅层包括未掺杂层、分别设置于所述未掺杂层两侧的重掺杂层及设置于所述重掺杂层和所述未掺杂层之间的 轻掺杂层；
    栅极绝缘层，设置于所述多晶硅层上，所述栅极绝缘层包括与所述未掺杂层相对的第一层、与所述轻掺杂层相对的第二层以及与所述重掺杂层相对的第三层，所述第二层的厚度大于所述第一层的厚度和所述第三层的厚度；
    栅极，设置于所述第一层上；
    层间绝缘层，设置于所述栅极、所述栅极绝缘层和所述基板上；
    第一过孔和第二过孔，所述第一过孔贯穿所述层间绝缘层和所述第三层之一，所述第二过孔贯穿所述层间绝缘层和所述第三层之另一；
    源极和漏极，设置于所述层间绝缘层上，所述源极和所述漏极分别通过所述第一过孔和所述第二过孔与对应的所述重掺杂层接触；
    平坦层，设置于所述层间绝缘层、所述源极和所述漏极上；
    第三过孔，贯穿所述平坦层，以将所述漏极暴露；
    底电极，设置于所述平坦层上且通过所述第三过孔与所述漏极接触；
    像素限定层，设置于所述平坦层和所述底电极上；
    第四过孔，贯穿所述像素限定层，以将所述底电极暴露；
    有机电致发光器件，设置于所述底电极上；
    顶电极，设置于所述有机电致发光器件上。
  5. 根据权利要求4所述的有机发光显示器，其中，所述有机电致发光器件从底电极到顶电极顺序包括：空穴注入层、空穴传输层、有机发光层、电子传输层及电子注入层。
  6. 根据权利要求4所述的有机发光显示器，其中，所述底电极和所述顶电极中的一个是透明的或半透明的，另一个是不透明的且反射光的。
  7. 根据权利要求4所述的有机发光显示器，其中，还包括：缓冲层，设 置于所述基板与所述多晶硅层和所述层间绝缘层之间。
  8. 根据权利要求1所述的有机发光显示器，其中，所述轻掺杂层为N型轻掺杂层，所述重掺杂层为N型重掺杂层。
  9. 一种低温多晶硅薄膜晶体管的制作方法，其中，包括步骤：
    提供一基板；
    在所述基板上制作形成多晶硅层；
    在所述多晶硅层上制作形成栅极绝缘层，所述栅极绝缘层包括：第一层、分别设置于所述第一层两侧的第三层及设置于所述第一层和所述第三层之间的第二层，所述第二层的厚度大于所述第一层的厚度和所述第三层的厚度；
    在所述第一层上制作形成栅极；
    对所述多晶硅层进行离子注入，以形成与所述第一层相对的未掺杂层、与所述第二层相对的轻掺杂层以及与所述第三层相对的重掺杂层；
    在所述栅极、所述栅极绝缘层和所述基板上制作形成层间绝缘层；
    在所述层间绝缘层中制作形成贯穿所述层间绝缘层和所述第三层之一的第一过孔和贯穿所述层间绝缘层和所述第三层之另一的第二过孔；
    在所述层间绝缘层上制作形成填充所述第一过孔与对应的所述重掺杂层接触的源极和填充所述第二过孔与对应的所述重掺杂层接触的漏极。
  10. 根据权利要求9所述的低温多晶硅薄膜晶体管的制作方法，其中，在步骤“在所述基板上制作形成多晶硅层”之前，所述制作方法还包括步骤：在所述基板上制作形成缓冲层；
    步骤“在所述基板上制作形成多晶硅层”被替换为步骤“在所述缓冲层上制作形成多晶硅层”；
    步骤“在所述栅极、所述栅极绝缘层和所述基板上制作形成层间绝缘层”被替换为步骤“在所述栅极、所述栅极绝缘层和所述缓冲层上制作形成层间绝 缘层”。
  11. 根据权利要求9所述的低温多晶硅薄膜晶体管的制作方法，其中，实现步骤“在所述多晶硅层上制作形成栅极绝缘层”的具体方法包括：
    在所述多晶硅层和所述基板上制作形成绝缘材料层；
    利用半色调掩膜光罩对所述绝缘材料层进行曝光；所述半色调掩膜光罩包括：与所述第一层相对的第一部、与所述第二层相对的第二部、与所述第三层相对的第三部以及与所述基板上的绝缘材料层相对的第四部，所述第四部的透光率大于所述第一部、所述第二部和所述第三部的透光率，所述第一部和所述第三部的透光率大于所述第二部的透光率；
    对曝光后的绝缘材料层进行显影和刻蚀。
  12. 根据权利要求10所述的低温多晶硅薄膜晶体管的制作方法，其中，实现步骤“在所述多晶硅层上制作形成栅极绝缘层”的具体方法包括：
    在所述多晶硅层和所述基板上制作形成绝缘材料层；
    利用半色调掩膜光罩对所述绝缘材料层进行曝光；所述半色调掩膜光罩包括：与所述第一层相对的第一部、与所述第二层相对的第二部、与所述第三层相对的第三部以及与所述基板上的绝缘材料层相对的第四部，所述第四部的透光率大于所述第一部、所述第二部和所述第三部的透光率，所述第一部和所述第三部的透光率大于所述第二部的透光率；
    对曝光后的绝缘材料层进行显影和刻蚀。
  13. 根据权利要求9所述的低温多晶硅薄膜晶体管，其中，所述轻掺杂层为N型轻掺杂层，所述重掺杂层为N型重掺杂层。
PCT/CN2017/100585 2017-07-27 2017-09-05 低温多晶硅薄膜晶体管及其制作方法、有机发光显示器 Ceased WO2019019268A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US15/577,448 US10516059B1 (en) 2017-07-27 2017-09-05 Lower temperature polycrystalline silicon thin film transistor and method of manufacture thereof and OLED display device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201710625402.4A CN107393953B (zh) 2017-07-27 2017-07-27 低温多晶硅薄膜晶体管及其制作方法、有机发光显示器
CN201710625402.4 2017-07-27

Publications (1)

Publication Number Publication Date
WO2019019268A1 true WO2019019268A1 (zh) 2019-01-31

Family

ID=60342199

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/100585 Ceased WO2019019268A1 (zh) 2017-07-27 2017-09-05 低温多晶硅薄膜晶体管及其制作方法、有机发光显示器

Country Status (3)

Country Link
US (1) US10516059B1 (zh)
CN (1) CN107393953B (zh)
WO (1) WO2019019268A1 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109212854B (zh) * 2018-08-29 2021-06-01 武汉华星光电技术有限公司 一种ltps阵列基板的制造方法
CN109659371B (zh) * 2018-12-21 2020-11-24 武汉华星光电技术有限公司 薄膜晶体管、薄膜晶体管的制作方法和液晶显示屏

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5767531A (en) * 1994-08-29 1998-06-16 Sharp Kabushiki Kaisha Thin-film transistor, method of fabricating the same, and liquid-crystal display apparatus
JP2005191212A (ja) * 2003-12-25 2005-07-14 Semiconductor Energy Lab Co Ltd 半導体装置及びその作製方法
CN104347819A (zh) * 2013-07-30 2015-02-11 乐金显示有限公司 柔性有机电致发光器件及其制造方法
CN104485278A (zh) * 2014-12-12 2015-04-01 深圳市华星光电技术有限公司 一种阵列基板的掺杂方法和掺杂设备
CN105097550A (zh) * 2015-08-04 2015-11-25 深圳市华星光电技术有限公司 低温多晶硅薄膜晶体管的制作方法及低温多晶硅薄膜晶体管

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6974972B1 (en) * 1999-10-21 2005-12-13 Matsushita Electric Industrial Co., Ltd. Thin-film transistor, and liquid crystal display device using the same
US7064021B2 (en) * 2003-07-02 2006-06-20 Au Optronics Corp. Method for fomring a self-aligned LTPS TFT
KR102081283B1 (ko) * 2013-02-14 2020-04-16 삼성디스플레이 주식회사 박막 반도체 장치, 유기 발광 표시 장치, 및 이의 제조 방법
CN105390451B (zh) * 2015-12-03 2018-03-30 深圳市华星光电技术有限公司 低温多晶硅tft基板的制作方法
CN105957814B (zh) * 2016-07-11 2019-05-17 昆山国显光电有限公司 薄膜晶体管及其制备方法
CN106876430A (zh) * 2017-02-20 2017-06-20 武汉华星光电技术有限公司 有机电致发光显示装置及其制作方法
CN106847703B (zh) * 2017-04-11 2020-04-10 京东方科技集团股份有限公司 低温多晶硅薄膜晶体管的制造方法和显示装置
CN106981520B (zh) * 2017-04-12 2020-07-07 京东方科技集团股份有限公司 薄膜晶体管及其制备方法、阵列基板和显示装置
US20190096918A1 (en) * 2017-09-27 2019-03-28 Wuhan China Star Optelectronics Technology Co., Ltd. An array substrate, mask plate and array substrate manufacturing method

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5767531A (en) * 1994-08-29 1998-06-16 Sharp Kabushiki Kaisha Thin-film transistor, method of fabricating the same, and liquid-crystal display apparatus
JP2005191212A (ja) * 2003-12-25 2005-07-14 Semiconductor Energy Lab Co Ltd 半導体装置及びその作製方法
CN104347819A (zh) * 2013-07-30 2015-02-11 乐金显示有限公司 柔性有机电致发光器件及其制造方法
CN104485278A (zh) * 2014-12-12 2015-04-01 深圳市华星光电技术有限公司 一种阵列基板的掺杂方法和掺杂设备
CN105097550A (zh) * 2015-08-04 2015-11-25 深圳市华星光电技术有限公司 低温多晶硅薄膜晶体管的制作方法及低温多晶硅薄膜晶体管

Also Published As

Publication number Publication date
CN107393953B (zh) 2020-04-10
US10516059B1 (en) 2019-12-24
US20190386146A1 (en) 2019-12-19
CN107393953A (zh) 2017-11-24

Similar Documents

Publication Publication Date Title
CN107424957B (zh) 柔性tft基板的制作方法
US10038043B2 (en) Method for manufacturing AMOLED backplane and structure thereof
JP6460582B2 (ja) Ａｍｏｌｅｄバックパネルの製造方法
US9947736B2 (en) Manufacture method of AMOLED back plate and structure thereof
US10068809B2 (en) TFT backplane manufacturing method and TFT backplane
US20190386083A1 (en) Method for manufacturing oled backplane
US10192993B2 (en) Thin film transfer, manufacturing method thereof, array substrate and manufacturing method thereof
WO2016112663A1 (zh) 制作阵列基板的方法和阵列基板
WO2016173322A1 (zh) 一种阵列基板及其制作方法、及显示装置
WO2018188146A1 (zh) 一种阵列基板、显示装置及其制作方法
WO2017210926A1 (zh) Tft背板的制作方法及tft背板
US20160307978A1 (en) Manufacturing method of array substrate, array substrate and display device
US9876040B1 (en) Method for manufacturing TFT substrate
WO2017028461A1 (zh) 薄膜晶体管及阵列基板的制备方法、阵列基板及显示装置
WO2019028955A1 (zh) 有机电致发光显示面板及其制作方法
US9735186B2 (en) Manufacturing method and structure thereof of TFT backplane
US20170352711A1 (en) Manufacturing method of tft backplane and tft backplane
US10672912B2 (en) N-type thin film transistor, manufacturing method thereof and manufacturing method of an OLED display panel
US10192903B2 (en) Method for manufacturing TFT substrate
WO2019019268A1 (zh) 低温多晶硅薄膜晶体管及其制作方法、有机发光显示器
WO2018192009A1 (zh) 一种制作低温多晶硅薄膜晶体管的方法
US10672797B2 (en) Array substrate, method for fabricating array substrate and display
US20190221637A1 (en) Low-temperature polysilicon thin film transistor and manufacturing method and display device thereof
WO2019019277A1 (zh) 低温多晶硅薄膜晶体管及其制作方法、显示设备

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17918748

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 17918748

Country of ref document: EP

Kind code of ref document: A1