WO2019015171A1 - 一种显示面板及显示面板栅极信号的控制方法 - Google Patents

一种显示面板及显示面板栅极信号的控制方法 Download PDF

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Publication number
WO2019015171A1
WO2019015171A1 PCT/CN2017/109529 CN2017109529W WO2019015171A1 WO 2019015171 A1 WO2019015171 A1 WO 2019015171A1 CN 2017109529 W CN2017109529 W CN 2017109529W WO 2019015171 A1 WO2019015171 A1 WO 2019015171A1
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WIPO (PCT)
Prior art keywords
output end
driving circuit
output
input
row
Prior art date
Application number
PCT/CN2017/109529
Other languages
English (en)
French (fr)
Inventor
张先明
Original Assignee
深圳市华星光电半导体显示技术有限公司
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Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Priority to US15/735,720 priority Critical patent/US20190114982A1/en
Publication of WO2019015171A1 publication Critical patent/WO2019015171A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/027—Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0291—Details of output amplifiers or buffers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
    • H03K17/6872—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor using complementary field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/017509—Interface arrangements

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a control method for a display panel and a display panel gate signal.
  • the existing display panel mainly includes liquid crystal (Liquid Crystal) Display, LCD) display panel and OLED (Organic Light Emitting Diode, OLED) display panel.
  • the OLED display panel has self-illumination, low driving voltage, high luminous efficiency, short response time, high definition and contrast, near 180° viewing angle, wide temperature range, flexible display and large-area full-color display. It is recognized by the industry as the most promising display panel.
  • Gate drive substrate (GOA, Gate on Array), that is, using TFT-LCD internal TFT line and CB power-on displacement converter (Level Shifter The IC) generates the required gate signal, which effectively omits the Gate IC, resulting in cost-saving benefits.
  • An object of the present invention is to provide a control method for a display panel and a display panel gate signal, which solves the problem that the gate signal inside the existing panel has a great difference at the far and near ends.
  • the pixel driving circuit provided by the present invention adopts the following technical solutions:
  • a display panel comprising:
  • the gate driving substrate includes a pixel array region and a circuit placement region located at a side of the pixel array region, the pixel array region including a plurality of rows of row pixel units;
  • a plurality of gate driving units disposed on the circuit placement area for outputting scan signals to the row pixel units of the pixel array area;
  • An electric displacement converter electrically connected to the plurality of the gate driving units for outputting a control signal
  • the driving circuit includes an input end, an output end and a control end, and a control end of the driving circuit is connected to an output end of the potential shifter for controlling the turning on and off of the input end and the output end of the driving circuit,
  • the output end of the driving circuit is connected to the row pixel unit through the gate driving unit;
  • a voltage control circuit an output end of the voltage control circuit is connected to an input end of the driving circuit, and the voltage control circuit sets different output voltages to be input to the driving circuit according to a row pixel unit corresponding to an output signal of an output end of the driving circuit
  • the input end is such that the on and off speeds of the input end and the output end of the driving circuit become larger row by row;
  • the voltage control circuit includes a digital-to-analog converter, an adder, and a digital voltage generator, an output of the adder is coupled to an input of the driver circuit, and a first input of the adder is coupled to a reference voltage, the adder The second input is connected to the digital to analog converter;
  • the digital-to-analog converter sets different adjustment voltages according to the row pixel units corresponding to the output signals of the output end of the driving circuit, so that the conduction and closing speeds of the input end and the output end of the driving circuit become larger row by row;
  • An output end of the digital voltage generator is connected to an input end of the driving circuit, and the digital voltage generator sets different output voltages according to the row pixel unit corresponding to the output signal of the output end of the driving circuit, so that the driving circuit is The turn-on and turn-off speeds of the input and output are progressively larger.
  • the driving circuit includes a PMOS transistor and an NMOS transistor, and a control end of the PMOS transistor is connected to an output end of the electric displacement converter, and an output end of the PMOS transistor is connected to the driving The output of the circuit;
  • the control end of the NMOS transistor is connected to the output end of the electric displacement converter, and the output end of the NMOS transistor is connected to the voltage control circuit;
  • An input end of the PMOS transistor is connected to an output end of the voltage control circuit, and/or an input end of the NMOS transistor is connected to an output end of the driving circuit, and is used for a row pixel unit corresponding to an output signal of the output end of the driving circuit.
  • Different adjustment voltages are set to make the on and off speeds of the PMOS and NMOS transistors progressively larger.
  • the driving circuit includes a PMOS transistor and an NMOS transistor, and a control end of the PMOS transistor is connected to an output end of the electric displacement converter, and an output end of the PMOS transistor is connected to the driving The output of the circuit;
  • the control end of the NMOS transistor is connected to the output end of the electric displacement converter, and the output end of the NMOS transistor is connected to the voltage control circuit;
  • the digital voltage generator includes a first output end and a second output end respectively connected to an input end of the PMOS transistor and an input end of the NMOS transistor for corresponding row pixels according to an output signal of an output end of the driving circuit
  • the unit sets different output voltages to make the on and off speeds of the PMOS and NMOS transistors progressively larger.
  • the digital voltage generator is a digital voltage generator of 10 bits or more.
  • the voltage control circuit includes a digital voltage generator, and an output end of the digital voltage generator is connected to an input end of the driving circuit;
  • the digital voltage generator sets different output voltages according to the row pixel units corresponding to the output signals of the output end of the driving circuit, so that the conduction and closing speeds of the input end and the output end of the driving circuit become larger row by row;
  • the digital voltage generator is a digital voltage generator of 10 bits or more.
  • the digital voltage generator includes a first output end and a second output end, respectively connected to an input end of the PMOS transistor and an input end of the NMOS transistor, according to the driving circuit
  • the row pixel unit corresponding to the output signal of the output terminal sets different output voltages to make the on and off speeds of the PMOS tube and the NMOS tube become larger row by row.
  • the pixel driving circuit provided by the present invention also adopts the following technical solutions:
  • a display panel comprising:
  • the gate driving substrate includes a pixel array region and a circuit placement region located at a side of the pixel array region, the pixel array region including a plurality of rows of row pixel units;
  • a plurality of gate driving units disposed on the circuit placement area for outputting scan signals to the row pixel units of the pixel array area;
  • An electric displacement converter electrically connected to the plurality of the gate driving units for outputting a control signal
  • the driving circuit includes an input end, an output end and a control end, and a control end of the driving circuit is connected to an output end of the potential shifter for controlling the turning on and off of the input end and the output end of the driving circuit,
  • the output end of the driving circuit is connected to the row pixel unit through the gate driving unit;
  • a voltage control circuit an output end of the voltage control circuit is connected to an input end of the driving circuit, and the voltage control circuit sets different output voltages to be input to the driving circuit according to a row pixel unit corresponding to an output signal of an output end of the driving circuit
  • the input terminal is such that the on and off speeds of the input end and the output end of the drive circuit become larger row by row.
  • the voltage control circuit includes a digital-to-analog converter and an adder, the output end of the adder is connected to an input end of the driving circuit, and the first input end of the adder is connected to a reference voltage.
  • the second input of the adder is connected to the digital to analog converter;
  • the digital-to-analog converter sets different adjustment voltages according to row pixel units corresponding to the output signals of the output end of the driving circuit, so that the on and off speeds of the input end and the output end of the driving circuit become larger row by row.
  • the driving circuit includes a PMOS transistor and an NMOS transistor, and a control end of the PMOS transistor is connected to an output end of the electric displacement converter, and an output end of the PMOS transistor is connected to the driving The output of the circuit;
  • the control end of the NMOS transistor is connected to the output end of the electric displacement converter, and the output end of the NMOS transistor is connected to the voltage control circuit;
  • An input end of the PMOS transistor is connected to an output end of the voltage control circuit, and/or an input end of the NMOS transistor is connected to an output end of the driving circuit, and is used for a row pixel unit corresponding to an output signal of the output end of the driving circuit.
  • Different adjustment voltages are set to make the on and off speeds of the PMOS and NMOS transistors progressively larger.
  • the voltage control circuit includes a digital voltage generator, and an output end of the digital voltage generator is connected to an input end of the driving circuit;
  • the digital voltage generator sets different output voltages according to the row pixel units corresponding to the output signals of the output end of the driving circuit, so that the on and off speeds of the input end and the output end of the driving circuit become larger row by row.
  • the driving circuit includes a PMOS transistor and an NMOS transistor, and a control end of the PMOS transistor is connected to an output end of the electric displacement converter, and an output end of the PMOS transistor is connected to the driving The output of the circuit;
  • the control end of the NMOS transistor is connected to the output end of the electric displacement converter, and the output end of the NMOS transistor is connected to the voltage control circuit;
  • the digital voltage generator includes a first output end and a second output end respectively connected to an input end of the PMOS transistor and an input end of the NMOS transistor for corresponding row pixels according to an output signal of an output end of the driving circuit
  • the unit sets different output voltages to make the on and off speeds of the PMOS and NMOS transistors progressively larger.
  • the voltage control circuit includes a digital voltage generator, and an output end of the digital voltage generator is connected to an input end of the driving circuit;
  • the digital voltage generator sets different output voltages according to the row pixel units corresponding to the output signals of the output end of the driving circuit, so that the on and off speeds of the input end and the output end of the driving circuit become larger row by row.
  • the digital voltage generator includes a first output end and a second output end, respectively connected to an input end of the PMOS transistor and an input end of the NMOS transistor, according to the driving circuit
  • the row pixel unit corresponding to the output signal of the output terminal sets different output voltages to make the on and off speeds of the PMOS tube and the NMOS tube become larger row by row.
  • the digital voltage generator is a digital voltage generator of 10 bits or more.
  • the invention also provides a control method for the display panel gate signal, and the technical scheme is as follows:
  • a control method for displaying a panel gate signal comprising a gate driving substrate, a plurality of gate driving units, a potential shifter and a driving circuit;
  • the gate driving substrate comprising a pixel array region and located at the a circuit placement area on a side of the pixel array area, the pixel array area includes a plurality of rows of row pixel units;
  • the plurality of gate driving units are disposed on the circuit placement area for outputting a scan signal to the pixel array Row pixel unit of the region;
  • the control method includes:
  • the voltage of the input terminal of the driving circuit is controlled according to the row pixel unit corresponding to the output signal of the output end of the driving circuit, so that the conduction and closing speeds of the input end and the output end of the driving circuit become larger row by row.
  • the method further includes:
  • control terminal of the driving circuit is such that the on and off speeds of the input terminal and the output terminal of the driving circuit become larger row by row.
  • the method further includes:
  • the driving circuit includes a PMOS transistor and an NMOS transistor, and a control end of the PMOS transistor is connected to an output end of the electric displacement converter, and an output end of the PMOS transistor is connected to an output end of the driving circuit;
  • the control end of the NMOS transistor is connected to the output end of the electric displacement converter, and the output end of the NMOS transistor is connected to the voltage control circuit;
  • the method further includes:
  • the method further includes:
  • the driving circuit includes a PMOS transistor and an NMOS transistor, and a control end of the PMOS transistor is connected to an output end of the electric displacement converter, and an output end of the PMOS transistor is connected to an output end of the driving circuit;
  • the control end of the NMOS transistor is connected to the output end of the electric displacement converter, and the output end of the NMOS transistor is connected to the voltage control circuit;
  • the output voltage of the first output terminal of the digital voltage generator is controlled to be gradually decreased
  • the output voltage of the second output terminal of the digital voltage generator is controlled to gradually become larger.
  • the method further includes:
  • the method further includes:
  • the output voltage of the first output terminal of the digital voltage generator is controlled to be gradually decreased
  • the output voltage of the second output terminal of the digital voltage generator is controlled to gradually become larger.
  • setting different input voltages of the driving circuit by using a digital voltage generator includes:
  • Different input voltages are greater than or equal to 1024 different input voltages.
  • the voltage control circuit sets different output voltages to input the input end of the driving circuit according to the row pixel unit corresponding to the output signal of the output end of the driving circuit, so that the The on and off speeds of the input and output terminals of the drive circuit are progressively larger.
  • the CK waveform of the row pixel unit corresponding to each row of the output of the electric displacement converter is transmitted to each row pixel unit, the CK waveforms acquired by the row row pixel units are substantially identical, and the gate signals of the pixel rows of the row driving substrate are turned on.
  • the voltage is consistent, solving the problem of color shift and uneven brightness.
  • FIG. 1 is a schematic structural view of a display panel according to an embodiment of the present invention.
  • FIG. 2 is a schematic diagram of waveforms generated by an electric displacement converter according to an embodiment of the present invention.
  • FIG. 3 is a schematic diagram of a waveform of the waveform of FIG. 2 after reaching a panel;
  • FIG. 4 is a schematic diagram of waveforms generated by a voltage control circuit according to an embodiment of the present invention.
  • FIG. 5 is a schematic diagram of a driving circuit according to an embodiment of the present invention.
  • FIG. 6 is a schematic diagram of a voltage control circuit according to an embodiment of the present invention.
  • FIG. 7 is another schematic diagram of a voltage control circuit according to an embodiment of the present invention.
  • FIG. 8 is a flowchart of a method for controlling a gate signal of a panel according to an embodiment of the present invention.
  • an embodiment of the present invention discloses a display panel including a gate driving substrate 100 , a plurality of gate driving units 130 , an electric displacement converter 140 , a driving circuit 150 , and a voltage control circuit 160 . among them
  • the gate driving substrate 100 includes a pixel array region 110 and a circuit placement region 120 located at a side of the pixel array region, and the pixel array region 110 includes a plurality of rows of row pixel units.
  • a plurality of gate driving units 130 are disposed on the circuit placement region 120 for outputting scan signals to the row pixel units of the pixel array region 110.
  • the electric displacement converter 140 is electrically connected to the plurality of the gate driving units 130 for outputting a control signal.
  • the driving circuit 150 includes an input end, an output end and a control end, and the control end of the driving circuit 150 is connected to the output end of the potential shifter 140 for controlling the turning on and off of the input end and the output end of the driving circuit,
  • the output terminal of the driving circuit 150 is connected to the row pixel unit through the gate driving unit 130.
  • An output end of the voltage control circuit 160 is connected to an input end of the driving circuit 150.
  • the voltage control circuit 160 sets a different output voltage to input the input of the driving circuit 150 according to a row pixel unit corresponding to an output signal of an output end of the driving circuit 150. The end is such that the on and off speeds of the input terminal and the output terminal of the driving circuit 150 become larger row by row.
  • the voltage control circuit 160 sets different output voltages to the input terminals of the driving circuit according to the row pixel units corresponding to the output signals of the output ends of the driving circuit, so that the input and output terminals of the driving circuit are turned on.
  • the closing speed becomes larger row by row.
  • HD High For example, as shown in Figure 2, the 4CK generates a total of 768 pulses and 768 pulse waveforms. As shown in Figure 3, the CK waveforms that can be used in each row of the panel, the pulse waveforms of different rows are getting larger and larger. It can be seen that the longer the trace in the panel, that is, the far end, the more the waveform of the CK is distorted.
  • this embodiment uses an electric displacement transducer (Level Shifter) internal compensation function, adjust the impedance matching of CK output according to the output of different CK lines to make it Level
  • the output of the first line of Shifter is basically the same as the waveform actually used by the last row of panels.
  • the circuit placement area 120 may be disposed on one side or both sides of the pixel array area 110.
  • the voltage control circuit 160 includes a digital-to-analog converter (DAC) 162 and an adder 161, the output of the adder 161 is coupled to an input of a driver circuit, the adder 161 The first input is connected to the reference voltage, and the second input of the adder 161 is connected to the digital-to-analog converter 162;
  • DAC digital-to-analog converter
  • the digital-to-analog converter 162 sets different adjustment voltages according to the row pixel units corresponding to the output signals of the output ends of the driving circuit, so that the on and off speeds of the input end and the output end of the driving circuit become larger row by row.
  • the driving circuit includes a PMOS transistor and an NMOS transistor, and a control end of the PMOS transistor is connected to an output end of the electric displacement converter 140, and an output end of the PMOS transistor is connected to an output end of the driving circuit. ;
  • the control end of the NMOS transistor is connected to the output end of the electric displacement converter 140, the output end of the NMOS transistor is connected to the voltage control circuit 160;
  • An input end of the PMOS transistor is connected to an output end of the voltage control circuit 160, and/or an input end of the NMOS transistor is connected to an output end of the driving circuit, and is used for a row pixel corresponding to an output signal of the output end of the driving circuit.
  • the cells are set with different adjustment voltages to make the on and off speeds of the PMOS and NMOS transistors progressively larger.
  • the DAC When opening different rows of pixel units, use the DAC to generate different voltages to add the Vref reference voltage to generate the required V_Gate signal.
  • the DAC is Negative pressure causes the opening and closing speeds of the rows to gradually increase, and the opening of the NMOS tube is a positive pressure, so that the opening and closing speed of the lower tube is gradually increased.
  • the voltage control circuit 160 includes a digital voltage generator 163, and an output end of the digital voltage generator 163 is connected to an input end of the driving circuit;
  • the digital voltage generator 163 sets different output voltages according to the row pixel units corresponding to the output signals of the output terminals of the driving circuit, so that the on and off speeds of the input end and the output end of the driving circuit become larger row by row.
  • the driving circuit includes a PMOS transistor and an NMOS transistor, and a control end of the PMOS transistor is connected to an output end of the electric displacement converter 140, and an output end of the PMOS transistor is connected to an output end of the driving circuit. ;
  • the control end of the NMOS transistor is connected to the output end of the electric displacement converter 140, the output end of the NMOS transistor is connected to the voltage control circuit 160;
  • the digital voltage generator 163 includes a first output end and a second output end respectively connected to the input end of the PMOS transistor and the input end of the NMOS transistor for corresponding rows according to an output signal of the output end of the driving circuit
  • the pixel unit sets different output voltages to make the on and off speeds of the PMOS and NMOS transistors progressively larger.
  • VGH-VGL internally sets a voltage of 1024 (10bits), and can control different opening speeds by controlling the number of different bits of the PMOS tube to open, and achieve the same compensation effect as the above embodiment, that is, when the PMOS tube is turned on, the output is made.
  • the number of voltage bits is gradually reduced, the impedance is lowered, and the switching speed is increased.
  • the NMOS transistor is turned on, the number of output bits is gradually increased, and the impedance is also lowered to increase the switching speed.
  • bit number digital voltage generators 163 such as 9bit, 11bit, 12bit, 15bit, etc., can also be used.
  • the above embodiment can start at the first line, the switching speed is slow, and the switching speed is gradually increased later, so that the Gate voltages that are turned on in each row are consistent, and the problem of color shift, brightness unevenness (mura) and the like can be solved by this method.
  • an embodiment of the present invention further discloses a method for controlling a gate signal of a display panel, where the display panel includes a gate driving substrate, a plurality of gate driving units, a potential shifter, and a driving circuit;
  • the gate driving substrate includes a pixel array region and a circuit placement region located at a side of the pixel array region, the pixel array region includes a plurality of rows of row pixel units; and the plurality of gate driving units are disposed in the circuit placement region And a row pixel unit for outputting a scan signal to the pixel array area;
  • the control method includes steps S201-S203.
  • S202 connecting a control end of the driving circuit to an output end of the potential shifter for controlling conduction and closing of an input end and an output end of the driving circuit, and connecting an output end of the driving circuit through a gate driving unit Row pixel unit;
  • S203 Control a voltage change at an input end of the driving circuit according to the row pixel unit corresponding to the output signal of the output end of the driving circuit, so that the conduction and closing speeds of the input end and the output end of the driving circuit become larger row by row.
  • the row pixel unit corresponding to the output signal of the output end of the driving circuit different output voltages are input to the input end of the driving circuit, so that the conduction and closing speeds of the input end and the output end of the driving circuit are progressive. Become bigger.
  • the CK waveform of the row pixel unit corresponding to each row of the output of the electric displacement converter is transmitted to each row pixel unit, the CK waveforms acquired by the row row pixel units are substantially identical, and the gate signals of the pixel rows of the row driving substrate are turned on. The voltage is consistent, solving the problem of color shift and uneven brightness.
  • the method further includes: inputting a reference voltage to the first input end of the adder, setting an adjustment voltage according to the row pixel unit corresponding to the output signal of the output end of the driving circuit, and inputting the adjustment voltage to the second input of the adder End, the output end of the adder is connected to the control end of the driving circuit, so that the conduction and closing speeds of the input end and the output end of the driving circuit become larger row by row.
  • the method further includes: the driving circuit includes a PMOS transistor and an NMOS transistor, a control end of the PMOS transistor is connected to an output end of the electric displacement converter, and an output end of the PMOS transistor is connected to the driving The output of the circuit;
  • the control end of the NMOS transistor is connected to the output end of the electric displacement converter, and the output end of the NMOS transistor is connected to the voltage control circuit;
  • the DAC When opening different rows of pixel units, use the DAC to generate different voltages to add the Vref reference voltage to generate the required V_Gate signal.
  • the DAC is Negative pressure causes the opening and closing speeds of the rows to gradually increase, and the opening of the NMOS tube is a positive pressure, so that the opening and closing speed of the lower tube is gradually increased.
  • the method further includes: setting, according to the row pixel unit corresponding to the output signal of the output end of the driving circuit, different input voltages of the driving circuit by using a digital voltage generator, so as to input and output the driving circuit
  • the turn-on and turn-off speeds of the terminals become larger row by row.
  • the method further includes: the driving circuit includes a PMOS transistor and an NMOS transistor, a control end of the PMOS transistor is connected to an output end of the electric displacement converter, and an output end of the PMOS transistor is connected to the driving The output of the circuit;
  • the control end of the NMOS transistor is connected to the output end of the electric displacement converter, and the output end of the NMOS transistor is connected to the voltage control circuit;
  • the output voltage of the first output terminal of the digital voltage generator is controlled to be gradually decreased
  • the output voltage of the second output terminal of the digital voltage generator is controlled to gradually become larger.
  • VGH-VGL internally sets a voltage of 1024 (10bits), and can control different opening speeds by controlling the number of different bits of the PMOS tube to open, and achieve the same compensation effect as the above embodiment, that is, when the PMOS tube is turned on, the output is made.
  • the number of voltage bits is gradually reduced, the impedance is lowered, and the switching speed is increased.
  • the NMOS transistor is turned on, the number of output bits is gradually increased, and the impedance is also lowered to increase the switching speed.
  • bit number digital voltage generators 163 such as 9bit, 11bit, 12bit, 15bit, etc., can also be used.

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Abstract

一种显示面板及显示面板栅极信号的控制方法，显示面板包括：电位移转器(140)、驱动电路(150)和电压控制电路(160)；驱动电路(150)的控制端连接电位转移器(140)的输出端；电压控制电路(160)的输出端连接驱动电路(150)的输入端，电压控制电路(160)根据驱动电路(150)对应的行像素单元，设置不同输出电压，以使驱动电路(150)输入端和输出端的导通和关闭速度逐行变大。

Description

一种显示面板及显示面板栅极信号的控制方法 技术领域
本发明涉及显示技术领域，特别涉及一种显示面板及显示面板栅极信号的控制方法。
 背景技术
现有的显示面板主要包括有液晶(Liquid Crystal Display，LCD)显示面板和OLED(Organic Light Emitting Diode，OLED)显示面板。其中，OLED显示面板具有自发光、驱动电压低、发光效率高、响应时间短、清晰度与对比度高、近180°视角、使用温度范围宽，可实现柔性显示与大面积全色显示等诸多优点，被业界公认为是最有发展潜力的显示面板。
栅极驱动基板（GOA，Gate on array），即使用TFT-LCD内部TFT线路与CB上电位移转器（Level Shifter IC）产生所需要的栅极（Gate）信号，通过此方法可以有效的省略Gate IC，产生降低成本的效益。
但是这种方法会遇到IC内部走线所产生寄生电阻以及电容，特别是远端的电阻与近端的电阻会有极大的差异，导致最终进入面板内部的栅极信号在远近端有极大的差异。
 技术问题
本发明的目的在于提供一种显示面板及显示面板栅极信号的控制方法，解决现有的面板内部的栅极信号在远近端有极大的差异。
 技术解决方案
为达到上述目的，本发明提供的像素驱动电路采用如下技术方案：
一种显示面板，其包括：
栅极驱动基板，所述栅极驱动基板包括像素阵列区以及位于所述像素阵列区侧边的电路放置区，所述像素阵列区包括多行的行像素单元；
多个栅极驱动单元，设置在所述电路放置区上，用于输出扫描信号至所述像素阵列区的行像素单元；
电位移转器，与所述多个所述栅极驱动单元电性连接，用于输出控制信号；
驱动电路，所述驱动电路包括输入端、输出端和控制端，所述驱动电路的控制端连接所述电位转移器的输出端，用于控制驱动电路的输入端和输出端的导通和关闭，所述驱动电路的输出端通过栅极驱动单元连接行像素单元；
电压控制电路，所述电压控制电路的输出端连接所述驱动电路的输入端，所述电压控制电路根据驱动电路输出端的输出信号对应的行像素单元，设置不同的输出电压输入所述驱动电路的输入端，以使所述驱动电路的输入端和输出端的导通和关闭速度逐行变大；
所述电压控制电路包括数字模拟转换器、加法器和数字电压发生器，所述加法器的输出端连接驱动电路的输入端，所述加法器的第一输入端连接基准电压，所述加法器的第二输入端连接数字模拟转换器；
所述数字模拟转换器根据所述驱动电路输出端的输出信号对应的行像素单元，设置不同的调整电压，以使所述驱动电路的输入端和输出端的导通和关闭速度逐行变大；
所述数字电压发生器的输出端连接驱动电路的输入端，所述数字电压发生器根据所述驱动电路输出端的输出信号对应的行像素单元，设置不同的输出电压，以使所述驱动电路的输入端和输出端的导通和关闭速度逐行变大。
在本发明的显示面板中，所述驱动电路包括一个PMOS管和一个NMOS管，所述PMOS管的控制端连接所述电位移转器的输出端，所述PMOS管的输出端连接所述驱动电路的输出端；
所述NMOS管的控制端连接所述电位移转器的输出端，所述NMOS管的输出端连接电压控制电路；
所述PMOS管的输入端连接电压控制电路的输出端，和/或所述NMOS管的输入端连接所述驱动电路的输出端，用于根据所述驱动电路输出端的输出信号对应的行像素单元，设置不同的调整电压，以使所述PMOS管和NMOS管的导通和关闭速度逐行变大。
在本发明的显示面板中，所述驱动电路包括一个PMOS管和一个NMOS管，所述PMOS管的控制端连接所述电位移转器的输出端，所述PMOS管的输出端连接所述驱动电路的输出端；
所述NMOS管的控制端连接所述电位移转器的输出端，所述NMOS管的输出端连接电压控制电路；
所述数字电压发生器包括第一输出端和第二输出端，分别连接所述PMOS管的输入端和所述NMOS管的输入端，用于根据所述驱动电路输出端的输出信号对应的行像素单元，设置不同的输出电压，以使所述PMOS管和NMOS管的导通和关闭速度逐行变大。
在本发明的显示面板中，所述数字电压发生器为大于等于10bit的数字电压发生器。
在本发明的显示面板中，所述电压控制电路包括数字电压发生器，所述数字电压发生器的输出端连接驱动电路的输入端；
所述数字电压发生器根据所述驱动电路输出端的输出信号对应的行像素单元，设置不同的输出电压，以使所述驱动电路的输入端和输出端的导通和关闭速度逐行变大；
所述数字电压发生器为大于等于10bit的数字电压发生器。
在本发明的显示面板中，所述数字电压发生器包括第一输出端和第二输出端，分别连接所述PMOS管的输入端和所述NMOS管的输入端，用于根据所述驱动电路输出端的输出信号对应的行像素单元，设置不同的输出电压，以使所述PMOS管和NMOS管的导通和关闭速度逐行变大。
为达到上述目的，本发明提供的像素驱动电路还采用如下技术方案：
一种显示面板，其包括：
栅极驱动基板，所述栅极驱动基板包括像素阵列区以及位于所述像素阵列区侧边的电路放置区，所述像素阵列区包括多行的行像素单元；
多个栅极驱动单元，设置在所述电路放置区上，用于输出扫描信号至所述像素阵列区的行像素单元；
电位移转器，与所述多个所述栅极驱动单元电性连接，用于输出控制信号；
驱动电路，所述驱动电路包括输入端、输出端和控制端，所述驱动电路的控制端连接所述电位转移器的输出端，用于控制驱动电路的输入端和输出端的导通和关闭，所述驱动电路的输出端通过栅极驱动单元连接行像素单元；
电压控制电路，所述电压控制电路的输出端连接所述驱动电路的输入端，所述电压控制电路根据驱动电路输出端的输出信号对应的行像素单元，设置不同的输出电压输入所述驱动电路的输入端，以使所述驱动电路的输入端和输出端的导通和关闭速度逐行变大。
在本发明的显示面板中，所述电压控制电路包括数字模拟转换器和加法器，所述加法器的输出端连接驱动电路的输入端，所述加法器的第一输入端连接基准电压，所述加法器的第二输入端连接数字模拟转换器；
所述数字模拟转换器根据所述驱动电路输出端的输出信号对应的行像素单元，设置不同的调整电压，以使所述驱动电路的输入端和输出端的导通和关闭速度逐行变大。
在本发明的显示面板中，所述驱动电路包括一个PMOS管和一个NMOS管，所述PMOS管的控制端连接所述电位移转器的输出端，所述PMOS管的输出端连接所述驱动电路的输出端；
所述NMOS管的控制端连接所述电位移转器的输出端，所述NMOS管的输出端连接电压控制电路；
所述PMOS管的输入端连接电压控制电路的输出端，和/或所述NMOS管的输入端连接所述驱动电路的输出端，用于根据所述驱动电路输出端的输出信号对应的行像素单元，设置不同的调整电压，以使所述PMOS管和NMOS管的导通和关闭速度逐行变大。
在本发明的显示面板中，所述电压控制电路包括数字电压发生器，所述数字电压发生器的输出端连接驱动电路的输入端；
所述数字电压发生器根据所述驱动电路输出端的输出信号对应的行像素单元，设置不同的输出电压，以使所述驱动电路的输入端和输出端的导通和关闭速度逐行变大。
在本发明的显示面板中，所述驱动电路包括一个PMOS管和一个NMOS管，所述PMOS管的控制端连接所述电位移转器的输出端，所述PMOS管的输出端连接所述驱动电路的输出端；
所述NMOS管的控制端连接所述电位移转器的输出端，所述NMOS管的输出端连接电压控制电路；
所述数字电压发生器包括第一输出端和第二输出端，分别连接所述PMOS管的输入端和所述NMOS管的输入端，用于根据所述驱动电路输出端的输出信号对应的行像素单元，设置不同的输出电压，以使所述PMOS管和NMOS管的导通和关闭速度逐行变大。
在本发明的显示面板中，所述电压控制电路包括数字电压发生器，所述数字电压发生器的输出端连接驱动电路的输入端；
所述数字电压发生器根据所述驱动电路输出端的输出信号对应的行像素单元，设置不同的输出电压，以使所述驱动电路的输入端和输出端的导通和关闭速度逐行变大。
在本发明的显示面板中，所述数字电压发生器包括第一输出端和第二输出端，分别连接所述PMOS管的输入端和所述NMOS管的输入端，用于根据所述驱动电路输出端的输出信号对应的行像素单元，设置不同的输出电压，以使所述PMOS管和NMOS管的导通和关闭速度逐行变大。
在本发明的显示面板中，所述数字电压发生器为大于等于10bit的数字电压发生器。
本发明还提供了一种显示面板栅极信号的控制方法，技术方案如下：
一种显示面板栅极信号的控制方法，其所述显示面板包括栅极驱动基板、多个栅极驱动单元、电位转移器和驱动电路；所述栅极驱动基板包括像素阵列区以及位于所述像素阵列区侧边的电路放置区，所述像素阵列区包括多行的行像素单元；所述多个栅极驱动单元设置在所述电路放置区上，用于输出扫描信号至所述像素阵列区的行像素单元；
所述控制方法包括：
将所述电位移转器与所述多个所述栅极驱动单元电性连接，用于输出控制信号；
将所述驱动电路的控制端连接所述电位转移器的输出端，用于控制驱动电路的输入端和输出端的导通和关闭，将所述驱动电路的输出端通过栅极驱动单元连接行像素单元；
根据驱动电路输出端的输出信号对应的行像素单元，控制驱动电路的输入端电压变化，以使所述驱动电路的输入端和输出端的导通和关闭速度逐行变大。
在本发明的显示面板栅极信号的控制方法中，该方法还包括：
将基准电压输入加法器的第一输入端，根据所述驱动电路输出端的输出信号对应的行像素单元设置调整电压，将所述调整电压输入加法器第二输入端，将加法器的输出端连接驱动电路的控制端，以使所述驱动电路的输入端和输出端的导通和关闭速度逐行变大。
在本发明的显示面板栅极信号的控制方法中，该方法还包括：
所述驱动电路包括一个PMOS管和一个NMOS管，所述PMOS管的控制端连接所述电位移转器的输出端，所述PMOS管的输出端连接所述驱动电路的输出端；
所述NMOS管的控制端连接所述电位移转器的输出端，所述NMOS管的输出端连接电压控制电路；
当PMOS管打开时，将为负电压的调整电压输入所述加法器第二输入端，且所述调整电压逐渐变小；
当NMOS管打开时，将为正电压的调整电压输入所述加法器第二输入端，且所述调整电压逐渐变大。
在本发明的显示面板栅极信号的控制方法中，该方法还包括：
根据所述驱动电路输出端的输出信号对应的行像素单元，利用数字电压发生器设置所述驱动电路不同的输入电压，以使所述驱动电路的输入端和输出端的导通和关闭速度逐行变大。
在本发明的显示面板栅极信号的控制方法中，该方法还包括：
所述驱动电路包括一个PMOS管和一个NMOS管，所述PMOS管的控制端连接所述电位移转器的输出端，所述PMOS管的输出端连接所述驱动电路的输出端；
所述NMOS管的控制端连接所述电位移转器的输出端，所述NMOS管的输出端连接电压控制电路；
将所述数字电压发生器的第一输出端和第二输出端，分别连接所述PMOS管的输入端和所述NMOS管的输入端；
当PMOS管打开时，控制所述数字电压发生器的第一输出端输出电压逐渐变小；
当NMOS管打开时，控制所述数字电压发生器的第二输出端输出电压逐渐变大。
在本发明的显示面板栅极信号的控制方法中，该方法还包括：
根据所述驱动电路输出端的输出信号对应的行像素单元，利用数字电压发生器设置所述驱动电路不同的输入电压，以使所述驱动电路的输入端和输出端的导通和关闭速度逐行变大。
在本发明的显示面板栅极信号的控制方法中，该方法还包括：
将所述数字电压发生器的第一输出端和第二输出端，分别连接所述PMOS管的输入端和所述NMOS管的输入端；
当PMOS管打开时，控制所述数字电压发生器的第一输出端输出电压逐渐变小；
当NMOS管打开时，控制所述数字电压发生器的第二输出端输出电压逐渐变大。
在本发明的显示面板栅极信号的控制方法中，利用数字电压发生器设置所述驱动电路不同的输入电压包括：
不同的输入电压大于或等于1024种不同的输入电压。
 有益效果
本发明的显示面板及显示面板栅极信号的控制方法，电压控制电路根据驱动电路的输出端的输出信号对应的行像素单元，设置不同的输出电压输入所述驱动电路的输入端，以使所述驱动电路的输入端和输出端的导通和关闭速度逐行变大。使电位移转器输出的对应每一行的行像素单元的CK波形传输到各行行像素单元时，各行行像素单元获取的CK波形基本一致，达到栅极驱动基板各行行像素单元打开的栅极信号电压是一致的，解决色偏，亮度不均匀等问题。
为让本发明的上述内容能更明显易懂，下文特举优选实施例，并配合所附图式，作详细说明如下：
 附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其它有益效果显而易见。
图1为本发明实施例显示面板的结构示意图；
图2为本发明实施例电位移转器产生的波形示意图；
图3为图2中波形到达面板后的波形的示意图；
图4为本发明实施例经电压控制电路控制产生的波形示意图；
图5为本发明实施例驱动电路的示意图；
图6为本发明实施例电压控制电路的示意图；
图7为本发明实施例电压控制电路的另一示意图；
图8为本发明实施例显示面板栅极信号的控制方法的流程图。
 本发明的最佳实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
如图1所示，本发明实施例公开了一种显示面板，该显示面板包括栅极驱动基板100、多个栅极驱动单元130、电位移转器140、驱动电路150和电压控制电路160。其中
所述栅极驱动基板100包括像素阵列区110以及位于所述像素阵列区侧边的电路放置区120，所述像素阵列区110包括多行的行像素单元。多个栅极驱动单元130设置在所述电路放置区120上，用于输出扫描信号至所述像素阵列区110的行像素单元。电位移转器140与所述多个所述栅极驱动单元130电性连接，用于输出控制信号。
驱动电路150包括输入端、输出端和控制端，所述驱动电路150的控制端连接所述电位转移器140的输出端，用于控制驱动电路的输入端和输出端的导通和关闭，所述驱动电路150的输出端通过栅极驱动单元130连接行像素单元。
电压控制电路160的输出端连接所述驱动电路150的输入端，所述电压控制电路160根据驱动电路150输出端的输出信号对应的行像素单元，设置不同的输出电压输入所述驱动电路150的输入端，以使所述驱动电路150的输入端和输出端的导通和关闭速度逐行变大。
本实施例电压控制电路160根据驱动电路的输出端的输出信号对应的行像素单元，设置不同的输出电压输入所述驱动电路的输入端，以使所述驱动电路的输入端和输出端的导通和关闭速度逐行变大。使电位移转器140输出的对应每一行的行像素单元的CK波形传输到各行行像素单元时，各行行像素单元获取的CK波形基本一致，达到栅极驱动基板100各行行像素单元打开的栅极信号电压是一致的，解决色偏，亮度不均匀等问题。
下面以HD（High Definition，高清）机种为例，如图2所示，4CK共产生面板所需要的768个pulse，768个pulse波形一致。如图3所示，面板内各行所能使用到的CK波形，不同行的pulse波形差异越来越大。可以看到，在面板内走线越长，即远端，CK的波形就越失真。
如图4所示，本实施使用电位移转器（Level Shifter）内部补偿作用，将CK的输出根据输出不同CK行时，调整不同的阻抗匹配，使其Level Shifter第一行的输出与最后一行面板实际运用的波形基本一致。
其中可以在像素阵列区110一侧或两侧设置电路放置区120。
如图5和图6所示，所述电压控制电路160包括数字模拟转换器（DAC）162和加法器161，所述加法器161的输出端连接驱动电路的输入端，所述加法器161的第一输入端连接基准电压，所述加法器161的第二输入端连接数字模拟转换器162；
所述数字模拟转换器162根据所述驱动电路输出端的输出信号对应的行像素单元，设置不同的调整电压，以使所述驱动电路的输入端和输出端的导通和关闭速度逐行变大。
进一步的，所述驱动电路包括一个PMOS管和一个NMOS管，所述PMOS管的控制端连接所述电位移转器140的输出端，所述PMOS管的输出端连接所述驱动电路的输出端；
所述NMOS管的控制端连接所述电位移转器140的输出端，所述NMOS管的输出端连接电压控制电路160；
所述PMOS管的输入端连接电压控制电路160的输出端，和/或所述NMOS管的输入端连接所述驱动电路的输出端，用于根据所述驱动电路输出端的输出信号对应的行像素单元，设置不同的调整电压，以使所述PMOS管和NMOS管的导通和关闭速度逐行变大。
控制MOS管的Gate电压即可实现不同的阻抗设定，对于打开不同行像素单元时，使用DAC产生不同的电压以加入Vref基准电压，产生所需要的V_Gate信号，对于PMOS管的打开是DAC为负压，使各行的打开与关闭速度逐渐增加，对于NMOS管的打开是正压，使下管的打开与关闭速度逐渐增加。
如图5和图7所示，所述电压控制电路160包括数字电压发生器163，所述数字电压发生器163的输出端连接驱动电路的输入端；
所述数字电压发生器163根据所述驱动电路输出端的输出信号对应的行像素单元，设置不同的输出电压，以使所述驱动电路的输入端和输出端的导通和关闭速度逐行变大。
进一步的，所述驱动电路包括一个PMOS管和一个NMOS管，所述PMOS管的控制端连接所述电位移转器140的输出端，所述PMOS管的输出端连接所述驱动电路的输出端；
所述NMOS管的控制端连接所述电位移转器140的输出端，所述NMOS管的输出端连接电压控制电路160；
所述数字电压发生器163包括第一输出端和第二输出端，分别连接所述PMOS管的输入端和所述NMOS管的输入端，用于根据所述驱动电路输出端的输出信号对应的行像素单元，设置不同的输出电压，以使所述PMOS管和NMOS管的导通和关闭速度逐行变大。
将VGH-VGL内部设定一个1024(10bits)电压，通过控制PMOS管不同bits数进行打开即可控制不同的打开速度，实现与上述实施方式相同的补偿效果，即在打开PMOS管时，使输出的电压bit数逐渐降低，降低阻抗，使开关速度增加，在打开NMOS管时，使输出bit数逐渐增加，同样降低阻抗，使开关速度增加。当然还可以采用其他bit数的数字电压发生器163，如9bit、11bit、12bit、15bit等。
上述实施方式可以在第一行开始，开关速度是缓慢的，后面逐渐增加开关速度，以达到各行打开的Gate电压是一致的，通过此方法可以解决色偏，亮度不均匀（mura）等问题。
如图8所示，本发明实施例还公开了一种显示面板栅极信号的控制方法，所述显示面板包括栅极驱动基板、多个栅极驱动单元、电位转移器和驱动电路；所述栅极驱动基板包括像素阵列区以及位于所述像素阵列区侧边的电路放置区，所述像素阵列区包括多行的行像素单元；所述多个栅极驱动单元设置在所述电路放置区上，用于输出扫描信号至所述像素阵列区的行像素单元；
所述控制方法包括步骤S201-S203。
S201：将所述电位移转器与所述多个所述栅极驱动单元电性连接，用于输出控制信号；
S202：将所述驱动电路的控制端连接所述电位转移器的输出端，用于控制驱动电路的输入端和输出端的导通和关闭，将所述驱动电路的输出端通过栅极驱动单元连接行像素单元；
S203：根据驱动电路输出端的输出信号对应的行像素单元，控制驱动电路的输入端电压变化，以使所述驱动电路的输入端和输出端的导通和关闭速度逐行变大。
本实施例根据驱动电路的输出端的输出信号对应的行像素单元，设置不同的输出电压输入所述驱动电路的输入端，以使所述驱动电路的输入端和输出端的导通和关闭速度逐行变大。使电位移转器输出的对应每一行的行像素单元的CK波形传输到各行行像素单元时，各行行像素单元获取的CK波形基本一致，达到栅极驱动基板各行行像素单元打开的栅极信号电压是一致的，解决色偏，亮度不均匀等问题。
可选的，该方法还包括：将基准电压输入加法器的第一输入端，根据所述驱动电路输出端的输出信号对应的行像素单元设置调整电压，将所述调整电压输入加法器第二输入端，将加法器的输出端连接驱动电路的控制端，以使所述驱动电路的输入端和输出端的导通和关闭速度逐行变大。
进一步的，该方法还包括：所述驱动电路包括一个PMOS管和一个NMOS管，所述PMOS管的控制端连接所述电位移转器的输出端，所述PMOS管的输出端连接所述驱动电路的输出端；
所述NMOS管的控制端连接所述电位移转器的输出端，所述NMOS管的输出端连接电压控制电路；
当PMOS管打开时，将为负电压的调整电压输入所述加法器第二输入端，且所述调整电压逐渐变小；
当NMOS管打开时，将为正电压的调整电压输入所述加法器第二输入端，且所述调整电压逐渐变大。
控制MOS管的Gate电压即可实现不同的阻抗设定，对于打开不同行像素单元时，使用DAC产生不同的电压以加入Vref基准电压，产生所需要的V_Gate信号，对于PMOS管的打开是DAC为负压，使各行的打开与关闭速度逐渐增加，对于NMOS管的打开是正压，使下管的打开与关闭速度逐渐增加。
可选的，该方法还包括：根据所述驱动电路输出端的输出信号对应的行像素单元，利用数字电压发生器设置所述驱动电路不同的输入电压，以使所述驱动电路的输入端和输出端的导通和关闭速度逐行变大。
进一步的，该方法还包括：所述驱动电路包括一个PMOS管和一个NMOS管，所述PMOS管的控制端连接所述电位移转器的输出端，所述PMOS管的输出端连接所述驱动电路的输出端；
所述NMOS管的控制端连接所述电位移转器的输出端，所述NMOS管的输出端连接电压控制电路；
将所述数字电压发生器的第一输出端和第二输出端，分别连接所述PMOS管的输入端和所述NMOS管的输入端；
当PMOS管打开时，控制所述数字电压发生器的第一输出端输出电压逐渐变小；
当NMOS管打开时，控制所述数字电压发生器的第二输出端输出电压逐渐变大。
将VGH-VGL内部设定一个1024(10bits)电压，通过控制PMOS管不同bits数进行打开即可控制不同的打开速度，实现与上述实施方式相同的补偿效果，即在打开PMOS管时，使输出的电压bit数逐渐降低，降低阻抗，使开关速度增加，在打开NMOS管时，使输出bit数逐渐增加，同样降低阻抗，使开关速度增加。当然还可以采用其他bit数的数字电压发生器163，如9bit、11bit、12bit、15bit等。
综上，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种显示面板，其包括：
    栅极驱动基板，所述栅极驱动基板包括像素阵列区以及位于所述像素阵列区侧边的电路放置区，所述像素阵列区包括多行的行像素单元；
    多个栅极驱动单元，设置在所述电路放置区上，用于输出扫描信号至所述像素阵列区的行像素单元；
    电位移转器，与所述多个所述栅极驱动单元电性连接，用于输出控制信号；
    驱动电路，所述驱动电路包括输入端、输出端和控制端，所述驱动电路的控制端连接所述电位转移器的输出端，用于控制驱动电路的输入端和输出端的导通和关闭，所述驱动电路的输出端通过栅极驱动单元连接行像素单元；
    电压控制电路，所述电压控制电路的输出端连接所述驱动电路的输入端，所述电压控制电路根据驱动电路输出端的输出信号对应的行像素单元，设置不同的输出电压输入所述驱动电路的输入端，以使所述驱动电路的输入端和输出端的导通和关闭速度逐行变大；
    所述电压控制电路包括数字模拟转换器、加法器和数字电压发生器，所述加法器的输出端连接驱动电路的输入端，所述加法器的第一输入端连接基准电压，所述加法器的第二输入端连接数字模拟转换器；
    所述数字模拟转换器根据所述驱动电路输出端的输出信号对应的行像素单元，设置不同的调整电压，以使所述驱动电路的输入端和输出端的导通和关闭速度逐行变大；
    所述数字电压发生器的输出端连接驱动电路的输入端，所述数字电压发生器根据所述驱动电路输出端的输出信号对应的行像素单元，设置不同的输出电压，以使所述驱动电路的输入端和输出端的导通和关闭速度逐行变大。
  2. 根据权利要求1所述的显示面板，其中所述驱动电路包括一个PMOS管和一个NMOS管，所述PMOS管的控制端连接所述电位移转器的输出端，所述PMOS管的输出端连接所述驱动电路的输出端；
    所述NMOS管的控制端连接所述电位移转器的输出端，所述NMOS管的输出端连接电压控制电路；
    所述PMOS管的输入端连接电压控制电路的输出端，和/或所述NMOS管的输入端连接所述驱动电路的输出端，用于根据所述驱动电路输出端的输出信号对应的行像素单元，设置不同的调整电压，以使所述PMOS管和NMOS管的导通和关闭速度逐行变大。
  3. 根据权利要求1所述的显示面板，其中所述驱动电路包括一个PMOS管和一个NMOS管，所述PMOS管的控制端连接所述电位移转器的输出端，所述PMOS管的输出端连接所述驱动电路的输出端；
    所述NMOS管的控制端连接所述电位移转器的输出端，所述NMOS管的输出端连接电压控制电路；
    所述数字电压发生器包括第一输出端和第二输出端，分别连接所述PMOS管的输入端和所述NMOS管的输入端，用于根据所述驱动电路输出端的输出信号对应的行像素单元，设置不同的输出电压，以使所述PMOS管和NMOS管的导通和关闭速度逐行变大。
  4. 根据权利要求1所述的显示面板，其中所述数字电压发生器为大于等于10bit的数字电压发生器。
  5. 一种显示面板，其包括：
    栅极驱动基板，所述栅极驱动基板包括像素阵列区以及位于所述像素阵列区侧边的电路放置区，所述像素阵列区包括多行的行像素单元；
    多个栅极驱动单元，设置在所述电路放置区上，用于输出扫描信号至所述像素阵列区的行像素单元；
    电位移转器，与所述多个所述栅极驱动单元电性连接，用于输出控制信号；
    驱动电路，所述驱动电路包括输入端、输出端和控制端，所述驱动电路的控制端连接所述电位转移器的输出端，用于控制驱动电路的输入端和输出端的导通和关闭，所述驱动电路的输出端通过栅极驱动单元连接行像素单元；
    电压控制电路，所述电压控制电路的输出端连接所述驱动电路的输入端，所述电压控制电路根据驱动电路输出端的输出信号对应的行像素单元，设置不同的输出电压输入所述驱动电路的输入端，以使所述驱动电路的输入端和输出端的导通和关闭速度逐行变大。
  6. 根据权利要求5所述的显示面板，其中所述电压控制电路包括数字模拟转换器和加法器，所述加法器的输出端连接驱动电路的输入端，所述加法器的第一输入端连接基准电压，所述加法器的第二输入端连接数字模拟转换器；
    所述数字模拟转换器根据所述驱动电路输出端的输出信号对应的行像素单元，设置不同的调整电压，以使所述驱动电路的输入端和输出端的导通和关闭速度逐行变大。
  7. 根据权利要求6所述的显示面板，其中所述驱动电路包括一个PMOS管和一个NMOS管，所述PMOS管的控制端连接所述电位移转器的输出端，所述PMOS管的输出端连接所述驱动电路的输出端；
    所述NMOS管的控制端连接所述电位移转器的输出端，所述NMOS管的输出端连接电压控制电路；
    所述PMOS管的输入端连接电压控制电路的输出端，和/或所述NMOS管的输入端连接所述驱动电路的输出端，用于根据所述驱动电路输出端的输出信号对应的行像素单元，设置不同的调整电压，以使所述PMOS管和NMOS管的导通和关闭速度逐行变大。
  8. 根据权利要求5所述的显示面板，其中所述电压控制电路包括数字电压发生器，所述数字电压发生器的输出端连接驱动电路的输入端；
    所述数字电压发生器根据所述驱动电路输出端的输出信号对应的行像素单元，设置不同的输出电压，以使所述驱动电路的输入端和输出端的导通和关闭速度逐行变大。
  9. 根据权利要求8所述的显示面板，其中所述驱动电路包括一个PMOS管和一个NMOS管，所述PMOS管的控制端连接所述电位移转器的输出端，所述PMOS管的输出端连接所述驱动电路的输出端；
    所述NMOS管的控制端连接所述电位移转器的输出端，所述NMOS管的输出端连接电压控制电路；
    所述数字电压发生器包括第一输出端和第二输出端，分别连接所述PMOS管的输入端和所述NMOS管的输入端，用于根据所述驱动电路输出端的输出信号对应的行像素单元，设置不同的输出电压，以使所述PMOS管和NMOS管的导通和关闭速度逐行变大。
  10. 根据权利要求8所述的显示面板，其中所述数字电压发生器为大于等于10bit的数字电压发生器。
  11. 根据权利要求7所述的显示面板，其中所述电压控制电路包括数字电压发生器，所述数字电压发生器的输出端连接驱动电路的输入端；
    所述数字电压发生器根据所述驱动电路输出端的输出信号对应的行像素单元，设置不同的输出电压，以使所述驱动电路的输入端和输出端的导通和关闭速度逐行变大；
    所述数字电压发生器为大于等于10bit的数字电压发生器。
  12. 根据权利要求11所述的显示面板，其中所述数字电压发生器包括第一输出端和第二输出端，分别连接所述PMOS管的输入端和所述NMOS管的输入端，用于根据所述驱动电路输出端的输出信号对应的行像素单元，设置不同的输出电压，以使所述PMOS管和NMOS管的导通和关闭速度逐行变大。
  13. 一种显示面板栅极信号的控制方法，其所述显示面板包括栅极驱动基板、多个栅极驱动单元、电位转移器和驱动电路；所述栅极驱动基板包括像素阵列区以及位于所述像素阵列区侧边的电路放置区，所述像素阵列区包括多行的行像素单元；所述多个栅极驱动单元设置在所述电路放置区上，用于输出扫描信号至所述像素阵列区的行像素单元；
    所述控制方法包括：
    将所述电位移转器与所述多个所述栅极驱动单元电性连接，用于输出控制信号；
    将所述驱动电路的控制端连接所述电位转移器的输出端，用于控制驱动电路的输入端和输出端的导通和关闭，将所述驱动电路的输出端通过栅极驱动单元连接行像素单元；
    根据驱动电路输出端的输出信号对应的行像素单元，控制驱动电路的输入端电压变化，以使所述驱动电路的输入端和输出端的导通和关闭速度逐行变大。
  14. 根据权利要求13所述的显示面板栅极信号的控制方法，其中该方法还包括：
    将基准电压输入加法器的第一输入端，根据所述驱动电路输出端的输出信号对应的行像素单元设置调整电压，将所述调整电压输入加法器第二输入端，将加法器的输出端连接驱动电路的控制端，以使所述驱动电路的输入端和输出端的导通和关闭速度逐行变大。
  15. 根据权利要求14所述的显示面板栅极信号的控制方法，其中该方法还包括：
    所述驱动电路包括一个PMOS管和一个NMOS管，所述PMOS管的控制端连接所述电位移转器的输出端，所述PMOS管的输出端连接所述驱动电路的输出端；
    所述NMOS管的控制端连接所述电位移转器的输出端，所述NMOS管的输出端连接电压控制电路；
    当PMOS管打开时，将为负电压的调整电压输入所述加法器第二输入端，且所述调整电压逐渐变小；
    当NMOS管打开时，将为正电压的调整电压输入所述加法器第二输入端，且所述调整电压逐渐变大。
  16. 根据权利要求13所述的显示面板栅极信号的控制方法，其中该方法还包括：
    根据所述驱动电路输出端的输出信号对应的行像素单元，利用数字电压发生器设置所述驱动电路不同的输入电压，以使所述驱动电路的输入端和输出端的导通和关闭速度逐行变大。
  17. 根据权利要求16所述的显示面板栅极信号的控制方法，其中该方法还包括：
    所述驱动电路包括一个PMOS管和一个NMOS管，所述PMOS管的控制端连接所述电位移转器的输出端，所述PMOS管的输出端连接所述驱动电路的输出端；
    所述NMOS管的控制端连接所述电位移转器的输出端，所述NMOS管的输出端连接电压控制电路；
    将所述数字电压发生器的第一输出端和第二输出端，分别连接所述PMOS管的输入端和所述NMOS管的输入端；
    当PMOS管打开时，控制所述数字电压发生器的第一输出端输出电压逐渐变小；
    当NMOS管打开时，控制所述数字电压发生器的第二输出端输出电压逐渐变大。
  18. 根据权利要求16所述的显示面板栅极信号的控制方法，其中利用数字电压发生器设置所述驱动电路不同的输入电压包括：
    不同的输入电压大于或等于1024种不同的输入电压。
  19. 根据权利要求15所述的显示面板栅极信号的控制方法，其中该方法还包括：
    根据所述驱动电路输出端的输出信号对应的行像素单元，利用数字电压发生器设置所述驱动电路不同的输入电压，以使所述驱动电路的输入端和输出端的导通和关闭速度逐行变大。
  20. 根据权利要求19所述的显示面板栅极信号的控制方法，其中该方法还包括：
    将所述数字电压发生器的第一输出端和第二输出端，分别连接所述PMOS管的输入端和所述NMOS管的输入端；
    当PMOS管打开时，控制所述数字电压发生器的第一输出端输出电压逐渐变小；
    当NMOS管打开时，控制所述数字电压发生器的第二输出端输出电压逐渐变大。
PCT/CN2017/109529 2017-07-19 2017-11-06 一种显示面板及显示面板栅极信号的控制方法 WO2019015171A1 (zh)

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