WO2019015074A1 - 显示面板的驱动方法及驱动装置 - Google Patents

显示面板的驱动方法及驱动装置 Download PDF

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Publication number
WO2019015074A1
WO2019015074A1 PCT/CN2017/102462 CN2017102462W WO2019015074A1 WO 2019015074 A1 WO2019015074 A1 WO 2019015074A1 CN 2017102462 W CN2017102462 W CN 2017102462W WO 2019015074 A1 WO2019015074 A1 WO 2019015074A1
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Prior art keywords
data line
output signal
data
falling edge
fan
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PCT/CN2017/102462
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English (en)
French (fr)
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胡水秀
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惠科股份有限公司
重庆惠科金渝光电科技有限公司
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Priority to US16/631,112 priority Critical patent/US10984720B2/en
Publication of WO2019015074A1 publication Critical patent/WO2019015074A1/zh

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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
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    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a driving method and a driving device for a display panel.
  • the thin film transistor liquid crystal display (TFT-LCD) technology needs to perform the layout processing of the output line of the driver IC in the bonding area when performing the matrix design of the display panel. Fan-out layout. Therefore, the distance that the driver IC outputs to each data line in the display area is not equal, so that the impedance of each data line in the fan-out area cannot be agreed, and the degree of RC delay of each data line is different, and finally On the same scan line, the effective charging time of the pixels driven by each data line is inconsistent resulting in a color shift.
  • TFT-LCD thin film transistor liquid crystal display
  • the traditional solution for improving the color shift includes making the trace of the data line on the fan-out area into a copper material, which is costly in the TFT-LCD process. It also includes reducing the number of output channels per driver IC. In this scheme, the data lines required for the entire panel are fixed due to the panel resolution, and reducing the number of output channels per driver IC will cause the driver IC. The increase in the number of costs has led to an increase in costs.
  • a driving method of a display panel includes:
  • the data line includes a first data line and a second data line;
  • the detecting data line is before the voltage change delay time of the fan-out area, and includes the steps of:
  • the step of detecting a voltage change delay time of the data line in the fan-out area includes:
  • the voltage change delay time of the trace is calculated according to the trace impedance.
  • the step of adjusting the data output signal of the data line according to the voltage change delay time comprises:
  • the data output signal falling edge time of the first data line and the second data line are kept the same;
  • the falling edge time of the data output signal for controlling the first data line is delayed.
  • the step of adjusting the scan line driving voltage signal according to the data output signal to make the effective charging time of the pixels driven by the different data lines consistent includes:
  • first data line is advanced relative to the falling edge time of the data output signal of the second data line, inputting the scan line driving voltage signal according to the falling edge time of the data output signal of the first data line;
  • the scan line driving voltage signal is input according to the falling edge time of the data output signal of the second data line.
  • a driving device for a display panel includes a detecting module, a timing module, and an adjusting module. among them:
  • a setting module configured to select a second data line, and set a data output signal of the second data line
  • a detecting module configured to detect a voltage change delay time of the data line in the fan-out area
  • a time control module configured to control a data output signal of the data line according to the voltage change delay time
  • an adjustment module configured to adjust the scan line driving voltage signal according to the data output signal, so that the effective charging time of the pixels driven by the first data line and the second data line are consistent.
  • the detection module includes a measurement unit and a calculation unit, wherein:
  • the measuring unit is configured to measure a length of a trace of the first data line and the second data line on a fan-out area
  • the calculating unit is configured to calculate a trace impedance according to the trace length, and calculate a voltage change delay time according to the trace impedance.
  • the time control module includes a comparison unit and a time shift unit, wherein:
  • a comparison unit configured to compare a voltage change delay time of the first data line and the second data line in a fan-out area
  • a time shifting unit configured to control an output signal falling edge time of the first data line to be advanced or delayed
  • the falling edge time of the data output signal of the data line is kept the same
  • the falling edge time of the data output signal for controlling the first data line is delayed.
  • the adjustment module includes a determination unit and an input unit, wherein:
  • a comparing unit configured to compare a falling edge time of the data output signal of the first data line with respect to the second data line.
  • first data line is advanced relative to the falling edge time of the data output signal of the second data line, inputting the scan line driving voltage signal according to the falling edge time of the data output signal of the first data line;
  • the scan line driving voltage signal is input according to the falling edge time of the data output signal of the second data line.
  • a driving method of the display panel further includes:
  • Determining whether the length of the trace is greater than a preset value if yes, controlling a falling edge time of the data output signal of the data line is advanced; otherwise, controlling a falling edge time of the data output signal of the data line is delayed;
  • the driving method and the driving device of the above display panel improve the color shift problem caused by the difference in voltage variation delay by changing the falling edge time of the data output signal on different data lines, Increased the optical quality of the product. Moreover, this method does not change process requirements and product costs.
  • FIG. 1 is a flow chart of a driving method of a display panel according to an embodiment
  • FIG. 2 is a flow chart of an implementation method of step S100 in FIG. 1;
  • FIG. 3 is a flowchart of an implementation method of step S200 in FIG. 1;
  • step S300 in FIG. 1 is a flowchart of an implementation method of step S300 in FIG. 1;
  • FIG. 5 is a block diagram showing the structure of a driving device of a display panel according to an embodiment
  • FIG. 6 is a structural block diagram of the module 120 of FIG. 5;
  • FIG. 7 is a structural block diagram of the module 130 of FIG. 5;
  • FIG. 8 is a structural block diagram of the module 140 of FIG. 5;
  • FIG. 9 is a schematic diagram of a display device of a display panel according to an embodiment.
  • FIG. 10 is a schematic diagram showing the arrangement of pixels of the display area 500 in FIG. 9;
  • FIG. 11 is a schematic diagram of a voltage variation delay of the data line of FIG. 9;
  • FIG. 12 is a schematic diagram showing the relationship between the data output signal, the data line, and the scanning direction in FIG. 9;
  • FIG. 13 is a flow chart showing a driving method of a display panel according to another embodiment.
  • 1 is a flow chart of a driving method of a display panel according to an embodiment, the method includes:
  • Step S100 Detecting a voltage change delay time of the data line in the fan-out area. Since the TFT-LCD is designed for the pixel matrix, it is necessary to arrange the output lines of the driver IC in the nip area for centralized layout processing, and the processing method is the fan-out layout. Therefore, the distance that the driver IC outputs to each data line in the display area is not equal, so that the impedances of the data lines in the fan-out area cannot be agreed, and the delay time of the voltage change of each data line is different.
  • the data line is divided into a first data line and a second data line, wherein the first data line is a data line that needs to be improved in the color-shifted area, and the second data line is distributed in an ideal area of the picture display.
  • Data line is divided into a first data line and a second data line, wherein the first data line is a data line that needs to be improved in the color-shifted area, and the second data line is distributed in an ideal area of the picture display.
  • Step S200 Control the data output signal of the data line according to the voltage change delay time.
  • the data output signal is the output signal of the data from the driver IC to the display area, that is, the TP signal. Since the delay time of the trace voltage change of the first data line and the second data line in the fan-out area is different, if the falling edge time of the data output signal of the first data line is the same as the falling edge time of the data output signal of the second data line, The effective charging time of the pixels corresponding to the first data line and the second data line will be inconsistent on the same scan line, thereby causing color shift. Therefore, their effective charging times can be made uniform by controlling the relative transition of the data output signals of the first data line and the second data line relative to each other, such as advance or postponement.
  • Step S300 Adjust the scan line driving voltage signal according to the data output signal, so that the effective charging time of the pixels driven by the different data lines on the same scan line is consistent.
  • the scan line driving voltage signal is provided by the scan line driver IC, and its function is to drive the display panel by controlling a thin film transistor (TFT) switch.
  • TFT thin film transistor
  • the effective charging times of the pixels corresponding to the first data line and the second data line are identical on the same scanning line, and the scanning line driving voltage signals are matched to make their charging efficiency. Equal, thus improving the picture display color shift problem.
  • the method further includes the steps of: selecting the second data line, and setting a falling edge time of the data output signal of the second data line.
  • the second data line here may be any one of the output lines of the driver IC, and the second data line represents the display of the ideal picture according to the screen display requirement.
  • the voltage change delay time of the second data line is a preset degree; and the effective charging time of the pixels on the second data line is a preset effective charging time.
  • the voltage change delay time and the effective charging time have a one-to-one correspondence, so that the effective charging time of the pixels on the first data line can be obtained according to the voltage variation delay time of detecting the first data line, and according to the pixels on the second data line.
  • the effective charging time sets the falling edge time of the data output signal of the first data line. For example, on the same scan line, when the effective charging time of the pixels on the first data line is longer than the effective charging time of the pixels on the second data line, the data output signal falling edge time of the first data line is postponed; When the effective charging time of the pixels on the first data line is shorter than the effective charging time of the pixels on the second data line, the data output signal of the first data line is advanced by the falling edge time.
  • step S100 includes the following steps:
  • Step S110 measuring the length of the trace of the first data line and the second data line on the fan-out area.
  • Step S120 Calculate the trace impedance according to the length of the trace.
  • Step S130 Calculate the voltage change delay time of the trace according to the trace impedance.
  • calculating the voltage variation delay time of the trace further determines parameters: a charging capacitor (C), a voltage between the charging capacitor and the impedance (V0), and a voltage (V1) when the charging capacitor is completed.
  • the delay time of the voltage change of the trace is:
  • step S200 includes the following steps:
  • Step S210 Comparing the voltage change delay time of the first data line and the second data line in the fan-out area.
  • Step S220 If the voltage change delay time of the first data line in the fan-out area is greater than the voltage change delay time of the second data line in the fan-out area, the falling edge time of the data output signal of the control first data line is advanced.
  • Step S230 If the voltage change delay time of the first data line in the fan-out area is equal to the voltage change delay time of the second data line in the fan-out area, the data output signal falling edge time of the first data line and the second data line is maintained. the same.
  • Step S240 If the voltage change delay time of the first data line in the fan-out area is less than the voltage change delay time of the second data line in the fan-out area, the falling edge time of the data output signal of the control first data line is delayed.
  • the voltage change delay time is the voltage change delay time
  • the effective charging time can be determined by the voltage change delay time, and the falling edge time of the data output signal of the first data line and the second data line can be adjusted. Make the effective charging times of the pixels on the same scan line they drive consistent.
  • step S300 includes the following steps:
  • Step S310 Comparing the falling edge time of the data output signal of the first data line with respect to the second data line.
  • Step S320 If the first data line is advanced relative to the falling edge time of the data output signal of the second data line, the scan line driving voltage signal is input according to the falling edge time of the data output signal of the first data line.
  • Step S330 If the data output signal of the first data line and the second data line have the same falling edge time, input the scan line driving voltage signal according to the falling edge time of the data output signal.
  • Step S334 If the falling edge time of the data output signal of the first data line relative to the second data line is delayed, inputting the scan line driving voltage signal according to the falling edge time of the data output signal of the second data line.
  • the scan line driving voltage signal is emitted by the scan line driving chip, and its function is to control the TFT switch, thereby controlling the charge and discharge of the pixel.
  • the TFT switches in the row of the scan line are turned on at the same time, and the pixels of the row are charged to their respective required voltages.
  • the scan line driving voltage signal should be an input standard according to the data line whose leading edge of the data output signal falls. That is, when the data line voltage signal of the leading edge of the falling edge of the data output signal is input, the scan line driving voltage signal is simultaneously input to cause the data output signal to be charged along the data line of the previous time.
  • FIG. 5 is a structural block diagram of a driving device of a display panel according to an embodiment.
  • the driving device 100 of the display panel includes: a setting module 110, a detecting module 120, a timing module 130, and an adjusting module 140.
  • the setting module 110 is configured to select a second data line and set a data output signal of the second data line.
  • the detecting module 120 is configured to detect a voltage change delay time of the first data line and the second data line in the fan-out area.
  • the time control module 130 is configured to control data output signals of the first data line and the second data line according to a voltage change delay time.
  • the adjusting module 140 is configured to adjust the scan line driving voltage signal according to the data output signal, so that the effective charging time of the pixels driven by the first data line and the second data line are consistent on the same scan line.
  • the driving device 100 of the display panel detects the voltage change delay time of each of the data lines in the fan-out area by unequal distances, and then determines the effective charging time of the pixels on each data line from the voltage change delay time. Then, according to the effective charging time, the falling edge time of the data output signal of each data line is controlled, and finally, the waveforms of the driving voltage signals of the scanning lines are adjusted to make their effective charging efficiency uniform.
  • the driving device 100 of the display panel avoids: the use of copper material for data line routing, resulting in TFT-LCD process modification and process yield problems, and also includes cost increase problems; reducing the output of each data line driver chip The number of channels leads to an increase in the number of data line driver chips, which in turn increases the cost.
  • the detection module 120 includes a measurement unit 121 and a calculation unit 122.
  • a measuring unit 121 configured to measure a length of a trace of the first data line and the second data line on the fan-out area
  • the calculating unit 122 is configured to calculate a trace impedance according to the length of the trace, and calculate a voltage change delay time according to the trace impedance.
  • the measuring unit 121 is further configured to detect the charging capacitor (C), the voltage between the charging capacitor and the impedance (V0), and the voltage (V1) when the charging capacitor is completed.
  • the calculating unit 122 calculates the trace impedance R and the voltage change delay time according to the parameters detected by the detecting unit:
  • the time control module 130 includes a comparison unit 131 and a time shift unit 132.
  • the comparing unit 131 is configured to compare the voltage change delay time of the first data line and the second data line in the fan-out area.
  • the time shifting unit 132 is configured to control the falling edge time of the data output signal of the first data line to be advanced or delayed.
  • the falling edge time of the data output signal of the control first data line is advanced.
  • the data output signal falling edge time of the first data line and the second data line are kept the same.
  • the falling edge time of the data output signal for controlling the first data line is delayed.
  • the voltage change delay time is the voltage change delay time
  • the effective charging time can be determined by the voltage change delay time, and the falling edge time of the data output signal of the first data line and the second data line can be adjusted.
  • the time shifting unit 132 is a timing controller (TCON), and the timing controller can control the output signal (data output signal) of the data from the scan line driving chip to the display screen, that is, the timing controller realizes the data by programming.
  • the output signal is advanced or delayed by the falling edge time.
  • the adjustment module 140 includes a comparison unit 141 and an input unit 142.
  • the comparing unit 141 is configured to compare the falling edge time of the data output signal of the first data line with respect to the second data line.
  • An input unit 142 configured to input a scan line driving voltage signal
  • the scan line driving voltage signal is input according to the falling edge time of the data output signal of the first data line.
  • the scan line driving voltage signal is input according to the falling edge time of the data output signal.
  • the scan line driving voltage signal is input according to the falling edge time of the data output signal of the second data line.
  • the driving method of the above display panel is applied to a display device.
  • FIG. 9 the figure is a schematic diagram of a display device of a display panel according to an embodiment.
  • the display device includes two data line driving chips 200, three scanning line driving chips 300, and a display panel.
  • the data line driving chip 200 outputs a plurality of data lines, which are respectively Data 1, Data 2, ..., and Data n; and the scanning line driving chip 300 outputs a plurality of scanning lines Gate 1, Gate 2, ..., and Gate n ( Not shown in the figure).
  • the display panel can be divided into a fan-out area 400 and a display area 500 according to the wiring pattern of the data lines.
  • the lengths of the traces of the data lines are different, the data lines at the center of the data line driver chip are the shortest, and the lengths of the data lines from the center to the sides are sequentially increased; in the display area, the data lines The length of the trace is the same.
  • the figure is a schematic diagram of a pixel arrangement of the display area 500 in FIG.
  • the pixel unit of the display panel includes three sub-pixels having three different colors of red (R), green (G), and blue (B), and each pixel unit is provided with one data line and three scan lines. Further, each sub-pixel is driven by a corresponding scan line; each pixel unit is driven by a corresponding data line.
  • the pixel unit P1 is provided with the data line Data 1 and the scan lines Gate 1, Gate 2, and Gate 3.
  • the data line Data 1 is used to input color data information; the scan lines Gate 1, Gate 2, and Gate 3 are respectively used to control the TFT switches of the blue (B), green (G), and red (R) sub-pixels in the pixel unit. Tube, which in turn controls the writing of color data information.
  • the voltage variation delays of different data lines are different, when the data information of the mixed color picture is controlled, the longer data lines are insufficiently charged, resulting in insufficient writing of some colors, so the screen display chromatic aberration.
  • the figure is a schematic diagram of the voltage variation delay of the data lines Data 1 and Data n/4 in FIG. Since the data line Data 1 is away from the center position of the data line driving chip 200, the data line Data n/4 is located at the center position of the data line driving chip 200. Therefore, the trace of the data line Data 1 in the fan-out area 400 is longer than the data line Data n/4, and the corresponding impedance is also large, and the influence of the voltage variation delay generated is also more serious, resulting in lower charging efficiency.
  • the area of the horizontal shadow portion represents the charging efficiency of the green (G) sub-pixel
  • the area of the hatched portion of the vertical line represents the charging efficiency of the red (R) sub-pixel
  • the area of the horizontal shadow portion of the data line Data 1 is smaller than the data line Data n
  • the lateral shadow portion area of /4 that is, the charging efficiency of the green (G) sub-pixel of the data line Data 1 is lower than the charging efficiency of the green (G) sub-pixel of the data line Data n/4.
  • the green (G) data information of the data line Data 1 may be insufficiently written due to insufficient charging efficiency, and the data line Data n/4 Compared with the area, it is yellowish red.
  • the figure is a schematic diagram of the relationship between the data output signal, the data line, and the scan line in FIG.
  • the data output signal corresponding to the data line Data 1 is TP1
  • the data output signal corresponding to the data line Data n/4 is TPn/4.
  • the falling edge time of the output signal is earlier than the falling edge time of the data output signal of the data line Data n/4, so when the falling edge time of the data output signal of the data line Data 1 comes, the scanning line Gata 2 inputs the driving voltage signal, and then the data line Data 1 Write green (G) data information.
  • the scanning line Gata 2 driving voltage signal is turned off, the scanning line Gata 3 inputs the driving voltage signal, and then the data line Data 1 starts writing the red (R) data information.
  • the data line Data n/4 also performs the color writing process described above after the data line Data1.
  • the shaded area of the horizontal line is the charging efficiency of the green (G) data information
  • the shaded area of the vertical line is the charging efficiency of the red (R) data information.
  • the display device may be a display device of a Tri-Gate drive architecture, and the pixels are arranged in a RGB dot-reverse vertical arrangement, but are not limited thereto.
  • the driving method of the display panel of the present disclosure can also be applied to other display devices and display panels, such as: LCD display (Liquid Crystal Display) panels, OLED (Organic Light Emitting Diode) display panels, curved display panels, or Other display panels.
  • the display device when the display device is a liquid crystal display device, the display device may be a TN, OCB, VA type or curved liquid crystal display device, but is not limited thereto.
  • the liquid crystal display device can use a direct backlight, and the backlight can be a white light, an RGB three-color light source, a WRGB four-color light source or a YRGB four-color light source, but is not limited thereto.
  • the driving method of the display panel further includes:
  • Step S100' detecting the length of the trace of the data line in the fan-out area.
  • the lengths of the traces of the data lines of the display panel in the fan-out area are not equal, and the lengths of the traces are related to their arrangement positions in the fan-out area. If the display panel has two source drivers, respectively driving the left half and the right half of the display panel, the data lines are routed in the middle and on both sides of the fan-out area.
  • Step S200' determining whether the length of the trace is greater than a preset value, if yes, executing step S300a, otherwise performing step S300b.
  • the length of the data line trace corresponding to the sub-pixel whose image display effect is ideal is used as a preset value.
  • Step S300a Controlling the falling edge time of the data output signal of the data line is advanced.
  • Step S300b Controlling the falling edge time of the data output signal of the data line is delayed.
  • Step S400' adjusting the scan line driving voltage signal according to the falling edge time of the data output signal, so that the effective charging times of the pixels driven by the different data lines are consistent.
  • the driving method and the driving device of the above display panel improve the color shift problem caused by the difference in voltage variation delay by changing the falling edge time of the data output signal on different data lines, thereby improving the optical quality of the product. Moreover, this method does not change process requirements and product costs.
  • the disclosed systems, devices, and/or methods may be implemented in other ways.
  • the device embodiments described above are merely illustrative.
  • the division of the unit is only a logical function division.
  • there may be another division manner for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored or not executed.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, and may be in an electrical, mechanical or other form.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. You can choose some or all of them according to actual needs.
  • the unit is to achieve the purpose of the solution of the embodiment.
  • each functional unit in various embodiments of the present disclosure may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
  • the above integrated unit can be implemented in the form of hardware or in the form of hardware plus software functional units.
  • the above-described integrated unit implemented in the form of a software functional unit can be stored in a computer readable storage medium.
  • the above software functional unit is stored in a storage medium and includes instructions for causing one or more processors of a computer device (which may be a personal computer, a server, or a network device, etc.) to perform the methods described in various embodiments of the present disclosure. Part of the steps.
  • the foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, and the like, and the program code can be stored. Medium.

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Abstract

一种显示面板的驱动方法及驱动装置。该驱动方法包括：检测数据线在扇出区的电压变化延迟时间（S100）；根据电压变化延迟时间，控制数据线的数据输出信号（S200）；根据数据输出信号调整扫描线驱动电压信号，使不同数据线所驱动的像素的有效充电时间一致（S300）。

Description

显示面板的驱动方法及驱动装置 技术领域
本公开涉及显示技术领域，特别是涉及一种显示面板的驱动方法及驱动装置。
背景技术
薄膜晶体管液晶显示(TFT-LCD)技术在进行显示面板矩阵设计时，需要将驱动集成电路(driver IC)的输出走线在压合(bonding)区进行集中布局(layout)处理，其处理方式为扇出(fan-out)布局。因此driver IC输出到显示区各数据线的距离不等，使得fan-out区域各数据线的阻抗无法达成一致，从而引起每条数据线电压变化延时(RC delay)的程度不一样，最终使在同一扫描线上，每条数据线所驱动的像素的有效充电时间不一致引起颜色漂移(color shift)。
传统的改善色偏的方案包括将数据线在fan-out区上的走线制作成铜材质，该方案在TFT-LCD制程上成本变高。还包括减少每个driver IC的输出通道数，该方案中，因面板解析度确定的情况下整个面板所需要的数据线是固定的，而减少每个driver IC的输出通道数就会使driver IC的数量上升，导致成本增加。
发明内容
基于此，有必要针对在同一扫描线上，不同数据线上的像素的有效充电时间不一致引起颜色漂移问题，提供一种显示面板的驱动方法及驱动装置。
具体地，一种显示面板的驱动方法，包括：
检测数据线在扇出区的电压变化延迟时间；所述数据线包括第一数据线和第二数据线；
根据所述电压变化延迟时间，控制数据线的数据输出信号；
根据所述数据输出信号调整扫描线驱动电压信号，使不同数据线所驱动的像素的有效充电时间一致。
在其中一个实施例中，所述检测数据线在扇出区的电压变化延迟时间之前，包括步骤：
选取第二数据线，并设置所述第二数据线的数据输出信号下降沿时间。
在其中一个实施例中，所述检测数据线在扇出区的电压变化延迟时间的步骤包括：
测量所述第一数据线与所述第二数据线在扇出区上的走线长度；
根据所述走线长度计算走线阻抗；
根据所述走线阻抗计算走线的电压变化延迟时间。
在其中一个实施例中，所述根据电压变化延迟时间，调整数据线的数据输出信号的步骤包括：
比较所述第一数据线与所述第二数据线在扇出区的电压变化延迟时间；
若第一数据线在扇出区的电压变化延迟时间大于第二数据线在扇出区的电压变化延迟时间，则控制第一数据线的数据输出信号下降沿时间提前；
若第一数据线在扇出区的电压变化延迟时间等于第二数据线在扇出区的电压变化延迟时间，则保持第一数据线与第二数据线的数据输出信号下降沿时间相同；
若第一数据线在扇出区的电压变化延迟时间小于第二数据线在扇出区的电压变化延迟时间，则控制第一数据线的数据输出信号下降沿时间推迟。
在其中一个实施例中，所述根据数据输出信号调整扫描线驱动电压信号，使不同数据线所驱动的像素的有效充电时间一致的步骤包括：
比较所述第一数据线相对所述第二数据线的数据输出信号下降沿时间；
若第一数据线相对第二数据线的数据输出信号下降沿时间提前，则根据第一数据线的数据输出信号下降沿时间输入扫描线驱动电压信号；
若第一数据线与第二数据线的数据输出信号下降沿时间相同，则根据所述的数据输出信号下降沿时间输入扫描线驱动电压信号；
若第一数据线相对第二数据线的数据输出信号下降沿时间推迟，则根据第二数据线的数据输出信号下降沿时间输入扫描线驱动电压信号。
此外，一种显示面板的驱动装置，包括检测模块、时控模块及调整模块。其中：
设置模块，用于选取第二数据线，并设置所述第二数据线的数据输出信号；
检测模块，用于检测数据线在扇出区的电压变化延迟时间；
时控模块，用于根据所述电压变化延迟时间，控制数据线的数据输出信号；
调整模块，用于根据所述数据输出信号调整扫描线驱动电压信号，使第一数据线和第二数据线所驱动的像素的有效充电时间一致。
在其中一个实施例中，所述检测模块包括测量单元以及计算单元，其中：
所述测量单元，用于测量所述第一数据线与所述第二数据线在扇出区上的走线长度；
所述计算单元，用于根据所述走线长度计算走线阻抗，以及根据所述走线阻抗计算电压变化延迟时间。
在其中一个实施例中，所述时控模块包括比较单元和时移单元，其中：
比较单元，用于比较所述第一数据线与所述第二数据线在扇出区的电压变化延迟时间；
时移单元，用于控制所述第一数据线的输出信号下降沿时间提前或推迟，
若第一数据线在扇出区的电压变化延迟时间大于第二数据线在扇出区的电 压变化延迟时间，则控制第一数据线的数据输出信号下降沿时间提前；
若第一数据线在扇出区的电压变化延迟时间等于第二数据线在扇出区的电压变化延迟时间，则保持数据线的数据输出信号下降沿时间相同；
若第一数据线在扇出区的电压变化延迟时间小于第二数据线在扇出区的电压变化延迟时间，则控制第一数据线的数据输出信号下降沿时间推迟。
在其中一个实施例中，所述调整模块包括判断单元和输入单元，其中：
对比单元，用于比较所述第一数据线相对所述第二数据线的数据输出信号下降沿时间。
输入单元，用于输入扫描线驱动电压信号，
若第一数据线相对第二数据线的数据输出信号下降沿时间提前，则根据第一数据线的数据输出信号下降沿时间输入扫描线驱动电压信号；
若第一数据线与第二数据线的数据输出信号下降沿时间相同，则根据所述的数据输出信号下降沿时间输入扫描线驱动电压信号；
若第一数据线相对第二数据线的数据输出信号下降沿时间推迟，则根据第二数据线的数据输出信号下降沿时间输入扫描线驱动电压信号。
另外，一种显示面板的驱动方法，还包括：
检测数据线在扇出区的走线长度；
判断所述走线长度是否大于预设值，若是，则控制所述数据线的数据输出信号下降沿时间提前；否则，控制所述数据线的数据输出信号下降沿时间推迟；
根据所述数据输出信号下降沿时间调整扫描线驱动电压信号，使不同数据线所驱动的像素的有效充电时间一致。
上述显示面板的驱动方法及驱动装置，通过改变不同数据线上的数据输出信号下降沿时间，从而改善了由于电压变化延时不一样所带来的色偏问题，提 升了产品的光学品位。并且，此方法对制程需求和产品成本不变。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，附图中具有相同参考数字标号的元件表示为类似的元件，除非有特别申明，附图中的图不构成比例限制。
图1为一实施例的显示面板的驱动方法流程图；
图2为图1中步骤S100的一种实现方法的流程图；
图3为图1中步骤S200的一种实现方法的流程图；
图4为图1中步骤S300的一种实现方法的流程图；
图5为一实施例的显示面板的驱动装置结构框图；
图6为图5中模块120的一种结构框图；
图7为图5中模块130的一种结构框图；
图8为图5中模块140的一种结构框图；
图9为一实施例的显示面板的显示装置示意图；
图10为图9中显示区500的像素排列方式示意图；
图11为图9中数据线的电压变化延时示意图；
图12为图9中数据输出信号、数据线及扫描向的关系示意图；
图13为另一实施例的显示面板的驱动方法流程图。
具体实施方式
为了便于理解本公开，下面将参照相关附图对本公开进行更全面的描述。附图中给出了本公开的较佳实施例。但是，本公开可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本公开的内容的理解更加透彻全面。
图1为一实施例的显示面板的驱动方法流程图，该方法包括：
步骤S100：检测数据线在扇出区的电压变化延迟时间。由于TFT-LCD在进行像素矩阵设计时，需要将driver IC的输出走线在压合区进行集中布局处理，其处理方式为扇出布局。因此driver IC输出到显示区各数据线的距离不等，使得扇出区中各数据线的阻抗无法达成一致，从而引起每条数据线的电压变化延迟时间不一样。为描述方便，故将数据线分为第一数据线和第二数据线，其中，第一数据线为需要改善色偏区域所分布的数据线，第二数据线为画面显示理想的区域所分布的数据线。
步骤S200：根据电压变化延迟时间，控制数据线的数据输出信号。数据输出信号为数据从driver IC到显示区的输出信号，即TP信号。由于第一数据线和第二数据线在扇出区的走线电压变化延迟时间不同，若第一数据线的数据输出信号下降沿时间和第二数据线的数据输出信号下降沿时间设置一样，将导致在同一扫描线上，第一数据线和第二数据线上所对应的像素的有效充电时间不一致，从而引起色偏。因此，可通过控制第一数据线和第二数据线的数据输出信号下降沿时间相对平移，诸如提前或推迟，来使它们的有效充电时间一致。
步骤S300：根据数据输出信号调整扫描线驱动电压信号，使在同一扫描线上，不同数据线所驱动的像素的有效充电时间一致。其中，扫描线驱动电压信号由扫描线driver IC提供，其作用是通过控制薄膜晶体管(TFT)开关，以驱动显示面板。当数据输出信号下降沿时间到来的时候，输入扫描线驱动电压信号，此时数据线上的颜色数据信息通过扇出区的走线输送给相应的TFT开关来控制液晶的旋转。因此，通过控制数据输出信号下降沿时间可以使在同一扫描线上，第一数据线和第二数据线所对应的像素的有效充电时间一致，进而配合扫描线驱动电压信号，使它们的充电效率相等，从而改善画面显示色偏问题。
上述实施例中，步骤S100之前还包括步骤：选取第二数据线，并设置第二数据线的数据输出信号下降沿时间。这里的第二数据线可以为driver IC的输出走线中的任意一条，根据画面显示需求，第二数据线代表理想画面的显示。进一步地，第二数据线的电压变化延迟时间为预设程度；第二数据线上的像素的有效充电时间为预设有效充电时间。电压变化延迟时间和有效充电时间为一一对应的关系，因此可以根据检测第一数据线的电压变化延迟时间得到第一数据线上的像素的有效充电时间，并根据第二数据线上的像素的有效充电时间设定第一数据线的数据输出信号下降沿时间。例如，在同一扫描线上，当第一数据线上的像素的有效充电时间比第二数据线上的像素的有效充电时间长时，则推迟第一数据线的数据输出信号下降沿时间；当第一数据线上的像素的有效充电时间比第二数据线上的像素的有效充电时间短时，则提前第一数据线的数据输出信号下降沿时间。
具体地，如图2所示，步骤S100包括以下步骤：
步骤S110：测量第一数据线与第二数据线在扇出区上的走线长度。
步骤S120：根据走线长度计算走线阻抗。
步骤S130：根据走线阻抗计算走线的电压变化延迟时间。
进一步地，计算走线的电压变化延迟时间还需确定参数：充电电容(C)、充电电容与阻抗之间的电压(V0)及充电电容完成充电时的电压(V1)。当计算得到的走线阻抗为R时，走线的电压变化延时时间为：
……R*C*ln((V0-V1)/V0)
其中，ln为自然对数。
具体地，如图3所示，步骤S200包括以下步骤：
步骤S210：比较第一数据线与第二数据线在扇出区的电压变化延迟时间。
步骤S220：若第一数据线在扇出区的电压变化延迟时间大于第二数据线在扇出区的电压变化延迟时间，则控制第一数据线的数据输出信号下降沿时间提前。
步骤S230：若第一数据线在扇出区的电压变化延迟时间等于第二数据线在扇出区的电压变化延迟时间，则保持第一数据线与第二数据线的数据输出信号下降沿时间相同。
步骤S240：若第一数据线在扇出区的电压变化延迟时间小于第二数据线在扇出区的电压变化延迟时间，则控制第一数据线的数据输出信号下降沿时间推迟。
在本实施例中，电压变化延迟时间即为电压变化延时时间，通过电压变化延时时间可以确定有效充电时间，而通过调节第一数据线与第二数据线的数据输出信号下降沿时间可以使它们所驱动的同一扫描线上的像素的有效充电时间一致。
具体地，如图4所示，步骤S300包括以下步骤：
步骤S310：比较第一数据线相对第二数据线的数据输出信号下降沿时间。
步骤S320：若第一数据线相对第二数据线的数据输出信号下降沿时间提前，则根据第一数据线的数据输出信号下降沿时间输入扫描线驱动电压信号。
步骤S330：若第一数据线与第二数据线的数据输出信号下降沿时间相同，则根据所述的数据输出信号下降沿时间输入扫描线驱动电压信号。
步骤S334：若第一数据线相对第二数据线的数据输出信号下降沿时间推迟，则根据第二数据线的数据输出信号下降沿时间输入扫描线驱动电压信号。
在本实施例中，扫描线驱动电压信号由扫描线驱动芯片发出，其作用是控制TFT开关，进而控制像素的充放电。以行驱动为例，当输入扫描线驱动电压 信号时，扫描线所在行的TFT开关同时打开，并且所在行的像素充电到各自所需的电压。但由于第一数据线与第二数据线的数据输出信号下降沿的时间经调整后存在先后次序，因此扫描线驱动电压信号应根据数据输出信号下降沿时间靠前的数据线为输入标准。即，当数据输出信号下降沿时间靠前的数据线电压信号输入时，同时输入扫描线驱动电压信号，以让数据输出信号下降沿时间靠前的数据线进行充电。
图5为一实施例的显示面板的驱动装置结构框图，该显示面板的驱动装置100包括：设置模块110、检测模块120、时控模块130和调整模块140。
设置模块110，用于选取第二数据线，并设置第二数据线的数据输出信号。
检测模块120，用于检测第一数据线和第二数据线在扇出区的电压变化延迟时间。
时控模块130，用于根据电压变化延迟时间，控制所述第一数据线和第二数据线的数据输出信号。
调整模块140，用于根据数据输出信号调整扫描线驱动电压信号，使在同一扫描线上，第一数据线和第二数据线所驱动的像素的有效充电时间一致。
上述显示面板的驱动装置100，通过各数据线在扇出区走线的距离各不相等检测它们的电压变化延迟时间，然后从电压变化延迟时间中确定各数据线上的像素的有效充电时间，再根据有效充电时间控制各数据线的数据输出信号下降沿时间，最后通过调整扫描线驱动电压信号的波形使得它们的有效充电效率一致。这种显示面板的驱动装置100避免了：采用铜材质做成数据线走线，导致TFT-LCD制程改造及制程良率问题，同时还包括成本变高问题；减少每个数据线驱动芯片的输出通道的数量，导致数据线驱动芯片的数量上升，进而成本增加的问题。
具体地，如图6所示，检测模块120包括测量单元121和计算单元122。
测量单元121，用于测量第一数据线与第二数据线在扇出区上的走线长度；
计算单元122，用于根据走线长度计算走线阻抗，以及根据走线阻抗计算电压变化延迟时间。
在一实施例中，测量单元121还用于检测充电电容(C)、充电电容与阻抗之间的电压(V0)及充电电容完成充电时的电压(V1)。计算单元122根据检测单元所检测的参数计算走线阻抗R及电压变化延时时间：
—R*C*ln((V0-V1)/V0)。
具体地，如图7所示，时控模块130包括比较单元131和时移单元132。
比较单元131，用于比较第一数据线与第二数据线在扇出区的电压变化延迟时间。
时移单元132，用于控制第一数据线的数据输出信号下降沿时间提前或推迟。
若第一数据线在扇出区的电压变化延迟时间大于第二数据线在扇出区的电压变化延迟时间，则控制第一数据线的数据输出信号下降沿时间提前。
若第一数据线在扇出区的电压变化延迟时间等于第二数据线在扇出区的电压变化延迟时间，则保持第一数据线与第二数据线的数据输出信号下降沿时间相同。
若第一数据线在扇出区的电压变化延迟时间小于第二数据线在扇出区的电压变化延迟时间，则控制第一数据线的数据输出信号下降沿时间推迟。
在一实施例中，电压变化延迟时间即为电压变化延时时间，通过电压变化延时时间可以确定有效充电时间，而通过调节第一数据线与第二数据线的数据输出信号下降沿时间可以使它们所驱动的同一扫描线上的像素的有效充电时间 一致。
在一实施例中，时移单元132为时序控制器(TCON)，时序控制器可控制数据从扫描线驱动芯片到显示屏的输出信号(数据输出信号)，即时序控制器通过编程实现对数据输出信号下降沿时间的提前或推迟。
具体地，如图8所示，调整模块140包括对比单元141和输入单元142。
对比单元141，用于比较第一数据线相对第二数据线的数据输出信号下降沿时间。
输入单元142，用于输入扫描线驱动电压信号，
若第一数据线相对第二数据线的数据输出信号下降沿时间提前，则根据第一数据线的数据输出信号下降沿时间输入扫描线驱动电压信号。
若第一数据线与第二数据线的数据输出信号下降沿时间相同，则根据所述的数据输出信号下降沿时间输入扫描线驱动电压信号。
若第一数据线相对第二数据线的数据输出信号下降沿时间推迟，则根据第二数据线的数据输出信号下降沿时间输入扫描线驱动电压信号。
上述显示面板的驱动方法应用于显示装置。具体的，如图9所示，该图为一实施例的显示面板的显示装置示意图。该显示装置包括两个数据线驱动芯片200、三个扫描线驱动芯片300以及显示面板。其中，数据线驱动芯片200输出多条数据线，分别为Data 1、Data 2、……、及Data n；扫描线驱动芯片300输出多条扫描线Gate 1、Gate2、……、及Gate n(图中未画出)。根据数据线的布线方式可将显示面板分为扇出区400和显示区500。在扇出区中，各数据线的走线长度不同，位于数据线驱动芯片中心位置的数据线走线最短，且由中心向两侧展开数据线的长度依次增加；在显示区，各数据线的走线长度一致。
具体地，如图10所示，该图为图9中显示区500的像素排列方式示意图。 该显示面板的像素单元包括具有红色(R)、绿色(G)和蓝色(B)三种不同颜色的三个子像素，且每个像素单元设置有一条数据线和三条扫描线。进一步地，每个子像素均由相应的扫描线驱动；每个像素单元均由相应的数据线驱动。例如，像素单元P1设置有数据线Data 1和扫描线Gate 1、Gate 2及Gate 3。其中，数据线Data 1用于输入颜色数据信息；扫描线Gate 1、Gate 2及Gate 3分别用于控制像素单元中蓝色(B)、绿色(G)及红色(R)子像素的TFT开关管，进而控制颜色数据信息的写入。然而，由于不同数据线的电压变化延时不一样，在控制混色画面数据信息的写入时，较长数据线由于充电不足，导致某些颜色的写入不足，因此画面显示出现色差。
具体地，如图11所示，该图为图9中数据线Data 1和Data n/4的电压变化延时示意图。由于数据线Data 1远离数据线驱动芯片200的中心位置，而数据线Data n/4正好位于数据线驱动芯片200的中心位置。所以数据线Data 1在扇出区400的走线比数据线Data n/4长，相应的阻抗也就大，产生的电压变化延时影响也更严重，从而导致充电效率更低。从图中可知，横向阴影部分面积代表绿色(G)子像素的充电效率，竖线阴影部分面积代表红色(R)子像素的充电效率；数据线Data 1的横向阴影部分面积小于数据线Data n/4的横向阴影部分面积，即数据线Data 1的绿色(G)子像素的充电效率低于数据线Data n/4的绿色(G)子像素的充电效率。因此，在显示黄色画面时，若像素单元先写入绿色再写入红色，则数据线Data 1的绿色(G)数据信息会因充电效率不足而写入不充分，与数据线Data n/4所在区域相比呈黄色偏红的现象。
进一步地，如图12所示，该图为图9中数据输出信号、数据线及扫描线的关系示意图。图中，数据线Data 1对应的数据输出信号为TP1，数据线Data n/4对应的数据输出信号为TPn/4。在显示黄色画面时，由于数据线Data 1的数据输 出信号下降沿时间较数据线Data n/4的数据输出信号下降沿时间提前，故在数据线Data 1的数据输出信号下降沿时间到来时，扫描线Gata 2输入驱动电压信号，然后数据线Data 1写入绿色(G)数据信息。当绿色(G)数据信息写入完成时，扫描线Gata 2驱动电压信号关闭，扫描线Gata 3输入驱动电压信号，然后数据线Data 1开始写入红色(R)数据信息。同样，数据线Data n/4在数据线Data 1之后也执行上述的颜色写入过程。从图中可知，横线阴影部分面积为绿色(G)数据信息的充电效率，竖线阴影部分面积为红色(R)数据信息的充电效率。通过调整合适的数据输出信号下降沿时间可以使数据线Data 1和数据线Data n/4的绿色(G)数据信息的充电效率一致，从而改善色偏问题。
上述显示装置可以为Tri-Gate驱动架构的显示装置，其像素的排列方式为RGB点反转纵向排列，但不限于此。本公开的显示面板的驱动方法还可用于其他显示装置和显示面板，例如：LCD显示(Liquid Crystal Display，液晶显示)面板、OLED(Organic Light Emitting Diode，有机发光二极管)显示面板、曲面显示面板或其他显示面板。
其中，在显示装置为液晶显示装置时，显示装置可以为TN、OCB、VA型、曲面型液晶显示装置，但并不限于此。其中，液晶显示装置可以运用直下背光，背光源可以为白光、RGB三色光源、WRGB四色光源或者YRGB四色光源，但并不限于此。
在一实施例中，如图13所示，显示面板的驱动方法还包括：
步骤S100'：检测数据线在扇出区的走线长度。显示面板的数据线在扇出区的走线长度各不相等，走线长度与它们在扇出区的排布位置有关。若显示面板有两个源极驱动器，分别驱动左半部和右半部显示面板，则数据线的走线在扇出区的中间及两侧较长。
步骤S200'：判断所述走线长度是否大于预设值，若是则执行步骤S300a，否则执行步骤S300b。在显示面板中，将画面显示效果理想的子像素所对应的数据线走线的长度作为预设值。
步骤S300a：控制所述数据线的数据输出信号下降沿时间提前。
步骤S300b：控制所述数据线的数据输出信号下降沿时间推迟。
步骤S400'：根据所述数据输出信号下降沿时间调整扫描线驱动电压信号，使不同数据线所驱动的像素的有效充电时间一致。
上述显示面板的驱动方法及驱动装置，通过改变不同数据线上的数据输出信号下降沿时间，从而改善了由于电压变化延时不一样所带来的色偏问题，提升了产品的光学品位。并且，此方法对制程需求和产品成本不变。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
在本申请所提供的各个实施例中，应该理解到，所揭露的系统，装置和/或方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多路单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多路网络单元上。可以根据实际的需要选择其中的部分或者全部 单元来实现本实施例方案的目的。
另外，在本公开各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用硬件加软件功能单元的形式实现。
上述以软件功能单元的形式实现的集成的单元，可以存储在一个计算机可读取存储介质中。上述软件功能单元存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)的一个或多个处理器执行本公开各个实施例所述方法的部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(Read-Only Memory，简称ROM)、随机存取存储器(Random Access Memory，简称RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
最后应说明的是：以上实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述实施例对本公开进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本公开各实施例技术方案的精神和范围。

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  1. 一种显示面板的驱动方法，包括：
    检测数据线在扇出区的电压变化延迟时间，所述数据线包括第一数据线和第二数据线；
    根据所述电压变化延迟时间，控制所述数据线的数据输出信号；
    根据所述数据输出信号调整扫描线驱动电压信号，使不同数据线所驱动的像素的有效充电时间一致；
    其中，所述根据电压变化延迟时间，控制所述数据线的数据输出信号的步骤包括：
    比较所述第一数据线与所述第二数据线在扇出区的电压变化延迟时间；
    若第一数据线在扇出区的电压变化延迟时间大于第二数据线在扇出区的电压变化延迟时间，则控制第一数据线的数据输出信号下降沿时间提前；
    若第一数据线在扇出区的电压变化延迟时间等于第二数据线在扇出区的电压变化延迟时间，则保持第一数据线与第二数据线的数据输出信号下降沿时间相同；
    若第一数据线在扇出区的电压变化延迟时间小于第二数据线在扇出区的电压变化延迟时间，则控制第一数据线的数据输出信号下降沿时间推迟；
    其中，所述根据数据输出信号调整扫描线驱动电压信号，使不同数据线所驱动的像素的有效充电时间一致的步骤包括：
    比较所述第一数据线相对所述第二数据线的数据输出信号下降沿时间；
    若第一数据线相对第二数据线的数据输出信号下降沿时间提前，则根据第一数据线的数据输出信号下降沿时间输入扫描线驱动电压信号；
    若第一数据线与第二数据线的数据输出信号下降沿时间相同，则根据所述的数据输出信号下降沿时间输入扫描线驱动电压信号；
    若第一数据线相对第二数据线的数据输出信号下降沿时间推迟，则根据第二数据线的数据输出信号下降沿时间输入扫描线驱动电压信号。
  2. 根据权利要求1所述的显示面板的驱动方法，其中，所述检测数据线在扇出区的电压变化延迟时间之前，包括步骤：
    选取第二数据线，并设置所述第二数据线的数据输出信号下降沿时间。
  3. 根据权利要求1所述的显示面板的驱动方法，其中，所述检测数据线在扇出区的电压变化延迟时间的步骤包括：
    测量所述第一数据线与所述第二数据线在扇出区上的走线长度；
    根据所述走线长度计算走线阻抗；
    根据所述走线阻抗计算走线的电压变化延迟时间。
  4. 根据权利要求1所述的显示面板的驱动方法，其中，所述检测数据线在扇出区的电压变化延迟时间之前，包括步骤：
    选取第二数据线，并设置所述第二数据线的数据输出信号下降沿时间；
    其中，所述检测数据线在扇出区的电压变化延迟时间的步骤包括：
    测量所述第一数据线与所述第二数据线在扇出区上的走线长度；
    根据所述走线长度计算走线阻抗；
    根据所述走线阻抗计算走线的电压变化延迟时间。
  5. 根据权利要求1所述的显示面板的驱动方法，其中，所述显示面板为液晶显示面板、有机发光二极管显示面板或曲面显示面板。
  6. 根据权利要求1所述的显示面板的驱动方法，其中，所述显示面板包括所述扇出区和显示区，所述第一数据线和所述第二数据线在所述扇出区的走线 长度不同且在所述显示区的走线长度一致。
  7. 一种显示面板的驱动装置，包括：
    设置模块，用于选取第二数据线，并设置所述第二数据线的数据输出信号；
    检测模块，用于检测第一数据线和所述第二数据线在扇出区的电压变化延迟时间；
    时控模块，用于根据所述电压变化延迟时间，控制所述第一数据线和所述第二数据线的数据输出信号；
    调整模块，用于根据所述数据输出信号调整扫描线驱动电压信号，使所述第一数据线和所述第二数据线所驱动的像素的有效充电时间一致。
  8. 根据权利要求7所述的显示面板的驱动装置，其中，所述检测模块包括测量单元以及计算单元，其中：
    所述测量单元，用于测量所述第一数据线与所述第二数据线在扇出区上的走线长度；
    所述计算单元，用于根据所述走线长度计算走线阻抗，以及根据所述走线阻抗计算电压变化延迟时间。
  9. 根据权利要求7所述的显示面板的驱动装置，其中，所述时控模块包括比较单元和时移单元，其中：
    比较单元，用于比较所述第一数据线与所述第二数据线在扇出区的电压变化延迟时间；
    时移单元，用于控制所述第一数据线的输出信号下降沿时间提前或推迟，
    若第一数据线在扇出区的电压变化延迟时间大于第二数据线在扇出区的电压变化延迟时间，则控制第一数据线的数据输出信号下降沿时间提前；
    若第一数据线在扇出区的电压变化延迟时间等于第二数据线在扇出区的电 压变化延迟时间，则保持第一数据线与第二数据线的数据输出信号下降沿时间相同；
    若第一数据线在扇出区的电压变化延迟时间小于第二数据线在扇出区的电压变化延迟时间，则控制第一数据线的数据输出信号下降沿时间推迟。
  10. 根据权利要求7所述的显示面板的驱动装置，其中，所述调整模块包括对比单元和输入单元，其中：
    对比单元，用于比较所述第一数据线相对所述第二数据线的数据输出信号下降沿时间；
    输入单元，用于输入扫描线驱动电压信号，
    若第一数据线相对第二数据线的数据输出信号下降沿时间提前，则根据第一数据线的数据输出信号下降沿时间输入扫描线驱动电压信号；
    若第一数据线与第二数据线的数据输出信号下降沿时间相同，则根据所述的数据输出信号下降沿时间输入扫描线驱动电压信号；
    若第一数据线相对第二数据线的数据输出信号下降沿时间推迟，则根据第二数据线的数据输出信号下降沿时间输入扫描线驱动电压信号。
  11. 根据权利要求7所述的显示面板的驱动装置，其中，所述检测模块包括测量单元以及计算单元，其中：
    所述测量单元，用于测量所述第一数据线与所述第二数据线在扇出区上的走线长度；
    所述计算单元，用于根据所述走线长度计算走线阻抗，以及根据所述走线阻抗计算电压变化延迟时间；
    其中，所述时控模块包括比较单元和时移单元，其中：
    比较单元，用于比较所述第一数据线与所述第二数据线在扇出区的电 压变化延迟时间；
    时移单元，用于控制所述第一数据线的输出信号下降沿时间提前或推迟，
    若第一数据线在扇出区的电压变化延迟时间大于第二数据线在扇出区的电压变化延迟时间，则控制第一数据线的数据输出信号下降沿时间提前；
    若第一数据线在扇出区的电压变化延迟时间等于第二数据线在扇出区的电压变化延迟时间，则保持第一数据线与第二数据线的数据输出信号下降沿时间相同；
    若第一数据线在扇出区的电压变化延迟时间小于第二数据线在扇出区的电压变化延迟时间，则控制第一数据线的数据输出信号下降沿时间推迟。
  12. 根据权利要求7所述的显示面板的驱动装置，其中，所述检测模块包括测量单元以及计算单元，其中：
    所述测量单元，用于测量所述第一数据线与所述第二数据线在扇出区上的走线长度；
    所述计算单元，用于根据所述走线长度计算走线阻抗，以及根据所述走线阻抗计算电压变化延迟时间；
    其中，所述调整模块包括对比单元和输入单元，其中：
    对比单元，用于比较所述第一数据线相对所述第二数据线的数据输出信号下降沿时间；
    输入单元，用于输入扫描线驱动电压信号，
    若第一数据线相对第二数据线的数据输出信号下降沿时间提前，则根据第一数据线的数据输出信号下降沿时间输入扫描线驱动电压信号；
    若第一数据线与第二数据线的数据输出信号下降沿时间相同，则根据 所述的数据输出信号下降沿时间输入扫描线驱动电压信号；
    若第一数据线相对第二数据线的数据输出信号下降沿时间推迟，则根据第二数据线的数据输出信号下降沿时间输入扫描线驱动电压信号。
  13. 根据权利要求7所述的显示面板的驱动装置，其中，所述检测模块包括测量单元以及计算单元，其中：
    所述测量单元，用于测量所述第一数据线与所述第二数据线在扇出区上的走线长度；
    所述计算单元，用于根据所述走线长度计算走线阻抗，以及根据所述走线阻抗计算电压变化延迟时间；
    其中，所述时控模块包括比较单元和时移单元，其中：
    比较单元，用于比较所述第一数据线与所述第二数据线在扇出区的电压变化延迟时间；
    时移单元，用于控制所述第一数据线的输出信号下降沿时间提前或推迟，
    若第一数据线在扇出区的电压变化延迟时间大于第二数据线在扇出区的电压变化延迟时间，则控制第一数据线的数据输出信号下降沿时间提前；
    若第一数据线在扇出区的电压变化延迟时间等于第二数据线在扇出区的电压变化延迟时间，则保持第一数据线与第二数据线的数据输出信号下降沿时间相同；
    若第一数据线在扇出区的电压变化延迟时间小于第二数据线在扇出区的电压变化延迟时间，则控制第一数据线的数据输出信号下降沿时间推迟；
    其中，所述调整模块包括对比单元和输入单元，其中：
    对比单元，用于比较所述第一数据线相对所述第二数据线的数据输出 信号下降沿时间；
    输入单元，用于输入扫描线驱动电压信号，
    若第一数据线相对第二数据线的数据输出信号下降沿时间提前，则根据第一数据线的数据输出信号下降沿时间输入扫描线驱动电压信号；
    若第一数据线与第二数据线的数据输出信号下降沿时间相同，则根据所述的数据输出信号下降沿时间输入扫描线驱动电压信号；
    若第一数据线相对第二数据线的数据输出信号下降沿时间推迟，则根据第二数据线的数据输出信号下降沿时间输入扫描线驱动电压信号。
  14. 根据权利要求7所述的显示面板的驱动装置，其中，所述时控模块包括比较单元和时移单元，其中：
    比较单元，用于比较所述第一数据线与所述第二数据线在扇出区的电压变化延迟时间；
    时移单元，用于控制所述第一数据线的输出信号下降沿时间提前或推迟，
    若第一数据线在扇出区的电压变化延迟时间大于第二数据线在扇出区的电压变化延迟时间，则控制第一数据线的数据输出信号下降沿时间提前；
    若第一数据线在扇出区的电压变化延迟时间等于第二数据线在扇出区的电压变化延迟时间，则保持第一数据线与第二数据线的数据输出信号下降沿时间相同；
    若第一数据线在扇出区的电压变化延迟时间小于第二数据线在扇出区的电压变化延迟时间，则控制第一数据线的数据输出信号下降沿时间推迟；
    其中，所述调整模块包括对比单元和输入单元，其中：
    对比单元，用于比较所述第一数据线相对所述第二数据线的数据输出 信号下降沿时间；
    输入单元，用于输入扫描线驱动电压信号，
    若第一数据线相对第二数据线的数据输出信号下降沿时间提前，则根据第一数据线的数据输出信号下降沿时间输入扫描线驱动电压信号；
    若第一数据线与第二数据线的数据输出信号下降沿时间相同，则根据所述的数据输出信号下降沿时间输入扫描线驱动电压信号；
    若第一数据线相对第二数据线的数据输出信号下降沿时间推迟，则根据第二数据线的数据输出信号下降沿时间输入扫描线驱动电压信号。
  15. 根据权利要求7所述的显示面板的驱动装置，其中，所述显示面板为液晶显示面板、有机发光二极管显示面板或曲面显示面板。
  16. 根据权利要求7所述的显示面板的驱动装置，其中，所述显示面板包括所述扇出区和显示区，所述第一数据线和所述第二数据线在所述扇出区的走线长度不同且在所述显示区的走线长度一致。
  17. 一种显示面板的驱动方法，包括：
    检测数据线在扇出区的走线长度；
    判断所述走线长度是否大于预设值，若是，则控制所述数据线的数据输出信号下降沿时间提前；否则，控制所述数据线的数据输出信号下降沿时间推迟；
    根据所述数据输出信号下降沿时间调整扫描线驱动电压信号，使不同数据线所驱动的像素的有效充电时间一致。
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