WO2019001285A1 - 阵列基板及其制备方法和显示装置 - Google Patents

阵列基板及其制备方法和显示装置 Download PDF

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Publication number
WO2019001285A1
WO2019001285A1 PCT/CN2018/091320 CN2018091320W WO2019001285A1 WO 2019001285 A1 WO2019001285 A1 WO 2019001285A1 CN 2018091320 W CN2018091320 W CN 2018091320W WO 2019001285 A1 WO2019001285 A1 WO 2019001285A1
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Prior art keywords
substrate
insulating layer
layer
array substrate
light
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PCT/CN2018/091320
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English (en)
French (fr)
Inventor
张正东
周刚
田华
杨小飞
代科
苏磊
牟勋
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/327,697 priority Critical patent/US10797087B2/en
Publication of WO2019001285A1 publication Critical patent/WO2019001285A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1296—Multistep manufacturing methods adapted to increase the uniformity of device parameters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78678—Polycrystalline or microcrystalline silicon transistor with inverted-type structure, e.g. with bottom gate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133509—Filters, e.g. light shielding masks
    • G02F1/133514—Colour filters
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/40—Arrangements for improving the aperture ratio
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
    • G02F2202/02—Materials and properties organic material
    • G02F2202/022—Materials and properties organic material polymeric
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
    • G02F2202/04—Materials and properties dye

Definitions

  • Embodiments of the present disclosure relate to an array substrate, a method of fabricating the same, and a display device.
  • an acrylic layer is required for increasing the storage capacitance.
  • Acrylic is a plastic polymer material which has good permeability and easy dyeing characteristics.
  • the acrylic layer can increase the transmittance and flatness, but there is still a case where the aperture ratio is insufficient.
  • the traditional black matrix light blocking layer is designed on the color film substrate, and the width of the black matrix light blocking layer is wide, so that the aperture ratio of the liquid crystal screen is small, and the high aperture ratio of the high pixel product cannot be satisfied.
  • One of the objects of the present disclosure is to provide an array substrate which can increase the aperture ratio of a display device.
  • an array substrate including a substrate substrate and an insulating layer, a gate line, a source, a drain, and a data line on the substrate, wherein the insulating layer includes a light transmitting portion And a light shielding portion, and an orthographic projection of the gate line, the source, the drain, and the data line on the base substrate is located in an orthographic projection of the light shielding portion on the base substrate .
  • a display device including the aforementioned array substrate is provided.
  • a method of fabricating an array substrate is provided: providing a substrate; and forming an insulating layer, a gate line, a source, a drain, and a data line on the substrate;
  • the insulating layer includes a light transmitting portion and a light shielding portion, and an orthographic projection of the gate line, the source, the drain, and the data line on the base substrate is located at the light shielding portion on the substrate In the orthographic projection on the substrate.
  • FIG. 1 is a schematic structural view of an array substrate according to an embodiment of the present disclosure
  • FIG. 2 is a schematic structural view of an array substrate according to another embodiment of the present disclosure.
  • FIG. 3 is a plan view of an array substrate of one embodiment of the present disclosure.
  • FIG. 4 is a cross-sectional structural view of the array substrate shown in FIG. 3 taken along line A-A;
  • FIG. 5 is a schematic structural diagram of an array substrate according to still another embodiment of the present disclosure.
  • FIG. 6 is a flow chart of preparing an insulating layer according to still another embodiment of the present disclosure.
  • FIG. 7 is a flow chart of preparing an insulating layer according to still another embodiment of the present disclosure.
  • 8A to 8E are schematic flow charts of preparing an insulating layer according to an embodiment of the present disclosure.
  • FIG. 9 is a schematic structural view of an insulating layer according to an embodiment of the present disclosure.
  • FIG. 10 is a schematic structural view of a display panel according to an embodiment of the present disclosure.
  • the array substrate includes a base substrate 20 and an insulating layer 10 disposed on the base substrate 20.
  • the insulating layer 10 includes a light transmitting portion 12 and a light shielding portion 11, and the gate line 30, the source 40, and the drain 50
  • the orthographic projection of the data line 130 on the base substrate 20 is located in the orthographic projection of the light shielding portion 11 on the base substrate 20. Therefore, the light shielding portion of the insulating layer can replace the conventional black matrix, and the black matrix is not required to be formed on the color filter substrate of the array substrate with the array substrate, the product structure is simplified, the product thickness is reduced, and the size of the light shielding portion can be smaller than the conventional black matrix.
  • the size of the opening increases the aperture ratio; the insulating layer can also function to increase the brightness and flattening, and the subsequent process can be directly operated on the operation, and the operation is simple and convenient.
  • the orthographic projection of the light shielding portion 11 on the substrate substrate 20 may be opposite to the gate line 30, the source 40,
  • the orthographic projections of the drain 50 and the data line 130 on the base substrate 20 completely overlap, that is, the area of the orthographic projection of the light shielding portion 11 on the base substrate 20 and the gate line 30, the source 40, the drain 50, and the data line 130.
  • the area of the orthographic projection on the base substrate 20 is the same.
  • the material for forming the insulating layer is not particularly limited as long as the use requirements of the array substrate are satisfied, and the light-shielding portion may be formed on the insulating layer by light transmission and by some physical or chemical process.
  • the material forming the insulating layer is acrylic. Thereby, the insulation effect is good, the transmittance is high, the dyeing is easy, and the flattening effect can be achieved.
  • the acrylic layer is usually disposed in the existing array substrate, the light shielding portion can be directly formed on the structure of the existing acrylic layer, which simplifies the manufacturing process of the product.
  • a portion of the insulating layer may be doped or coated with a light-shielding particle such as black particles.
  • a light-shielding particle such as black particles.
  • the light transmitting portion 12 is made of an insulating material
  • the light shielding portion 11 is made of the insulating material doped with black particles (as shown in FIG. 8E)
  • the light transmitting portion 12 is composed of
  • the insulating material is made of the insulating material whose surface is coated with black particles (as shown in FIG. 9). That is, the portion of the insulating material has a light-shielding property by doping in a portion of the insulating material or coating black ions on the surface thereof, thus forming a light-shielding portion.
  • the insulating material is acrylic.
  • a specific kind of black particles that can be employed is not particularly required as long as it can be effectively doped to a corresponding position of the insulating layer, and can perform a good light-shielding effect.
  • the black particles may be ferroferric oxide particles.
  • the specific arrangement position of the insulating layer in the array substrate is not particularly limited as long as the normal operation of the array substrate is not affected, and at the same time, the shading effect can be effectively exerted.
  • the insulating layer is disposed between the common electrode and the source, the drain, and the data line, that is, the source, the drain, and the data line are disposed on a side of the insulating layer near the gate, common The electrode is disposed on a side of the insulating layer away from the gate.
  • the insulating layer can simultaneously have the functions of insulation, planarization, increased transmittance, storage capacitance, and light shielding, and the area of the light shielding portion can be smaller than the area of the conventional black matrix, thereby effectively increasing the aperture ratio.
  • the array substrate of the present disclosure may have the structure of a conventional array substrate in the art, including but not limited to an ADS mode array substrate, an LTPS (low temperature polysilicon) mode array substrate, and the like.
  • ADS mode array substrate an ADS mode array substrate
  • LTPS low temperature polysilicon
  • the specific structure of the array substrate of the present disclosure will be described below by taking an ADS mode array substrate and an LTPS (low temperature polysilicon) mode array substrate as an example.
  • the array substrate is, for example, an ADS mode array substrate, and the array substrate includes the substrate substrate 20,
  • the gate electrode 100 is disposed in the same layer as the gate line 30 and disposed on one side of the substrate substrate 20;
  • the gate insulating layer 90 is disposed on a side of the gate electrode 100 and the gate line 30 away from the substrate substrate 20, and covers the gate electrode 100 and
  • the gate line 30 is disposed on a side of the gate insulating layer 90 away from the substrate substrate 20 and corresponding to the gate 100;
  • the pixel electrode 60 is located on a side of the gate insulating layer 90 away from the substrate 20, the pixel electrode 60 and the active layer 80 are on the same gate insulating layer 90;
  • the source 40, the drain 50 and the data line 130 are disposed in the same layer, and are located on the side of the active layer 80 away from the substrate 20;
  • the insulating layer 10 is disposed on The source layer 80 is away from
  • the common electrode 70 is disposed on the insulating layer 10 away from the substrate 20. side. It should be noted that the gate electrode 100 and the gate line 30 are connected to each other and together constitute the same conductive pattern, wherein the structure of the switching device portion (the portion corresponding to the active layer) constitutes the gate electrode 100, and the other portions constitute the gate line 30, the source The pole 40 and the data line 130 are connected together and constitute the same conductive pattern, wherein a portion close to the active layer and connected to the active layer constitutes the source 40, and other portions constitute the data line 130.
  • the insulating layer 10 includes a light shielding portion 11 and a light transmitting portion 12, and an orthographic projection of the gate line 30, the source electrode 40, the drain electrode 50, and the data line 130 on the substrate substrate 20 is located at the light shielding portion 11 on the substrate. In the orthographic projection on the substrate 20.
  • the array substrate of the embodiment of the present disclosure is an LTPS mode array substrate.
  • the array substrate may include: a substrate substrate 20; and a buffer layer 22 disposed on one side of the substrate substrate 20.
  • An active layer 80 disposed on a side of the buffer layer 22 away from the substrate 20; a gate insulating layer 90 disposed on the buffer layer 22 away from the substrate 20 and covering the active layer 80; and disposed on the gate insulating layer 90 a gate electrode 100 and a gate line 30 disposed on the side of the substrate substrate 20 and disposed in the same layer; an interlayer insulating layer disposed on a side of the gate insulating layer 90 away from the substrate substrate 20 and covering the gate electrode 100 and the gate line 30 a source 40 and a drain 50 disposed on a side of the interlayer insulating layer 110 away from the substrate 20 and electrically connected to the active layer 80; and disposed on the interlayer insulating layer 110 away from the lining
  • the source 40 is connected to the data line 130, and the light shielding portion in the insulating layer also covers the data line, except that the data line 130 is not shown in FIG.
  • the insulating layer portion corresponding to the active layer may be provided as a light shielding portion in the array substrate shown in FIG. Therefore, the manufacturing process is simple, and the entire light-emitting device portion is completely blocked, and the display effect is better.
  • the insulating layer 10 includes a light shielding portion 11 and a light transmitting portion 12, and an orthographic projection of the gate line 30, the source electrode 40, and the drain electrode 50 on the substrate substrate 20 is located on the substrate substrate 20 of the light shielding portion 11. In the orthographic projection.
  • the acryl layer on the conventional ADS display mode array substrate or the LTPS mode array substrate can be appropriately processed to form the insulating layer 10, which can not only increase the transmittance, but also play a flattening effect, and can also replace the traditional black.
  • the role of the matrix, and its light-shielding area can be smaller than the area of the conventional black matrix, greatly increasing the aperture ratio.
  • the new structure is not added, the thickness of the product is not increased, and the color matrix substrate of the array substrate is not required to be provided with a black matrix, which simplifies the product structure.
  • the pixel electrode and the common electrode on the ADS display mode array substrate or the LTPS mode array substrate are all interchangeable, and FIG. 4 and FIG. 5 only show one case, and cannot be understood as Limitations of the disclosure.
  • An embodiment of the present disclosure further provides a display device including the array substrate described in any of the preceding embodiments.
  • the structure is simple, the thickness is thin, the aperture ratio is large, and the display quality is high.
  • the display device has all the features and advantages described above, and will not be further described herein.
  • the specific type of the display device is not particularly limited, and may be any device or device having a display function in the art, such as, but not limited to, a mobile phone, a tablet computer, a computer display, a game machine, a television, a display. Screens, wearables, and other living appliances or household appliances with display functions.
  • the display device of the embodiment of the present disclosure includes an array substrate 01 and a color filter substrate 02 which are disposed opposite each other.
  • the array substrate 01 includes a glass substrate 100 and an insulating layer 10.
  • the insulating layer 10 includes a light-shielding portion 11 and a light-transmitting portion 12.
  • the color filter substrate 02 includes a glass substrate 200, a color film layer 210, and a planarization layer 220. Since the light shielding portion 11 can replace the black matrix, the color film substrate 02 has no black matrix, and when the two are paired, the light shielding portion 11 can function as a black matrix.
  • the color film layer 210 includes a plurality of color film units R, G, B, and the light shielding portion 11 corresponds to the intersection of any two adjacent color film units, that is, the orthographic projection of the light shielding portion 11 on the glass substrate 200 is in any phase.
  • the junction of two adjacent color film units is not limited to one color film units.
  • a display device may further include the necessary structures and components of a conventional display device, and the mobile phone is taken as an example, except for having the present disclosure.
  • the mobile phone In addition to the array substrate of the embodiment, it may also have the structure and components of a conventional mobile phone such as a touch screen, a casing, a CPU, a camera module, a fingerprint recognition module, a sound processing system, etc., and will not be described in detail herein. .
  • Embodiments of the present disclosure also provide a method of preparing an array substrate.
  • the method includes: providing a substrate substrate 20; and forming an insulating layer 10, a gate line 30, a source 40, a drain 50, and a data line 130 on the substrate substrate 20;
  • the insulating layer 10 includes a light transmitting portion 12 and a light shielding portion 11, and an orthographic projection of the gate line 30, the source electrode 40, and the drain electrode 50 on the base substrate 20 is located at an orthographic projection of the light shielding portion 11 on the substrate substrate 20. in.
  • the process is mature, the operation is simple, and the industrial production is easy, and since the insulating layer has a light-shielding portion, it can replace the traditional black matrix, and the obtained matrix substrate does not need to be provided with a black matrix on the color filter substrate of the box, which simplifies the product structure. And the area of the light shielding portion can be smaller than the conventional black matrix, which greatly increases the aperture ratio.
  • the step of forming the insulating layer includes:
  • the material for forming the insulating layer is not particularly limited as long as the use requirements of the array substrate are satisfied, and the light-shielding portion may be formed on the insulating layer by light transmission and by some physical or chemical process.
  • the material forming the insulating layer is acrylic. Therefore, the insulating effect is good, the transmittance is high, the dyeing is easy, and the flattening effect can be achieved.
  • the acrylic layer is usually provided in the existing array substrate, the structure of the existing acrylic layer can be directly formed. The formation of a light-shielding portion simplifies the production process of the product.
  • a portion of the insulating layer may be doped or coated with a light-shielding particle such as black particles.
  • a light-shielding particle such as black particles.
  • methods of forming a light transmissive layer include, but are not limited to, deposition, coating, printing, and the like.
  • S200 Doping a portion of the light transmissive layer with a mask to form a light shielding portion to obtain the insulating layer.
  • the specific operation mode of this step is not particularly limited as long as the substance having a light-shielding effect can be effectively doped to the corresponding position of the light-transmitting layer to form the light-shielding portion.
  • the light-transmissive layer is doped by using a mask, and the forming the light-shielding portion includes:
  • the specific method of forming the photoresist layer in this step is not particularly limited, and those skilled in the art can flexibly select according to needs, for example, any method for forming a photoresist known in the art, including It is not limited to methods such as coating, printing, and the like.
  • the specific kind of the photoresist is also not particularly limited, and may be a positive photoresist or a negative photoresist.
  • S220 Exposing the photoresist layer 2 using the mask 3, see FIG. 8B.
  • this step can be performed in accordance with conventional operations in the art.
  • the reticle used may have a pattern corresponding to or opposite to the light-shielding pattern.
  • this step can be performed in accordance with conventional operations in the art.
  • the light-transmitting layer is doped with black particles by chemical vapor deposition, see FIG. 8D.
  • the specific kind of the black particles is not particularly required, and can be effectively doped to the corresponding position of the insulating layer, and can achieve a good light-shielding effect.
  • the black particles may be ferroferric oxide particles.
  • the micro-black particles Fe 3 O 4 are doped into the light-transmitting layer of the acrylic layer by chemical vapor deposition CVD, and the Fe 3 O 4 may be combined with the polymethyl methacrylate (acrylic).
  • a black acrylic material having a light-shielding effect is formed, thereby forming a light-shielding portion 11 capable of functioning as a black matrix (BM) light blocking.
  • BM black matrix
  • the remaining photoresist may be stripped off by a strip process to obtain a desired insulating layer designed as a BM light blocking layer.
  • steps of forming the insulating layer the steps of forming other structures of the conventional array substrate may also be included, such as forming the gate, the gate line, the gate insulating layer, the active layer, and the source. Steps such as a pole, a drain, a common electrode, an interlayer insulating layer, and a pixel electrode.
  • the above-described step of forming the insulating layer may be performed after the step of forming the source and the drain, and before the step of forming the common electrode.
  • the forming the insulating layer includes: forming a light transmissive layer; and coating a portion of the light transmissive layer with a light shielding material by using a mask to form the light shielding portion to obtain the insulating layer .
  • a mask 3 of FIG. 8B may be employed to apply a light-shielding material on a surface of a portion of the light-transmitting layer 1 corresponding to the light-transmitting region of the mask 3, thereby forming the light-shielding portion 11. Since the method does not need to form the photoresist layer 2 on the light transmissive layer 1, the process is simpler and easier to operate.
  • the method for fabricating the ADS display mode array substrate shown in FIG. 3 includes:
  • S303 forming source 40, drain 50 and data line 130 by one patterning process
  • a photoresist (PR glue) is coated on the transparent acryl layer, and the corresponding gate line 30, the source 40, the drain 50, and the PR glue over the data line 130 are exposed by a mask.
  • Development is performed to form a photoresist retention region and a photoresist removal region, and a portion of the transparent acryl layer in the photoresist removal region is doped with a fine black particle Fe 3 O 4 by a CVD method.
  • Fe 3 O 4 and polymethyl methacrylate (acrylic) are cross-linked copolymerized or cured by cross-linking to form a black acrylic material having a light-shielding effect, that is, a light-shielding portion 11, thereby being capable of functioning as a BM light blocking.
  • the strip process is stripped off the remaining PR glue to obtain the desired acrylic layer 10 as both the BM light blocking layer and the insulating layer.
  • the common electrode 70 is formed on one side of the acryl layer 10 having the light shielding portion away from the substrate 20 by one patterning process.
  • the method for fabricating the LTPS mode array substrate shown in FIG. 5 includes:
  • the buffer layer 22 may be formed by chemical vapor deposition or physical vapor deposition.
  • the material forming the buffer layer 22 may be at least one of SiN x and SiO 2 , or may be a multilayer structure formed of different materials, for example, may be one. A two-layer structure of a layer of SiN x layer and a layer of SiO 2 layer.
  • the active layer 80 is formed by a patterning process. For example, an entire layer of amorphous silicon layer may be formed on the buffer layer 22, followed by dehydrogenation, HF cleaning, laser annealing, etching, stripping of the photoresist, and Vth doping to form the active layer 80.
  • dehydrogenation can remove hydrogen in amorphous silicon, so that hydrogen explosion does not occur during laser annealing, and V th doping can adjust the electrical properties of polycrystalline silicon to meet product design specifications.
  • S402 depositing a gate insulating layer 90 covering the active layer 80 on the buffer layer 22, and performing a C st doping step on the active layer 80 using a mask.
  • the C st doping may cause the polysilicon to have a conductive property and form a storage capacitor with the gate.
  • the gate electrode 100 and the gate line 30 are formed on a side of the gate insulating layer 90 away from the substrate substrate 20 by a patterning process.
  • a Mo plating layer may be formed on a side of the gate insulating layer 90 away from the substrate substrate 20, and then the Mo plating layer may be etched, doped, or the like to form the gate electrode 100 and the gate line 30.
  • interlayer insulating layer 110 depositing an interlayer insulating layer 110 on a side of the gate insulating layer 90 away from the substrate 20. For example, in this step, steps of interlayer insulating layer plating, activation, hydrogenation, via etching, and the like are sequentially performed to form the interlayer insulating layer 110.
  • the material forming the interlayer insulating layer 110 may be at least one of SiN x and SiO 2 , or may be a multilayer structure formed of different materials, for example, a double layer structure of a layer of SiO 2 and a layer of SiN x . .
  • a source 40, a drain 50, and a data line 130 are formed on a side of the interlayer insulating layer 110 away from the substrate 20.
  • a Ti/Al/Ti plating film may be formed on a side of the interlayer insulating layer 110 away from the substrate 20, and then etched to form a source 40 and a drain electrically connected to the active layer 80 through the interlayer insulating layer 110. 50 and data line 130.
  • the light-transmitting acryl layer may be formed by a coating or deposition method, then the PR paste is coated on the light-transmitting acryl layer, and the corresponding gate line 30, source 40, drain 50, and data line 130 are masked by a mask.
  • the PR adhesive is exposed and developed to form a photoresist retention region and a photoresist removal region, and then a part of the transparent acryl layer in the photoresist removal region is doped with a fine black particle Fe 3 O 4 , Fe 3 O by a CVD method.
  • a black acrylic material having a light-shielding effect that is, a light-shielding portion 11 is formed, thereby being capable of functioning as a BM light blocking.
  • the Strip process is stripped off the PR glue in other places to obtain the desired acrylic layer 10 which is also designed as the BM light blocking layer and the insulating layer.
  • the common electrode 70 and the connection electrode 72 are formed on the side of the acryl layer 10 away from the substrate 20 by one patterning process.
  • an a-ITO plating film may be formed on the side of the acrylic layer 10 away from the substrate 20, and then subjected to etching, annealing, or the like to form the common electrode 70 and the connection electrode 72.
  • the annealing treatment can form a-ITO into P-ITO (polycrystalline ITO) to make it more stable.
  • S408 Form a second insulating layer 120 on a side of the acryl layer 10 away from the substrate 20.
  • an insulating layer plating film may be formed and then etched to form the second insulating layer 120.
  • S409 Forming the pixel electrode 60 on a side of the second insulating layer 120 away from the base substrate 20.
  • the a-ITO plating film may be formed first, then etched and annealed to form the pixel electrode 60.

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Abstract

一种阵列基板及其制备方法和显示装置。该阵列基板(01)包括衬底基板(20)和位于所述衬底基板(20)上的绝缘层(10)、栅线(30)、源极(40)、漏极(50)和数据线(130)，其中所述绝缘层(10)包括透光部分(12)和遮光部分(11)，且所述栅线(30)、所述源极(40)、所述漏极(50)和所述数据线(130)在所述衬底基板(20)上的正投影位于所述遮光部分(11)在所述衬底基板(20)上的正投影中。由于阵列基板(01)上的遮光部分(11)可以替代黑矩阵，简化产品结构、减小产品厚度，有利于增大开口率。

Description

阵列基板及其制备方法和显示装置
相关申请的交叉引用
本申请基于并且要求于2017年6月28日递交的中国专利申请第201710512261.5号的优先权，在此全文引用上述中国专利申请公开的内容。
技术领域
本公开实施例涉及阵列基板及其制备方法和显示装置。
背景技术
在液晶显示器中，一般为增加存储电容需要做亚克力层，亚克力是一种可塑性高分子材料，有较好的透过性和易染色的特点。亚克力层可以增加透过率和平坦度，但还是存在开口率不足的情况。传统黑矩阵挡光层设计在彩膜基板上，黑矩阵挡光层的宽度较宽，从而使液晶屏的开口率较小，不能满足高像素产品对高开口率的需求。
发明内容
本公开的其中一个目的在于提出一种可以提高显示器件开口率的阵列基板。
在本公开的一个方面，提供了一种阵列基板包括衬底基板和位于所述衬底基板上的绝缘层、栅线、源极、漏极和数据线，其中所述绝缘层包括透光部分和遮光部分，且所述栅线、所述源极、所述漏极和所述数据线在所述衬底基板上的正投影位于所述遮光部分在所述衬底基板上的正投影中。
在本公开的另一方面，提供了一种显示装置，包括前述的阵列基板。
在本公开的又一方面，提供了一种阵列基板的制备方法：提供衬底基板；以及在所述衬底基板上形成绝缘层、栅线、源极、漏极和数据线；其中所述绝缘层包括透光部分和遮光部分，且所述栅线、所述源极、所述漏极和所述数据线在所述衬底基板上的正投影位于所述遮光部分在所述衬底基板上的正投影中。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1是本公开一个实施例的阵列基板的结构示意图；
图2是本公开另一个实施例的阵列基板的结构示意图；
图3是本公开一个实施例的阵列基板的平面照片；
图4是图3所示的阵列基板沿A-A线的剖面结构示意图；
图5是本公开再一个实施例的阵列基板的结构示意图；
图6是本公开又一个实施例制备绝缘层的流程图；
图7是本公开又一个实施例制备绝缘层的流程图；
图8A至图8E是本公开一个实施例的制备绝缘层的流程示意图；
图9是本公开一个实施例的绝缘层的结构示意图；
图10是本公开一个实施例的显示面板的结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另作定义，此处使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本公开专利申请说明书以及权利要求书中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现在“包括”或者“包含”前面的元件或者物件涵盖出现在“包括”或者“包含”后面列举的元件或者物件及其等同，并不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对 位置改变后，则该相对位置关系也可能相应地改变。
本公开实施例提供了一种阵列基板。参照图1，该阵列基板包括衬底基板20和设置在衬底基板20上的绝缘层10，绝缘层10包括透光部分12和遮光部分11，且栅线30、源极40、漏极50和数据线130在衬底基板20上的正投影位于遮光部分11在衬底基板20上的正投影中。由此，绝缘层的遮光部分可以替代常规黑矩阵，与该阵列基板对盒的彩膜基板上不需要制作黑矩阵，简化产品结构、减小产品厚度，且遮光部分的尺寸可以小于常规黑矩阵的尺寸，增大开口率；绝缘层还可以起到提高亮度和平坦化的作用，后续工艺可以直接在此之上进行操作，操作简单方便。
根据本公开的实施例，为了进一步减小绝缘层中遮光部分的面积，增大开口率，参照图2，遮光部分11在衬底基板20上的正投影可以与栅线30、源极40、漏极50和数据线130在衬底基板20上的正投影完全重叠，即遮光部分11在衬底基板20上的正投影的面积与栅线30、源极40、漏极50和数据线130在衬底基板20上的正投影的面积相同。由此，在保证栅线、源极、漏极和数据线被遮光部分完全遮住的前提下，可以进一步减小遮光部分的尺寸，有效增大开口率。
根据本公开的实施例，形成绝缘层的材料没有特殊的限制，只要满足阵列基板的使用要求，透光且通过一些物理或化学工艺可以在该绝缘层上形成遮光部分即可。在本公开的一些实施例中，形成绝缘层的材料为亚克力。由此，绝缘效果好，透过率高，易染色，而且可以起到平坦化的作用。另外，由于现有阵列基板中通常会设置亚克力层，由此可以直接在现有亚克力层的结构上形成遮光部分，简化了产品的制作工艺。例如，为了在绝缘层上形成遮光部分，可以在部分绝缘层中掺杂或在其表面涂覆遮光粒子，例如黑色粒子。由此，可以有效遮挡光线，且掺杂黑色粒子的操作简单、易于控制，且不会增加产品厚度。
根据本公开的实施例，透光部分12由绝缘材料制成，所述遮光部分11由掺杂有黑色粒子的所述绝缘材料制成(如图8E所示)，或者，透光部分12由绝缘材料制成，所述遮光部分11由表面涂覆有黑色粒子的所述绝缘材料制成(如图9所示)。也就是说，通过在部分绝缘材料中掺杂或在其表面涂覆黑色离子，使该部分绝缘材料具有遮光性能，如此形成遮光部分。例如， 该绝缘材料为亚克力。
根据本公开的实施例，可以采用的黑色粒子的具体种类没有特殊要求，只要其能够有效掺杂到绝缘层的相应位置，且能够起到良好的遮光效果即可。根据本公开的一些实施例，黑色粒子可以为四氧化三铁粒子。由此，来源广泛，成本较低，遮光效果好，且易于掺杂到绝缘层中。
根据本公开的实施例，绝缘层在阵列基板中的具体设置位置没有特别限制，只要不影响阵列基板的正常工作，且同时能够有效发挥遮光作用即可。在本公开的一些实施例中，绝缘层设置于公共电极与源极、漏极和数据线之间，即源极、漏极和数据线设置于所述绝缘层靠近栅极的一侧，公共电极设置于所述绝缘层远离所述栅极的一侧。由此，绝缘层可以同时具有绝缘、平坦化、增加透过率和存储电容和遮光的作用，且遮光部分的面积可以小于常规黑矩阵的面积，进而有效增大开口率。
本领域技术人员可以理解，除了上述绝缘层之外，本公开的阵列基板可以具有本领域常规阵列基板的结构，包括但不限于ADS模式阵列基板，LTPS(低温多晶硅)模式阵列基板等。下面以ADS模式阵列基板，LTPS(低温多晶硅)模式阵列基板为例说明本公开的阵列基板的具体结构。
在本公开的一些实施例中，参照图3(形成源极和漏极后获得的实际产品照片)和图4，该阵列基板例如为ADS模式阵列基板，且该阵列基板包括衬底基板20，栅极100与栅线30同层设置，设置于衬底基板20的一侧；栅绝缘层90设置于栅极100和栅线30远离于衬底基板20的一侧，且覆盖栅极100和栅线30；有源层80设置于栅绝缘层90远离衬底基板20的一侧，且与栅极100对应；像素电极60位于栅绝缘层90远离衬底基板20的一侧，该像素电极60和有源层80位于同一栅绝缘层90上；源极40、漏极50和数据线130同层设置，且位于有源层80远离衬底基板20的一侧；绝缘层10设置于有源层80远离衬底基板20的一侧，且覆盖像素电极60、源极40、漏极50、有源层80和数据线130；公共电极70设置于绝缘层10远离衬底基板20的一侧。需要说明的是，栅极100和栅线30相连且共同构成同一导电图案，其中，位于开关器件部分的结构(与有源层对应的部分)构成栅极100，其他部分构成栅线30，源极40和数据线130相连且共同构成同一导电图案，其中，靠近有源层且与有源层相连的部分构成源极40，其他部分构成数据线 130。
如图4所示，绝缘层10包括遮光部分11和透光部分12，栅线30、源极40、漏极50和数据线130在衬底基板20上的正投影位于遮光部分11在衬底基板20上的正投影中。
在本公开的另一些实施例中，本公开实施例的阵列基板为LTPS模式阵列基板，参照图5，该阵列基板可以包括：衬底基板20；设置于衬底基板20一侧的缓冲层22；设置于缓冲层22远离衬底基板20一侧的有源层80；设置于缓冲层22远离衬底基板20一侧，且覆盖有源层80的栅绝缘层90；设置于栅绝缘层90远离衬底基板20一侧、且同层设置的栅极100和栅线30；设置于栅绝缘层90远离衬底基板20的一侧、且覆盖栅极100和栅线30的层间绝缘层110；设置于层间绝缘层110远离衬底基板20的一侧，且贯穿层间绝缘层100与有源层80电连接的源极40和漏极50；设置于层间绝缘层110远离衬底基板20的一侧，且覆盖源极40和漏极50的绝缘层10；设置于绝缘层10远离衬底基板20一侧的公共电极70；设置于绝缘层10远离衬底基板20一侧、且贯穿绝缘层10与漏极50电连接的连接电极72；设置于绝缘层10远离衬底基板20一侧、且覆盖公共电极70和连接电极72的第二绝缘层120；设置于第二绝缘层120远离衬底基板20的一侧、且贯穿第二绝缘层120与连接电极电连接的像素电极60。需要说明的是，源极40与数据线130连接，绝缘层中的遮光部分同样覆盖数据线，只是图5中未示出数据线130。另外，出于制作方便等的考虑，图5所示的阵列基板中还可以将与有源层对应的绝缘层部分均设置为遮光部分。由此将制作步骤简单，且将整个开光器件部分全部遮挡，显示效果更佳。
如图5所示，绝缘层10包括遮光部分11和透光部分12，栅线30、源极40、漏极50在衬底基板20上的正投影位于遮光部分11在衬底基板20上的正投影中。
本申请实施例中，可以对传统ADS显示模式阵列基板或LTPS模式阵列基板上的亚克力层进行适当处理形成上述绝缘层10，其不仅可以增加透过率、发挥平坦化作用，还可以替代传统黑矩阵的作用，且其遮光面积可以小于传统黑矩阵的面积，大大提高开口率。另外，并未增加新的结构，不会增加产品厚度，且与该阵列基板对盒的彩膜基板不需要设置黑矩阵，简化了产 品结构。另外，本领域技术人员可以理解，ADS显示模式阵列基板或LTPS模式阵列基板上的像素电极和公共电极均是可以互换的，图4和图5仅示出了一种情况，并不能理解为对本公开的限制。
本公开实施例还提供了一种显示装置，该显示装置包括前面任一实施例所述的阵列基板。由此，结构简单，厚度较薄，且开口率较大，显示品质高。且该显示装置具有前面所述的所有特征和优点，在此不再一一赘述。
根据本公开的实施例，该显示装置的具体种类没有特别限制，可以为本领域任何具有显示功能的装置、设备，例如包括但不限于手机、平板电脑、计算机显示器、游戏机、电视机、显示屏幕、可穿戴设备及其他具有显示功能的生活电器或家用电器等。
如图10所示，本公开实施例的显示装置包括相对设置的阵列基板01和彩膜基板02。例如，阵列基板01包括玻璃基板100和绝缘层10。绝缘层10包括遮光部分11和透光部分12，有关绝缘层10在阵列基板01上的具体结构和材料可参见前面实施例中的描述，此处不再赘述。彩膜基板02包括玻璃基板200、彩膜层210和平坦化层220。由于遮光部分11可以替代黑矩阵，所述彩膜基板02上无黑矩阵，当二者对盒后，遮光部分11可以起到黑矩阵的作用。
例如，彩膜层210包括多个彩膜单元R、G、B，遮光部分11对应于任意两个相邻彩膜单元的交界处，即遮光部分11在玻璃基板200上的正投影位于任意相邻的两个彩膜单元的交界处。
本领域技术人员可以理解，除了前面所述的阵列基板，本公开实施例所述的显示装置还可以包括常规显示装置所具有的必要的结构和部件，以手机为例进行说明，除了具有本公开实施例的阵列基板件外，其还可以具有触控屏、外壳、CPU、照相模组、指纹识别模组、声音处理系统等等常规手机所具有的结构和部件，在此不再过多赘述。
本公开实施例还提供了一种制备阵列基板的方法。参照图1，根据本公开的实施例，该方法包括：提供衬底基板20；以及在衬底基板20上形成绝缘层10、栅线30、源极40、漏极50和数据线130；其中该绝缘层10包括透光部分12和遮光部分11，且栅线30、源极40和漏极50在所述衬底基板20上的正投影位于遮光部分11在衬底基板20上的正投影中。由此，工艺成熟， 操作简便，易于工业化生产，且由于绝缘层具有遮光部分，可以替代传统黑矩阵，与获得的阵列基板对盒的彩膜基板上不再需要设置黑矩阵，简化了产品结构，且遮光部分的面积可以小于传统黑矩阵，大大提高了开口率。
根据本公开的实施例，参照图6，形成所述绝缘层的步骤包括：
S100：形成透光层。
根据本公开的实施例，形成绝缘层的材料没有特殊的限制，只要满足阵列基板的使用要求，透光且通过一些物理或化学工艺可以在该绝缘层上形成遮光部分即可。在本公开的一些实施例中，形成绝缘层的材料为亚克力。由此，绝缘效果好，透过率高，易染色，而且可以起到平坦化的作用，另外，由于现有阵列基板中通常会设置亚克力层，由此可以直接在现有亚克力层的结构上形成遮光部分，简化了产品的制作工艺。例如，为了在绝缘层上形成遮光部分，可以在部分绝缘层中掺杂或在其表面涂覆遮光粒子，例如黑色粒子。由此，可以有效遮挡光线，且掺杂黑色粒子的操作简单、易于控制，且不会增加产品厚度。
根据本公开的实施例，形成透光层的方法也没有特殊要求，本领域人员可以根据实际需求灵活选择。根据本公开的一些实施例，形成透光层的方法包括但不限于沉积、涂覆、印刷等。
S200：利用掩模对部分所述透光层进行掺杂处理，形成遮光部分，以得到所述绝缘层。
根据本公开的实施例，该步骤的具体操作方式没有特别限制，只要能够有效将具有遮光作用的物质掺杂到透光层的相应位置以形成遮光部分即可。在本公开的一些实施例中，参照图7，利用掩模对透光层进行掺杂处理，形成遮光部分包括：
S210：在透光层1上形成光刻胶层2，参见图8A。
根据本公开的实施例，该步骤中形成光刻胶层的具体方法没有特别限制，本领域技术人员可以根据需要灵活选择，例如可以为本领域任何已知的形成光刻胶的方法，包括但不限于涂覆、印刷等方法。根据本公开的实施例，光刻胶的具体种类也没有特别限制，如可以为正性光刻胶，也可以为负性光刻胶。
S220：利用掩模3对光刻胶层2进行曝光，参见图8B。
根据本公开的实施例，该步骤可以按照本领域常规操作进行。采用的掩模版上可以具有与遮光图案对应或相反的图案。
S230：对经过曝光的光刻胶层进行显影，参见图8C，从而形成光刻胶保留区201和光刻胶去除区202。
根据本公开的实施例，该步骤可以按照本领域常规操作进行。
S240：利用化学气相沉积法对透光层掺杂黑色粒子，参见图8D。
根据本公开的实施例，黑色粒子的具体种类没有特殊要求，能够有效掺杂到绝缘层的相应位置，且能够起到良好的遮光效果即可。根据本公开的一些实施例，黑色粒子可以为四氧化三铁粒子。由此，来源广泛，成本较低，遮光效果好，且易于掺杂到绝缘层中。
在本公开的一些具体实施例中，采用化学气相沉积CVD方式向亚克力层透光层中掺杂微小黑色粒子Fe 3O 4，Fe 3O 4可以与聚甲基丙烯酸甲酯(亚克力)以副价交联共聚或固化交联后，形成具有遮光效果的黑色亚克力材料，从而形成能够起到黑矩阵(BM)挡光作用的遮光部分11。
S250：去除剩余的光刻胶层，参见图8E。
根据本公开的实施例，该步骤中，可以通过剥离(Strip)工艺剥离掉剩余的光刻胶，得到所需要的同时作为BM挡光层设计的绝缘层。当然，本领域技术人员可以理解，除了上述形成绝缘层的步骤，还可以包括形成常规阵列基板的其他结构的步骤，如还可以包括形成栅极、栅线、栅绝缘层、有源层、源极、漏极、公共电极、层间绝缘层、像素电极等步骤。例如，上述形成绝缘层的步骤，可以在形成源极、漏极的步骤之后，且形成公共电极的步骤之前。
根据本公开的另一实施例，形成绝缘层的步骤包括：形成透光层；以及利用掩模在部分所述透光层上涂覆遮光材料，形成所述遮光部分，以得到所述绝缘层。
例如，参见图9，可以采用图8B的掩模3，在透光层1与掩模3的透光区域相对应的部分的表面上涂覆遮光材料，从而形成遮光部分11。由于该方法无需在透光层1上制作光刻胶层2，工艺更加简单，便于操作。
下面以图3至图5所示的阵列基板为例说明本申请的制备阵列基板的具体方法。
在本公开的一些实施例中，图3所示的ADS显示模式阵列基板的制作方法包括：
S300：通过一次构图工艺在衬底基板20上形成栅极100和栅线30；
S301：沉积覆盖栅极100和栅线30的栅绝缘层90；
S302：通过一次构图工艺在栅绝缘层90远离衬底基板20的一侧形成有源层80；
S303：通过一次构图工艺形成源极40、漏极50和数据线130；
S304：通过一个构图工艺形成像素电极60；
S305：在栅绝缘层90远离衬底基板20的一侧沉积亚克力层10，接着参照前面实施例中描述的掺杂或涂覆工艺执行。
例如，在沉积透光亚克力层后，在透光亚克力层上涂上光刻胶(PR胶)，采用掩模将对应栅线30、源极40、漏极50和数据线130上方的PR胶曝光、显影以形成光刻胶保留区和光刻胶去除区，再采用CVD方法在光刻胶去除区中的部分透光亚克力层中掺杂微小黑色粒子Fe 3O 4。Fe 3O 4与聚甲基丙烯酸甲酯(亚克力)以副价交联共聚或固化交联后，形成具有遮光效果的黑色亚克力材料，即遮光部分11，从而能够起到BM挡光作用。掺杂工艺完成后，再进行Strip工艺剥离掉剩余的PR胶，得到所需要的同时作为BM挡光层以及绝缘层的亚克力层10。
S306：通过一次构图工艺在具有遮光部分的亚克力层10远离衬底基板20的一侧形成公共电极70。
在本公开的另一些实施例中，图5所示的LTPS模式阵列基板的制备方法包括：
S400：在衬底基板20上沉积缓冲层22。例如，可以通过化学气相沉积或物理气相沉积形成缓冲层22，形成缓冲层22的材料可以为SiN x和SiO 2中的至少一种，也可以为不同材料形成的多层结构，例如可以为一层SiN x层和一层SiO 2层的双层结构。
S401：通过构图工艺形成有源层80。例如，可以先在缓冲层22上形成整层的非晶硅层，然后进行脱氢、HF清洗、激光退火、刻蚀、剥离光刻胶和V th掺杂，形成有源层80。其中，脱氢可以去除非晶硅内氢，使得激光退火时不会发生氢爆，V th掺杂可以调节多晶硅的电学特性，使其满足产品设计 规格。
S402：在缓冲层22上沉积覆盖有源层80的栅绝缘层90，并利用掩模对有源层80进行C st掺杂步骤。该步骤中，C st掺杂可以使得多晶硅具有导电特性并与栅极之间形成存储电容。
S403：通过构图工艺在栅绝缘层90远离衬底基板20的一侧形成栅极100和栅线30。例如，可以在栅绝缘层90远离衬底基板20的一侧形成Mo镀层，然后对Mo镀层进行刻蚀、掺杂等步骤，形成栅极100和栅线30。
S404：在栅绝缘层90远离衬底基板20的一侧沉积层间绝缘层110。例如，该步骤中，依次进行层间绝缘层镀膜、活化、加氢、过孔刻蚀等步骤，形成层间绝缘层110。形成层间绝缘层110的材料可以为SiN x和SiO 2中的至少一种，也可以为不同材料形成的多层结构，例如可以为一层SiO 2层和一层SiN x层的双层结构。
S405：在层间绝缘层110远离衬底基板20的一侧形成源极40、漏极50和数据线130(图中未示出)。例如，可以在层间绝缘层110远离衬底基板20的一侧形成Ti/Al/Ti镀膜，然后进行刻蚀形成贯穿层间绝缘层110与有源层80电连接的源极40、漏极50和数据线130。
S406：在层间绝缘层110远离衬底基板20的一侧形成亚克力层。例如，可以先通过涂覆或沉积方法形成透光亚克力层，然后在透光亚克力层上涂上PR胶，采用掩模将对应栅线30、源极40、漏极50和数据线130上方的PR胶曝光、显影以形成光刻胶保留区和光刻胶去除区，再采用CVD方法在光刻胶去除区中的部分透光亚克力层中掺杂微小黑色粒子Fe 3O 4，Fe 3O 4与聚甲基丙烯酸甲酯(亚克力)以副价交联共聚或固化交联后，形成具有遮光效果的黑色亚克力材料，即遮光部分11，从而能够起到BM挡光作用。掺杂工艺完成后，再进行Strip工艺剥离掉其它地方的PR胶，得到所需要的同时作为BM挡光层和绝缘层设计的亚克力层10。
S407：通过一次构图工艺在亚克力层10远离衬底基板20的一侧形成公共电极70和连接电极72。例如，可以先在亚克力层10远离衬底基板20的一侧形成a-ITO镀膜，然后进行刻蚀、退火等处理，形成公共电极70和连接电极72。其中，退火处理可以将a-ITO形成P-ITO(多晶ITO)，使其更加稳定。
S408：在亚克力层10远离衬底基板20的一侧形成第二绝缘层120。例如，可以形成绝缘层镀膜，然后进行刻蚀，形成第二绝缘层120。
S409：在第二绝缘层120远离衬底基板20的一侧形成像素电极60。例如，可以先形成a-ITO镀膜，然后进行刻蚀，退火处理，形成像素电极60。
本文中，有以下几点需要说明：
(1)本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)为了清晰起见，在用于描述本公开的实施例的附图中，层或区域的厚度被放大或缩小，即这些附图并非按照实际的比例绘制。
(3)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述仅是本公开的示范性实施方式，而非用于限制本公开的保护范围，本公开的保护范围由所附的权利要求确定。

Claims (16)

  1. 一种阵列基板，包括衬底基板和位于所述衬底基板上的绝缘层、栅线、源极、漏极和数据线，
    其中所述绝缘层包括透光部分和遮光部分，且所述栅线、所述源极、所述漏极和所述数据线在所述衬底基板上的正投影位于所述遮光部分在所述衬底基板上的正投影中。
  2. 根据权利要求1所述的阵列基板，其中所述遮光部分在所述衬底基板上的正投影与所述栅线、源极、漏极和数据线在所述衬底基板上的正投影完全重叠。
  3. 根据权利要求1所述的阵列基板，其中形成所述绝缘层的材料为亚克力。
  4. 根据权利要求1所述的阵列基板，其中所述遮光部分掺杂或涂覆有黑色粒子。
  5. 根据权利要求4所述的阵列基板，其中所述黑色粒子包括四氧化三铁粒子。
  6. 根据权利要求1所述的阵列基板，其中所述透光部分由绝缘材料制成，所述遮光部分由掺杂有黑色粒子的所述绝缘材料制成。
  7. 根据权利要求1所述的阵列基板，其中所述透光部分由绝缘材料制成，所述遮光部分由表面涂覆有黑色粒子的所述绝缘材料制成。
  8. 根据权利要求1-7中任一项所述的阵列基板，还包括公共电极，其中所述源极、所述漏极和所述数据线设置于所述绝缘层靠近所述栅线的一侧，所述公共电极设置于所述绝缘层远离所述栅线的一侧。
  9. 一种显示装置，包括权利要求1-8中任一项所述的阵列基板。
  10. 根据权利要求9所述的显示装置，还包括与所述阵列基板相对设置的对置基板，所述对置基板上无遮光材料。
  11. 根据权利要求10所述的显示装置，其中所述对置基板为彩膜基板，所述彩膜基板包括彩膜层，所述彩膜基板上无黑矩阵。
  12. 根据权利要求11所述的显示装置，其中所述彩膜层包括多个彩膜单元，其中所述阵列基板的遮光部分对应于任意两个相邻彩膜单元的交界处。
  13. 一种阵列基板的制备方法，包括：
    提供衬底基板；以及
    在所述衬底基板上形成绝缘层、栅线、源极、漏极和数据线；
    其中所述绝缘层包括透光部分和遮光部分，且所述栅线、所述源极、所述漏极和所述数据线在所述衬底基板上的正投影位于所述遮光部分在所述衬底基板上的正投影中。
  14. 根据权利要求13所述的制备方法，其中形成所述绝缘层包括：
    形成透光层；以及
    利用掩模对部分所述透光层进行掺杂处理，形成所述遮光部分，以得到所述绝缘层。
  15. 根据权利要求14所述的制备方法，其中利用掩模对所述透光层进行掺杂处理包括：
    在所述透光层上形成光刻胶层；
    利用所述掩模对所述光刻胶层进行曝光、显影以形成光刻胶保留区和光刻胶去除区；
    利用化学气相沉积法对所述光刻胶去除区中的所述透光层掺杂黑色粒子；以及
    去除剩余的光刻胶层。
  16. 根据权利要求13所述的制备方法，其中形成所述绝缘层包括：
    形成透光层；以及
    利用掩模在部分所述透光层上涂覆遮光材料，形成所述遮光部分，以得到所述绝缘层。
PCT/CN2018/091320 2017-06-28 2018-06-14 阵列基板及其制备方法和显示装置 WO2019001285A1 (zh)

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