WO2019001159A1 - 一种编码方法及装置、计算机存储介质 - Google Patents

一种编码方法及装置、计算机存储介质 Download PDF

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WO2019001159A1
WO2019001159A1 PCT/CN2018/086927 CN2018086927W WO2019001159A1 WO 2019001159 A1 WO2019001159 A1 WO 2019001159A1 CN 2018086927 W CN2018086927 W CN 2018086927W WO 2019001159 A1 WO2019001159 A1 WO 2019001159A1
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matrix
cyclic coefficient
sub
check
base graph
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WO2019001159A9 (zh
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王加庆
穆锡金
张荻
白宝明
孙韶辉
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电信科学技术研究院有限公司
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Priority to EP18822587.4A priority Critical patent/EP3648357B1/en
Priority to KR1020207002393A priority patent/KR102300273B1/ko
Priority to JP2019572228A priority patent/JP7091375B2/ja
Priority to US16/626,284 priority patent/US11038531B2/en
Publication of WO2019001159A1 publication Critical patent/WO2019001159A1/zh
Publication of WO2019001159A9 publication Critical patent/WO2019001159A9/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/033—Theoretical methods to calculate these checking codes
    • H03M13/036—Heuristic code construction methods, i.e. code construction or code search based on using trial-and-error
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1105—Decoding
    • H03M13/1131—Scheduling of bit node or check node processing
    • H03M13/1137—Partly parallel processing, i.e. sub-blocks or sub-groups of nodes being processed in parallel
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/118—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure
    • H03M13/1185—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure wherein the parity-check matrix comprises a part with a double-diagonal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/118—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure
    • H03M13/1185—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure wherein the parity-check matrix comprises a part with a double-diagonal
    • H03M13/1188—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure wherein the parity-check matrix comprises a part with a double-diagonal wherein in the part with the double-diagonal at least one column has an odd column weight equal or greater than three
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/61—Aspects and characteristics of methods and arrangements for error correction or error detection, not provided for otherwise
    • H03M13/615—Use of computational or mathematical techniques
    • H03M13/616—Matrix operations, especially for generator matrices or check matrices, e.g. column or row permutations
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/63—Joint error correction and other techniques
    • H03M13/6306—Error control coding in combination with Automatic Repeat reQuest [ARQ] and diversity transmission, e.g. coding schemes for the multiple transmission of the same information or the transmission of incremental redundancy
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/63—Joint error correction and other techniques
    • H03M13/635—Error control coding in combination with rate matching
    • H03M13/6362—Error control coding in combination with rate matching by puncturing
    • H03M13/6368—Error control coding in combination with rate matching by puncturing using rate compatible puncturing or complementary puncturing
    • H03M13/6393—Rate compatible low-density parity check [LDPC] codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6502—Reduction of hardware complexity or efficient processing
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6508—Flexibility, adaptability, parametrability and configurability of the implementation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6508—Flexibility, adaptability, parametrability and configurability of the implementation
    • H03M13/6516—Support of multiple code parameters, e.g. generalized Reed-Solomon decoder for a variety of generator polynomials or Galois fields
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0041—Arrangements at the transmitter end
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0041—Arrangements at the transmitter end
    • H04L1/0043—Realisations of complexity reduction techniques, e.g. use of look-up tables
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes

Definitions

  • the present application relates to the field of communications technologies, and in particular, to an encoding method and apparatus, and a computer storage medium.
  • the current 3rd Generation Partnership Project (3GPP) proposes to provide a Low Density Parity Check Code (LDPC) channel coding design for the 5G Mobile Broadband Enhanced (eMBB) scenario.
  • LDPC Low Density Parity Check Code
  • the LDPC code is a kind of linear code defined by the check matrix.
  • the check matrix needs to satisfy the sparsity when the code length is long, that is, the density of 1 in the check matrix is relatively low, that is, the check is required.
  • the number of 1s in the matrix is much smaller than the number of 0, and the longer the code length, the lower the density.
  • the embodiment of the present application provides an encoding method and device, and a computer storage medium, which are used to improve LDPC encoding performance, and thus are applicable to a 5G system.
  • LDPC encoding is performed according to the sub-circulant matrix and the base graph.
  • the constructing a cyclic coefficient index matrix specifically includes:
  • Step 1 divide the set of dimension Z of the sub-circulant matrix that needs to be supported into multiple subsets
  • Step 2 generating a set of cyclic coefficient exponential matrix for each of the subsets
  • Step 3 Determine, according to the cyclic coefficient exponential matrix, a cyclic coefficient corresponding to Z of the plurality of subsets;
  • Step 4 For each Z, it is detected whether the performance of the determined cyclic coefficient exponent matrix satisfies a preset condition, and if so, the process ends. Otherwise, step 2 is re-executed.
  • Z a ⁇ 2 j ; performing the first step in one of the following ways:
  • Method 1 According to the value of a, divide Z into multiple subsets
  • Method 2 According to the value of j, divide Z into multiple subsets
  • Mode 3 Divide Z into multiple subsets according to the length of the information bits.
  • the step 3 specifically includes: determining a cyclic coefficient P i,j corresponding to each Z by using the following formula:
  • V i,j is the cyclic coefficient corresponding to the (i,j)th element of the cyclic coefficient exponential matrix.
  • the determined cyclic coefficient exponent matrix is as shown in the following table:
  • the determined cyclic coefficient exponent matrix is as shown in the following table:
  • the determined cyclic coefficient exponent matrix is as shown in the following table:
  • the determined cyclic coefficient exponent matrix is as shown in the following table:
  • the determined cyclic coefficient exponent matrix is as shown in the following table:
  • the determined cyclic coefficient exponent matrix is as shown in the following table:
  • the method further includes:
  • the sub-circulant matrix is updated using the updated cyclic coefficient exponent matrix.
  • the update includes at least row and column permutation of matrix elements.
  • the LDPC encoding is performed according to the sub-circulant matrix and the base graph, and specifically includes:
  • the LDPC encoding is performed using the check matrix.
  • the method further includes: performing row and column permutation on the check matrix;
  • the LDPC encoding is performed by using the check matrix, and specifically includes: performing LDPC encoding by using a check matrix after row and column replacement.
  • the row and column replacement of the check matrix includes:
  • a first unit configured to determine a base graph of a low density parity check code LDPC matrix, and construct a cyclic coefficient exponential matrix
  • a second unit configured to determine a sub-circulation matrix according to the cyclic coefficient exponential matrix
  • a third unit configured to perform LDPC encoding according to the sub-circulation matrix and the base graph.
  • the first unit constructs a cyclic coefficient exponential matrix, and specifically includes:
  • Step 1 divide the set of dimension Z of the sub-circulant matrix that needs to be supported into multiple subsets
  • Step 2 generating a set of cyclic coefficient exponential matrix for each of the subsets
  • Step 3 Determine, according to the cyclic coefficient exponential matrix, a cyclic coefficient corresponding to Z of the plurality of subsets;
  • Step 4 For each Z, it is detected whether the performance of the determined cyclic coefficient exponent matrix satisfies a preset condition, and if so, the process ends. Otherwise, step 2 is re-executed.
  • the first unit performs the step 1 in one of the following ways:
  • Method 1 According to the value of a, divide Z into multiple subsets
  • Method 2 According to the value of j, divide Z into multiple subsets
  • Mode 3 Divide Z into multiple subsets according to the length of the information bits.
  • the step 3 specifically includes: determining a cyclic coefficient P i,j corresponding to each Z by using the following formula:
  • V i,j is the cyclic coefficient corresponding to the (i,j)th element of the cyclic coefficient exponential matrix.
  • the determined cyclic coefficient exponent matrix is as shown in the following table:
  • the determined cyclic coefficient exponent matrix is as shown in the following table:
  • the determined cyclic coefficient exponent matrix is as shown in the following table:
  • the determined cyclic coefficient exponent matrix is as shown in the following table:
  • the determined cyclic coefficient exponent matrix is as shown in the following table:
  • the determined cyclic coefficient exponent matrix is as shown in the following table:
  • the second unit is further configured to:
  • the sub-circulant matrix is updated using the updated cyclic coefficient exponent matrix.
  • the update includes at least row and column permutation of matrix elements.
  • the third unit is specifically configured to:
  • the LDPC encoding is performed using the check matrix.
  • the third unit is further configured to perform row and column permutation on the check matrix after determining the check matrix;
  • the third unit performs LDPC encoding by using the check matrix, and specifically includes: performing LDPC encoding by using a check matrix after row and column replacement.
  • the third unit performs row and row replacement on the check matrix, and specifically includes:
  • Another encoding apparatus includes a memory and a processor, wherein the memory is used to store program instructions, and the processor is configured to invoke program instructions stored in the memory, and execute according to the obtained program. Any of the above methods.
  • a computer storage medium storing the computer executable instructions for causing the computer to execute any of the above methods.
  • FIG. 1 is a schematic structural diagram of a Base matrix according to an embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of a matrix P provided by an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of an LDPC check matrix supporting redundancy increment provided by an embodiment of the present application
  • FIG. 6 is a schematic diagram of a set of cyclic matrix sizes Z supported by a 5G LDPC requirement provided by an embodiment of the present application;
  • FIG. 7 is a schematic structural diagram of a Base graph #2 according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic structural diagram of a first cyclic coefficient exponent matrix according to an embodiment of the present disclosure.
  • FIG. 9 is a schematic structural diagram of a second cyclic coefficient exponent matrix according to an embodiment of the present disclosure.
  • FIG. 10 is a schematic structural diagram of a third cyclic coefficient exponent matrix according to an embodiment of the present application.
  • FIG. 11 is a schematic structural diagram of a fourth cyclic coefficient exponent matrix according to an embodiment of the present disclosure.
  • FIG. 12 is a schematic structural diagram of a fifth cyclic coefficient exponent matrix according to an embodiment of the present disclosure.
  • FIG. 13 is a schematic structural diagram of a sixth cyclic coefficient exponent matrix according to an embodiment of the present disclosure.
  • 15 is a schematic diagram of performance of an LDPC cyclic coefficient according to an embodiment of the present application.
  • FIG. 16 is a schematic flowchart diagram of an encoding method according to an embodiment of the present application.
  • FIG. 17 is a schematic structural diagram of an encoding apparatus according to an embodiment of the present disclosure.
  • FIG. 18 is a schematic structural diagram of another encoding apparatus according to an embodiment of the present application.
  • the embodiment of the present application provides an encoding method and device, and a computer storage medium, which are used to improve LDPC encoding performance, and thus are applicable to a 5G system.
  • the technical solution provided by the embodiment of the present application provides LDPC coding for the data channel of the eMMB scenario instead of the turbo coding of the original long term evolution (LTE) system, that is, an LDPC coding scheme applicable to the 5G system.
  • LTE long term evolution
  • the 5G LDPC code design requires a quasi-cyclic LDPC code, and its check matrix H can be expressed as follows:
  • a i,j is a z ⁇ z cyclic permutation matrix.
  • a base matrix of size ⁇ c is constructed, and the elements of the matrix are not 0 or 1, as shown in FIG. 1 .
  • each element of the base matrix B is expanded into a z ⁇ z Circular Permutation Matrix (CPM), and the 0 element of the base matrix is expanded to a z ⁇ z all-zero matrix, and the Base matrix B is later
  • the original pattern map based LDPC construction method is called a base graph (BG).
  • Each z ⁇ z cyclic permutation matrix is represented by P i , where the matrix P is a matrix obtained by shifting the unit array cycle one bit to the right, as shown in FIG.
  • each cyclic permutation matrix P i is actually shifted by the unit array I by a right shift i, and the cyclic permutation matrix cyclic shift label i satisfies
  • the cyclically shifted reference number i described above is also referred to as the shifting coefficients of the LDPC check matrix.
  • the coefficient matrix thus obtained is also called a shifting coefficient exponent matrix (SEM).
  • Fig. 4 shows an example of a cyclic coefficient index matrix.
  • BG is a base graph of 3 rows and 6 columns, and each element in the base graph corresponds to a sub-circular matrix of 8 rows and 8 columns, and the base graph is replaced by a cyclic shift coefficient of each sub-circular matrix, wherein 0 is used by -1 Replace to get the cyclic coefficient exponent matrix.
  • the sub-circular matrix (CM) corresponding to the quasi-cyclic LDPC code described above may have a column weight greater than 1, for example, a column weight of 2 or greater, and the sub-circulant matrix is no longer a cyclic permutation matrix (CPM).
  • CPM cyclic permutation matrix
  • the 5G LDPC code design must support IR (Incremental Redundancy)-HARQ (Hybrid Automatic Repeat Request). Therefore, the LDPC code for 5G scenarios can be constructed by incremental redundancy. Construct a high-rate LDPC code, then generate more parity bits by incremental redundancy, and then obtain a low-rate LDPC code.
  • the LDPC code constructed based on the incremental redundancy method has excellent performance, code length, and code. It has the advantages of wide coverage, high reusability, easy hardware implementation, and can be directly encoded by the check matrix.
  • An example of a specific structure is shown in FIG. Where B is a double diagonal or quasi-double diagonal matrix, C is a 0 matrix, and E is a lower triangular expansion matrix.
  • the design of the LDPC check matrix depends mainly on the design of A, D, and E1.
  • LDPC performance depends on two of the most important factors, one is the design of the base matrix, and the other is a z ⁇ z cyclic permutation matrix that expands each non-zero element in the base matrix into a way. These two factors play a decisive role in LDPC performance.
  • the improper design of the base matrix and the extended sub-circulant permutation matrix can greatly deteriorate the performance of the LDPC code.
  • the LDPC check matrix in the 5G design is being designed. Since the 5G requirement supports flexible LDPC, taking the eMBB data channel as an example, the 3GPP requires that up to two LDPC check matrixes obtained by two base graph extensions support up to 8 /9 code rate, the lowest 1/5, the longest information bit is 8448 bits shortest 40bits; the two base graphs, the large base graph is 46x68 columns, of which the first 22 columns correspond to information bits, the lowest code rate is 1/3 The small base graph size is 42x52 columns, and the lowest code rate is 1/5.
  • the sub-circular matrix corresponding to each 1 of the base graph is expanded into a sub-circulant matrix of different sizes, that is, the size of the sub-circulant matrix.
  • Z can support different values.
  • the sub-circular matrix dimension Z a ⁇ 2 j required by the 3GPP is shown, and its value is as shown in FIG. 6.
  • Each Z in the table shown in Figure 6 corresponds to a check matrix of the LDPC. It seems that the 5G LDPC code design requires a lot of check matrices to be designed. If a cyclic coefficient matrix is designed for each Z, it is not easy to store and the workload is huge.
  • the first step is to determine the base graph based on the density evolution P-EXIT Chart decoding threshold (the lowest decoding threshold when the code length is infinitely long, that is, the lowest required SNR value), and the actual simulation performance;
  • the second step constructing a cyclic coefficient exponential matrix, wherein each value of the cyclic coefficient represents a cyclic coefficient of a sub-matrix, and according to the foregoing description, the P i coefficient i is located at an exponential position, so here is called a cyclic coefficient index A matrix can also be called an exponent matrix.
  • the second step specifically includes the following steps 1 through 4:
  • Kb*Z is the length of information bits, where Kb is the number of columns of information bits in the base graph, which is different from the number K of information bits.
  • Kb is the number of columns of information bits in the base graph, which is different from the number K of information bits.
  • kb 22
  • the classification of Z by size naturally equivalent to the size of the information bit length K classification.
  • the integer power of 2 is an example. The smaller Z is denser, and the larger Z is sparse.
  • Step 2 For each subset, for example, a set of cyclic coefficient exponential matrices can be generated by a combination of algebra and random. Among them, the random method is to randomly generate an exponential matrix, and then select the optimal one by subsequent methods. Algebraic methods, for example, can first construct a large exponential matrix and then use a random masked matrix to get an exponential matrix. As a result, 8 sets of cyclic coefficient exponential matrices are required for 8 subsets.
  • Step 3 According to the cyclic coefficient exponential matrix determined in step two, further determine each Z in the previously described eight subsets (each set corresponds to a set of cyclic coefficient exponential matrices) and the Z elements outside the partial set
  • the cyclic coefficient corresponding to Z since the Z element outside the set is considered in addition to considering the elements in the set in the embodiment of the present application, so that the coefficient exponent matrix has better adaptability, firstly because the Z in the set often still has Larger spacing, unable to achieve 1-bit granularity, considering the Z element outside the set to participate in the cyclic coefficient design, will increase the robustness of the coefficient exponential matrix to different Z performance, and the other gain is technically different.
  • each subset produces an exponential matrix, which is actually generated according to the largest Z in the subset, and each specific Z coefficient in the subset is a function of the exponential matrix generated by the maximum Z, and the design loop coefficient is such that The performance of all Z's cyclic coefficients in the subset is excellent, and the exponential matrix corresponding to this subset is qualified.
  • An example of a method for determining a cyclic coefficient corresponding to each Z according to a cyclic coefficient exponent matrix is that the cyclic coefficient P i,j can be calculated by the following function:
  • V i,j is the cyclic coefficient corresponding to the (i,j)th element of the coefficient exponent matrix
  • function f is defined as:
  • Step 4 For all the Zs in each subset, for example, the minimum distance estimation of the ring distribution and the codeword is used as the basic measure, and the probabilities of the set-level cyclic coefficient exponential matrix determined in the second step are judged, and the ring number and the minimum distance are larger. The better the codeword performance. If the performance of the aggregation coefficient matrix of the collection level is not good, return to step two again.
  • the ring distribution is a distribution of a ring length, for example, a rectangle has a ring length of 4, and the larger the better, the structure is not closed forever, and the figure is not closed, and the tree is called in the graph theory.
  • the minimum distance is the smallest difference between any two codewords. The smaller the difference, the easier it is to distinguish, the worse the performance of the codeword. Therefore, only the minimum distance is large, and the coded codeword performance is good, so that the search is out.
  • the third step according to the cyclic coefficient exponential matrix determined in the second step, each cyclic coefficient is expanded into a corresponding sub-circular matrix, and finally the parity check matrix H of the LDPC code is obtained.
  • the H matrix is composed of 42 rows and 52 columns of sub-circular matrices. Substituting each sub-circulant matrix with 0 or 1 is a base graph. Each element of each base graph is replaced with a sub-circular matrix to obtain an H-matrix. The circular matrix replaces the 1 in the base graph, which is to design the cyclic coefficients of each sub-matrix. All the cyclic coefficients are described in a matrix as the cyclic coefficient exponential matrix.
  • the fourth step using the check matrix H to complete the LDPC encoding, with the cyclic coefficient and Z, each sub-circle matrix is obtained directly, thereby obtaining the entire H matrix.
  • the base graph #2 used in the 5G LDPC design is 42 rows and 52 columns.
  • the base graph determined at present is shown in Fig. 7.
  • 42 rows correspond to check nodes
  • 52 columns correspond to variable nodes.
  • Kb in the base graph is less than 10
  • the set of the cyclic matrix size Z shown in FIG. 6 is classified according to a, that is, according to each column of FIG. 6, a has 8 different values, and correspondingly obtains 8 different Zs.
  • the Z set corresponding to a 9
  • the design consideration is considered.
  • the girth distribution is as shown in Fig. 14. Since both are 6 rings and 8 rings, the performance is excellent.
  • FIG. 15 An example of the LDPC performance of the base graph design shown in FIG. 8 to FIG. 13 is shown in FIG. 15. It can be seen that the performance of the LDPC code corresponding to the base graph in the embodiment of the present application is better.
  • the method may further include:
  • the sub-circulant matrix is updated using the updated cyclic coefficient exponent matrix.
  • the update includes at least row and column permutation of matrix elements.
  • the row and column permutation may be performed on the designed check matrix H.
  • the row and column permutation includes the replacement of the row and column elements, and the matrix B in FIG.
  • the double diagonal matrix shown and the lower triangular structure shown by the matrix E can maintain the double-pair angle and the lower triangular structure without replacing the other elements in the row and column.
  • this permutation can be the exchange between different rows and columns of the exponential matrix, or it can be the exchange of internal rows or columns of a row of sub-circular matrices represented by one row in the exponential matrix, such as the first of the sub-circulant matrices.
  • the row is replaced by the last row of the sub-circulant matrix, so that the response is the original coefficient value plus a certain value in the value of the exponential matrix.
  • an encoding method provided by an embodiment of the present application includes:
  • the constructing a cyclic coefficient index matrix specifically includes:
  • Step 1 divide the set of dimension Z of the sub-circulant matrix that needs to be supported into multiple subsets
  • Step 2 generating a set of cyclic coefficient exponential matrix for each of the subsets
  • Step 3 Determine, according to the cyclic coefficient exponential matrix, a cyclic coefficient corresponding to Z of the plurality of subsets;
  • Step 4 For each Z, it is detected whether the performance of the determined cyclic coefficient exponent matrix satisfies a preset condition, and if so, the process ends. Otherwise, step 2 is re-executed.
  • Method 1 According to the value of a, divide Z into 8 subsets;
  • Mode 3 According to the length of the information bits, Z is divided into 8 subsets.
  • the step 3 specifically includes: determining a cyclic coefficient P i,j corresponding to each Z by using the following formula:
  • V i,j is the cyclic coefficient corresponding to the (i,j)th element of the cyclic coefficient exponential matrix.
  • the LDPC encoding is performed according to the sub-circulant matrix and the base graph, and specifically includes:
  • the LDPC encoding is performed using the check matrix.
  • the method further includes: performing row and column permutation on the check matrix;
  • the LDPC encoding is performed by using the check matrix, and specifically includes: performing LDPC encoding by using a check matrix after row and column replacement.
  • the row and column replacement of the check matrix includes:
  • an encoding apparatus provided by an embodiment of the present application includes:
  • the first unit 11 is configured to determine a base graph of a low density parity check code LDPC matrix, and construct a cyclic coefficient exponential matrix;
  • a second unit 12 configured to determine a sub-circulation matrix according to the cyclic coefficient exponential matrix
  • the third unit 13 is configured to perform LDPC encoding according to the sub-circulation matrix and the base graph.
  • the first unit constructs a cyclic coefficient exponential matrix, and specifically includes:
  • Step 1 divide the set of dimension Z of the sub-circulant matrix that needs to be supported into multiple subsets
  • Step 2 generating a set of cyclic coefficient exponential matrix for each of the subsets
  • Step 3 Determine, according to the cyclic coefficient exponential matrix, a cyclic coefficient corresponding to Z of the plurality of subsets;
  • Step 4 For each Z, it is detected whether the performance of the determined cyclic coefficient exponent matrix satisfies a preset condition, and if so, the process ends. Otherwise, step 2 is re-executed.
  • step one the first unit performs the method in one of the following manners step one:
  • Method 1 According to the value of a, divide Z into 8 subsets;
  • Mode 3 According to the length of the information bits, Z is divided into 8 subsets.
  • the step 3 specifically includes: determining a cyclic coefficient P i,j corresponding to each Z by using the following formula:
  • V i,j is the cyclic coefficient corresponding to the (i,j)th element of the cyclic coefficient exponential matrix.
  • the third unit is specifically configured to:
  • the LDPC encoding is performed using the check matrix.
  • the third unit is further configured to perform row and column permutation on the check matrix after determining the check matrix;
  • the third unit performs LDPC encoding by using the check matrix, and specifically includes: performing LDPC encoding by using a check matrix after row and column replacement.
  • the third unit performs row and row replacement on the check matrix, and specifically includes:
  • Another encoding apparatus includes a memory and a processor, wherein the memory is used to store program instructions, and the processor is configured to invoke program instructions stored in the memory, and execute according to the obtained program. Any of the above methods.
  • a processor 500 for reading a program in the memory 520, performs the following process:
  • LDPC encoding is performed according to the sub-circulant matrix and the base graph.
  • the processor 500 constructs a cyclic coefficient exponent matrix, and specifically includes:
  • Step 1 divide the set of dimension Z of the sub-circulant matrix that needs to be supported into multiple subsets
  • Step 2 generating a set of cyclic coefficient exponential matrix for each of the subsets
  • Step 3 Determine, according to the cyclic coefficient exponential matrix, a cyclic coefficient corresponding to Z of the plurality of subsets;
  • Step 4 For each Z, it is detected whether the performance of the determined cyclic coefficient exponent matrix satisfies a preset condition, and if so, the process ends. Otherwise, step 2 is re-executed.
  • step one the processor 500 performs the method in one of the following ways step one:
  • Method 1 According to the value of a, divide Z into 8 subsets;
  • Mode 3 According to the length of the information bits, Z is divided into 8 subsets.
  • the step 3 specifically includes: determining a cyclic coefficient P i,j corresponding to each Z by using the following formula:
  • V i,j is the cyclic coefficient corresponding to the (i,j)th element of the cyclic coefficient exponential matrix.
  • the processor 500 performs LDPC encoding according to the sub-circulant matrix and the base graph, and specifically includes:
  • the LDPC encoding is performed using the check matrix.
  • the processor 500 is further configured to perform row and column permutation on the check matrix after determining the check matrix;
  • the processor 500 performs LDPC encoding by using the check matrix, and specifically includes: performing LDPC encoding by using a check matrix after row and column replacement.
  • the processor 500 performs row and row replacement on the check matrix, and specifically includes:
  • the transceiver 510 is configured to receive and transmit data under the control of the processor 500.
  • the bus architecture can include any number of interconnected buses and bridges, specifically linked by one or more processors represented by processor 500 and various circuits of memory represented by memory 520.
  • the bus architecture can also link various other circuits such as peripherals, voltage regulators, and power management circuits, which are well known in the art and, therefore, will not be further described herein.
  • the bus interface provides an interface.
  • Transceiver 510 can be a plurality of components, including a transmitter and a transceiver, providing means for communicating with various other devices on a transmission medium.
  • the processor 500 is responsible for managing the bus architecture and general processing, and the memory 520 can store data used by the processor 500 when performing operations.
  • the processor 500 can be a central buried device (CPU), an application specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or a complex programmable logic device (Complex Programmable Logic Device). , CPLD).
  • CPU central buried device
  • ASIC application specific integrated circuit
  • FPGA field-programmable gate array
  • CPLD complex programmable logic device
  • the encoding device provided by the embodiment of the present invention can also be regarded as a computing device, and the computing device can be specifically a desktop computer, a portable computer, a smart phone, a tablet computer, a personal digital assistant (PDA), or the like.
  • the computing device may include a central processing unit (CPU), a memory, an input/output device, etc.
  • the input device may include a keyboard, a mouse, a touch screen, etc.
  • the output device may include a display device such as a liquid crystal display (Liquid Crystal Display, LCD), cathode ray tube (CRT), etc.
  • LCD liquid crystal display
  • CRT cathode ray tube
  • the memory can include read only memory (ROM) and random access memory (RAM) and provides the processor with program instructions and data stored in the memory.
  • ROM read only memory
  • RAM random access memory
  • the memory may be used to store a program of the encoding method.
  • the processor is configured to execute the above encoding method in accordance with the obtained program instructions by calling a program instruction stored in the memory.
  • a computer storage medium provided by the embodiment of the present application is configured to store computer program instructions used by the computing device, and includes a program for executing the foregoing encoding method.
  • the computer storage medium can be any available media or data storage device accessible by a computer, including but not limited to magnetic storage (eg, floppy disk, hard disk, magnetic tape, magneto-optical disk (MO), etc.), optical storage (eg, CD, DVD, BD, HVD, etc.), and semiconductor memories (for example, ROM, EPROM, EEPROM, non-volatile memory (NAND FLASH), solid-state hard disk (SSD)).
  • magnetic storage eg, floppy disk, hard disk, magnetic tape, magneto-optical disk (MO), etc.
  • optical storage eg, CD, DVD, BD, HVD, etc.
  • semiconductor memories for example, ROM, EPROM, EEPROM, non-volatile memory (NAND FLASH), solid-state hard disk (SSD)).
  • embodiments of the present application can be provided as a method, system, or computer program product.
  • the present application can take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment in combination of software and hardware.
  • the application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.) including computer usable program code.
  • the computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device.
  • the apparatus implements the functions specified in one or more blocks of a flow or a flow and/or block diagram of the flowchart.
  • These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on a computer or other programmable device to produce computer-implemented processing for execution on a computer or other programmable device.
  • the instructions provide steps for implementing the functions specified in one or more of the flow or in a block or blocks of a flow diagram.

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Abstract

一种编码方法及装置、计算机存储介质，用以提高LDPC编码性能，从而适用于5G系统。本申请实施例提供的一种编码方法，包括：确定低密度奇偶校验码LDPC矩阵的基础图base graph，并构造循环系数指数矩阵；根据所述循环系数指数矩阵，确定子循环矩阵；根据所述子循环矩阵以及所述base graph，进行LDPC编码。

Description

一种编码方法及装置、计算机存储介质
本申请要求在2017年6月26日提交中国专利局、申请号为201710496055.X、发明名称为“一种编码方法及装置、计算机存储介质”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及通信技术领域，尤其涉及一种编码方法及装置、计算机存储介质。
背景技术
当前第三代合作伙伴计划(3GPP)提出需要针对5G中移动宽带增强(Enhanced Mobile Broadband，eMBB)场景，给出低密度奇偶校验码(Low Density Parity Check Code，LDPC)信道编码设计。
LDPC码是通过校验矩阵定义的一类线性码，为使译码可行，在码长较长时需要校验矩阵满足稀疏性，即校验矩阵中1的密度比较低，也就是要求校验矩阵中1的个数远小于0的个数，并且码长越长，密度就要越低。
但是，现有技术中没有给出适用于5G系统的LDPC的编码方案。
发明内容
本申请实施例提供了一种编码方法及装置、计算机存储介质，用以提高LDPC编码性能，从而适用于5G系统。
本申请实施例提供的一种编码方法，包括：
确定低密度奇偶校验码LDPC矩阵的基础图base graph，并构造循环系数指数矩阵；
根据所述循环系数指数矩阵，确定子循环矩阵；
根据所述子循环矩阵以及所述base graph，进行LDPC编码。
通过该方法，确定低密度奇偶校验码LDPC矩阵的基础图base graph，并构造循环系数指数矩阵，根据所述循环系数指数矩阵，确定子循环矩阵，根据所述子循环矩阵以及所述base graph，进行LDPC编码，从而提高了LDPC编码性能，适用于5G系统。
可选地，所述构造循环系数指数矩阵，具体包括：
步骤一：将需要支持的子循环矩阵的维数Z的集合划分为多个子集；
步骤二：针对每个所述子集，生成一套循环系数指数矩阵；
步骤三：根据所述循环系数指数矩阵，确定多个子集的Z所对应的循环系数；
步骤四：对每个Z，检测所确定的循环系数指数矩阵的性能是否满足预设条件，如果是，则结束，否则，重新执行步骤二。
可选地，Z＝a×2 j；采用下列方式之一执行所述步骤一：
方式一：根据a的取值，将Z分成多个子集；
方式二：根据j的取值，将Z分成多个子集；
方式三：根据信息比特的长度，将Z分成多个子集。
可选地，所述步骤三具体包括：采用如下公式确定每个Z所对应的循环系数P i,j：
Figure PCTCN2018086927-appb-000001
其中，V i,j是循环系数指数矩阵的第(i,j)个元素对应的循环系数。
可选地，当采用所述方式一时，确定的循环系数指数矩阵如下表所示：
Figure PCTCN2018086927-appb-000002
可选地，当采用所述方式一时，确定的循环系数指数矩阵如下表所示：
Figure PCTCN2018086927-appb-000003
可选地，当采用所述方式一时，确定的循环系数指数矩阵如下表所示：
Figure PCTCN2018086927-appb-000004
可选地，当采用所述方式一时，确定的循环系数指数矩阵如下表所示：
Figure PCTCN2018086927-appb-000005
可选地，当采用所述方式一时，确定的循环系数指数矩阵如下表所示：
Figure PCTCN2018086927-appb-000006
可选地，当采用所述方式一时，确定的循环系数指数矩阵如下表所示：
Figure PCTCN2018086927-appb-000007
可选地，该方法还包括：
对所述循环系数指数矩阵进行更新；
利用更新后的循环系数指数矩阵，更新所述子循环矩阵。
可选地，所述更新至少包括矩阵元素的行列置换。
可选地，根据所述子循环矩阵以及所述base graph，进行LDPC编码，具体包括：
根据所述子循环矩阵以及所述base graph，确定校验矩阵；
利用所述校验矩阵，进行LDPC编码。
可选地，确定校验矩阵之后，该方法还包括：对校验矩阵进行行列置换；
利用所述校验矩阵，进行LDPC编码，具体包括：利用行列置换后的校验矩阵，进行LDPC编码。
可选地，对所述校验矩阵进行行列置换，具体包括：
对校验矩阵中的部分行和/或列元素进行更新，和/或，对校验矩阵中的全部行和/或列元素进行更新。
本申请实施例提供的一种编码装置，包括：
第一单元，用于确定低密度奇偶校验码LDPC矩阵的基础图base graph，并构造循环系数指数矩阵；
第二单元，用于根据所述循环系数指数矩阵，确定子循环矩阵；
第三单元，用于根据所述子循环矩阵以及所述base graph，进行LDPC编码。
可选地，所述第一单元构造循环系数指数矩阵，具体包括：
步骤一：将需要支持的子循环矩阵的维数Z的集合划分为多个子集；
步骤二：针对每个所述子集，生成一套循环系数指数矩阵；
步骤三：根据所述循环系数指数矩阵，确定多个子集的Z所对应的循环系数；
步骤四：对每个Z，检测所确定的循环系数指数矩阵的性能是否满足预设条件，如果是，则结束，否则，重新执行步骤二。
可选地，Z＝a×2 j；所述第一单元采用下列方式之一执行所述步骤一：
方式一：根据a的取值，将Z分成多个子集；
方式二：根据j的取值，将Z分成多个子集；
方式三：根据信息比特的长度，将Z分成多个子集。
可选地，所述步骤三具体包括：采用如下公式确定每个Z所对应的循环系数P i,j：
Figure PCTCN2018086927-appb-000008
其中，V i,j是循环系数指数矩阵的第(i,j)个元素对应的循环系数。
可选地，当采用所述方式一时，确定的循环系数指数矩阵如下表所示：
Figure PCTCN2018086927-appb-000009
可选地，当采用所述方式一时，确定的循环系数指数矩阵如下表所示：
Figure PCTCN2018086927-appb-000010
可选地，当采用所述方式一时，确定的循环系数指数矩阵如下表所示：
Figure PCTCN2018086927-appb-000011
可选地，当采用所述方式一时，确定的循环系数指数矩阵如下表所示：
Figure PCTCN2018086927-appb-000012
可选地，当采用所述方式一时，确定的循环系数指数矩阵如下表所示：
Figure PCTCN2018086927-appb-000013
可选地，当采用所述方式一时，确定的循环系数指数矩阵如下表所示：
Figure PCTCN2018086927-appb-000014
可选地，所述第二单元还用于：
对所述循环系数指数矩阵进行更新；
利用更新后的循环系数指数矩阵，更新所述子循环矩阵。
可选地，所述更新至少包括矩阵元素的行列置换。
可选地，所述第三单元具体用于：
根据所述子循环矩阵以及所述base graph，确定校验矩阵；
利用所述校验矩阵，进行LDPC编码。
可选地，所述第三单元还用于：确定校验矩阵之后，对校验矩阵进行行列置换；
所述第三单元利用所述校验矩阵，进行LDPC编码，具体包括：利用行列置换后的校验矩阵，进行LDPC编码。
可选地，所述第三单元对所述校验矩阵进行行列置换，具体包括：
对校验矩阵中的部分行和/或列元素进行更新，和/或，对校验矩阵中的全部行和/或列元素进行更新。
本申请实施例提供的另一种编码装置，其包括存储器和处理器，其中， 所述存储器用于存储程序指令，所述处理器用于调用所述存储器中存储的程序指令，按照获得的程序执行上述任一种方法。
本申请实施例提供的一种计算机存储介质，所述计算机可读存储介质存储有计算机可执行指令，所述计算机可执行指令用于使所述计算机执行上述任一种方法。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简要介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域的普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的Base matrix的结构示意图；
图2本申请实施例提供的矩阵P的结构示意图；
图3本申请实施例提供的当z＝8时的循环置换矩阵的结构示意图；
图4本申请实施例提供的Base graph与循环系数矩阵(z＝8)的结构示意图；；
图5本申请实施例提供的支持冗余递增的LDPC校验矩阵的结构示意图；
图6本申请实施例提供的5G LDPC要求支持的循环矩阵大小Z的集合的示意图；
图7为本申请实施例提供的Base graph#2的结构示意图；
图8为本申请实施例提供的第一种循环系数指数矩阵的结构示意图；
图9为本申请实施例提供的第二种循环系数指数矩阵的结构示意图；
图10为本申请实施例提供的第三种循环系数指数矩阵的结构示意图；
图11为本申请实施例提供的第四种循环系数指数矩阵的结构示意图；
图12为本申请实施例提供的第五种循环系数指数矩阵的结构示意图；
图13为本申请实施例提供的第六种循环系数指数矩阵的结构示意图；
图14为本申请实施例提供的Z＝128时采用PCM2(a＝3)R＝1/5对应的校 验矩阵的其girth分布示意图；
图15为本申请实施例提供的LDPC循环系数性能的示意图；
图16为本申请实施例提供的一种编码方法的流程示意图；
图17为本申请实施例提供的一种编码装置的结构示意图；
图18为本申请实施例提供的另一种编码装置的结构示意图。
具体实施方式
本申请实施例提供了一种编码方法及装置、计算机存储介质，用以提高LDPC编码性能，从而适用于5G系统。
本申请实施例提供的技术方案，给出针对eMMB场景的数据信道采用LDPC编码替代原长期演进(long term evolution，LTE)系统采用的turbo编码，即给出适用于5G系统的LDPC编码方案。
5G的LDPC码设计要求采用准循环LDPC码，其校验矩阵H可以表示为如下形式：
Figure PCTCN2018086927-appb-000015
其中，A i,j是z×z循环置换矩阵。
对于准循环LDPC码有多种构造方法，例如，首先构造一个大小为ρ×c的基矩阵(Base matrix)，该矩阵的元素非0即1，如图1所示。然后对该基矩阵B的每个1元素扩展为一个z×z循环置换矩阵(Circular Permutation Matrix，CPM)，基矩阵的0元素则扩展为一个z×z的全0矩阵，Base matrix B在后来的基于原模图的LDPC构造方式中被称为基础图(base graph，BG)。用P i表示每个z×z循环置换矩阵，其中矩阵P就是单位阵循环向右移动一位得到的矩阵，如图2所示，而i是循环移位标号，即子矩阵的循环系数。图3给出了一个循环置换矩阵P i(子分组大小为8×8，即z＝8)的实例。
因此，每个循环置换矩阵P i实际上为单位阵I循环右移i次数，循环置换矩阵循环移位标号i满足
Figure PCTCN2018086927-appb-000016
上面所述的循环移位的标号i又称为LDPC校验矩阵的循环移位系数(shifting coefficients)。事实上，循环移位系数，即为子循环矩阵第一行1所处的列的index(标号从0开始，index＝列数-1)。将base graph中的每个1用所对应的子循环矩阵的循环移位系数替换，将base graph中每个0用-1替换，由于每个循环移位标号i是以矩阵指数的形式呈现，所以由此得到的系数矩阵又称为循环系数指数矩阵(shifting coefficients exponent matrix，SEM)。图4表示循环系数指数矩阵的一个例子。其中，BG为3行6列的Base graph，base graph中每个元素对应大小为8行8列的一个子循环矩阵，利用每个子循环矩阵的循环移位系数替换base graph，其中0用-1替换得到循环系数指数矩阵。
上面描述的准循环LDPC码对应的子循环矩阵(CM)，列重可以大于1，例如列重为2或者更大的值，此时子循环矩阵不再是一个循环置换阵(CPM)。
5G的LDPC码设计要求必须支持IR(Incremental redundancy，增量冗余)-HARQ(Hybrid Automatic Repeat Request，混合自动重复请求)，故可以采用递增冗余的方法构造针对5G场景的LDPC码，即首先构造一个高码率的LDPC码，然后采用递增冗余的方式产生更多的校验位，进而得到低码率的LDPC码，基于递增冗余方法构造的LDPC码具有性能优异、码长、码率覆盖范围广、复用度高、易于硬件实现、可以直接用校验矩阵进行编码等优点。具体结构的一个实例如图5所示。其中B是双对角或者准双对角矩阵，C是0矩阵，E是下三角扩展矩阵。LDPC校验矩阵设计主要取决于A、D、E1的设计。
LDPC性能取决于两个最重要的因素，一个是base matrix的设计，另一个为采取何种方式将base matrix中每个非零元素扩展成的一个z×z循环置换矩阵。这两个因素对LDPC性能起到了决定性的作用，base matrix与扩展的子循环置换矩阵的不恰当设计会极大恶化LDPC码性能。
综上所述，5G设计中LDPC校验矩阵正在设计中，由于5G要求支持flexible LDPC，以eMBB数据信道为例，3GPP要求通过两个base graph扩展得到的最多两个LDPC校验矩阵支持最高8/9码率，最低1/5，信息位最长为 8448bits最短40bits；所述的两个base graph，大的base graph为46x68列，其中前22列对应信息位，最低码率为1/3；而小的base graph大小为42x52列，最低码率为1/5。与大的base graph不同，小的base graph为了提高并译码行度，降低译码时延，3GPP目前的结论是当信息比特K>640时，base graph图中前10列对应信息位；当信息比特560<K<＝640时，base graph的前9列对应信息位，当信息比特192<K<＝560时，base graph的前8列对应信息位；当信息比特40<K<＝192时，base graph的前6列对应信息位。
5G LDPC设计中为了让固定的两个base graph支持40～8448的信息比特长度，采用base graph的每个1对应的子循环矩阵扩展成不同大小的子循环矩阵的方法，即子循环矩阵的大小Z可以支持不同的值。3GPP给出的要求支持的子循环矩阵维数Z＝a×2 j，其值具体如图6所示。图6所示的表格中的每一个Z都对应LDPC的一个校验矩阵，如此看来，5G LDPC码设计需要设计很多校验矩阵。如果为每个Z都设计一套循环系数矩阵，不容易存储且工作量巨大，因此找到恰当的支持多种码率与多种信息比特长度且存储复杂度低的LDPC码的循环系数设计方法是一个非常困难的问题，一种方法对多个Z采用相同的循环系数，但是这往往难以得到优异的性能；循环系数的设计对5G LDPC码的设计提出极大挑战。
下面给出本申请实施例提供的LDPC编码方法的详细介绍。
本申请实施例提供的LDPC编码方法，包括：
第一步：以基于密度进化P-EXIT Chart译码门限(码长无限长时的最低译码门限值，即所需的最低SNR值)为测度，结合实际的仿真性能确定base graph；
第二步：构造循环系数指数矩阵，其中，所述的循环系数的每个值代表一个子矩阵的循环系数，且根据前面描述P i系数i位于指数的位置，所以此处称为循环系数指数矩阵，也可以称为exponent matrix。该第二步具体包括下列步骤一至步骤四：
步骤一：将需要支持的子循环矩阵的维数Z的集合划分为多个子集。以 Z＝a×2 j,0≤j≤7,a＝{2,3,5,7,9,11,13,15}为例，可以采用下列方式之一确定多个子集：
方式一:可以根据a进行分类，例如a＝2时，Z＝2×2 j,0≤j≤7是一个子集，这样就将Z分成了8个子集，这8个子集实际上分别对应图6的8列，即第一个set就是图6中a＝2时对应的第一列的值，以此类推；
方式二：可以根据j分类，对j的每个具体取值，Z＝a×2 j,a＝{2,3,5,7,9,11,13,15}就构成一个子集，由于j恰好有8个值，故也对应8个子集，例如j＝0时，对应图6中的第一行中j＝0时对应的第一行的8个值，以此类推；
方式三：根据Z的大小进行分类，因为Kb*Z就是信息比特的长度，其中Kb是base graph图中信息位的列数，与信息比特的个数K不同，对于大的base graph，kb＝22，小的base graph，kb＝10，所以对Z按照大小分类，自然就等价于按照信息比特长度K的大小分类。例如：[2:1:15],[16:2:30],[32:4:64],[72:8:128],[144:16:192],[208:16:256],[288:32:320],[352:32:384]，这种分法实际上是根据信息比特的长度进行分段。信息比特长度K是以比特为单位的，K/kb＝Z的估计值，分段时，按照2的整数次幂就是一个例子，Z较小时分的密集一些，Z较大时分的稀疏一些。
步骤二：针对每个子集，例如可以利用代数与随机相结合的方法产生一套循环系数指数矩阵。其中，随机的方法比如就是随机产生一个指数矩阵，然后通过后续的方法挑选出最优的。代数的方法，例如可以首先构造一个大的指数矩阵，然后利用随机的masked matrix得到一个指数矩阵。如此一来，8个子集共需要8套循环系数指数矩阵。
步骤三：根据步骤二所确定的循环系数指数矩阵，对前面说的8个子集(每个集合对应一套循环系数指数矩阵)中的每个Z及其部分集合外的Z元素，进一步确定每个Z所对应的循环系数，由于本申请实施例中除了考虑集合内的元素还考虑集合外的Z元素，这样使得该系数指数矩阵具有更好的适应性，首先因为集合内的Z往往还是具有较大的间隔，无法达到1比特颗粒度，考虑集合以外的Z元素参与循环系数设计，会增加系数指数矩阵对不同Z 性能的鲁棒性，带来的另外一个增益就是技术上可以为不同的集合配置相同的系数指数矩阵，这样会进一步降低存储量与硬件设计复杂度。其中，每个子集产生一个指数矩阵，这个指数矩阵实际按照子集中最大的Z产生，而子集中每个具体的Z的系数是这个最大Z产生的指数矩阵的一个函数，设计循环系数要使得对子集内所有Z的循环系数性能优异，这个子集所对应的指数矩阵才是合格的。根据循环系数指数矩阵，确定每个Z对应的循环系数的方法的一个例子为：循环系数P i,j可以利用如下函数计算：
P i,j＝f(V i,j,Z)
其中，V i,j是系数指数矩阵的第(i,j)个元素对应的循环系数，函数f定义为：
Figure PCTCN2018086927-appb-000017
步骤四：对每个子集中所有的Z，例如以环分布与码字最小距离估计为基本的测度，判断步骤二所确定的集合级别的循环系数指数矩阵的优劣，环数与最小距离越大，码字性能越好。若集合级别的循环系数指数矩阵性能不好，则重新返回步骤二。其中，所述环分布就是环长的分布，例如矩形其环长为4，越大越好，永远构不成环就是图形不封闭，在图论上叫树。最小距离是任意两个码字间最小的差异，差异越小，就不容易区分，码字性能就越差，因此，只有最小距离大，编码出的码字性能才好，从而才说明搜索出的指数矩阵越好，否则说明该指数矩阵不应该被采用。
第三步：根据第二步确定的循环系数指数矩阵，将每个循环系数扩展为对应的子循环矩阵，最终得到LDPC码的校验矩阵H。
例如，H矩阵是42行52列子循环矩阵构成，将每个子循环矩阵用0或者1代替就是base graph，将每个base graph的每个1元素用子循环矩阵替代就得到H矩阵，用哪个子循环矩阵替代base graph中的1，就是设计每个子矩阵的循环系数，所有的循环系数放在一个矩阵里描述就是循环系数指数矩阵。
第四步：利用校验矩阵H完成LDPC编码，有了循环系数与Z，直接就得到每个子循环矩阵，从而得到整个H矩阵。
下面给出一个具体实施例的举例说明：
5G LDPC设计所采用的base graph#2为42行52列，目前所确定的base graph如图7所示。42行对应校验节点，52列对应变量节点，对于前面所述base graph中信息位Kb小于10的情形，例如Kb＝9，则直接将base graph中第10列删除，若kb＝6，则将base graph的第7,8,9,10列删除，而行不变。
根据图7所示的base graph，将图6所示的循环矩阵大小Z的集合按照a分类，即按照图6的每一列进行分割，a有8个不同的数值，对应得到8个不同的Z集合，例如a＝2对应的Z集合为Set1＝{2,4,8,16,32,64,128,256}，a＝3对应的Z集合为Set2＝{3,6,12,24,48,96,192,384}，a＝5对应的Z集合为Set3＝{5,10,20,40,80,160,320}，a＝7对应的Z集合为Set4＝{7,14,28,56,112,224}，a＝9对应的Z集合为Set5＝{9,18,36,72,144,288}，a＝11对应的Z集合为Set6＝{11,22,44,88,176,352}，a＝13对应的Z集合为Set7＝{13,26,52,104,208}，a＝15对应的Z集合为Set8＝{15,30,60,120,240}。
对每个Z集合按照上述第二步所述的方法，确定6个集合级别的循环系数指数矩阵PCMi,i＝1,2,3,..6分别为Seti i＝1,2,3,..6所对应的循环系数指数矩阵。其中，a＝2，集合Set1对应的循环系数指数矩阵PCM1具体如图8所示；a＝3，集合Set2对应的循环系数指数矩阵PCM2具体如图9所示，其中，图9中给出的矩阵是5G标准中校验矩阵，具体对照可以参见相关文稿；a＝5，集合Set3对应的循环系数指数矩阵PCM3具体如图10所示；a＝7，集合Set4对应的循环系数指数矩阵PCM4具体如图11所示；a＝9，集合Set5对应的循环系数指数矩阵PCM5具体如图12所示；a＝11，集合Set6对应的循环系数指数矩阵PCM6具体如图13所示。
如第二步所述，在为一个集合设计循环系数指数矩阵时，不但根据集合内系数优化，还根据集合外系数优化，以集合二Set2(a＝3)对应的PCM2为例，设计时考虑了集合一Set1(a＝2)中的某些Z，使得集合一Set1(a＝2)中的某些Z采用集合二Set2(a＝3)的PCM2矩阵也具有优异性能，以集合一Set1(a＝2)中的Z＝128，码率为1/5，采用PCM2对应的校验矩阵为例，其 girth分布如图14所示，由于都是6环与8环，所以性能优异。
根据图8至图13所示base graph设计LDPC性能的一个例子如图15所示，可以看到本申请实施例中的base graph对应的LDPC码性能较佳。
需要特别指出的是：
本申请实施例中，还可以包括：
对所述循环系数指数矩阵进行更新；
利用更新后的循环系数指数矩阵，更新所述子循环矩阵。
可选地，所述更新至少包括矩阵元素的行列置换。
本申请实施例中，还可以对所设计的校验矩阵H进行行列置换，行列置换除了包括普通意义的行列置换，还包括保持对行与列的部分元素进行置换，以图5中矩阵B所示的双对角矩阵与矩阵E所示的下三角结构为例，进行行列置换时可以保持双对角度与下三角结构不动，而置换行列中其他元素。从系数指数矩阵角度来看，这种置换可以是指数矩阵不同行列间的交换，还可以是指数矩阵中的一行即代表的一行子循环矩阵内部行或者列的交换，比如子循环矩阵的第一行置换到子循环矩阵的最后一行，这样反应在指数矩阵的数值上就是原来系数值加上某一个数值。
综上，参见图16，本申请实施例提供的一种编码方法，包括：
S101、确定低密度奇偶校验码LDPC矩阵的基础图base graph，并构造循环系数指数矩阵；
S102、根据所述循环系数指数矩阵，确定子循环矩阵；
S103、根据所述子循环矩阵以及所述base graph，进行LDPC编码。
通过该方法，确定低密度奇偶校验码LDPC矩阵的基础图base graph，并构造循环系数指数矩阵，根据所述循环系数指数矩阵，确定子循环矩阵，根据所述子循环矩阵以及所述base graph，进行LDPC编码，从而提高了LDPC编码性能，适用于5G系统。
可选地，所述构造循环系数指数矩阵，具体包括：
步骤一：将需要支持的子循环矩阵的维数Z的集合划分为多个子集；
步骤二：针对每个所述子集，生成一套循环系数指数矩阵；
步骤三：根据所述循环系数指数矩阵，确定多个子集的Z所对应的循环系数；
步骤四：对每个Z，检测所确定的循环系数指数矩阵的性能是否满足预设条件，如果是，则结束，否则，重新执行步骤二。
可选地，Z＝a×2 j,0≤j≤7,a＝{2,3,5,7,9,11,13,15}；采用下列方式之一执行所述步骤一：
方式一：根据a的取值，将Z分成8个子集；
方式二：根据j的取值，将Z分成8个子集；
方式三：根据信息比特的长度，将Z分成8个子集。
可选地，所述步骤三具体包括：采用如下公式确定每个Z所对应的循环系数P i,j：
Figure PCTCN2018086927-appb-000018
其中，V i,j是循环系数指数矩阵的第(i,j)个元素对应的循环系数。
可选地，根据所述子循环矩阵以及所述base graph，进行LDPC编码，具体包括：
根据所述子循环矩阵以及所述base graph，确定校验矩阵；
利用所述校验矩阵，进行LDPC编码。
可选地，确定校验矩阵之后，该方法还包括：对校验矩阵进行行列置换；
利用所述校验矩阵，进行LDPC编码，具体包括：利用行列置换后的校验矩阵，进行LDPC编码。
可选地，对所述校验矩阵进行行列置换，具体包括：
对校验矩阵中的部分行和/或列元素进行更新，和/或，对校验矩阵中的全部行和/或列元素进行更新。
与上述方法相对应地，参见图17，本申请实施例提供的一种编码装置，包括：
第一单元11，用于确定低密度奇偶校验码LDPC矩阵的基础图base graph，并构造循环系数指数矩阵；
第二单元12，用于根据所述循环系数指数矩阵，确定子循环矩阵；
第三单元13，用于根据所述子循环矩阵以及所述base graph，进行LDPC编码。
可选地，所述第一单元构造循环系数指数矩阵，具体包括：
步骤一：将需要支持的子循环矩阵的维数Z的集合划分为多个子集；
步骤二：针对每个所述子集，生成一套循环系数指数矩阵；
步骤三：根据所述循环系数指数矩阵，确定多个子集的Z所对应的循环系数；
步骤四：对每个Z，检测所确定的循环系数指数矩阵的性能是否满足预设条件，如果是，则结束，否则，重新执行步骤二。
可选地，Z＝a×2 j,0≤j≤7,a＝{2,3,5,7,9,11,13,15}；所述第一单元采用下列方式之一执行所述步骤一：
方式一：根据a的取值，将Z分成8个子集；
方式二：根据j的取值，将Z分成8个子集；
方式三：根据信息比特的长度，将Z分成8个子集。
可选地，所述步骤三具体包括：采用如下公式确定每个Z所对应的循环系数P i,j：
Figure PCTCN2018086927-appb-000019
其中，V i,j是循环系数指数矩阵的第(i,j)个元素对应的循环系数。
可选地，所述第三单元具体用于：
根据所述子循环矩阵以及所述base graph，确定校验矩阵；
利用所述校验矩阵，进行LDPC编码。
可选地，所述第三单元还用于：确定校验矩阵之后，对校验矩阵进行行列置换；
所述第三单元利用所述校验矩阵，进行LDPC编码，具体包括：利用行列置换后的校验矩阵，进行LDPC编码。
可选地，所述第三单元对所述校验矩阵进行行列置换，具体包括：
对校验矩阵中的部分行和/或列元素进行更新，和/或，对校验矩阵中的全部行和/或列元素进行更新。
本申请实施例提供的另一种编码装置，其包括存储器和处理器，其中，所述存储器用于存储程序指令，所述处理器用于调用所述存储器中存储的程序指令，按照获得的程序执行上述任一种方法。
例如，参见图18，本申请实施例提供的另一种编码装置，处理器500，用于读取存储器520中的程序，执行下列过程：
确定低密度奇偶校验码LDPC矩阵的基础图base graph，并构造循环系数指数矩阵；
根据所述循环系数指数矩阵，确定子循环矩阵；
根据所述子循环矩阵以及所述base graph，进行LDPC编码。
可选地，所述处理器500构造循环系数指数矩阵，具体包括：
步骤一：将需要支持的子循环矩阵的维数Z的集合划分为多个子集；
步骤二：针对每个所述子集，生成一套循环系数指数矩阵；
步骤三：根据所述循环系数指数矩阵，确定多个子集的Z所对应的循环系数；
步骤四：对每个Z，检测所确定的循环系数指数矩阵的性能是否满足预设条件，如果是，则结束，否则，重新执行步骤二。
可选地，Z＝a×2 j,0≤j≤7,a＝{2,3,5,7,9,11,13,15}；所述处理器500采用下列方式之一执行所述步骤一：
方式一：根据a的取值，将Z分成8个子集；
方式二：根据j的取值，将Z分成8个子集；
方式三：根据信息比特的长度，将Z分成8个子集。
可选地，所述步骤三具体包括：采用如下公式确定每个Z所对应的循环系数P i,j：
Figure PCTCN2018086927-appb-000020
其中，V i,j是循环系数指数矩阵的第(i,j)个元素对应的循环系数。
可选地，所述处理器500根据所述子循环矩阵以及所述base graph，进行LDPC编码，具体包括：
根据所述子循环矩阵以及所述base graph，确定校验矩阵；
利用所述校验矩阵，进行LDPC编码。
可选地，所述处理器500还用于：确定校验矩阵之后，对校验矩阵进行行列置换；
所述处理器500利用所述校验矩阵，进行LDPC编码，具体包括：利用行列置换后的校验矩阵，进行LDPC编码。
可选地，所述处理器500对所述校验矩阵进行行列置换，具体包括：
对校验矩阵中的部分行和/或列元素进行更新，和/或，对校验矩阵中的全部行和/或列元素进行更新。
收发机510，用于在处理器500的控制下接收和发送数据。
其中，在图18中，总线架构可以包括任意数量的互联的总线和桥，具体由处理器500代表的一个或多个处理器和存储器520代表的存储器的各种电路链接在一起。总线架构还可以将诸如外围设备、稳压器和功率管理电路等之类的各种其他电路链接在一起，这些都是本领域所公知的，因此，本文不再对其进行进一步描述。总线接口提供接口。收发机510可以是多个元件，即包括发送机和收发机，提供用于在传输介质上与各种其他装置通信的单元。处理器500负责管理总线架构和通常的处理，存储器520可以存储处理器500在执行操作时所使用的数据。
处理器500可以是中央处埋器(CPU)、专用集成电路(Application Specific Integrated Circuit，ASIC)、现场可编程门阵列(Field－Programmable Gate Array， FPGA)或复杂可编程逻辑器件(Complex Programmable Logic Device，CPLD)。
本申请实施例提供的编码装置，也可以看做是一种计算设备，该计算设备具体可以为桌面计算机、便携式计算机、智能手机、平板电脑、个人数字助理(Personal Digital Assistant，PDA)等。该计算设备可以包括中央处理器(Center Processing Unit，CPU)、存储器、输入/输出设备等，输入设备可以包括键盘、鼠标、触摸屏等，输出设备可以包括显示设备，如液晶显示器(Liquid Crystal Display，LCD)、阴极射线管(Cathode Ray Tube，CRT)等。
存储器可以包括只读存储器(ROM)和随机存取存储器(RAM)，并向处理器提供存储器中存储的程序指令和数据。在本申请实施例中，存储器可以用于存储编码方法的程序。
处理器通过调用存储器存储的程序指令，处理器用于按照获得的程序指令执行上述编码方法。
本申请实施例提供的一种计算机存储介质，用于储存为上述计算设备所用的计算机程序指令，其包含用于执行上述编码方法的程序。
所述计算机存储介质可以是计算机能够存取的任何可用介质或数据存储设备，包括但不限于磁性存储器(例如软盘、硬盘、磁带、磁光盘(MO)等)、光学存储器(例如CD、DVD、BD、HVD等)、以及半导体存储器(例如ROM、EPROM、EEPROM、非易失性存储器(NAND FLASH)、固态硬盘(SSD))等。
本领域内的技术人员应明白，本申请的实施例可提供为方法、系统、或计算机程序产品。因此，本申请可采用完全硬件实施例、完全软件实施例、或结合软件和硬件方面的实施例的形式。而且，本申请可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器和光学存储器等)上实施的计算机程序产品的形式。
本申请是参照根据本申请实施例的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程 和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
显然，本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的精神和范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (32)

  1. 一种编码方法，其特征在于，该方法包括：
    确定低密度奇偶校验码LDPC矩阵的基础图base graph，并构造循环系数指数矩阵；
    根据所述循环系数指数矩阵，确定子循环矩阵；
    根据所述子循环矩阵以及所述base graph，进行LDPC编码。
  2. 根据权利要求1所述的方法，其特征在于，所述构造循环系数指数矩阵，具体包括：
    步骤一：将需要支持的子循环矩阵的维数Z的集合划分为多个子集；
    步骤二：针对每个所述子集，生成一套循环系数指数矩阵；
    步骤三：根据所述循环系数指数矩阵，确定多个子集的Z所对应的循环系数；
    步骤四：对每个Z，检测所确定的循环系数指数矩阵的性能是否满足预设条件，如果是，则结束，否则，重新执行步骤二。
  3. 根据权利要求2所述的方法，其特征在于，Z＝a×2 j，采用下列方式之一执行所述步骤一：
    方式一：根据a的取值，将Z分成多个子集；
    方式二：根据j的取值，将Z分成多个子集；
    方式三：根据信息比特的长度，将Z分成多个子集。
  4. 根据权利要求3所述的方法，其特征在于，所述步骤三具体包括：采用如下公式确定每个Z所对应的循环系数P i,j：
    Figure PCTCN2018086927-appb-100001
    其中，V i,j是循环系数指数矩阵的第(i,j)个元素对应的循环系数。
  5. 根据权利要求4所述的方法，其特征在于，当采用所述方式一时，确定的循环系数指数矩阵如下表所示：
    Figure PCTCN2018086927-appb-100002
  6. 根据权利要求4所述的方法，其特征在于，当采用所述方式一时，确定的循环系数指数矩阵如下表所示：
    Figure PCTCN2018086927-appb-100003
  7. 根据权利要求4所述的方法，其特征在于，当采用所述方式一时，确 定的循环系数指数矩阵如下表所示：
    Figure PCTCN2018086927-appb-100004
  8. 根据权利要求4所述的方法，其特征在于，当采用所述方式一时，确定的循环系数指数矩阵如下表所示：
    Figure PCTCN2018086927-appb-100005
  9. 根据权利要求4所述的方法，其特征在于，当采用所述方式一时，确 定的循环系数指数矩阵如下表所示：
    Figure PCTCN2018086927-appb-100006
  10. 根据权利要求4所述的方法，其特征在于，当采用所述方式一时，确定的循环系数指数矩阵如下表所示：
    Figure PCTCN2018086927-appb-100007
  11. 根据权利要求1～10任一权项所述的方法，其特征在于，该方法还包括：
    对所述循环系数指数矩阵进行更新；
    利用更新后的循环系数指数矩阵，更新所述子循环矩阵。
  12. 根据权利要求11所述的方法，其特征在于，所述更新至少包括矩阵元素的行列置换。
  13. 根据权利要求1所述的方法，其特征在于，根据所述子循环矩阵以及所述base graph，进行LDPC编码，具体包括：
    根据所述子循环矩阵以及所述base graph，确定校验矩阵；
    利用所述校验矩阵，进行LDPC编码。
  14. 根据权利要求13所述的方法，其特征在于，确定校验矩阵之后，该方法还包括：对校验矩阵进行行列置换；
    利用所述校验矩阵，进行LDPC编码，具体包括：利用行列置换后的校验矩阵，进行LDPC编码。
  15. 根据权利要求14所述的方法，其特征在于，对所述校验矩阵进行行列置换，具体包括：
    对校验矩阵中的部分行和/或列元素进行更新，和/或，对校验矩阵中的全部行和/或列元素进行更新。
  16. 一种编码装置，其特征在于，包括：
    存储器，用于存储程序指令；
    处理器，用于调用所述存储器中存储的程序指令，按照获得的程序执行如下方法：
    确定低密度奇偶校验码LDPC矩阵的基础图base graph，并构造循环系数指数矩阵；
    根据所述循环系数指数矩阵，确定子循环矩阵；
    根据所述子循环矩阵以及所述base graph，进行LDPC编码。
  17. 根据权利要求16所述的装置，其特征在于，所述构造循环系数指数矩阵，具体包括：
    步骤一：将需要支持的子循环矩阵的维数Z的集合划分为多个子集；
    步骤二：针对每个所述子集，生成一套循环系数指数矩阵；
    步骤三：根据所述循环系数指数矩阵，确定多个子集的Z所对应的循环系数；
    步骤四：对每个Z，检测所确定的循环系数指数矩阵的性能是否满足预设条件，如果是，则结束，否则，重新执行步骤二。
  18. 根据权利要求17所述的装置，其特征在于，Z＝a×2 j；采用下列方式之一执行所述步骤一：
    方式一：根据a的取值，将Z分成多个子集；
    方式二：根据j的取值，将Z分成多个子集；
    方式三：根据信息比特的长度，将Z分成多个子集。
  19. 根据权利要求18所述的装置，其特征在于，所述步骤三具体包括：采用如下公式确定每个Z所对应的循环系数P i,j：
    Figure PCTCN2018086927-appb-100008
    其中，V i,j是循环系数指数矩阵的第(i,j)个元素对应的循环系数。
  20. 根据权利要求19所述的装置，其特征在于，当采用所述方式一时，确定的循环系数指数矩阵如下表所示：
    Figure PCTCN2018086927-appb-100009
  21. 根据权利要求19所述的装置，其特征在于，当采用所述方式一时，确定的循环系数指数矩阵如下表所示：
    Figure PCTCN2018086927-appb-100010
  22. 根据权利要求19所述的装置，其特征在于，当采用所述方式一时，确定的循环系数指数矩阵如下表所示：
    Figure PCTCN2018086927-appb-100011
  23. 根据权利要求19所述的装置，其特征在于，当采用所述方式一时， 确定的循环系数指数矩阵如下表所示：
    Figure PCTCN2018086927-appb-100012
  24. 根据权利要求19所述的装置，其特征在于，当采用所述方式一时，确定的循环系数指数矩阵如下表所示：
    Figure PCTCN2018086927-appb-100013
  25. 根据权利要求19所述的装置，其特征在于，当采用所述方式一时， 确定的循环系数指数矩阵如下表所示：
    Figure PCTCN2018086927-appb-100014
  26. 根据权利要求16～25任一权项所述的装置，其特征在于，还包括：
    对所述循环系数指数矩阵进行更新；
    利用更新后的循环系数指数矩阵，更新所述子循环矩阵。
  27. 根据权利要求26所述的装置，其特征在于，所述更新至少包括矩阵元素的行列置换。
  28. 根据权利要求16所述的装置，其特征在于，根据所述子循环矩阵以及所述base graph，进行LDPC编码，具体包括：
    根据所述子循环矩阵以及所述base graph，确定校验矩阵；
    利用所述校验矩阵，进行LDPC编码。
  29. 根据权利要求28所述的装置，其特征在于，确定校验矩阵之后，还包括：对校验矩阵进行行列置换；
    利用所述校验矩阵，进行LDPC编码，具体包括：利用行列置换后的校验矩阵，进行LDPC编码。
  30. 根据权利要求29所述的装置，其特征在于，对所述校验矩阵进行行列置换，具体包括：
    对校验矩阵中的部分行和/或列元素进行更新，和/或，对校验矩阵中的全部行和/或列元素进行更新。
  31. 一种编码装置，其特征在于，包括：
    第一单元，用于确定低密度奇偶校验码LDPC矩阵的基础图base graph，并构造循环系数指数矩阵；
    第二单元，用于根据所述循环系数指数矩阵，确定子循环矩阵；
    第三单元，用于根据所述子循环矩阵以及所述base graph，进行LDPC编码。
  32. 一种计算机存储介质，其特征在于，所述计算机可读存储介质存储有计算机可执行指令，所述计算机可执行指令用于使所述计算机执行权利要求1至15任一项所述的方法。
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2021010512A1 (ko) * 2019-07-16 2021-01-21 엘지전자 주식회사 무선 통신 시스템에서 프로토그래프로부터 생성된 저밀도 패리티 검사 부호의 패리티 검사 행렬에 기초하여 부호화를 수행하는 방법 및 장치
US11784663B2 (en) 2019-07-16 2023-10-10 Lg Electronics Inc. Method and apparatus for performing encoding on basis of parity check matrix of low density parity check code generated from protograph in wireless communication system
CN110611510A (zh) * 2019-09-17 2019-12-24 天地信息网络研究院(安徽)有限公司 一种二元ldpc短码构造方法及其构造装置、终端、存储介质
CN110611510B (zh) * 2019-09-17 2021-03-23 天地信息网络研究院(安徽)有限公司 一种二元ldpc短码构造方法及其构造装置、终端、存储介质

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US20200145025A1 (en) 2020-05-07
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JP7091375B2 (ja) 2022-06-27
TWI679854B (zh) 2019-12-11
JP2020527880A (ja) 2020-09-10
EP3648357A4 (en) 2020-07-01
TW201906328A (zh) 2019-02-01
CN109120275A (zh) 2019-01-01
WO2019001159A9 (zh) 2020-01-09
EP3648357B1 (en) 2023-04-05
KR102300273B1 (ko) 2021-09-08
US11038531B2 (en) 2021-06-15

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