WO2022135318A1 - 低密度奇偶校验编码方法、低密度奇偶校验译码方法、编码设备、译码设备及介质 - Google Patents

低密度奇偶校验编码方法、低密度奇偶校验译码方法、编码设备、译码设备及介质 Download PDF

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WO2022135318A1
WO2022135318A1 PCT/CN2021/139513 CN2021139513W WO2022135318A1 WO 2022135318 A1 WO2022135318 A1 WO 2022135318A1 CN 2021139513 W CN2021139513 W CN 2021139513W WO 2022135318 A1 WO2022135318 A1 WO 2022135318A1
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parity check
check matrix
matrix
target
boost value
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PCT/CN2021/139513
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English (en)
French (fr)
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李立广
许进
郁光辉
梁楚龙
徐俊
傅强
康健
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中兴通讯股份有限公司
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Priority to AU2021408115A priority Critical patent/AU2021408115A1/en
Priority to EP21909314.3A priority patent/EP4270793A1/en
Priority to KR1020237024766A priority patent/KR20230124036A/ko
Priority to US18/258,793 priority patent/US20240048160A1/en
Publication of WO2022135318A1 publication Critical patent/WO2022135318A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/118—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/61—Aspects and characteristics of methods and arrangements for error correction or error detection, not provided for otherwise
    • H03M13/615—Use of computational or mathematical techniques
    • H03M13/616—Matrix operations, especially for generator matrices or check matrices, e.g. column or row permutations
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/61—Aspects and characteristics of methods and arrangements for error correction or error detection, not provided for otherwise
    • H03M13/618—Shortening and extension of codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/63—Joint error correction and other techniques
    • H03M13/635—Error control coding in combination with rate matching
    • H03M13/6362—Error control coding in combination with rate matching by puncturing
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6508—Flexibility, adaptability, parametrability and configurability of the implementation
    • H03M13/6516—Support of multiple code parameters, e.g. generalized Reed-Solomon decoder for a variety of generator polynomials or Galois fields
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6522—Intended application, e.g. transmission or communication standard

Definitions

  • the present application relates to the field of wireless communication networks, for example, to a low density parity check encoding method, a low density parity check decoding method, an encoding device, a decoding device and a medium.
  • the transmitting end performs channel coding on the data to be transmitted to obtain a coded bit sequence, and then maps the coded bit sequence into a constellation modulation symbol and sends it to the receiving end.
  • the data transmission channel affected by factors such as multipath, movement, noise, interference, etc., the data transmission is distorted.
  • the receiving end needs to perform channel decoding on the received constellation modulation symbols to recover the transmitted data.
  • the receiving end can check and restore the transmitted data accordingly.
  • a Low Density Parity Check (LDPC) code is a linear block code defined by a sparse parity check matrix or a bipartite graph. Since the parity check matrix is very sparse, the decoding complexity can be reduced and the reliability is high. However, the maximum boost value of LDPC codes is fixed, only 384, and the dimension of the base matrix is large, which cannot support flexible code length and code rate, which limits the decoding parallelism of LDPC codes and the throughput of data transmission.
  • the present application provides a low density parity check encoding method, a low density parity check decoding method, an encoding device, a decoding device and a medium, so as to improve the flexibility of encoding and the throughput of data transmission.
  • An embodiment of the present application provides a low-density parity check encoding method, including:
  • the target parity check matrix belongs to the second parity check matrix set, and the base matrix of the second parity check matrix set is extracted from the base matrix of the first parity check matrix set Obtained; according to the target parity check matrix and the target boost value, low-density parity check coding is performed on the data to be transmitted.
  • the embodiment of the present application also provides a low-density parity check encoding method, including:
  • the target base matrix is the base matrix of the second parity check matrix set, and the base matrix of the second parity check matrix set is extracted from the base matrix of the first parity check matrix set. ; Perform low-density parity check coding on the data to be transmitted according to the target base matrix and the target boost value.
  • the embodiment of the present application also provides a low-density parity check decoding method, including:
  • the target parity check matrix belongs to the second parity check matrix set, and the base matrix of the second parity check matrix set is extracted from the base matrix of the first parity check matrix set Obtained: performing low-density parity-check decoding on the received data according to the target parity check matrix and the target boost value.
  • the embodiment of the present application also provides a low-density parity check decoding method, including:
  • the target base matrix is the base matrix of the second parity check matrix set, and the base matrix of the second parity check matrix set is extracted from the base matrix of the first parity check matrix set. ; Perform low-density parity-check decoding on the received data according to the target base matrix and the target boost value.
  • Embodiments of the present application further provide an encoding device, including a memory, a processor, and a computer program stored in the memory and running on the processor, where the processor implements the above-mentioned low-density parity check when executing the program encoding method.
  • Embodiments of the present application further provide a decoding device, including a memory, a processor, and a computer program stored in the memory and running on the processor, where the processor implements the above-mentioned low-density parity check when executing the program Check the decoding method.
  • Embodiments of the present application further provide a computer-readable storage medium, where a computer program is stored on the computer-readable storage medium, and when the program is executed by a processor, the above-mentioned low-density parity check encoding method or low-density parity check translation method is implemented. code method.
  • FIG. 1 is a flowchart of a low-density parity check encoding method provided by an embodiment
  • FIG. 2 is a flowchart of a low-density parity check encoding method provided by another embodiment
  • FIG. 3 is a schematic diagram of a simulation performance of LDPC encoding based on a target parity check matrix provided by an embodiment
  • FIG. 4 is a flowchart of a low-density parity check decoding method provided by an embodiment
  • FIG. 5 is a flowchart of a low-density parity-check decoding method provided by another embodiment
  • FIG. 6 is a schematic structural diagram of a low-density parity-check encoding apparatus provided by an embodiment
  • FIG. 7 is a schematic structural diagram of a low-density parity-check encoding apparatus provided by another embodiment
  • FIG. 8 is a schematic structural diagram of a low-density parity-check decoding apparatus according to an embodiment
  • FIG. 9 is a schematic structural diagram of a low-density parity-check decoding apparatus provided by another embodiment.
  • FIG. 10 is a schematic diagram of a hardware structure of an encoding device provided by an embodiment
  • FIG. 11 is a schematic diagram of a hardware structure of a decoding device according to an embodiment.
  • the check matrix H of the LDPC code is a matrix with mb ⁇ z rows and nb ⁇ z columns. It is composed of mb ⁇ nb sub-matrices P, each of which is a different power of the standard permutation matrix of z ⁇ z (corresponding to The cyclic shift matrix of the identity matrix) or the all-zero square matrix of z ⁇ z.
  • the check matrix H has the following form:
  • the corresponding submatrix is an all-zero square matrix of z ⁇ z; if is an integer greater than or equal to 0, the corresponding submatrix is the standard permutation matrix P 0 power, the standard permutation matrix P 0 of z ⁇ z has the following form:
  • Each sub-matrix can be uniquely identified. If a sub-matrix is an all-zero square matrix, the corresponding It is represented by -1 (it can also be represented by a null value); if a submatrix is obtained by cyclic shift s of the identity matrix, then equal to s, all A parity check matrix Hb is formed.
  • z is the dimension of the standard permutation matrix (and submatrices), called Lifting Size.
  • the LDPC code can be uniquely determined by the parity check matrix Hb and the boost value z. Correspondingly, by replacing all non-1 elements in the parity check matrix with "1”, and replacing all -1 elements with "0", the base matrix BG can be obtained.
  • the number of check columns of the matrix is equal to the number of matrix rows mb
  • the corresponding LDPC code is a systematic code, which consists of an LDPC code information bit sequence c of length kb*z and an LDPC code check bit sequence w of length mb*z.
  • the LDPC code information bit sequence c is known, and the essence of LDPC coding is to obtain the LDPC code check bit sequence w.
  • extracting a matrix B from a matrix A refers to: extracting the matrix A according to the row index sequence a and/or the column index sequence b to obtain a sub-matrix B.
  • the maximum boost value Zmax of the LDPC code is 384.
  • the maximum decoding parallelism of LDPC decoding can only reach 384 at most, and the dimension of the base matrix is large, which limits the throughput of LDPC decoding.
  • the LDPC coding method in this embodiment can be applied to a transmitter in a communication system, and the LDPC decoding method can be applied to a receiver in a communication system, and LDPC coding is used to protect the transmitted data.
  • the transmitter uses an LDPC encoder to perform LDPC encoding on the data information bit sequence to be transmitted
  • the receiver uses an LDPC decoder to perform LDPC decoding on the received information, thereby recovering the data information bit sequence.
  • the decoding process includes: the LDPC decoder iteratively performs parity check operations and variable node operations using parameters related to the parity check matrix, and continuously attempts to correct any bits in the LDPC codeword that may be received in error during each iteration.
  • the LDPC codeword may be a quasi-cyclic LDPC code, a structured LDPC code, or a boosted LDPC code.
  • the LDPC decoder includes multiple processing elements that can perform parity operations and variable node operations in parallel. For example, when processing an LDPC codeword with a boost value of z, the LDPC decoder may utilize several (eg, z, or positive integer factors of z) processing elements to perform parity and variable node operations concurrently.
  • a low-density parity check coding method which uses a target parity check matrix for coding, which can not only improve the throughput of data transmission and the decoding parallelism of LDPC codes, but also support flexible code length. and bit rate to improve coding flexibility.
  • FIG. 1 is a flowchart of a low density parity check encoding method according to an embodiment. As shown in FIG. 1 , the method provided in this embodiment includes step 110 and step 120 .
  • step 110 a target parity check matrix is determined, the target parity check matrix belongs to the second parity check matrix set, and the basis matrix of the second parity check matrix set is from the first parity check matrix set extracted from the base matrix.
  • step 120 low-density parity check encoding is performed on the data to be transmitted according to the target parity check matrix and the target boost value.
  • a target parity check matrix (hereinafter referred to as Hb) is selected from the second parity check matrix set (hereinafter referred to as the parity check matrix set P2), and Hb and the target boost value (hereinafter referred to as the Zc) Encode the data to be transmitted to obtain an LDPC code for transmission.
  • the parity check matrix set P2 is obtained according to the first parity check matrix set (hereinafter referred to as the parity check matrix set P1), and the basis matrices of the parity check matrix set P2 and the parity check matrix set P1 satisfy:
  • the base matrix of the parity check matrix set P2 is a submatrix extracted from the base matrix of the parity check matrix set P1.
  • the base matrix of the parity check matrix set P2 is a sub-matrix of the base matrix of the parity check matrix set P1, it means that the LDPC decoding using the parity check matrix set P2 will be compatible with the LDPC of the parity check matrix set P1.
  • the LDPC decoder equivalent to the parity check matrix set P2 only uses a part of the hardware circuit in the LDPC decoder of the parity check matrix set P1 (such as the variable in the LDPC decoder that uses the parity check matrix set P1).
  • the node update module and the check node update module, and the routing network of the LDPC decoder of the parity check matrix set P1 and the LDPC decoder of the parity check matrix set P2 are basically the same), so that the parity check matrix set can be
  • the decoding of P1 and the parity check matrix set P2 are completely compatible, which improves the decoding efficiency of LDPC, and the parity check matrix set P2 can be designed with a higher boost value, so that a higher decoding parallelism can be used, thereby achieving more efficient decoding. high-throughput decoding.
  • the parity check matrix set P1 may use a known parity check matrix set in a related standard protocol.
  • the parity check matrix set P1 and the parity check matrix set P2 may be equal, and the base matrix of the parity check matrix set P1 and the base matrix of the parity check matrix set P2 may be equal. In this case, it can be understood that according to all rows Indexes and column indexes are extracted.
  • the parity check matrix set P2 can be determined, and the parity check matrix set P2 can be determined from the parity check matrix set.
  • the Hb used for encoding is determined in P2.
  • the basis matrix of the parity check matrix set P2 is extracted from the basis matrix of the parity check matrix set P1
  • the number of systematic columns and/or the number of check columns of Hb can be reduced , so that the receiver can perform parallel decoding for more parity check matrices, which improves the parallelism of decoding and the throughput of data transmission, and this encoding method supports flexible encoding for any code length and code rate.
  • step 110 includes: determining a target parity check matrix of the second set of parity check matrices according to the first set of parity check matrices. That is, the parity check matrix set P2 is determined from the parity check matrix set P1, and Hb is determined from the parity check matrix set P2.
  • step 110 includes:
  • the base matrix of the second parity check matrix set is determined according to the base matrix of the first parity check matrix set; the target parity check matrix of the second parity check matrix set is determined according to the base matrix of the second parity check matrix set. That is, the basis matrix of the parity check matrix set P2 is determined according to the basis matrix of the parity check matrix set P1, and the Hb corresponding to the parity check matrix set P2 is determined according to the basis matrix of the parity check matrix set P2.
  • step 110 includes:
  • a second parity check matrix set is determined according to the index sequence and the first parity check matrix set; and a target parity check matrix is determined from the second parity check matrix set. That is, the parity check matrix set P2 is determined according to the index sequence and the parity check matrix set P1, and Hb is determined from P2.
  • the index sequence includes at least one of a row index sequence and a column index sequence.
  • step 110 includes:
  • the target parity check matrix is determined from the first set of parity check matrices or the second set of parity check matrices. That is, Hb belongs to the parity check matrix set P1 or the parity check matrix set P2.
  • the base matrix of the second set of parity check matrices is extracted from the base matrix of the first set of parity check matrices according to at least one of a row index sequence and a column index sequence.
  • the dimension of the base matrix of Hb is mb rows and nb columns, and both mb and nb are integers greater than 0.
  • the dimension of Hb is mb rows and nb columns.
  • the dimensions of the basis matrix of the parity check matrix set P1 are mb1 rows and nb1 columns, and both mb1 and nb1 are integers greater than 0.
  • the base matrix of the parity check matrix set P2 has a row number of mb2 and a column number of nb2, wherein both mb2 and nb2 are integers greater than 0.
  • the length of the row index sequence is mb2, and each element in the row index sequence is taken from the set ⁇ 0,1,2...,(mb1-1) ⁇ , and each element is independent of each other same.
  • One element in the row index sequence is 0, indicating that the first row is extracted from the basis matrix of the parity check matrix set P1.
  • the length of the column index sequence is nb2, and each element in the column index sequence takes values in the set ⁇ 0,1,2...,(nb1-1) ⁇ , and each element is different from each other.
  • One element in the column index sequence is 0, indicating that the first column is to be extracted from the basis matrix of the parity check matrix set P1.
  • mb2 is a positive integer less than mb1
  • nb2 is a positive integer less than nb1.
  • the row index sequence satisfies one of the following:
  • the elements in the row index sequence are consecutive ascending integers, which can also be understood as the row index sequence is a set of consecutive ascending integers; 2)
  • the elements in the row index sequence include discontinuous ascending integers, which can also be understood as the row index sequence.
  • the index sequence is a discontinuous set of ascending integers; 3)
  • the elements in the row index sequence are non-ascending integers, and the first M elements in the row index sequence are consecutive ascending integers, and M is an integer greater than 1 and less than mb2, which can also be understood , the row index sequence is a non-ascending integer set; 4) the row index sequence includes at least ⁇ 0, 1, 2, 3 ⁇ .
  • the first 4 elements in the row index sequence are ⁇ 0, 1, 2, 3 ⁇ .
  • the column index sequence satisfies one of the following:
  • the first E elements of the column index sequence are consecutive ascending integers, and E is greater than 1; 2) The first E elements of the column index sequence include discontinuous ascending integers, and E is greater than 1; 3) The column index sequence includes at least ⁇ 0, 1 ⁇ ; 4) The column index sequence includes at least ⁇ 22, 23, 24, 25 ⁇ .
  • the first 2 elements of the column index sequence are ⁇ 0, 1 ⁇ .
  • the row index sequence and the column index sequence include one of the following combinations:
  • the row index sequence is a continuous set of ascending integers; the first E elements of the column index sequence are discontinuous ascending integers, and E is an integer greater than 1; 2) The row index sequence is a discontinuous set of ascending integers; the column index sequence The first E elements of are discontinuous ascending integers, E is an integer greater than 1; 3) The row index sequence is a set of continuous ascending integers; the first E elements of the column index sequence are continuous ascending integers, E is greater than 1 Integer; 4) The row index sequence is a discontinuous set of ascending integers; the first E elements of the column index sequence are consecutive ascending integers, and E is an integer greater than 1.
  • E is an integer greater than 1 and less than or equal to kb2, and kb2 is equal to the difference between nb2 and mb2, that is, kb2 is equal to the number of systematic columns of the base matrix of the parity check matrix set P2 or the parity check in the parity check matrix set P1 The number of systematic columns of the matrix.
  • E is equal to kb2.
  • kb2 is equal to the number of systematic columns of the base matrix of the second set of parity check matrices, or equal to the difference between the number of columns and the number of rows of the base matrix of the second set of parity check matrices, or less than or equal to the first The number of systematic columns of parity check matrices in a parity check matrix set P1.
  • the number of systematic columns of the basis matrix of the parity check matrix set P1 is kb1, where kb1 is an integer greater than 0, and kb2 is smaller than kb1.
  • kb2 is a positive integer less than 22.
  • kb2 takes values in the set ⁇ 12, 14, 15, 16, 18, 20 ⁇ .
  • kb2 is a positive integer less than kb1-4.
  • kb2 takes values in the set ⁇ 12, 14, 15, 16, 17 ⁇ .
  • the first parity check matrix set includes a1 first parity check matrices, and the basis matrices of the a1 first parity check matrices are the same;
  • the second parity check matrix set includes a2 second parity check matrices. Parity check matrix, the base matrices of the a2 second parity check matrices are the same;
  • the maximum boost value Zmax2 (hereinafter referred to as Zmax2) of the second parity check matrix set is the i-th first parity check matrix in the first parity check matrix set.
  • the maximum boost value supported by the parity check matrix (hereinafter referred to as Zi) is D times, D is a positive integer power of 2, i is a non-negative integer less than a1, and Zi is the ith in the parity check matrix set P1.
  • the maximum boost value supported by the first parity check matrix is D times, D is a positive integer power of 2, i is a non-negative integer less than a1, and Zi is the ith in the parity check matrix set P1.
  • the maximum boost value supported by the i-th first parity check matrix in the parity check matrix set P1 is Zi, i is equal to one of 0, 1, 2, ... or (a1-1), the parity check matrix
  • the maximum boost value of the ith second parity check matrix in the set P2 is D times Zi, that is, equal to Zi*D.
  • D is an integer greater than 1, and D is equal to a positive integer power of 2, eg, D is equal to 2, 4, or 8.
  • Zmax2 is equal to one of the following: Z0, Z1, Z2, . . . , Z(a1-1).
  • the maximum boost value Zmax2 of the parity check matrix set P2 is greater than the maximum boost value Zmax1 of P1.
  • the maximum boost value supported by the parity check matrix set P1 is Zmax1
  • the maximum boost value supported by the parity check matrix set P2 is Zmax2, wherein both Zmax1 and Zmax2 are integers greater than 0, and Zmax2 is greater than Zmax1.
  • Zmax1 is equal to 384, and Zmax2 is a positive integer greater than 384.
  • Zmax2 is in the set ⁇ 416, 448, 480, 512, 576, 640, 704, 768, 832, 896, 960, 1024, 1152, 1280, 1408, 1536, 1664, 1792, 1920, 2048 ⁇ value.
  • the maximum boost value Zmax2 of the second set of parity check matrices is a ⁇ 2 b , where a is an odd number greater than 15, and b is a positive integer.
  • Zmax2 is equal to a ⁇ 2 b , where a is an odd number greater than 15, and b is a positive integer.
  • a takes values in the set ⁇ 17, 19, 21, 23, 25, 27, 29, 31, 33, 35, 37, 39, 41 ⁇ ; b takes values in the set ⁇ 4, 5, 6, 7 , 8, 9, 10 ⁇ .
  • the at least one subset of boost values supported by the second set of parity check matrices at least includes: a ⁇ 2 B , where a is an odd number greater than 15, and B is a set of non-negative integers.
  • a takes values in the set ⁇ 17, 19, 21, 23, 25, 27, 29, 31, 33, 35, 37, 39, 41 ⁇ ;
  • B is a set of consecutive non-negative integers gather.
  • B is the set consisting of B0 to B1, where B0 is equal to 2, 3, 4, or 5; B1 is equal to 5, 6, 7, or 8.
  • the minimum value in the 1 subset of boost values is greater than 384.
  • the target boost value belongs to one boost value subset in the G boost value subsets, where G is greater than 1, and there is no intersection between any two boost value subsets in the G boost value subsets.
  • G boost value subsets there are G boost value subsets, and the indices of each boost value subset are respectively recorded as 0, 1, ..., (G-1), G is an integer greater than 1, and any two boost value subsets are There is no intersection between sets.
  • the target lift value is 1 element in the subset of G lift values.
  • the indices of the boost value subsets supported by the first parity check matrix set constitute a set Set1; the indices of the boost value subsets supported by the second parity check matrix set constitute a set Set2.
  • Set2 is a subset of Set1, or the intersection of Set2 and Set1 is the empty set.
  • the boost values supported by the first parity check matrix set constitute the first boost value set Zset1
  • the boost values supported by the second parity check matrix set constitute the second boost value set Zset2
  • Zset1 and Zset2 satisfy one of the following: one:
  • Zset1 and Zset2 have no intersection; 2) Zset1 is a subset of Zset2; 3) The number of elements in the intersection Zset of Zset1 and Zset2 is less than the number of elements in Zset1 and less than the number of elements in Zset2.
  • the minimum boost value supported by the second parity check matrix set is greater than the maximum boost value supported by the first parity check matrix set; the boost value supported by the second parity check matrix set includes at least one of the following: 416 , 448, 480, 512, 576, 640, 704, 768, 832, 896, 960, 1024, 1152, 1280, 1408, 1536, 1664, 1792, 1920, 2048.
  • the maximum information length Kmax1 supported by the first set of parity check matrices is smaller than the maximum information length Kmax2 supported by the second set of parity check matrices.
  • Kmax1 is equal to 8448.
  • the second parity check matrix set includes at least one parity check matrix
  • the parity check matrix includes k0 upper and lower adjacent pairs
  • the k0 upper and lower adjacent pairs include k1 first type upper and lower pairs.
  • Adjacent pairs and k2 second-class up-down adjacent pairs, and k1 is greater than 3*k2, and both k1 and k2 are integers greater than 0; wherein, up-down adjacent pairs refer to any two indication units in the parity check matrix Arrays are cyclically shifted and located in the same column of adjacent elements; the difference between the two elements of the first type of upper and lower adjacent pairs is equal to 0; the difference between the two elements of the second type of upper and lower adjacent pairs is equal to 0 The result of taking the remainder of 2 is greater than 0.
  • the upper and lower adjacent pairs are defined as: any 2 elements in the parity check matrix ⁇ h i,j ,h (i+1) mod mb,j ⁇ , these 2 elements both indicate the unit matrix cycle Shifted element (not -1), mb is the number of rows of the parity check matrix, mod represents the remainder operation.
  • a is equal to 0, k0, k1 and k2 are all positive integers, and k1 is greater than 3 times of k2.
  • the identity matrix can be divided into multiple groups during the decoding process, and there is no address conflict between the update of the check nodes of each row, which can reduce the waiting time between the updates of the check nodes of each row, and the decoding speed is faster; If the result of taking the remainder of 2 is 1 instead of 0, and the difference is an odd number, the second type of upper and lower adjacent pair is formed. In this case, there is an address conflict between the update of the check nodes of each row, and the update of the check nodes of each row Waiting time is required, and the decoding speed is slow.
  • the number of upper and lower adjacent pairs of the first type may be appropriately increased.
  • the second parity check matrix set includes at least one parity check matrix
  • the parity check matrix includes k3 first-type elements indicating the cyclic shift of the identity matrix and k4 elements indicating the cyclic shift of the identity matrix.
  • the second type element of the bit, and k3 is greater than 3*k4, k3 and k4 are integers greater than 0; among them, the result of taking the remainder of the first type element to 2 is equal to 0; the result of taking the remainder of the second type element to 2 is greater than 0.
  • the parity check matrix set P2 includes at least one parity check matrix
  • the parity check matrix includes k3 first-type elements indicating the cyclic shift of the unit matrix and k4 elements indicating the cyclic shift of the unit matrix.
  • the second type of element where the first type element satisfies the following relation: mod(hi ,j ,2) ⁇ b, the second type element satisfies the following relation: mod(hi ,j ,2)>b, where h i , j is the element indicating the cyclic shift of the identity matrix in the parity check matrix whose abscissa is i and whose column is j.
  • b is equal to 0, k3 and k4 are positive integers, and k3 is greater than 3 times of k4.
  • the remainder operation is used to determine whether the element indicating the cyclic shift of the identity matrix is an odd number or an even number. If the result of taking the remainder of 2 is 0, it is an even number, which constitutes the first type element, the unit matrix indicated by the first type element, and there is no address conflict between the check node updates of each row, which can reduce the check node update time of each row.
  • the decoding speed is faster; if the result of taking the remainder of 2 is not 0, it is an odd number, which constitutes the second type element. Address conflict, waiting time is required between the update of the check nodes of each row, and the decoding speed is slow. Therefore, in the determined target parity check matrix, the greater the number of elements of the first type, the higher the decoding speed. When determining the target parity check matrix, the number of elements of the first type may be appropriately increased.
  • it also includes:
  • Step 100 determine a parity check matrix set from at least two parity check matrix sets as the target parity check matrix set according to the setting information; wherein, the setting information includes at least one of the following: Transport Block Size (Transport Block Size , TBS), code rate, high-layer signaling, modulation order, modulation and coding scheme index, modulation and coding strategy (Modulation and Coding Scheme, MCS) table index.
  • Transport Block Size Transport Block Size , TBS
  • code rate High-layer signaling
  • modulation order modulation order
  • modulation and coding scheme index modulation and coding strategy (Modulation and Coding Scheme, MCS) table index.
  • MCS Modulation and Coding Scheme
  • one of the at least two parity check matrix sets is determined as the target parity check matrix set according to the setting information, and Hb is determined from the target parity check matrix set.
  • the at least two parity check matrix sets there are two parity check matrix sets such that the base matrix of one parity check matrix set is a submatrix extracted from the base matrix of the other parity check matrix set.
  • the parity check matrix set P2 is determined according to the parity check matrix set P1, and the basis matrix of the parity check matrix set P2 is the basis of the parity check matrix set P1.
  • the submatrix extracted from the matrix According to the setting information, the parity check matrix set P1 or the parity check matrix set P2 can be selected as the target parity check matrix set, and a parity check matrix is determined as Hb.
  • a set of parity check matrices P1 and a third set of parity check matrices are given in the relevant standard protocol, and the parity check matrix is determined according to the set of parity check matrices P1.
  • the matrix set P2, the base matrix of the parity check matrix set P2 is a submatrix extracted from the base matrix of the parity check matrix set P1.
  • the parity check matrix set P1, the parity check matrix set P2 or the parity check matrix set P2' can be selected as the target parity check matrix set, and a parity check matrix is determined as Hb.
  • the parity check matrix set P2' can also be used as the target parity check matrix set.
  • the set of parity check matrices P2' includes a3 third parity check matrices, a3 being equal to the number a1 of the first parity check matrices in P1.
  • step 100 includes:
  • the second set of parity check matrices is used as the target set of parity check matrices:
  • TBS is greater than or equal to T0, and T0 is an integer greater than or equal to the maximum information length Kmax1 of the data to be transmitted supported by the parity check matrix set P1; 2)
  • the code rate is greater than or equal to R0, and R0 is a real number greater than 0 and less than 1 .
  • the set of target parity check matrices is determined according to TBS and code rate:
  • TBS is less than or equal to 292 bits, or TBS is less than or equal to 3824 bits and the code rate is less than or equal to 0.67, or the code rate is less than or equal to 0.25;
  • TBS is greater than or equal to T0, T0 is a positive value greater than or equal to Kmax1 Integer;
  • Condition 3 The code rate is greater than or equal to R0, which is a real number greater than 0 and less than 1.
  • the parity check matrix set P2' is used as the target parity check matrix set; if at least one of the conditions 2 and 3 is true, the parity check matrix set P2 is used as the target parity check matrix set ; If none of the above conditions hold, adopt the parity check matrix set P1 as the target parity check matrix set.
  • T0 is equal to X times Kmax2, where X is an integer greater than 1; R0 is equal to 1/2, 2/3, 3/4, 5/6, 6/7, 7/8, or 8/9; The value of R0 can be rounded to obtain a value with 2 decimal points or a value with 3 decimal points; R0 is equal to 0.5, 0.67, 0.75, 0.83, 0.86, 0.88 or 0.89.
  • a low-density parity check coding method which uses a target base matrix for coding, which can not only improve the throughput of data transmission and the decoding parallelism of LDPC codes, but also support flexible code length and Bit rate, improve coding flexibility.
  • a target base matrix for coding which can not only improve the throughput of data transmission and the decoding parallelism of LDPC codes, but also support flexible code length and Bit rate, improve coding flexibility.
  • FIG. 2 is a flowchart of a low-density parity check encoding method according to another embodiment. As shown in FIG. 2 , the method provided by this embodiment includes step 210 and step 220 .
  • a target basis matrix is determined, the target basis matrix is the basis matrix of the second parity check matrix set, and the basis matrix of the second parity check matrix set is obtained from the first parity check matrix set extracted from the base matrix.
  • step 220 low-density parity check encoding is performed on the data to be transmitted according to the target base matrix and the target boost value.
  • a target base matrix is selected from the base matrices of the second set of parity check matrices (ie, the set of parity check matrices P2), and the target base matrix and Zc are used to encode the data to be transmitted to obtain a base matrix for transmitting LDPC code.
  • the basis matrices of the parity check matrix set P2 and the parity check matrix set P1 satisfy:
  • the basis matrix of the parity check matrix set P2 is the basis matrix from the first parity check matrix set (ie, the parity check matrix set P1)
  • the parity check matrix set P1 may use a known parity check matrix set in a related standard protocol.
  • the basis matrix of the parity check matrix set P2 can be determined when the basis matrix of the parity check matrix set P1 is known, A target basis matrix for encoding is determined from the basis matrices of the parity check matrix set P2, and the target basis matrix corresponds to the target parity check matrix. Since the basis matrix of the parity check matrix set P2 is extracted from the basis matrix of the parity check matrix set P1, in the case of the same target boost value, the number of systematic columns and the corresponding target parity check matrix can be reduced.
  • step 220 includes:
  • a check matrix H (hereinafter referred to as H) is determined according to the target base matrix and the target boost value; based on the check matrix H, low-density parity check coding is performed on the data to be transmitted.
  • the target basis matrix is first determined, and H is determined according to the target basis matrix and Zc, where H corresponds to Hb, and the low-density parity check coding of the data to be transmitted is implemented based on H.
  • step 220 includes:
  • the target basis matrix is first determined, and Hb is determined according to the target basis matrix and Zc.
  • the dimension of the target basis matrix is mb rows and nb columns, and both mb and nb are integers greater than 0.
  • the target base matrix may be the base matrix of P2, which is a submatrix extracted from the base matrix of the parity check matrix set P1 according to the row index sequence and/or the column index sequence.
  • step 210 includes:
  • Step 220 includes:
  • step 210 includes:
  • the target basis matrix is determined from the basis matrix of P1 or the basis matrix of P2.
  • it also includes:
  • Step 200 Determine one parity check matrix set from at least two parity check matrix sets as the target parity check matrix set according to the setting information; wherein the setting information includes at least one of the following: transmission block size, code rate, High layer signaling, modulation order, modulation and coding scheme index, MCS table index.
  • step 200 includes:
  • the second set of parity check matrices is used as the target set of parity check matrices:
  • the transport block size is greater than or equal to T0, where T0 is an integer greater than or equal to the maximum information length Kmax1 supported by the first parity check matrix set, or T0 is equal to the maximum information length Kmax2 supported by the second parity check matrix set; the code rate is greater than or Equal to R0, which is a real number greater than 0 and less than 1.
  • one of the at least two parity check matrix sets is determined as the target parity check matrix set according to the setting information, the target base matrix corresponds to Hb, and Hb is determined from the target parity check matrix set.
  • the base matrix of the second parity check matrix set is extracted from the base matrix of the parity check matrix set P1 according to at least one of a row index sequence and a column index sequence.
  • the row index sequence satisfies one of the following:
  • the elements in the row index sequence are consecutive ascending integers; the elements in the row index sequence include discontinuous ascending integers; the elements in the row index sequence are non-ascending integers, and the first M elements in the row index sequence are consecutive ascending integers, M is greater than 1; the row index sequence includes at least ⁇ 0, 1, 2, 3 ⁇ .
  • the column index sequence satisfies one of the following:
  • the first kb2 elements of the column index sequence are consecutive ascending integers, and kb2 is greater than 1; the first kb2 elements of the column index sequence include discontinuous ascending integers, and kb2 is greater than 1; the column index sequence includes at least ⁇ 0, 1 ⁇ ; The index sequence includes at least ⁇ 22, 23, 24, 25 ⁇ .
  • kb2 is equal to the systematic column number of the base matrix of the parity check matrix set P2, or equal to the difference between the column number and the row number of the base matrix of the parity check matrix set P2, or less than or equal to the parity check matrix.
  • the first parity check matrix set includes a1 first parity check matrices, and the basis matrices of the a1 first parity check matrices are the same;
  • the second parity check matrix set includes a2 second parity check matrices. Parity check matrix, the base matrices of the a2 second parity check matrices are the same;
  • the maximum boost value Zmax2 of the second parity check matrix set is supported by the i-th first parity check matrix in the first parity check matrix set
  • the maximum boost value of Zi is D times D times, D is a positive integer power of 2, and i is a non-negative integer less than a1.
  • the maximum boost value Zmax2 of the second set of parity check matrices is greater than the maximum boost value Zmax1 of the first set of parity check matrices.
  • the maximum boost value Zmax2 of the second set of parity check matrices is a ⁇ 2 b , where a is an odd number greater than 15, and b is a positive integer.
  • the target boost value belongs to one boost value subset in the G boost value subsets, where G is greater than 1, and there is no intersection between any two boost value subsets in the G boost value subsets.
  • the boost values supported by the first parity check matrix set P1 constitute the first boost value set Zset1
  • the boost values supported by the second parity check matrix set constitute the second boost value set Zset2
  • the first boost value set Zset1 and the second set of boosted values Zset2 satisfy one of the following:
  • the first boost value set Zset1 and the second boost value set Zset2 have no intersection; the first boost value set Zset1 is a subset of the second boost value set Zset2; in the intersection Zset of the first boost value set Zset1 and the second boost value set Zset2
  • the number of elements of is less than the number of elements in the first boost value set Zset1, and is smaller than the number of elements in the second boost value set Zset2.
  • the minimum boost value supported by the second parity check matrix set is greater than the maximum boost value supported by the first parity check matrix set; the boost value supported by the second parity check matrix set includes at least one of the following: 416 , 448, 480, 512, 576, 640, 704, 768, 832, 896, 960, 1024, 1152, 1280, 1408, 1536, 1664, 1792, 1920, 2048.
  • the maximum information length Kmax1 supported by the first set of parity check matrices is smaller than the maximum information length Kmax2 supported by the second set of parity check matrices.
  • the second parity check matrix set includes at least one parity check matrix
  • the parity check matrix includes k0 upper and lower adjacent pairs
  • the k0 upper and lower adjacent pairs include k1 first type upper and lower pairs.
  • Adjacent pairs and k2 second-class up-down adjacent pairs, and k1 is greater than 3*k2, and both k1 and k2 are integers greater than 0; wherein, up-down adjacent pairs refer to any two indication units in the parity check matrix
  • the adjacent elements in the same column are cyclically shifted and located in the same column; the difference between the two elements of the upper and lower adjacent pairs of the first type is equal to 0; the difference between the two elements of the upper and lower adjacent pairs of the first type is equal to 0.
  • the result of taking the remainder of 2 is greater than 0.
  • the second parity check matrix set includes at least one parity check matrix
  • the parity check matrix includes k3 first-type elements indicating the cyclic shift of the identity matrix and k4 elements indicating the cyclic shift of the identity matrix.
  • the second type of element of the bit, and k3 is greater than 3 times of k4, and both k3 and k4 are integers greater than 0;
  • the result of taking the remainder of 2 for elements of the first type is equal to 0; the result of taking the remainder of 2 for elements of the second type is greater than 0.
  • the first set of parity check matrices is denoted as the set of parity check matrices P1
  • the second set of parity check matrices is denoted as the set of parity check matrices P2
  • the LDPC-coded input information bit sequence (ie, data to be transmitted) is represented as c 0 , c 1 , c 2 , c 3 , . . . , c K-1 , and its length is K bits.
  • the encoded bit sequence obtained after LDPC encoding is denoted as d 0 , d 1 , d 2 , . . . , d N-1 , and its length is N bits.
  • Z c is the target boost value of LDPC encoding
  • Z c is an integer greater than 0.
  • LDPC encoding is performed on the input information bit sequence, including the following steps:
  • Step 1 Determine the boost value subset index i LS .
  • Each index i LS defines a subset of boost values, and there is no intersection between any two subsets of boost values.
  • the index of the subset of boosted values that contains Z c is i LS .
  • the boost value subset index is the same as the index of the target parity check matrix (ie, the index of the target parity check matrix in the parity check matrix set).
  • Step 2 Store the 2nd Z c bits to the K-1th bits in the input information bit sequence c 0 , c 1 , c 2 , c 3 ,...,c K-1 into the encoded bit sequence d 0 , d 1 , d 2 ,...,d N-1 .
  • NULL means padding bits
  • Step 3 Determine the base matrix H BG2 of the parity check matrix set P2; determine the check matrix H according to the base matrix of the parity check matrix set P2 and the target boost value Z c ; and perform LDPC encoding to generate a check bit sequence.
  • the 0 in the satisfied relational expression refers to an all-zero vector, and the LDPC encoding operations are all performed on a 2-element Galois Field (GF(2)).
  • the determination process of the check matrix H includes:
  • the basis matrix includes at least two elements "0" and "1".
  • H BG1 is the basis matrix of the parity check matrix set P1
  • H BG2 is the basis matrix of the parity check matrix set P2
  • a new matrix similarly, H' BG (:, ⁇ ) means to take out all the columns with the column index ⁇ in the matrix H' BG and form a new matrix. That is, the base matrix H BG2 of the parity check matrix set P2 is a submatrix (or a decimation matrix) of the base matrix H BG1 of the parity check matrix set P1.
  • the target parity check matrix Hb belongs to the parity check matrix set P2, and correspondingly, the target base matrix H BG belongs to the base matrix H BG2 of the parity check matrix set P2.
  • the check matrix H can be obtained by replacing all elements in the target base matrix H BG with an all-zero square matrix or a matrix after cyclic shift of the identity matrix.
  • the dimensions of the all-zero square matrix or the identity matrix are Z c ⁇ Z c .
  • the process of obtaining the check matrix H includes:
  • I(P i,j ) represents a matrix obtained by performing right cyclic shift Pi ,j on an identity matrix of size Z c ⁇ Z c .
  • the elements of row i, column j, V i,j are determined according to the index i LS and the parity check matrix set P1, and the index i LS is the index of the first parity check matrix in the parity check matrix set P1; for the parity check matrix
  • the target parity check matrix of the parity check matrix set P2 is determined by the parity check matrix set P1, the row index sequence ⁇ and the column index sequence ⁇ , for example, the i-th LS second parity of the parity check matrix set P2 is determined
  • Step 4 Store the check bit sequence in the encoded bit sequence to obtain the encoded bit sequence.
  • N+2Z c -K check bits to be generated Stored in the encoded bit sequence d 0 , d 1 , d 2 ,...,d N-1 , the pseudo code is as follows:
  • Table 1 is a subset of boost values provided in an example.
  • the boost value subset indices i LS corresponding to the eight boost value subsets are 0 to 7, respectively.
  • Boosted value subset index (i LS ) boost value subset 0 ⁇ 2,4,8,16,32,64,128,256,512,1024 ⁇ 1 ⁇ 3,6,12,24,48,96,192,384,768 ⁇ 2 ⁇ 5,10,20,40,80,160,320,640 ⁇ 3 ⁇ 7,14,28,56,112,224,448,896 ⁇ 4 ⁇ 9,18,36,72,144,288,576 ⁇ 5 ⁇ 11,22,44,88,176,352,704 ⁇ 6 ⁇ 13,26,52,104,208,416,832 ⁇ 7 ⁇ 15,30,60,120,240,480,960 ⁇
  • the parity check matrix set P1 includes at least one of the parity check matrices shown in Table 3; or, the parity check matrix set P1 includes at least one of the parity check matrices shown in Table 11.
  • a submatrix for example, a submatrix formed by the first mb row and the first mb+16 column of a parity check matrix described in Table 11, where mb is an integer greater than 3, and mb is equal to 4, 6, 8, 10, or 18.
  • Table 2 shows the positions and element values of elements equal to 1 in the base matrix of the parity check matrix set P1 provided in an example, wherein the positions of elements equal to 1 are represented by row index (i) and column index (j), and the element equals to 1.
  • the position of 1 corresponds to the position indicating the cyclic shift element of the identity matrix, and defines the element value (V i,j ) at this position in the corresponding parity check matrix, that is, the number of bits of the cyclic shift; the basis matrix of P1 In H BG1 , the element value corresponding to the position of other row index or column index (that is, the position not defined in Table 2) is equal to "0", that is, corresponding to the position indicating the square matrix of all zeros.
  • each boost value subset index i LS corresponds to a first parity check matrix, respectively.
  • the parity check matrix set P1 includes at least one first parity check matrix as shown in Table 2.
  • Table 2 Positions and element values of elements equal to 1 in the basis matrix of the parity check matrix set P1
  • the set of parity check matrices P1 includes 8 first parity check matrices as in Table 2, ie the index is i LS equal to 0 to 7.
  • the ith LS -th boosted value subset of the parity check matrix set P1 corresponds to the set formed by all boosted values less than or equal to 384 in the i-th LS -th boosted value subset in Table 1.
  • the index i LS in Table 2 and Table 1 are the same, that is, the subset of boost values corresponding to the 0th first parity check matrix is ⁇ 2, 4, 8, 16, 32, 64, 128, 256 ⁇ , and the first
  • the boost value subset corresponding to the parity check matrix is ⁇ 3,6,12,24,48,96,192,384 ⁇
  • the boost value subset corresponding to the second first parity check matrix is ⁇ 5,10,20,40, 80,160,320 ⁇
  • the boost value subset corresponding to the third first parity check matrix is ⁇ 7,14,28,56,112,224 ⁇
  • the boost value subset corresponding to the fourth first parity check matrix is ⁇ 9,18, 36, 72, 144, 288 ⁇
  • the boost value subset corresponding to the fifth first parity check matrix is ⁇ 11, 22, 44, 88, 176, 352 ⁇
  • the boost value subset corresponding to the sixth first parity check matrix is ⁇ 13, 26, 52, 104, 208 ⁇
  • the parity check matrix set P2 includes a2 second parity check matrices, and the corresponding boost value subset includes at least one boost value subset in Table 1.
  • the boost value subset supported by the ith LS second parity check matrix of the parity check matrix set P2 corresponds to the ith LS boost value subset in Table 1, that is, they respectively correspond to: the 0th second parity check matrix.
  • the boost value subset corresponding to the test matrix is ⁇ 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024 ⁇
  • the boost value subset corresponding to the first second parity check matrix is ⁇ 3, 6, 12, 24, 48, 96, 192, 384, 768 ⁇
  • the boost value subset corresponding to the second second parity check matrix is ⁇ 5, 10, 20, 40, 80, 160, 320, 640 ⁇
  • the boost value subset corresponding to the third second parity check matrix is ⁇ 7,14,28,56,112,224,448,896 ⁇
  • the boost value subset corresponding to the fourth second parity check matrix is ⁇ 9,18,36,72,144,288,576 ⁇
  • the boost value subset corresponding to the fifth second parity check matrix is ⁇ 11, 22, 44, 88, 176, 352, 704 ⁇
  • the boost value subset corresponding to the sixth second parity check matrix is ⁇ 13, 26, 52, 104, 208, 416, 832 ⁇
  • the row index sequence and the column index sequence satisfy the following combinations: the row index sequence is a discontinuous set of ascending integers; the first kb2 elements of the column index sequence are consecutive ascending integers. Since the first kb2 elements of the column index sequence are consecutive integers in ascending order, in the LDPC decoder of the parity check matrix set P2, the variable node update module (corresponding to the update of a column in the parity check matrix) is fully compatible with the parity check matrix. The variable node of the LDPC decoder of the test matrix set P1 is updated; and the row index sequence is a discontinuous ascending integer set, which can ensure that the LDPC code has excellent decoding performance.
  • the first kb2 elements of the column index sequence are a set consisting of all integers from 0 to kb2-1, such as ⁇ 0,1,2,...,(kb2-2),(kb2-1) ⁇ , where kb2 is an integer greater than 1, and kb2 is the number of systematic columns of the basis matrix of the parity check matrix set P2 (the number of systematic columns is equal to the difference between the number of columns of the basis matrix and the number of rows of the basis matrix).
  • the row index sequence ⁇ is the set [0, 1, 2, 3, 4, 5, 6, 7, 8, 10, 11, 12, 13, 19, 20, 24, 25, 26, 27, 29, 30 ,31,32,33,34,35,36,37,38,39,41,42,44,45] a subset.
  • the row index sequence ⁇ [0, 1, 2, 3, 4, 5, 6, 7, 8, 10, 11, 12, 13, 19, 20, 24, 25, 26, 27, 29 , 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 41, 42, 44, 45].
  • the column index sequence ⁇ [0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,22,23,24,25,26, 27,28,29,30,32,33,34,35,41,42,46,47,48,49,51,52,53,54,55,56,57,58,59,60,61, 63, 64, 66, 67].
  • the row index sequence and the column index sequence satisfy the following combinations: the row index sequence is a continuous set of ascending integers; the first kb2 elements of the column index sequence are a discontinuous set of ascending integers. Since the row index sequence is a continuous set of ascending integers, in the LDPC decoder of the parity check matrix set P2, the check node update module (corresponding to the update of a row in the parity check matrix) is fully compatible with the parity check matrix set The check node of the LDPC decoder of P1 is updated; and the first kb2 elements of the column index sequence are a discontinuous set of ascending integers, which can ensure that the LDPC code has excellent decoding performance.
  • the position and element value of the element equal to 1 in the basis matrix of P1 may be different from those defined in Table 2.
  • Table 2 is only an exemplary description.
  • the index sequence ⁇ or ⁇ is different, in the basis matrix of P1
  • the position where the element equals 1 and the element value can also be different.
  • the row index sequence includes mb2 elements, which is a set ⁇ 0,1,2,...,(mb2-2),(mb2-1) composed of 0 to (mb2-1) ⁇ , where mb2 is an integer greater than 1, and mb2 is the base matrix row number of the parity check matrix set P2.
  • the row index sequence ⁇ is [0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33] a subset.
  • the first kb2 elements of the column index sequence ⁇ are discontinuous ascending integers, and the set formed by the first kb2 elements of the column index sequence ⁇ is [0,1,2,3,4,5,6,8,10, 12, 14, 17, 18, 19, 20, 21] a subset.
  • the set formed by the first kb2 elements of the column index sequence ⁇ is [0, 1, 2, 3, 4, 5, 6, 8, 10, 11, 13, 14, 16, 17, 19, 21 ]A subset of.
  • the set of parity check matrices P1 includes at least one of the first parity check matrices corresponding to indices i LS equal to 0 to 7.
  • the column index sequence ⁇ [0, 1, 2, 3, 4, 5, 6, 8, 10, 11, 13, 14, 16, 17, 19, 21, 22, 23, 24, 25 ,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50 , 51, 52, 53, 54, 55].
  • the set of parity check matrices P1 includes 8 first parity check matrices corresponding to indices i LS equal to 0 to 7.
  • the set of the first kb2 elements of the column index sequence ⁇ is [0, 1, 2, 3, 4, 6, 8, 9, 10, 13, 14, 16, 17, 19, 20, 21 ]A subset of.
  • the set of parity check matrices P1 includes at least one of the first parity check matrices corresponding to indices i LS equal to 0 to 7.
  • the column index sequence ⁇ [0, 1, 2, 3, 4, 6, 8, 9, 10, 13, 14, 16, 17, 19, 20, 21, 22, 23, 24, 25 ,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50 , 51, 52, 53, 54, 55].
  • the parity check matrix set P1 includes 8 first parity check matrices corresponding to indices i LS equal to 0 to 7.
  • the set formed by the first kb2 elements of the column index sequence ⁇ is [0, 1, 2, 3, 4, 6, 7, 8, 9, 11, 13, 16, 17, 18, 19, 21 ]A subset of.
  • the set of parity check matrices P1 includes at least one of the first parity check matrices corresponding to indices i LS equal to 0 to 7.
  • the column index sequence ⁇ [0,1,2,3,4,6,7,8,9,11,13,16,17,18,19,21,22,23,24,25 ,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50 , 51, 52, 53, 54, 55].
  • the parity check matrix set P1 includes 8 first parity check matrices corresponding to indices i LS equal to 0 to 7.
  • the row index sequence and the column index sequence satisfy the following combinations: the row index sequence is a set of discontinuous ascending integers; the first kb2 elements of the column index sequence are discontinuous ascending integers. Since the row index sequence is a discontinuous ascending integer set and the first kb2 elements of the column index sequence are discontinuous ascending integers, the LDPC code decoding can be guaranteed to have excellent decoding performance; and since the basis matrix of the parity check matrix set P2 It is still a sub-matrix (that is, the extraction matrix) of the base matrix of the parity check matrix set P1, so the two are still fully compatible on the LDPC decoding hardware, but only need to add some switch circuits.
  • the switch circuit is used to enable or Part of the routing circuit and the corresponding variable node update module or check node update module circuit are disabled.
  • the position and element value of the element equal to 1 in the basis matrix of P1 may be different from those defined in Table 2.
  • Table 2 is only an exemplary description.
  • the index sequence ⁇ or ⁇ is different, in the basis matrix of P1
  • the position where the element equals 1 and the element value can also be different.
  • the row index sequence ⁇ is [0, 1, 2, 3, 4, 5, 7, 8, 10, 11, 12, 13, 16, 17, 19, 20, 23, 24, 25, 26 ,27,28,30,32,33,35,36,38,39,41,42,43,44,45] a subset.
  • the first kb2 elements of the column index sequence ⁇ are discontinuous ascending integers
  • the set formed by the first kb2 elements of the column index sequence ⁇ is [0,1,2,3,4,5,6,7,8, 9,10,11,12,14,18,21] a subset.
  • the set of parity check matrices P1 includes at least one of the first parity check matrices corresponding to indices i LS equal to 0 to 7.
  • the row index sequence ⁇ [0,1,2,3,4,5,7,8,10,11,12,13,16,17,19,20,23,24,25,26,27, 28, 30, 32, 33, 35, 36, 38, 39, 41, 42, 43, 44, 45].
  • Column index sequence ⁇ [0,1,2,3,4,5,6,7,8,9,10,11,12,14,18,21,22,23,24,25,26,27, 29,30,32,33,34,35, 38,39,41,42,45,46,47,48,49,50,52,54,55,57,58,60,61,63,64, 65, 66, 67].
  • the set of parity check matrices P1 includes 8 first parity check matrices corresponding to indices i LS equal to 0 to 7.
  • the row index sequence ⁇ is [0, 1, 2, 3, 4, 5, 7, 8, 10, 11, 12, 13, 14, 16, 19, 20, 24, 25, 26, 27 ,30,31,32,33,34,35,36,38,39,41,42,43,44,45] a subset.
  • the first kb2 elements of the column index sequence ⁇ are discontinuous ascending integers
  • the set formed by the first kb2 elements of the column index sequence ⁇ is [0,1,2,3,4,5,6,7,8, 9,10,11,12,14,15,16] a subset.
  • the set of parity check matrices P1 includes at least one of the first parity check matrices corresponding to indices i LS equal to 0 to 7.
  • the row index sequence ⁇ [0,1,2,3,4,5,7,8,10,11,12,13,14,16,19,20,24,25,26,27,30, 31, 32, 33, 34, 35, 36, 38, 39, 41, 42, 43, 44, 45].
  • Column index sequence ⁇ [0,1,2,3,4,5,6,7,8,9,10,11,12,14,15,16,22,23,24,25,26,27, 29,30,32,33,34,35,36,38,41,42,46,47,48,49,52,53,54,55,56,57,58,60,61,63,64, 65, 66, 67].
  • the set of parity check matrices P1 includes 8 first parity check matrices corresponding to indices i LS equal to 0 to 7.
  • the row index sequence and the column index sequence satisfy the following combinations: the row index sequence is a set of consecutive ascending integers; the first kb2 elements of the column index sequence are consecutive ascending integers. Since the row index sequence is a continuous set of ascending integers, in the LDPC decoder of the parity check matrix set P2, the check node update module (corresponding to the update of a row in the parity check matrix) is fully compatible with the parity check matrix set The check node of the LDPC decoder of P1 is updated; and the first kb2 elements of the column index sequence are consecutive integers in ascending order, so in the LDPC decoder of the parity check matrix set P2, the variable node update module (corresponding to the parity The update of a certain column in the test matrix) is fully compatible with the variable node update of the LDPC decoder of the parity check matrix set P1.
  • the position and element value of the element equal to 1 in the basis matrix of P1 may be different from those defined in Table 2.
  • Table 2 is only an exemplary description.
  • the index sequence ⁇ or ⁇ is different, in the basis matrix of P1
  • the position where the element equals 1 and the element value can also be different.
  • the mb2 elements of the row index sequence are the set ⁇ 0,1,2,...,(mb2-2),(mb2-1) ⁇ , where mb2 is an integer greater than 1.
  • the row index sequence ⁇ is the set [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21 ,22,23,24,25,26,27,28,29,30,31,32,33] a subset.
  • the set formed by the first kb2 elements of the column index sequence ⁇ is ⁇ 0,1,2,...,(kb2-2),(kb2-1) ⁇ , where kb2 is an integer greater than 1.
  • the set of parity check matrices P1 includes at least one of the first parity check matrices corresponding to indices i LS equal to 0 to 7.
  • the row index sequence ⁇ [0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33].
  • the column index sequence ⁇ [0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,22,23,24,25,26, 27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51, 52, 53, 54, 55].
  • the set of parity check matrices P1 includes 8 first parity check matrices corresponding to indices i LS equal to 0 to 7.
  • the row index sequence satisfies: the elements in the row index sequence are non-ascending integers, the first M elements in the row index sequence are ascending integers, and M is an integer greater than 1 and less than mb2. Since the row index sequence is a non-ascending integer, the basis matrix of the parity check matrix set P2 is a sub-matrix of the basis matrix of the parity check matrix set P1, so it can have lower error leveling and waterfall block error rate (Block Error Rate, BLER).
  • the position where the element is equal to 1 and the value of the element in the basis matrix of the parity check matrix set P1 may be different from those defined in Table 2. Table 2 is only an exemplary description. In the case of different index sequences ⁇ or ⁇ , The position of the element equal to 1 in the basis matrix of P1 and the element value can also be different.
  • the row index sequence is the set [0,1,2,3,4,8,9,10,12,15,16,43,18,19,20,30,24,29,7,22 ,31,32,33,34,28,23,38,39,40,42,5,44,45,25] a subset.
  • the set formed by the first kb2 elements of the column index sequence ⁇ is one of [0, 1, 3, 4, 6, 7, 8, 10, 11, 12, 13, 14, 16, 17, 18, 21] Subset.
  • the set of parity check matrices P1 includes at least one of the first parity check matrices corresponding to indices i LS equal to 0 to 7.
  • the row index sequence ⁇ [0,1,2,3,4,8,9,10,12,15,16,43,18,19,20,30,24,29,7,22,31, 32, 33, 34, 28, 23, 38, 39, 40, 42, 5, 44, 45, 25].
  • the column index sequence ⁇ [0,1,3,4,6,7,8,10,11,12,13,14,16,17,18,21,22,23,24,25,26, 30,31,32,34,37,38,65,40,41,42,52,46,51,29,44,53,54,55,56,50,45,60,61,62,64, 27, 66, 67, 47].
  • the parity check matrix set P1 includes at least one of the parity check matrices shown in Table 3; or, the parity check matrix set P1 includes at least one of the parity check matrices shown in Table 11.
  • a submatrix for example, a submatrix formed by the first mb row and the first mb+16 column of a parity check matrix described in Table 11, where mb is an integer greater than 3, and mb is equal to 4, 6, 8, 10, or 18.
  • the basis matrix of the parity check matrix set P2 determined according to the row index sequence ⁇ , the column index sequence ⁇ and the basis matrix of the parity check matrix set P1, and then LDPC encoding is performed.
  • Table 3 provides the positions of elements equal to 1 and the element values in the base matrix of the parity check matrix set P1 provided by another example, wherein the positions of the elements equal to 1 in the base matrix of the parity check matrix set P1 are determined by row index (i) and the column index (j) indicates that the position where the element is equal to 1 corresponds to the position indicating the cyclically shifted element of the identity matrix, and defines the element value (V i,j ) at that position in the corresponding parity check matrix, i.e.
  • the parity check matrix set P1 includes at least one parity check matrix in Table 3.
  • the parity check matrix set P2 is determined by the parity check matrix set P1, the row index sequence ⁇ and the column index sequence ⁇ . LDPC encoding is performed according to the set of parity check matrices P2.
  • FIG. 3 is a schematic diagram of simulation performance of LDPC encoding based on a target parity check matrix according to an embodiment.
  • the abscissa is Signal Noise Ratio (SNR)
  • the unit is dB
  • the ordinate is BLER.
  • the code rate R includes ⁇ 8/ 9,5/6,3/4,2/3,1/2,2/5,1/3 ⁇ , it can be seen that in the case of different code rates, the target is determined from the second parity check matrix set
  • the parity check matrix has good performance for LDPC encoding, and there is no error leveling.
  • Table 3 Positions and element values of elements equal to 1 in the basis matrix of the parity check matrix set P1
  • the row index sequence ⁇ is a subset of or equal to the following set: [0,1,2,3,4,7,8,15,9,12,6,13,19,18,22 ,43,29,31,30,40,32,25,10,42,23,5,36,38,41,28,34,16,20,35];
  • the first kb2 elements of the column index sequence ⁇ constitute
  • the set of is a subset of or equal to the following set: [0,1,3,4,7,8,10,11,12,13,14,16,17,18,19,21].
  • the row index sequence ⁇ is a subset of or equal to the following set: [0,1,2,3,4,7,8,15,6,12,9,25,22,29,10,30 ,11,36,34,32,18,31,19,43,45,17,26,44,35,42,28,38,33,13];
  • the set composed of the first kb2 elements of the column index sequence ⁇ is a subset of or equal to the following set: [0,1,3,4,6,7,10,11,12,13,14,15,16,17,18,21].
  • the row index sequence ⁇ is a subset of or equal to the following set: [0,1,2,3,4,7,8,15,6,12,9,25,22,13,10,30 ,32,38,29,18,35,31,34,44,19,5,45,41,42,43,16,36,33,23];
  • the set of the first kb2 elements of the column index sequence ⁇ is a subset of or equal to the following set: [0,1,3,4,6,7,9,10,11,12,13,14,16,17,18,21].
  • the row index sequence ⁇ is a subset of or equal to the following set: [0,1,2,3,7,19,8,15,9,12,29,18,22,31,38,43 ,30,5,39,13,41,20,24,34,33,28,23,16,44,21,42,32,10,6];
  • the set of the first kb2 elements of the column index sequence ⁇ is a subset of or equal to the following set: [0,1,3,6,7,10,11,12,13,14,16,17,18,19,20,21].
  • the row index sequence ⁇ is a subset of or equal to the following set: [0,1,2,3,4,7,8,15,9,12,19,6,10,22,18,5 ,30,45,34,16,31,29,24,40,20,23,41,35,44,33,38,43,42,32];
  • the set of the first kb2 elements of the column index sequence ⁇ is a subset of or equal to the following set: [0,1,3,4,6,7,8,10,11,12,13,16,17,18,20,21].
  • the row index sequence ⁇ is a subset of or equal to the following set: [0,1,2,3,4,7,8,15,9,12,6,19,22,25,29,32 ,30,13,21,18,43,34,33,14,23,17,10,45,28,42,38,41,20,36];
  • the set of the first kb2 elements of the column index sequence ⁇ is a subset of or equal to the following set: [0,1,3,4,6,7,10,11,12,13,14,16,17,18,20,21].
  • the row index sequence ⁇ is a subset of or equal to the following set: [0,1,2,3,4,7,11,15,5,8,14,24,30,35,16,21 ,13,32,20,17,44,39,31,28,33,10,42,22,25,19,27,38,34,43];
  • the set of the first kb2 elements of the column index sequence ⁇ is a subset of or equal to the following set: [0,1,3,4,7,8,9,10,11,12,13,14,16,18,20,21].
  • the maximum boost value Zmax2 supported by the parity check matrix set P2 includes one of the following: 1408, 1536, 1664, 1792, 1920 or 2048. Since the maximum boost value Zmax2 supported by the parity check matrix set P2 is large, for example, greater than 384, the decoder of the parity check matrix set P2 can use a larger decoding parallelism, so its decoding speed is faster, The corresponding decoding throughput is higher.
  • Table 4 shows the boost values supported by the parity check matrix set P2 provided in an example. As shown in Table 4, the maximum boost value supported by the parity check matrix set P2 is 2048.
  • Boosted value subset index (i LS ) Boost values supported by P2 0 ⁇ 2,4,8,16,32,64,128,256,512,1024,2048 ⁇ 1 ⁇ 3,6,12,24,48,96,192,384,768,1536 ⁇ 2 ⁇ 5,10,20,40,80,160,320,640,1280 ⁇ 3 ⁇ 7,14,28,56,112,224,448,896,1792 ⁇ 4 ⁇ 9,18,36,72,144,288,576,1152 ⁇ 5 ⁇ 11,22,44,88,176,352,704,1408 ⁇ 6 ⁇ 13,26,52,104,208,416,832,1664 ⁇ 7 ⁇ 15,30,60,120,240,480,960,1920 ⁇
  • Table 5 shows the boost values supported by the parity check matrix set P2 provided in another example. As shown in Table 5, the maximum boost value supported by the parity check matrix set P2 is 1920.
  • Boosted value subset index (i LS ) Boost values supported by P2 0 ⁇ 2,4,8,16,32,64,128,256,512,1024 ⁇ 1 ⁇ 3,6,12,24,48,96,192,384,768,1536 ⁇ 2 ⁇ 5,10,20,40,80,160,320,640,1280 ⁇ 3 ⁇ 7,14,28,56,112,224,448,896,1792 ⁇ 4 ⁇ 9,18,36,72,144,288,576,1152 ⁇ 5 ⁇ 11,22,44,88,176,352,704,1408 ⁇ 6 ⁇ 13,26,52,104,208,416,832,1664 ⁇ 7 ⁇ 15,30,60,120,240,480,960,1920 ⁇
  • Table 6 shows the boost values supported by the set of parity check matrices P2 provided in yet another example. As shown in Table 6, the maximum boost value supported by the parity check matrix set P2 is 1664.
  • Boosted value subset index (i LS ) Boost values supported by P2 0 ⁇ 2,4,8,16,32,64,128,256,512,1024 ⁇ 1 ⁇ 3,6,12,24,48,96,192,384,768,1536 ⁇ 2 ⁇ 5,10,20,40,80,160,320,640,1280 ⁇ 3 ⁇ 7,14,28,56,112,224,448,896 ⁇ 4 ⁇ 9,18,36,72,144,288,576,1152 ⁇ 5 ⁇ 11,22,44,88,176,352,704,1408 ⁇ 6 ⁇ 13,26,52,104,208,416,832,1664 ⁇ 7 ⁇ 15,30,60,120,240,480,960 ⁇
  • the number of systematic columns of the basis matrix of the parity check matrix set P2 is kb2, and kb2 is equal to 12, 14, 16, 18 or 20.
  • the length of kb2 is equal to the difference between the length of the column index sequence and the length of the row index sequence. and, the length of the row index sequence is equal to 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 16, 18, 20, 22, 23, 26, 29, 30, 32, 34, 38 or 42.
  • the length of the row index sequence is equal to 42, 32, 22, 12, 9, 6 or 5.
  • the maximum information length supported by the parity check matrix set P2 is Kmax2, where Kmax2 is equal to 20480.
  • the length of the row index sequence is equal to 38, 29, 20, 11, 8, 6 or 5.
  • the maximum information length supported by the parity check matrix set P2 is Kmax2, where Kmax2 is equal to 18432.
  • the length of the row index sequence is equal to 34, 26, 18, 10, 8, 6 or 4.
  • the length of the row index sequence is equal to 30, 23, 16, 9, 7, 5 or 4.
  • the basis matrix of the parity check matrix set P2 only needs to be determined according to the row index sequence ⁇ and the basis matrix of the parity check matrix set P1.
  • the process of determining the basis matrix of the parity check matrix set P2 includes the following two formulas:
  • H' BG H BG1 ( ⁇ ,:)
  • H BG2 H' BG (:,[0 ⁇ (kb2-1),22+ ⁇ ])
  • H BG1 is the basis matrix of the parity check matrix set P1
  • H BG2 is the basis matrix of the parity check matrix set P2
  • H' BG (:,x) means to take out all the columns whose column index is x in the matrix H' BG and form a new matrix.
  • the base matrix H BG2 of the parity check matrix set P2 is a submatrix (or a decimation matrix) of the base matrix H BG1 of the parity check matrix set P1.
  • 0 ⁇ (kb2-1) represents the set formed by all integers from 0 to kb2-1
  • 22+ ⁇ represents the set formed by adding all elements in set ⁇ to 22 respectively
  • [0 ⁇ (kb2-1), 22+ ⁇ ] means that all integers from 0 to kb2-1 form the set and all elements in the set ⁇ are added to 22 to form the union of the set.
  • Row index sequence ⁇ [0,1,2,3,4,5,6,7,8,10,11,12,13,19,20,24,25,26,27,29,30,31, 32, 33, 34, 35, 36, 37, 38, 39, 41, 42, 44, 45]. It can be seen that it is equivalent to the set formed by the column index sequence ⁇ equal to 0 to kb2-1, where kb2 is equal to 12, 14, 15, 16, 17, 18, 19, or 20.
  • the basis matrix of the parity check matrix set P2 only needs to be determined according to the row index sequence ⁇ and the basis matrix of the parity check matrix set P1.
  • the process of determining the basis matrix of the parity check matrix set P2 includes the following two formulas:
  • H BG1 is the basis matrix of the parity check matrix set P1
  • H BG2 is the basis matrix of the parity check matrix set P2
  • H' BG (:,x) means to take out all the columns whose column index is x in the matrix H' BG and form a new matrix
  • the base matrix H BG2 of the parity check matrix set P2 is a submatrix (or a decimation matrix) of the base matrix H BG1 H BG1 of the parity check matrix set P1.
  • [0 to mb2-1] represents the set of all integers greater than or equal to 0 and less than or equal to mb2-1.
  • boost value subsets wherein the boost value subset indices are 0, 1, . No intersection.
  • the boost value subset indices supported by the parity check matrix set P1 constitute a set Set1; the boost value subset indices supported by the parity check matrix set P2 constitute a set Set2.
  • the intersection of Set2 and Set1 is the empty set.
  • the boost value subset supported by the parity check matrix set P2 includes at least one boost value subset with the following characteristics: all boost values of one boost value subset satisfy a 2 b , where a is an odd number greater than 15, b is a set of non-negative integers.
  • Table 7 is a subset of boost values supported by the parity check matrix set P1 provided in an example. As shown in Table 7, G is equal to 12, that is, there are 12 subsets of boost values.
  • boost value subsets wherein the boost value subset indices are 0, 1, . No intersection.
  • the boost value subset indices supported by the parity check matrix set P1 constitute a set Set1;
  • the boost value subset indices supported by the parity check matrix set P2 constitute a set Set2.
  • Set2 is a subset of Set1, and the length of Set2 is less than the length of Set1.
  • Set1 ⁇ 0, 1, 2, 3, 4, 5, 6, 7 ⁇ .
  • Table 8 is a subset of boost values supported by the parity check matrix set P1 provided in another example.
  • the parity check matrix set P1 supports a set composed of all promotion values less than or equal to 384, and the corresponding index is i LS equal to the integer in Set1, that is, equal to 0 to 7.
  • the boost values supported by the parity check matrix set P2 include one of the following:
  • Zset1 and Zset2 are Zset equal to ⁇ 2, 3, 4, 5, 6, 7, 8, 10, 12, 14, 16, 20, 24, 28, 32, 40, 48, 56, 64, 80, 96,112,128,160,192,224,256,320,384 ⁇
  • the number of elements of Zset (29) is less than the number of elements of Zset1 (51)
  • the number of elements of Zset is less than the number of elements of Zset2 (35).
  • the parity check matrix set P2 includes at least one parity check matrix
  • the parity check matrix (which is the second parity check matrix) includes k0 up and down adjacent pairs ⁇ h i,j ,h (i +1) mod mb,j ⁇ , the two elements in the upper and lower adjacent pairs are both elements indicating the cyclic shift of the identity matrix, and mb is the number of rows of the parity check matrix.
  • k0, k1 and k2 are all positive integers, and k1 is greater than 3 times of k2.
  • the parity check matrix set P2 includes at least one of the parity check matrices shown in Table 9; or, the parity check matrix set P2 includes at least one of the parity check matrices shown in Table 9.
  • a submatrix for example, a submatrix consisting of the first mb row and the first mb+16 column of a parity check matrix shown in Table 9, where mb is an integer greater than 3, and mb is equal to 4, 6, 8, 10, or 18.
  • LDPC encoding is performed according to the set of parity check matrices P2.
  • Table 9 shows the positions of elements equal to 1 and the element values in the basis matrix of the parity check matrix set P2 provided in an example, wherein the positions of elements equal to 1 are represented by the row index (i) and the column index (j), and the elements equal to The position of 1 corresponds to the position indicating the cyclic shift element of the identity matrix, and defines the element value (V i,j ) at this position in the corresponding parity check matrix, that is, the number of bits of the cyclic shift; the basis matrix of P2 In H BG1 , the element value corresponding to the position of other row index or column index (ie, the position not defined in Table 9) is equal to "0", that is, it corresponds to the position indicating the square matrix of all zeros.
  • k1 is greater than 5 times k2.
  • the set of parity check matrices P2 includes at least one of the second parity check matrices corresponding to indices i LS equal to 0 to 7 as shown in Table 9.
  • Table 9 Positions and element values of elements equal to 1 in the basis matrix of the parity check matrix set P2
  • the parity check matrix set P2 includes at least one parity check matrix, and the parity check matrix (being the second parity check matrix) satisfies: the parity check matrix includes k3 indicating unit matrix cyclic shifts The elements of the first type of and k4 elements of the second type indicating the cyclic shift of the identity matrix, wherein the elements of the first type indicating the cyclic shift of the identity matrix satisfy the following relationship: mod(h i,j ,2) ⁇ 0, indicating the unit The elements of the second type of matrix cyclic shift satisfy the following relation: mod(h i,j ,2)>0, where h i,j is an indicator identity matrix whose abscissa is i and the column coordinate is j in the parity check matrix Circularly shifted elements.
  • k3 and k4 are positive integers, and k3 is greater than 3 times of k4.
  • the position where the element is equal to 1 and the element value in the basis matrix of P2 may be different from those defined in Table 9.
  • Table 9 is only an exemplary description.
  • the index sequence ⁇ or ⁇ is different, in the basis matrix of P2
  • the position where the element equals 1 and the element value can also be different.
  • the target parity check matrix is determined according to the target base matrix H BG .
  • the LDPC-coded input information bit sequence (ie, data to be transmitted) is represented as c 0 , c 1 , c 2 , c 3 , . . . , c K-1 , and its length is K bits.
  • the encoded bit sequence obtained after LDPC encoding is denoted as d 0 , d 1 , d 2 , . . . , d N-1 , and its length is N bits.
  • LDPC encoding is performed on the input information bit sequence, including the following steps:
  • Step 1 Determine the boost value subset index i LS .
  • Each index i LS defines a subset of boost values.
  • the boost value subset index that contains the target boost value Z c is i LS .
  • Step 2 Store the 2nd Z c bits to the K-1th bits in the input information bit sequence c 0 , c 1 , c 2 , c 3 ,...,c K-1 into the encoded bit sequence d 0 , d 1 , d 2 ,...,d N-1 .
  • the 0 in the satisfied relational expression refers to an all-zero vector, and the LDPC encoding operations are all performed on a 2-element Galois Field (GF(2)).
  • the target parity check matrix Hb belongs to the parity check matrix set P2, and correspondingly, the target base matrix H BG belongs to the base matrix of the parity check matrix set P2.
  • the determination process of the check matrix H includes:
  • V i,j mod(V i,j ,Z c ), where V i,j is the i-th row and j-th column element in the i-th LS parity-check matrix in the parity-check matrix set P1, index i LS is the parity check matrix index in the parity check matrix set P1.
  • Step 4 the generated N+2Z c -K check bits Stored in the encoded bit sequence d 0 , d 1 , d 2 ,...,d N-1 .
  • the parity check matrix set P1 includes 8 first parity check matrices, and the index i LS of the first parity check matrix is equal to 0 to 7.
  • the parity check matrix set P2 includes at least one second parity check matrix as follows: the index corresponding to the second parity check matrix is i LS , Satisfy Wherein V i,j is the i-th row and jth column element of the i-th LS parity-check matrix in the parity-check matrix set P1 in the standard version Release 15, and V' i,j is the parity-check matrix in the standard version Release X
  • the elements of the i-th row and the j-th column of the i-th LS parity check matrix in the set P2, both V' i,j and V i,j are elements indicating the cyclic shift of the identity matrix, and there is at least one group of V' i, j and V i,j satisfy V' i,j ⁇ V i,j , and the second parity check matrix index i LS is equal to 1 integer from 0 to 7. in, is the
  • the dimension of the base matrix of the parity check matrix set P1 in the standard version Release 15 is 46 rows and 68 columns, and the 8 first parity check matrix indices i LS in the parity check matrix set P1 are equal to 0 to 7 (for example, the example 8 first parity check matrices shown in Table 10 in 20).
  • the parity check matrix set P2 in the standard version Release X includes 8 second parity check matrices, and the second parity check matrix index i LS is equal to 0 to 7.
  • the positions of elements equal to 1 in the basis matrix of P1 and the element values are shown in Table 2, and may also be different from those defined in Table 2; when the index sequence ⁇ or ⁇ is different, the elements in the basis matrix of P1 The position equal to 1 and the element value can also be different.
  • the dimension of the base matrix of the parity check matrix set P1 in the standard version Release 15 is 42 rows and 52 columns, the eight first parity check matrices in the parity check matrix set P1, the first parity check matrix
  • the test matrix index i LS is equal to 0 to 7.
  • the parity check matrix set P2 in the standard version Release X includes 8 second parity check matrices, and the second parity check matrix index i LS is equal to 0 to 7.
  • the standard version is Release X
  • the base matrix of the parity check matrix set P2 is a sub-matrix of the base matrix of the parity check matrix set P1 in the standard version of Release 15 (decimated matrix).
  • the dimension of the base matrix of the parity check matrix set P1 in the standard version Release 15 is 46 rows and 68 columns, and the parity check matrix set P1 includes 8 first parity check matrices (for example, as shown in Table 10 in Example 20) 8 first parity check matrices), the first parity check matrix index i LS is equal to 0 to 7.
  • the parity check matrix set P2 includes 8 second parity check matrices PCM, and the second parity check matrix index i LS is equal to 0 to 7.
  • a is equal to one row index sequence ⁇ in instance 1 to instance 6
  • b is equal to one row index sequence ⁇ in instance 1 to instance 6.
  • a is equal to ⁇ 0,1,2,3,4,5,6,7,8,10,11,12,13,19,20,24,25,26,27,29,30 ,31,32,33,34,35,36,37,38,39,41,42,44,45 ⁇
  • b is equal to ⁇ 0,1,2,3,4,5,6,7,8,9 ,10,11,12,13,14,15,22,23,24,25,26,27,28,29,30,32,33,34,35,41,42,46,47,48,49 ,51,52,53,54,55,56,57,58,59,60,61,63,64,66,67 ⁇ . That is, the dimension of the basis matrix of the parity check matrix set P2 in the standard version Release X is 34 rows and 50 columns.
  • the target parity check matrix Hb is first determined, and low-density parity check encoding is performed on the data to be transmitted according to Hb and the target boost value.
  • the LDPC-coded input information bit sequence (ie, data to be transmitted) is represented as c 0 , c 1 , c 2 , c 3 , . . . , c K-1 , and its length is K bits.
  • the encoded bit sequence obtained after LDPC encoding is denoted as d 0 , d 1 , d 2 , . . . , d N-1 , and its length is N bits.
  • Step 1 Determine the boost value subset index i LS .
  • Each index i LS defines a subset of boost values.
  • the boost value subset index that contains the boost value Z c is i LS .
  • Step 2 Store the 2nd Z c bits to the K-1th bits in the input information bit sequence c 0 , c 1 , c 2 , c 3 ,...,c K-1 into the encoded bit sequence d 0 , d 1 , d 2 ,...,d N-1 .
  • the 0 in the satisfied relational expression refers to an all-zero vector, and the LDPC encoding operations are all performed on a 2-element Galois Field (GF(2)).
  • the determination process of the check matrix H includes:
  • Step 4 the generated N+2Z c -K check bits Stored in the encoded bit sequence d 0 , d 1 , d 2 ,...,d N-1 .
  • parity check matrix set P2 there are one parity check matrix set P2 and one parity check matrix set P1.
  • the parity check matrix for LDPC encoding comes from the parity check matrix set P2 or the parity check matrix set P1.
  • the basis matrix of the parity check matrix set P1 has the number of rows mb1 and the number of columns nb1, where mb1 and nb1 are 46 and 68, respectively.
  • the base matrix of the parity check matrix set P2 has a row number of mb2 and a column number of nb2, wherein both mb2 and nb2 are integers greater than 0.
  • nb2 There is 1 row index sequence and 1 column index sequence.
  • the length of the row index sequence is mb2; the length of the column index sequence is equal to nb2.
  • mb2 is a positive integer less than mb1
  • nb2 is a positive integer less than nb1.
  • the parity check matrix of the parity check matrix set P2 is determined according to the row index sequence ⁇ , the column index sequence ⁇ and the parity check matrix set P1, that is, the parity check matrix of the LDPC encoding is determined. Among them, the parity check matrix of the parity check matrix set P2 is selected from the parity check matrix of the parity check matrix set P1 according to the elements in the row index sequence in order by selecting the corresponding rows and according to the elements in the column index sequence.
  • the submatrix formed after selecting the corresponding column including:
  • Hb2 Hb'(:, ⁇ )
  • Hb2 Hb'( ⁇ ,:)
  • Hb2 Hb1( ⁇ , ⁇ )
  • Hb1 is the i LS th parity check matrix of the parity check matrix set P1
  • Hb2 is the i LS th parity check matrix of the parity check matrix set P2.
  • V i,j is the i-th row and j-th column element in the i-th LS parity-check matrix .
  • the row index sequence ⁇ is a row index sequence as in Example 1-Example 6, and the column index sequence ⁇ is a column index sequence as in Example 1-Example 6; the position of the element in the base matrix of P1 equal to 1 and the element
  • the values are, for example, shown in Table 2, and may also be different from those defined in Table 2; if the index sequence ⁇ or ⁇ is different, the position where the element is equal to 1 and the element value in the basis matrix of P1 may also be different.
  • the basis matrix of the parity check matrix set P2 is first determined, and then the target parity check matrix of the parity check matrix set P2 is determined accordingly. as follows:
  • Step 1 Determine the boost value subset index i LS .
  • Step 2 Store the 2nd Z c bits to the K-1th bits in the input information bit sequence c 0 , c 1 , c 2 , c 3 ,...,c K-1 into the encoded bit sequence d 0 , d 1 , d 2 ,...,d N-1 .
  • Step 3 Determine the basis matrix of the parity check matrix set P2; determine the parity check matrix according to the basis matrix of the parity check matrix set P2; perform LDPC encoding according to the parity check matrix and the boost value to obtain an encoded bit sequence.
  • Generate N+2Z c -K check bits and satisfy where c [c 0 , c 1 , c 2 , . . . , c K-1 ] T .
  • the 0 in the satisfied relational expression refers to an all-zero vector, and the LDPC encoding operations are all performed on a 2-element Galois Field (GF(2)).
  • GF(2) 2-element Galois Field
  • the basis matrix includes at least two elements "0" and "1".
  • the basis matrix of the parity check matrix set P2 is determined by the basis matrix, the row index sequence ⁇ and the column index sequence ⁇ of the parity check matrix set P1, as follows:
  • H' BG H BG1 ( ⁇ ,:)
  • H BG2 H' BG (:, ⁇ )
  • H" BG H BG1 (:, ⁇ )
  • H BG2 H" BG ( ⁇ ,:)
  • H BG2 H BG1 ( ⁇ , ⁇ )
  • H BG1 is the basis matrix of the parity check matrix set P1
  • H BG2 is the basis matrix of the parity check matrix set P2
  • a new matrix similarly, H' BG (:, ⁇ ) means to take out all the columns with the column index ⁇ in the matrix H' BG and form a new matrix. That is, the basis matrix of the parity check matrix set P2 is that in the basis matrix of the parity check matrix set P1, the corresponding rows are selected in sequence according to the elements in the row index sequence and the corresponding columns are selected in sequence according to the elements in the column index sequence. composed of sub-matrices.
  • the parity check matrix Hb of the parity check matrix set P2 is determined according to the basis matrix of the parity check matrix set P2.
  • Vi ,j is determined by the parity check matrix index i LS .
  • Vi ,j is determined, for example, by Table 10 in Example 20 and the parity check matrix index i LS .
  • Obtaining the matrix H includes the following three processes:
  • one parity check matrix is determined from the parity check matrix set P1 or the parity check matrix set P2, and then the process of LDPC encoding is performed. as follows:
  • Step 1 Determine the boost value subset index i LS .
  • Step 2 Store the 2nd Z c bits to the K-1th bits in the input information bit sequence c 0 , c 1 , c 2 , c 3 ,...,c K-1 into the encoded bit sequence d 0 , d 1 , d 2 ,...,d N-1 .
  • Step 3 Determine and determine one parity check matrix from the parity check matrix set P1 or the parity check matrix set P2; perform LDPC encoding according to the parity check matrix and the boost value to obtain an encoded bit sequence.
  • Generate N+2Z c -K check bits and satisfy where c [c 0 , c 1 , c 2 , . . . , c K-1 ] T .
  • the 0 in the satisfied relational expression refers to an all-zero vector, and the LDPC encoding operations are all performed on a 2-element Galois Field (GF(2)).
  • GF(2) 2-element Galois Field
  • the basis matrix H BG includes at least two elements "0" and "1".
  • Matrix H can be obtained by replacing all elements in the base matrix H BG with an all-zero square matrix or a matrix after cyclic shift of the identity matrix.
  • the dimensions of the all-zero square matrix or the identity matrix are Z c ⁇ Z c .
  • Obtaining the check matrix H includes:
  • the basis matrix of the parity check matrix set P2 is a sub-matrix (or extraction matrix) of the basis matrix of the parity check matrix set P1, that is, the basis matrix of the parity check matrix set P2 is equal to the basis matrix of the parity check matrix set P1.
  • a submatrix (or a decimation matrix) obtained by decimation of the row index sequence a and the column index sequence b.
  • the length of a is less than the number of rows of the base matrix of the parity check matrix set P1
  • the length of b is less than the number of columns of the base matrix of the parity check matrix set P1.
  • the dimension of the base matrix of the parity check matrix set P1 is 46 rows and 68 columns, and the eight first parity check matrices in the parity check matrix set P1 are shown in Table 10 of Example 20, and the first parity check matrix index i LS equals 0 to 7.
  • the parity check matrix set P2 includes 8 second parity check matrices, and the second parity check matrix index i LS is equal to 0 to 7.
  • a and b are equal to one row index sequence ⁇ and one row index sequence ⁇ in Examples 1 to 6.
  • a is equal to ⁇ 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20, 21,22,23,24,25,26,27,28,29,30,31,32,33 ⁇
  • b is equal to ⁇ 0,1,2,3,4,5,6,7,8,9, 10,11,12,13,14,15,22,23,24,25,26,27,28,29,30,32,33,34,35,41,42,46,47,48,49, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 63, 64, 66, 67 ⁇
  • the dimension of the basis matrix of the parity check matrix set P1 is 34 rows and 50 columns.
  • the parity check matrix set P1 includes 8 parity check matrices corresponding to indices i LS equal to 0 to 7.
  • Table 10 shows the positions and element values of elements equal to 1 in the basis matrix of the parity check matrix set P1 provided in another example, wherein the positions of elements equal to 1 are represented by row index (i) and column index (j), and the element A position equal to 1 corresponds to a position indicating a cyclically shifted element of the identity matrix, and defines the element value (V i,j ) at that position in the corresponding parity check matrix, that is, the number of bits of cyclic shift; the basis of P1 In the matrix H BG1 , the positions of other row indices or column indices (that is, positions not defined in Table 10) correspond to element values equal to "0", that is, corresponding to the positions indicating the all-zero square matrix.
  • each boost value subset index i LS corresponds to a first parity check matrix, respectively.
  • the parity check matrix set P2 includes at least one of the parity check matrices shown in Table 11; or, the parity check matrix set P2 includes at least one of the parity check matrices shown in Table 11.
  • a submatrix for example, a submatrix formed by the first mb row and the first mb+16 column of the one parity check matrix, where mb is an integer greater than 3, where mb is equal to 4, 6, 8, 10, or 18.
  • LDPC encoding is performed according to the set of parity check matrices P2.
  • Table 11 provides another example of the position of the element equal to 1 and the element value in the basis matrix of the parity check matrix set P2, wherein the position of the element equal to 1 is represented by the row index (i) and the column index (j), and the element is equal to The position of 1 corresponds to the position indicating the cyclic shift element of the identity matrix, and defines the element value (V i,j ) at that position in the corresponding parity check matrix, that is, the number of bits of the cyclic shift; no The value of the element corresponding to the position of the defined row index or column index is equal to "0", that is, it corresponds to the position indicating the square matrix of all zeros.
  • each i LS corresponds to a parity check matrix, and i LS is equal to 0, 1, 2, . . . , 7.
  • the basis matrix shown in Table 11 is a sub-matrix (or a basis matrix in the 5th Generation Mobile Communication Technology (5G) standard version 15 or 16) shown in Table 10 in Example 20.
  • Extraction matrix where the corresponding row index sequence is: ⁇ 0,1,2,3,4,8,9,10,12,15,16,43,18,19,20,30,24,29,7 ,22,31,32,33,34,28,23,38,39,40,42,5,44,45,25 ⁇
  • the column index sequence is: ⁇ 0,1,3,4,6,7, 8,10,11,12,13,14,16,17,18,21,22,23,24,25,26,30,31,32,34,37,38,65,40,41,42, 52,46,51,29,44,53,54,55,56,50,45,60,61,62,64,27,66,67,47 ⁇ .
  • the maximum boost value is 1024.
  • the simulation performance of the target parity check matrix for LDPC encoding from Table 11 is shown in Figure 3, the corresponding information length is 16384, and the code rate includes ⁇ 8/9, 5/6, 3/4, 2/3, 1/2, 2/5, 1/3 ⁇ , it can be seen that in the case of different code rates, determining the target parity check matrix from the second parity check matrix set for LDPC encoding has good performance, and there is no Error leveling layer; and the maximum boost value it supports can reach 1024, and the parallelism of LDPC decoding is high, so the decoding throughput is large.
  • Table 11 Positions and element values of elements equal to 1 in the basis matrix of the parity check matrix set P2
  • the parity check matrix set P2' can also be used as the target parity check matrix set, wherein the parity check matrix set P2' includes 8 parity check matrix sets.
  • the maximum information length supported by the parity check matrix set P2' is 3840, and the dimension of the base matrix is 42 rows and 52 columns.
  • At least one of the following setting information is used to determine from three types of parity check matrix sets ⁇ parity check matrix set P1, parity check matrix set P2 and parity check matrix set P2' ⁇ Target parity check matrix set for LDPC encoding (or determining the index of the target parity check matrix set): transport block size (TBS), code rate, higher layer signaling, modulation order, modulation and coding scheme index, MCS table.
  • TBS transport block size
  • code rate higher layer signaling
  • modulation order modulation order
  • modulation and coding scheme index MCS table.
  • the process of determining the target parity check matrix set according to the transport block size and the code rate is as follows:
  • TBS is less than or equal to 292, or TBS is less than or equal to 3824 and the code rate is less than or equal to 0.67, or the code rate is less than or equal to 0.25.
  • TBS is greater than or equal to T0, which is a positive integer greater than Kmax1.
  • Condition 3 The code rate is greater than or equal to R0, which is a real number greater than 0 and less than 1.
  • the parity check matrix set P2' is used as the target parity check matrix set for LDPC encoding
  • condition 2 is established
  • the parity check matrix set P2 is used as the target parity check matrix set for LDPC encoding
  • the parity check matrix set P1 is used as the target parity check matrix set to perform LDPC encoding.
  • the parity check matrix set P2' is used as the target parity check matrix set to perform LDPC encoding
  • condition 3 the parity check matrix set P2 is used as the target parity check matrix set to perform LDPC encoding.
  • the parity check matrix set P1 is used as the target parity check matrix set to perform LDPC encoding.
  • the parity check matrix set P2' is used as the target parity check matrix set to perform LDPC encoding; if condition 2 is established and condition 3 is also established, the parity check matrix set P2 is used as the target parity check matrix set.
  • the test matrix set is used for LDPC encoding; in other cases, the parity check matrix set P1 is used as the target parity check matrix set to perform LDPC encoding.
  • T0 is equal to X times Kmax2, where X is an integer greater than or equal to 1; R0 is equal to 1/2, 2/3, 3/4, 5/6, 6/7, 7/8, or 8/ 9. The value of R0 can be rounded to obtain a value with 2 decimal points or a value with 3 decimal points. X is equal to 1, 2, 3, 4, 5, 6, 7, 8 or 10.
  • Kmax1 is the maximum information length of the parity check matrix set P1
  • Kmax2 is the maximum information length of the parity check matrix set P2.
  • an example of determining the parity check matrix set (or determining the index of the target parity check matrix set) according to high layer signaling, transport block size, and code rate is as follows: if high layer signaling is enabled, the parity check matrix is used.
  • the check matrix set P2 is used as the target parity check matrix set for LDPC encoding; otherwise, if the above condition 1 is established, the parity check matrix set P2' is used as the target parity check matrix set for LDPC coding, otherwise the parity check matrix set is used.
  • P1 is used as the target parity check matrix set for LDPC encoding.
  • an example of determining the parity check matrix set (or determining the index of the target parity check matrix set) according to the modulation order, transport block size, and code rate is as follows: if the modulation order is greater than or equal to the parameter Y, then The parity check matrix set P2 is used as the target parity check matrix set for LDPC coding; otherwise, if the above condition 1 is established, the parity check matrix set P2' is used as the target parity check matrix set for LDPC coding, otherwise the parity check matrix set is used for LDPC coding.
  • the test matrix set P1 is used as the target parity check matrix set to perform LDPC encoding. where parameter Y is equal to one of the following: 4, 6, 8, 10, 12, 14.
  • an example of determining the parity check matrix set (or determining the index of the target parity check matrix set) according to the modulation and coding scheme index, transport block size, and code rate is as follows: if the modulation and coding scheme index is greater than or equal to the parameter 1 , the parity check matrix set P2 is used as the target parity check matrix set to perform LDPC encoding; otherwise, if the above condition 1 is established, the parity check matrix set P2' is used as the target parity check matrix set for LDPC coding, otherwise, the The parity check matrix set P1 is used as the target parity check matrix set to perform LDPC encoding.
  • parameter I is equal to 15, 18, 20, 21, 22, 23, 24, 25, 26, 27, 28 or 29; or parameter I is equal to one of the MCS indices under the maximum modulation order in the used MCS table.
  • an example of determining the parity check matrix set (or determining the index of the target parity check matrix set) according to the MCS table is as follows: if the MCS table is a preset high-speed data rate MCS table, the parity check matrix set P2 is used. Perform LDPC encoding as the target parity check matrix set; otherwise, if the above condition 1 is established, then adopt the parity check matrix set P2' as the target parity check matrix set to carry out LDPC encoding; otherwise, adopt the parity check matrix set P1 as the target parity set The check matrix set is used as the target parity check matrix set for LDPC encoding.
  • an example of determining the parity check matrix set (or determining the index of the target parity check matrix set) according to the MCS table and the modulation and coding scheme index is as follows: if the MCS table is a preset high-speed data rate MCS table, and the modulation coding The scheme index is greater than or equal to the parameter I, then the parity check matrix set P2 is used as the target parity check matrix set for LDPC encoding; otherwise, if the above condition 1 is established, the parity check matrix set P2' is used as the target parity check matrix set.
  • LDPC encoding is performed, otherwise, the parity check matrix set P1 is used as the target parity check matrix set to perform LDPC encoding.
  • parameter I is equal to 10, 15, 18, 20, 21, 22, 23, 24, 25, 26, 27, 28, or 29; or parameter I is equal to 1 of the modulations under the maximum modulation order in the MCS table used Encoding scheme index.
  • an example of determining the parity check matrix set (or determining the index of the target parity check matrix set) according to the MCS table and the modulation order is as follows: if the MCS table is a preset high-speed data rate MCS table, and the modulation order is greater than or equal to the parameter Y, the parity check matrix set P2 is used as the target parity check matrix set for LDPC encoding; otherwise, if the above condition 1 is established, the parity check matrix set P2' is used as the target parity check matrix set for LDPC encoding. encoding, otherwise the parity check matrix set P1 is used as the target parity check matrix set to perform LDPC encoding.
  • parameter Y is equal to one of the following: 6, 8, 10, 12, 14.
  • an example of determining a set of parity check matrices (or determining an index of a target set of parity check matrices) according to TBS is as follows. It is determined according to at least one of the following conditions: Condition 1: TBS is less than or equal to T1; Condition 2: TBS is greater than T1 and less than or equal to T2; Condition 3: TBS is greater than T2. Among them, T1 is an integer greater than 0, and T2 is an integer greater than T1.
  • condition 1 the parity check matrix set P2' is used as the target parity check matrix set for LDPC encoding
  • condition 2 is established
  • the parity check matrix set P1 is used as the target parity check matrix set for LDPC encoding.
  • condition 3 the parity check matrix set P2 is used as the target parity check matrix set to perform LDPC encoding.
  • the MCS table includes at least the following fields: modulation and coding scheme index, modulation order, and target code rate.
  • modulation coding scheme index is an integer greater than or equal to 0 and less than 2 n , where n is equal to 4, 5 or 6.
  • modulation order is an integer greater than 0.
  • target code rate is a real number greater than 0 and less than 1, and the target code rate can be expressed in the format of x/1024.
  • a low-density parity check decoding method which uses a target parity check matrix for decoding, which can not only improve the throughput of data transmission and the decoding parallelism of LDPC codes, but also supports flexible
  • the code length and code rate can improve the decoding flexibility.
  • FIG. 4 is a flowchart of a low density parity check decoding method according to an embodiment. As shown in FIG. 4 , the method provided by this embodiment includes step 310 and step 320 .
  • a target parity check matrix is determined, the target parity check matrix belongs to the second parity check matrix set, and the basis matrix of the second parity check matrix set is from the first parity check matrix set extracted from the base matrix.
  • step 320 low-density parity check decoding is performed on the received data according to the target parity check matrix and the target boost value.
  • determining the target parity check matrix includes:
  • a target parity check matrix of the second set of parity check matrices is determined according to the first set of parity check matrices.
  • determining the target parity check matrix includes:
  • the base matrix of the second parity check matrix set is extracted from the base matrix of the first parity check matrix set according to at least one of a row index sequence and a column index sequence.
  • the row index sequence satisfies one of the following:
  • the elements in the row index sequence are consecutive ascending integers; the elements in the row index sequence include discontinuous ascending integers; the elements in the row index sequence are non-ascending integers, and the first
  • the M elements are consecutive integers in ascending order, and M is greater than 1; the row index sequence includes at least ⁇ 0, 1, 2, 3 ⁇ .
  • the column index sequence satisfies one of the following:
  • the first kb2 elements of the column index sequence are consecutive integers in ascending order, and kb2 is greater than 1; the first kb2 elements of the column index sequence include discontinuous ascending integers, and kb2 is greater than 1; the column index sequence includes at least ⁇ 0, 1 ⁇ ; the column index sequence includes at least ⁇ 22, 23, 24, 25 ⁇ .
  • kb2 is equal to the number of systematic columns of the base matrix of the second set of parity check matrices, or is equal to the difference between the number of columns and the number of rows of the base matrix of the second set of parity check matrices, or is less than or equal to the number of systematic columns of parity check matrices in the first set of parity check matrices.
  • the first set of parity check matrices includes a1 first parity check matrices, and the base matrices of the a1 first parity check matrices are the same;
  • the second set of parity check matrices including a2 second parity check matrices, the base matrices of the a2 second parity check matrices are the same;
  • the maximum boost value Zmax2 of the second parity check matrix set is the first parity check matrix set D times the maximum boost value Zi supported by the i-th first parity check matrix, D is a positive integer power of 2, and i is a non-negative integer less than a1.
  • the maximum boost value Zmax2 of the second set of parity check matrices is greater than the maximum boost value Zmax1 of the first set of parity check matrices.
  • the maximum boost value Zmax2 of the second set of parity check matrices is a ⁇ 2 b , where a is an odd number greater than 15, and b is a positive integer.
  • the target boost value belongs to one boost value subset in the G boost value subsets, wherein G is greater than 1, and there is no intersection between any two boost value subsets in the G boost value subsets. .
  • the boost values supported by the first parity check matrix set constitute a first boost value set Zset1
  • the boost values supported by the second parity check matrix set constitute a second boost value set Zset2
  • the The first boost value set Zset1 and the second boost value set Zset2 satisfy one of the following:
  • the first boost value set Zset1 and the second boost value set Zset2 have no intersection; the first boost value set Zset1 is a subset of the second boost value set Zset2; the first boost value set Zset1 and The number of elements in the intersection Zset of the second boost value set Zset2 is smaller than the number of elements in the first boost value set Zset1 and smaller than the number of elements in the second boost value set Zset2.
  • the minimum boost value supported by the second set of parity check matrices is greater than the maximum boost value supported by the first set of parity check matrices
  • the boost value supported by the second parity check matrix set includes at least one of the following: 416, 448, 480, 512, 576, 640, 704, 768, 832, 896, 960, 1024, 1152, 1280, 1408, 1536 , 1664, 1792, 1920, 2048.
  • the maximum information length Kmax1 supported by the first set of parity check matrices is smaller than the maximum information length Kmax2 supported by the second set of parity check matrices.
  • the second parity check matrix set includes at least one parity check matrix
  • the parity check matrix includes k0 upper and lower adjacent pairs
  • the k0 upper and lower adjacent pairs include k1 first type upper and lower pairs.
  • the second parity check matrix set includes at least one parity check matrix
  • the parity check matrix includes k3 first-type elements indicating the cyclic shift of the identity matrix and k4 elements indicating the cyclic shift of the identity matrix.
  • the second type element of the bit, and k3 is greater than 3*k4, and both k3 and k4 are integers greater than 0; wherein, the result of taking the remainder of the first type element to 2 is equal to 0; the second type element is equal to 2 The remainder of the result is greater than 0.
  • it also includes:
  • Step 300 Determine one parity check matrix set from at least two parity check matrix sets as the target parity check matrix set according to the setting information; wherein, the setting information includes at least one of the following: transmission block size, code Rate, high layer signaling, modulation order, modulation and coding scheme index, modulation and coding strategy MCS table index.
  • determining one parity check matrix set from at least two parity check matrix sets as the target parity check matrix set according to the setting information including:
  • the second set of parity check matrices is used as the set of target parity check matrices:
  • the transport block size is greater than or equal to T0, which is an integer greater than or equal to the maximum information length Kmax1 supported by the first parity check matrix set; the code rate is greater than or equal to R0, and R0 is a real number greater than 0 and less than 1.
  • a low-density parity check decoding method which uses a target base matrix for encoding, which can not only improve the throughput of data transmission and the decoding parallelism of LDPC codes, but also support flexible code length. and bit rate to improve coding flexibility.
  • a target base matrix for encoding which can not only improve the throughput of data transmission and the decoding parallelism of LDPC codes, but also support flexible code length. and bit rate to improve coding flexibility.
  • FIG. 5 is a flowchart of a low density parity check decoding method provided by another embodiment. As shown in FIG. 5 , the method provided by this embodiment includes step 410 and step 420 .
  • a target basis matrix is determined, the target basis matrix is the basis matrix of the second parity check matrix set, and the basis matrix of the second parity check matrix set is obtained from the first parity check matrix set extracted from the base matrix.
  • step 420 low-density parity check decoding is performed on the received data according to the target base matrix and the target boost value.
  • determining the target parity check matrix includes:
  • a target parity check matrix of the second set of parity check matrices is determined according to the first set of parity check matrices.
  • determining the target parity check matrix includes:
  • the base matrix of the second parity check matrix set is extracted from the base matrix of the first parity check matrix set according to at least one of a row index sequence and a column index sequence.
  • the row index sequence satisfies one of the following:
  • the elements in the row index sequence are consecutive ascending integers; the elements in the row index sequence include discontinuous ascending integers; the elements in the row index sequence are non-ascending integers, and the first
  • the M elements are consecutive integers in ascending order, and M is greater than 1; the row index sequence includes at least ⁇ 0, 1, 2, 3 ⁇ .
  • the column index sequence satisfies one of the following:
  • the first kb2 elements of the column index sequence are consecutive integers in ascending order, and kb2 is greater than 1; the first kb2 elements of the column index sequence include discontinuous ascending integers, and kb2 is greater than 1; the column index sequence includes at least ⁇ 0, 1 ⁇ ; the column index sequence includes at least ⁇ 22, 23, 24, 25 ⁇ .
  • kb2 is equal to the number of systematic columns of the base matrix of the second set of parity check matrices, or is equal to the difference between the number of columns and the number of rows of the base matrix of the second set of parity check matrices, or is less than or equal to the number of systematic columns of parity check matrices in the first set of parity check matrices.
  • the first set of parity check matrices includes a1 first parity check matrices, and the base matrices of the a1 first parity check matrices are the same;
  • the second set of parity check matrices including a2 second parity check matrices, the base matrices of the a2 second parity check matrices are the same;
  • the maximum boost value Zmax2 of the second parity check matrix set is the first parity check matrix set D times the maximum boost value Zi supported by the i-th first parity check matrix, D is a positive integer power of 2, and i is a non-negative integer less than a1.
  • the maximum boost value Zmax2 of the second set of parity check matrices is greater than the maximum boost value Zmax1 of the first set of parity check matrices.
  • the maximum boost value Zmax2 of the second set of parity check matrices is a ⁇ 2 b , where a is an odd number greater than 15, and b is a positive integer.
  • the target boost value belongs to one boost value subset in the G boost value subsets, wherein G is greater than 1, and there is no intersection between any two boost value subsets in the G boost value subsets. .
  • the boost values supported by the first parity check matrix set constitute a first boost value set Zset1
  • the boost values supported by the second parity check matrix set constitute a second boost value set Zset2
  • the The first boost value set Zset1 and the second boost value set Zset2 satisfy one of the following:
  • the first boost value set Zset1 and the second boost value set Zset2 have no intersection; the first boost value set Zset1 is a subset of the second boost value set Zset2; the first boost value set Zset1 and The number of elements in the intersection Zset of the second boost value set Zset2 is smaller than the number of elements in the first boost value set Zset1 and smaller than the number of elements in the second boost value set Zset2.
  • the minimum boost value supported by the second parity check matrix set is greater than the maximum boost value supported by the first parity check matrix set; the boost value supported by the second parity check matrix set includes: At least one of the following: 416, 448, 480, 512, 576, 640, 704, 768, 832, 896, 960, 1024, 1152, 1280, 1408, 1536, 1664, 1792, 1920, 2048.
  • the maximum information length Kmax1 supported by the first set of parity check matrices is smaller than the maximum information length Kmax2 supported by the second set of parity check matrices.
  • the second parity check matrix set includes at least one parity check matrix
  • the parity check matrix includes k0 upper and lower adjacent pairs
  • the k0 upper and lower adjacent pairs include k1 first type upper and lower pairs.
  • the second parity check matrix set includes at least one parity check matrix
  • the parity check matrix includes k3 first-type elements indicating the cyclic shift of the identity matrix and k4 elements indicating the cyclic shift of the identity matrix.
  • the second type element of the bit, and k3 is greater than 3*k4, and both k3 and k4 are integers greater than 0; wherein, the result of taking the remainder of the first type element to 2 is equal to 0; the second type element is equal to 2 The remainder of the result is greater than 0.
  • it also includes:
  • Step 400 Determine one parity check matrix set from at least two parity check matrix sets as the target parity check matrix set according to the setting information; wherein the setting information includes at least one of the following: a transmission block size, a code Rate, high layer signaling, modulation order, modulation and coding scheme index, modulation and coding strategy MCS table index.
  • determining one parity check matrix set from at least two parity check matrix sets as the target parity check matrix set according to the setting information including:
  • the second set of parity check matrices is used as the set of target parity check matrices:
  • the transport block size is greater than or equal to T0, which is an integer greater than or equal to the maximum information length Kmax1 supported by the first parity check matrix set; the code rate is greater than or equal to R0, and R0 is a real number greater than 0 and less than 1.
  • FIG. 6 is a schematic structural diagram of a low-density parity check encoding apparatus according to an embodiment. As shown in FIG. 6 , the low density parity check encoding apparatus includes: a first matrix determination module 510 and a first encoding module 520 .
  • the first matrix determination module 510 is configured to determine a target parity check matrix, the target parity check matrix belongs to the second parity check matrix set, and the basis matrix of the second parity check matrix set is from the first parity check matrix.
  • the first encoding module 520 is configured to perform low-density parity check encoding on the data to be transmitted according to the target parity check matrix and the target boost value.
  • the low-density parity check coding apparatus of this embodiment uses the target parity check matrix for coding, which can not only improve the throughput of data transmission and the decoding parallelism of LDPC codes, but also support flexible code length and code rate, and improve coding flexibility.
  • the first matrix determination module 510 is configured as:
  • a target parity check matrix of the second set of parity check matrices is determined according to the first set of parity check matrices.
  • the first matrix determination module 510 is configured as:
  • the base matrix of the second parity check matrix set is extracted from the base matrix of the first parity check matrix set according to at least one of a row index sequence and a column index sequence.
  • the row index sequence satisfies one of the following:
  • the elements in the row index sequence are consecutive ascending integers; the elements in the row index sequence include discontinuous ascending integers; the elements in the row index sequence are non-ascending integers, and the first
  • the M elements are consecutive integers in ascending order, and M is greater than 1; the row index sequence includes at least ⁇ 0, 1, 2, 3 ⁇ .
  • the column index sequence satisfies one of the following:
  • the first kb2 elements of the column index sequence are consecutive integers in ascending order, and kb2 is greater than 1; the first kb2 elements of the column index sequence include discontinuous ascending integers, and kb2 is greater than 1; the column index sequence includes at least ⁇ 0, 1 ⁇ ; the column index sequence includes at least ⁇ 22, 23, 24, 25 ⁇ .
  • kb2 is equal to the number of systematic columns of the base matrix of the second set of parity check matrices, or is equal to the difference between the number of columns and the number of rows of the base matrix of the second set of parity check matrices, or is less than or equal to the number of systematic columns of parity check matrices in the first set of parity check matrices.
  • the first set of parity check matrices includes a1 first parity check matrices, and the base matrices of the a1 first parity check matrices are the same;
  • the second set of parity check matrices including a2 second parity check matrices, the base matrices of the a2 second parity check matrices are the same;
  • the maximum boost value Zmax2 of the second parity check matrix set is the first parity check matrix set D times the maximum boost value Zi supported by the i-th first parity check matrix, D is a positive integer power of 2, and i is a non-negative integer less than a1.
  • the maximum boost value Zmax2 of the second set of parity check matrices is greater than the maximum boost value Zmax1 of the first set of parity check matrices.
  • the maximum boost value Zmax2 of the second set of parity check matrices is a ⁇ 2 b , where a is an odd number greater than 15, and b is a positive integer.
  • the target boost value belongs to one boost value subset in the G boost value subsets, wherein G is greater than 1, and there is no intersection between any two boost value subsets in the G boost value subsets. .
  • the boost values supported by the first parity check matrix set constitute a first boost value set Zset1
  • the boost values supported by the second parity check matrix set constitute a second boost value set Zset2
  • the The first boost value set Zset1 and the second boost value set Zset2 satisfy one of the following:
  • the first boost value set Zset1 and the second boost value set Zset2 have no intersection; the first boost value set Zset1 is a subset of the second boost value set Zset2; the first boost value set Zset1 and The number of elements in the intersection Zset of the second boost value set Zset2 is smaller than the number of elements in the first boost value set Zset1 and smaller than the number of elements in the second boost value set Zset2.
  • the minimum boost value supported by the second parity check matrix set is greater than the maximum boost value supported by the first parity check matrix set; the boost value supported by the second parity check matrix set includes: At least one of the following: 416, 448, 480, 512, 576, 640, 704, 768, 832, 896, 960, 1024, 1152, 1280, 1408, 1536, 1664, 1792, 1920, 2048.
  • the maximum information length Kmax1 supported by the first set of parity check matrices is smaller than the maximum information length Kmax2 supported by the second set of parity check matrices.
  • the second parity check matrix set includes at least one parity check matrix
  • the parity check matrix includes k0 upper and lower adjacent pairs
  • the k0 upper and lower adjacent pairs include k1 first Class top-bottom adjacent pairs and k2 second-type top-bottom adjacent pairs, and k1 is greater than 3*k2, and k1 and k2 are both integers greater than 0; wherein, the top-bottom adjacent pairs refer to any arbitrary number in the parity check matrix.
  • the second parity check matrix set includes at least one parity check matrix
  • the parity check matrix includes k3 elements of the first type indicating the cyclic shift of the identity matrix and k4 indicating the identity matrix.
  • the second-type element of the cyclic shift, and k3 is greater than 3*k4, and both k3 and k4 are integers greater than 0; wherein, the result of taking the remainder of 2 for the first-type element is equal to 0; the second-type element pair The result of taking the remainder of 2 is greater than 0.
  • it also includes:
  • the first set determination module is configured to determine a parity check matrix set from at least two parity check matrix sets as the target parity check matrix set according to the setting information; wherein, the setting information includes at least one of the following: Transport block size, code rate, higher layer signaling, modulation order, modulation and coding scheme index, MCS table index.
  • the first set determination module is set to:
  • the second set of parity check matrices is used as the set of target parity check matrices:
  • the transport block size is greater than or equal to T0, which is an integer greater than or equal to the maximum information length Kmax1 supported by the first parity check matrix set; the code rate is greater than or equal to R0, and R0 is a real number greater than 0 and less than 1.
  • the low-density parity-check encoding device proposed in this embodiment and the low-density parity-check encoding method proposed in the above-mentioned embodiments belong to the same concept.
  • the example has the same effect as that of the low-density parity-check encoding method.
  • FIG. 7 is a schematic structural diagram of a low-density parity check encoding apparatus according to another embodiment. As shown in FIG. 7 , the low-density parity check encoding apparatus includes: a second matrix determination module 610 and a second encoding module 620 .
  • the second matrix determination module 610 is configured to determine a target base matrix, where the target base matrix is a base matrix of the second parity check matrix set, and the base matrix of the second parity check matrix set is determined from the first parity check matrix.
  • the second encoding module 620 is configured to perform low-density parity check encoding on the data to be transmitted according to the target base matrix and the target boost value.
  • the low-density parity check coding apparatus of this embodiment uses the target base matrix for coding, which can not only improve the throughput of data transmission and the decoding parallelism of LDPC codes, but also support flexible code length and code rate, and improve coding flexibility .
  • the target base matrix for coding can not only improve the throughput of data transmission and the decoding parallelism of LDPC codes, but also support flexible code length and code rate, and improve coding flexibility .
  • the second encoding module 620 is configured to determine a parity check matrix H according to the target base matrix and the target boost value; perform low-density parity check encoding on the data to be transmitted based on the check matrix H.
  • the second encoding module 620 is configured to determine a target parity check matrix according to the target base matrix; perform low-density parity check on the data to be transmitted based on the target parity check matrix and the target boost value coding.
  • it also includes:
  • the second set determining module is configured to determine one parity check matrix set from at least two parity check matrix sets as the target parity check matrix set according to the setting information; wherein, the setting information includes at least one of the following: Transport block size, code rate, higher layer signaling, modulation order, modulation and coding scheme index, MCS table index.
  • the low-density parity-check encoding device proposed in this embodiment and the low-density parity-check encoding method proposed in the above-mentioned embodiments belong to the same concept.
  • the example has the same effect as that of the low-density parity-check encoding method.
  • FIG. 8 is a schematic structural diagram of a low density parity check decoding apparatus according to an embodiment. As shown in FIG. 8 , the low density parity check decoding apparatus includes: a third matrix determination module 710 and a first decoding module 720 .
  • the third matrix determination module 710 is configured to determine a target parity check matrix, the target parity check matrix belongs to the second parity check matrix set, and the basis matrix of the second parity check matrix set is from the first parity check matrix Extracted from the base matrix of the check matrix set; the first decoding module 720 is configured to perform low-density parity check decoding on the received data according to the target parity check matrix and the target boost value.
  • the low-density parity-check decoding device of this embodiment uses the target parity-check matrix for encoding, which can not only improve the throughput of data transmission and the decoding parallelism of the LDPC code, but also support flexible code length and code rate, and improve the Coding flexibility.
  • it also includes:
  • the third set determination module is configured to determine one parity check matrix set from at least two parity check matrix sets as the target parity check matrix set according to the setting information; wherein, the setting information includes at least one of the following: Transport block size, code rate, higher layer signaling, modulation order, modulation and coding scheme index, MCS table index.
  • the third set determination module is set to:
  • the second set of parity check matrices is used as the set of target parity check matrices:
  • the transport block size is greater than or equal to T0, and T0 is an integer greater than or equal to the maximum information length Kmax1 supported by the first parity check matrix set; the code rate is greater than or equal to R0, and R0 is a real number greater than 0 and less than 1
  • the low-density parity-check decoding apparatus proposed in this embodiment and the low-density parity-check decoding method proposed in the above-mentioned embodiments belong to the same concept, and the technical details not described in detail in this embodiment can refer to any of the above-mentioned embodiments, and This embodiment has the same effect as that of the low-density parity check decoding method.
  • FIG. 9 is a schematic structural diagram of a low density parity check decoding apparatus according to another embodiment. As shown in FIG. 9 , the low density parity check decoding apparatus includes: a fourth matrix determination module 810 and a second decoding module 820 .
  • the fourth matrix determination module 810 is configured to determine a target base matrix, where the target base matrix is the base matrix of the second parity check matrix set, and the base matrix of the second parity check matrix set is obtained from the first parity check matrix.
  • the second decoding module 820 is configured to perform low-density parity check decoding on the received data according to the target base matrix and the target boost value.
  • the low-density parity-check decoding device of this embodiment uses the target base matrix for encoding, which can not only improve the throughput of data transmission and the decoding parallelism of LDPC codes, but also support flexible code length and code rate, and improve the flexibility of encoding. sex. For technical details not described in detail in this embodiment, reference may be made to any of the foregoing embodiments.
  • it also includes:
  • the fourth set determination module is configured to determine one parity check matrix set from at least two parity check matrix sets as the target parity check matrix set according to the setting information; wherein, the setting information includes at least one of the following: Transport block size, code rate, higher layer signaling, modulation order, modulation and coding scheme index, MCS table index.
  • the low-density parity-check decoding apparatus proposed in this embodiment and the low-density parity-check decoding method proposed in the above-mentioned embodiments belong to the same concept, and the technical details not described in detail in this embodiment can refer to any of the above-mentioned embodiments, and This embodiment has the same effect as that of the low-density parity check decoding method.
  • FIG. 10 is a schematic diagram of a hardware structure of an encoding device provided by an embodiment.
  • the encoding device provided by the present application includes a memory 12 , a processor 11 and A computer program stored on the memory 12 and executable on the processor 11 , when the processor 11 executes the program, the above-mentioned low-density parity check encoding method is implemented.
  • the encoding device may include a memory 12; the number of processors 11 in the encoding device may be one or more, and one processor 11 is taken as an example in FIG. 10; the memory 12 is used to store one or more programs; the one or more The program is executed by the one or more processors 11, so that the one or more processors 11 implement the low density parity check encoding method as described in the embodiments of the present application.
  • the encoding device further includes: a communication device 13 , an input device 14 and an output device 15 .
  • the processor 11 , the memory 12 , the communication device 13 , the input device 14 and the output device 15 in the encoding device may be connected by a bus or in other ways, and the connection by a bus is taken as an example in FIG. 10 .
  • the input device 14 may be used to receive input numerical or character information, and to generate key signal input related to user settings and function control of the encoding device.
  • the output device 15 may include a display device such as a display screen.
  • the communication device 13 may include a receiver and a transmitter.
  • the communication device 13 is configured to transmit and receive information according to the control of the processor 11 .
  • the memory 12 can be configured to store software programs, computer-executable programs, and modules, such as program instructions/modules corresponding to the low-density parity-check encoding method described in the embodiments of the present application (for example, low-density parity-check coding methods).
  • the memory 12 may include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function; the storage data area may store data created according to the use of the encoding apparatus, and the like.
  • memory 12 may include high-speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid-state storage device.
  • memory 12 may include memory located remotely from processor 11, which may be connected to the encoding device through a network. Examples of such networks include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.
  • FIG. 11 is a schematic diagram of a hardware structure of a decoding device provided by an embodiment.
  • the decoding device provided by the present application includes a memory 22, a processing The processor 21 and a computer program stored in the memory 22 and executable on the processor 21, the processor 21 implements the above-mentioned low-density parity check decoding method when the program is executed.
  • the decoding device may include a memory 22; the number of processors 21 in the decoding device may be one or more, and one processor 21 is taken as an example in FIG. 11; the memory 22 is used to store one or more programs; the one or A plurality of programs are executed by the one or more processors 21, so that the one or more processors 21 implement the low density parity check decoding method as described in the embodiments of the present application.
  • the decoding device further includes: a communication device 23 , an input device 24 and an output device 25 .
  • the processor 21 , the memory 22 , the communication device 23 , the input device 24 and the output device 25 in the decoding device may be connected by a bus or in other ways.
  • the connection by a bus is taken as an example.
  • the input device 24 may be used to receive input numerical or character information, and to generate key signal input related to user settings and function control of the decoding device.
  • the output device 25 may include a display device such as a display screen.
  • the communication device 23 may include a receiver and a transmitter.
  • the communication device 23 is configured to transmit and receive information according to the control of the processor 21 .
  • the memory 22 can be configured to store software programs, computer-executable programs, and modules, such as program instructions/modules corresponding to the low-density parity-check decoding method described in the embodiments of the present application (for example, low-density parity-check decoding methods).
  • the memory 22 may include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function; the storage data area may store data created according to the use of the decoding device, and the like.
  • memory 22 may include high speed random access memory, and may also include nonvolatile memory, such as at least one magnetic disk storage device, flash memory device, or other nonvolatile solid state storage device.
  • memory 22 may include memory located remotely from processor 21, which may be connected to the decoding device through a network. Examples of such networks include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.
  • An embodiment of the present application further provides a storage medium, where a computer program is stored in the storage medium, and when the computer program is executed by a processor, the low-density parity check coding method or the low-density parity check coding method described in any one of the embodiments of the present application is implemented. Parity check decoding method.
  • the encoding method includes:
  • the target parity check matrix belongs to the second parity check matrix set, and the base matrix of the second parity check matrix set is extracted from the base matrix of the first parity check matrix set Obtained; according to the target parity check matrix and the target boost value, low-density parity check coding is performed on the data to be transmitted.
  • the encoding method including:
  • the target base matrix is the base matrix of the second parity check matrix set, and the base matrix of the second parity check matrix set is extracted from the base matrix of the first parity check matrix set. ; Perform low-density parity check coding on the data to be transmitted according to the target base matrix and the target boost value.
  • the decoding method includes:
  • the target parity check matrix belongs to the second parity check matrix set, and the base matrix of the second parity check matrix set is extracted from the base matrix of the first parity check matrix set Obtained: performing low-density parity-check decoding on the received data according to the target parity check matrix and the target boost value.
  • the decoding method includes:
  • the target base matrix is the base matrix of the second parity check matrix set, and the base matrix of the second parity check matrix set is extracted from the base matrix of the first parity check matrix set. ; Perform low-density parity-check decoding on the received data according to the target base matrix and the target boost value.
  • the computer storage medium of the embodiments of the present application may adopt any combination of one or more computer-readable media.
  • the computer-readable medium may be a computer-readable signal medium or a computer-readable storage medium.
  • the computer-readable storage medium can be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared or semiconductor system, apparatus or device, or any combination of the above.
  • Examples (non-exhaustive list) of computer readable storage media include: electrical connections with one or more wires, portable computer disks, hard disks, random access memory (RAM), read only memory (Read Only Memory) Memory, ROM), erasable programmable read only memory (Erasable Programmable Read Only Memory, EPROM), flash memory, optical fiber, portable CD-ROM, optical storage device, magnetic storage device or any suitable combination of the above.
  • a computer-readable storage medium can be any tangible medium that contains or stores a program that can be used by or in connection with an instruction execution system, apparatus, or device.
  • a computer-readable signal medium may include a propagated data signal in baseband or as part of a carrier wave, with computer-readable program code embodied thereon. Such propagated data signals may take a variety of forms including, but not limited to, electromagnetic signals, optical signals, or any suitable combination of the foregoing.
  • a computer-readable signal medium can also be any computer-readable medium other than a computer-readable storage medium that can transmit, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device .
  • Program code embodied on a computer-readable medium may be transmitted using any suitable medium, including but not limited to: wireless, wire, optical fiber cable, radio frequency (RF), etc., or any suitable combination of the foregoing.
  • suitable medium including but not limited to: wireless, wire, optical fiber cable, radio frequency (RF), etc., or any suitable combination of the foregoing.
  • Computer program code for carrying out the operations of the present application may be written in one or more programming languages, including object-oriented programming languages, such as Java, Smalltalk, C++, and conventional A procedural programming language, such as the "C" language or similar programming language.
  • the program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server.
  • the remote computer may be connected to the user's computer through any kind of network, including a Local Area Network (LAN) or Wide Area Network (WAN), or may be connected to an external computer (eg use an internet service provider to connect via the internet).
  • LAN Local Area Network
  • WAN Wide Area Network
  • user terminal encompasses any suitable type of wireless user equipment such as a mobile telephone, portable data processing device, portable web browser or vehicle mounted mobile station.
  • the various embodiments of the present application may be implemented in hardware or special purpose circuits, software, logic, or any combination thereof.
  • some aspects may be implemented in hardware, while other aspects may be implemented in firmware or software that may be executed by a controller, microprocessor or other computing device, although the application is not limited thereto.
  • Embodiments of the present application may be implemented by the execution of computer program instructions by a data processor of a mobile device, eg in a processor entity, or by hardware, or by a combination of software and hardware.
  • Computer program instructions may be assembly instructions, Instruction Set Architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or written in any combination of one or more programming languages source code or object code.
  • ISA Instruction Set Architecture
  • the block diagrams of any logic flow in the figures of the present application may represent program steps, or may represent interconnected logic circuits, modules and functions, or may represent a combination of program steps and logic circuits, modules and functions.
  • Computer programs can be stored on memory.
  • the memory may be of any type suitable for the local technical environment and may be implemented using any suitable data storage technology, such as, but not limited to, Read-Only Memory (ROM), Random Access Memory (RAM), optical Memory devices and systems (Digital Video Disc (DVD) or Compact Disk (CD)), etc.
  • Computer-readable media may include non-transitory storage media.
  • the data processor may be of any type suitable for the local technical environment, such as, but not limited to, a general purpose computer, a special purpose computer, a microprocessor, a Digital Signal Processing (DSP), an Application Specific Integrated Circuit (ASIC) ), programmable logic devices (Field-Programmable Gate Array, FPGA) and processors based on multi-core processor architecture.
  • a general purpose computer such as, but not limited to, a general purpose computer, a special purpose computer, a microprocessor, a Digital Signal Processing (DSP), an Application Specific Integrated Circuit (ASIC) ), programmable logic devices (Field-Programmable Gate Array, FPGA) and processors based on multi-core processor architecture.
  • DSP Digital Signal Processing
  • ASIC Application Specific Integrated Circuit
  • FPGA Field-Programmable Gate Array

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Abstract

一种低密度奇偶校验编码方法、低密度奇偶校验译码方法、编码设备、译码设备及介质。该低密度奇偶校验编码方法包括：确定目标奇偶校验矩阵，所述目标奇偶校验矩阵属于第二奇偶校验矩阵集合，并且，所述第二奇偶校验矩阵集合的基矩阵从第一奇偶校验矩阵集合的基矩阵中抽取得到（110）；根据所述目标奇偶校验矩阵和目标提升值对待传输数据进行低密度奇偶校验编码（120）。

Description

低密度奇偶校验编码方法、低密度奇偶校验译码方法、编码设备、译码设备及介质 技术领域
本申请涉及无线通信网络领域，例如涉及一种低密度奇偶校验编码方法、低密度奇偶校验译码方法、编码设备、译码设备及介质。
背景技术
随着大数据、云计算、时延敏感网络等技术的快速发展，无线通信网络中的用户设备呈现爆炸式增长，无线通信网络将承载多样的应用和海量的数据，这对于数据传输速率、吞吐量、数据纠错校验等都提出了很高的要求。在无线通信系统中，发送端对待传输的数据进行信道编码获得编码比特序列，然后将编码比特序列映射成星座调制符号发送至接收端。在数据传输信道中，受到多径、移动、噪声、干扰等因素的影响，数据传输失真。接收端需要对接收到的星座调制符号进行信道解码才能恢复出传输的数据。在信道编码过程中，通过在传输的数据序列中添加一些冗余信息，接收端据此可以校验并恢复传输的数据。
低密度奇偶校验(Low Density Parity Check，LDPC)码是一种利用稀疏的校验矩阵或二分图来定义的线性分组码。由于校验矩阵非常稀疏，可以降低解码的复杂度，具有较高的可靠性。但是，LDPC码的最大提升值是固定的，仅为384，并且基矩阵维数较大，不能支持灵活的码长和码率，限制了LDPC码的译码并行度和数据传输的吞吐量。
发明内容
本申请提供一种低密度奇偶校验编码方法、低密度奇偶校验译码方法、编码设备、译码设备及介质，以提高编码的灵活性以及数据传输的吞吐量。
本申请实施例提供一种低密度奇偶校验编码方法，包括：
确定目标奇偶校验矩阵，所述目标奇偶校验矩阵属于第二奇偶校验矩阵集合，并且，所述第二奇偶校验矩阵集合的基矩阵从第一奇偶校验矩阵集合的基矩阵中抽取得到；根据所述目标奇偶校验矩阵和目标提升值对待传输数据进行低密度奇偶校验编码。
本申请实施例还提供了一种低密度奇偶校验编码方法，包括：
确定目标基矩阵，所述目标基矩阵为第二奇偶校验矩阵集合的基矩阵，并且，所述第二奇偶校验矩阵集合的基矩阵从第一奇偶校验矩阵集合的基矩阵中抽取得到；根据所述目标基矩阵和目标提升值对待传输数据进行低密度奇偶校验编码。
本申请实施例还提供了一种低密度奇偶校验译码方法，包括：
确定目标奇偶校验矩阵，所述目标奇偶校验矩阵属于第二奇偶校验矩阵集合，并且，所述第二奇偶校验矩阵集合的基矩阵从第一奇偶校验矩阵集合的基矩阵中抽取得到；根据所述目标奇偶校验矩阵和目标提升值对接收数据进行低密度奇偶校验译码。
本申请实施例还提供了一种低密度奇偶校验译码方法，包括：
确定目标基矩阵，所述目标基矩阵为第二奇偶校验矩阵集合的基矩阵，并且，所述第二奇偶校验矩阵集合的基矩阵从第一奇偶校验矩阵集合的基矩阵中抽取得到；根据所述目标基矩阵和目标提升值对接收数据进行低密度奇偶校验译码。
本申请实施例还提供了一种编码设备，包括存储器、处理器以及存储在存储器上并可在处理器上运行的计算机程序，所述处理器执行所述程序时实现上述的低密度奇偶校验编码方法。
本申请实施例还提供了一种译码设备，包括存储器、处理器以及存储在存储器上并可在处理器上运行的计算机程序，所述处理器执行所述程序时实现上述的低密度奇偶校验译码方法。
本申请实施例还提供了一种计算机可读存储介质，计算机可读存储介质上存储有计算机程序，该程序被处理器执行时实现上述的低密度奇偶校验编码方法或低密度奇偶校验译码方法。
附图说明
图1为一实施例提供的一种低密度奇偶校验编码方法的流程图；
图2为另一实施例提供的一种低密度奇偶校验编码方法的流程图；
图3为一实施例提供的一种基于目标奇偶校验矩阵进行LDPC编码的仿真性能的示意图；
图4为一实施例提供的一种低密度奇偶校验译码方法的流程图；
图5为另一实施例提供的一种低密度奇偶校验译码方法的流程图；
图6为一实施例提供的一种低密度奇偶校验编码装置的结构示意图；
图7为另一实施例提供的一种低密度奇偶校验编码装置的结构示意图；
图8为一实施例提供的一种低密度奇偶校验译码装置的结构示意图；
图9为另一实施例提供的一种低密度奇偶校验译码装置的结构示意图；
图10为一实施例提供的一种编码设备的硬件结构示意图；
图11为一实施例提供的一种译码设备的硬件结构示意图。
具体实施方式
下面结合附图和实施例对本申请进行说明。此处所描述的具体实施例仅仅用于解释本申请。为了便于描述，附图中仅示出了与本申请相关的部分。
LDPC码的校验矩阵H为mb×z行和nb×z列的矩阵，它是由mb×nb个子矩阵P构成，每个子矩阵都是z×z的标准置换矩阵的不同幂次(对应于单位阵的循环移位矩阵)或者z×z的全零方阵。校验矩阵H形式如下：
Figure PCTCN2021139513-appb-000001
其中，如果
Figure PCTCN2021139513-appb-000002
则对应的子矩阵
Figure PCTCN2021139513-appb-000003
为z×z的全零方阵；如果
Figure PCTCN2021139513-appb-000004
是大于或等于0的整数，对应的子矩阵
Figure PCTCN2021139513-appb-000005
为标准置换矩阵P 0的
Figure PCTCN2021139513-appb-000006
次幂，z×z的标准置换矩阵P 0形式如下：
Figure PCTCN2021139513-appb-000007
由此，
Figure PCTCN2021139513-appb-000008
可以唯一标识每一个子矩阵，如果一个子矩阵为全零方阵，对应的
Figure PCTCN2021139513-appb-000009
用-1来表示(也可以采用空值表示)；如果一个子矩阵是由单位阵循环移位s获得，则
Figure PCTCN2021139513-appb-000010
等于s，所有
Figure PCTCN2021139513-appb-000011
构成一个奇偶校验矩阵Hb。
z是标准置换矩阵(以及子矩阵)的维数，称为提升值(Lifting Size)。
LDPC码可以由奇偶校验矩阵Hb和提升值z唯一确定。对应的，将奇偶校验矩阵中所有非-1的元素置换成“1”，以及将所有-1的元素置换成“0”，可以获得基矩阵BG。
基矩阵中只包括2种元素：“0”和“1”，其中，“0”用于指示全零方阵，“1”用 于指示单位阵的循环移位，实际循环移位的位数需要由奇偶校验矩阵确定。
例如，一个奇偶校验矩阵(2行4列)为
Figure PCTCN2021139513-appb-000012
提升值z＝4，则校验矩阵为：
Figure PCTCN2021139513-appb-000013
对应的基矩阵为：
Figure PCTCN2021139513-appb-000014
此外，对于一个维数为mb×nb的奇偶校验矩阵，该奇偶校验矩阵的系统列数等于矩阵列数nb和矩阵行数mb的差值(kb＝nb-mb)，该奇偶校验矩阵的校验列数等于矩阵行数mb，对应的LDPC码是一种系统码，由长度为kb*z的LDPC码信息比特序列c和长度为mb*z的LDPC码校验比特序列w构成。LDPC码信息比特序列c是已知的，LDPC编码的本质就是求取LDPC码校验比特序列w。类似的，校验矩阵H也可以分为两部分：系统块Hc和校验块Hw，其中H＝[Hc,Hw]，即Hc为校验矩阵H中的前kb*z列构成(维数为mb*z行和kb*z列)，Hw为校验矩阵H中的后mb*z列构成(维数为mb*z行和mb*z列)。因此，LDPC码字满足如下公式：[Hc,Hw]·[c,w] T＝0。进而，Hw·W T＝Hc·C T。最终由以下公式计算出LDPC码校验比特序列w：w T＝Hw -1·Hc·c T，实现LDPC编码。
在本申请实施例中，从一个矩阵A中抽取得到矩阵B是指：按行索引序列a和/或列索引序列b对矩阵A进行抽取获得一个子矩阵B。例如，
Figure PCTCN2021139513-appb-000015
行索引序列为a＝{0,1,3}，则按该行索引序列a从矩阵A中抽取得到的子矩阵为：
Figure PCTCN2021139513-appb-000016
如果列索引序列为b＝{0,2,3}，则按该列索引序列b 从矩阵A中抽取得到的子矩阵为
Figure PCTCN2021139513-appb-000017
按行索引序列a＝{0,1,3}和列索引序列b＝{0,2,3}从矩阵A中抽取得到的子矩阵为
Figure PCTCN2021139513-appb-000018
在相关标准协议中，LDPC码的最大提升值Zmax为384。在分层译码中，为了避免地址冲突，LDPC译码的最大译码并行度最大只能达到384，并且基矩阵维数较大，限制了LDPC译码的吞吐量。
本实施例的低密度奇偶校验编码方法可应用于通信系统中的发射机，低密度奇偶校验译码方法可应用于通信系统中的接收机，采用LDPC编码对传输的数据进行保护。例如，发射机采用LDPC编码器对待传输的数据信息比特序列执行LDPC编码，接收机采用LDPC译码器对接收到的信息进行LDPC译码，从而恢复出数据信息比特序列。
译码过程包括：LDPC译码器利用奇偶校验矩阵相关的参数迭代执行奇偶校验操作和变量节点操作，在每次迭代过程中不断尝试校正LDPC码字中可能接收出错的任何比特。在一些实施例中，LDPC码字可以是准循环LDPC码、结构化LDPC码或者经提升的LDPC码。在一些实施例中，LDPC译码器包括多个处理元件，可并行执行奇偶校验操作和变量节点操作。例如，当处理具有提升值为z的LDPC码字时，LDPC译码器可利用若干个(如z个，或者z的正整数因子个)处理元件并发执行奇偶校验操作和变量节点操作。
在本申请实施例中，提供一种低密度奇偶校验编码方法，利用目标奇偶校验矩阵进行编码，不仅可以提高数据传输的吞吐量以及LDPC码的译码并行度，而且支持灵活的码长和码率，提高编码灵活性。
图1为一实施例提供的一种低密度奇偶校验编码方法的流程图。如图1所示，本实施例提供的方法包括步骤110和步骤120。
在步骤110中，确定目标奇偶校验矩阵，所述目标奇偶校验矩阵属于第二奇偶校验矩阵集合，并且，所述第二奇偶校验矩阵集合的基矩阵从第一奇偶校验矩阵集合的基矩阵中抽取得到。
在步骤120中，根据所述目标奇偶校验矩阵和目标提升值对待传输数据进行低密度奇偶校验编码。
本实施例中，从第二奇偶校验矩阵集合(以下记为奇偶校验矩阵集合P2)中选定一个目标奇偶校验矩阵(以下记为Hb)，利用Hb和目标提升值(以下 记为Zc)对待传输数据进行编码，得到用于传输的LDPC码。其中，奇偶校验矩阵集合P2是根据第一奇偶校验矩阵集合(以下记为奇偶校验矩阵集合P1)得到的，奇偶校验矩阵集合P2与奇偶校验矩阵集合P1的基矩阵满足：奇偶校验矩阵集合P2的基矩阵是从奇偶校验矩阵集合P1的基矩阵中抽取得到的子矩阵。由于奇偶校验矩阵集合P2的基矩阵是奇偶校验矩阵集合P1的基矩阵的子矩阵，那么意味着采用奇偶校验矩阵集合P2进行的LDPC译码将会兼容奇偶校验矩阵集合P1的LDPC译码，相当于奇偶校验矩阵集合P2的LDPC译码器只采用奇偶校验矩阵集合P1的LDPC译码器中一部分硬件电路(如采用奇偶校验矩阵集合P1的LDPC译码器中的变量节点更新模块和校验节点更新模块，并且奇偶校验矩阵集合P1的LDPC译码器与奇偶校验矩阵集合P2的LDPC译码器的路由网络也基本相同)，从而可以使得奇偶校验矩阵集合P1和奇偶校验矩阵集合P2的译码完全兼容，提高LDPC译码效率，而且奇偶校验矩阵集合P2可以采用更高的提升值设计，从而可以采用更高的译码并行度，进而实现更高吞吐量的译码。奇偶校验矩阵集合P1可以采用相关标准协议中已知的奇偶校验矩阵集合。奇偶校验矩阵集合P1和奇偶校验矩阵集合P2可以相等，奇偶校验矩阵集合P1的基矩阵和奇偶校验矩阵集合P2的基矩阵可以相等，这种情况下，可以理解为按照所有的行索引和列索引进行抽取。
本实施例基于奇偶校验矩阵集合P2与奇偶校验矩阵集合P1的基矩阵的关系，在奇偶校验矩阵集合P1已知的情况下可以确定奇偶校验矩阵集合P2，从奇偶校验矩阵集合P2中确定用于编码的Hb。由于奇偶校验矩阵集合P2的基矩阵是从奇偶校验矩阵集合P1的基矩阵中抽取得到的，在相同的目标提升值的情况下，能够减少Hb的系统列数和/或校验列数，使接收机可针对更多的奇偶校验矩阵进行并行译码，提高了译码并行度以及数据传输的吞吐量，并且这种编码方式支持针对任意码长和码率的灵活编码。
在一实施例中，步骤110包括：根据第一奇偶校验矩阵集合确定第二奇偶校验矩阵集合的目标奇偶校验矩阵。即，根据奇偶校验矩阵集合P1确定奇偶校验矩阵集合P2，从奇偶校验矩阵集合P2中确定Hb。
在一实施例中，步骤110包括：
根据第一奇偶校验矩阵集合的基矩阵确定第二奇偶校验矩阵集合的基矩阵；根据第二奇偶校验矩阵集合的基矩阵确定第二奇偶校验矩阵集合的目标奇偶校验矩阵。即，根据奇偶校验矩阵集合P1的基矩阵确定奇偶校验矩阵集合P2的基矩阵，根据奇偶校验矩阵集合P2的基矩阵确定奇偶校验矩阵集合P2对应的Hb。
在一实施例中，步骤110包括：
依据索引序列和第一奇偶校验矩阵集合确定第二奇偶校验矩阵集合；从第二奇偶校验矩阵集合中确定目标奇偶校验矩阵。即，根据索引序列和奇偶校验矩阵集合P1确定奇偶校验矩阵集合P2，从P2中确定Hb。本实施例中，索引序列包括行索引序列和列索引序列中的至少之一。
在一实施例中，步骤110包括：
从第一奇偶校验矩阵集合或第二奇偶校验矩阵集合中确定目标奇偶校验矩阵。即，Hb属于奇偶校验矩阵集合P1或奇偶校验矩阵集合P2。
在一实施例中，第二奇偶校验矩阵集合的基矩阵按照行索引序列和列索引序列中的至少之一从第一奇偶校验矩阵集合的基矩阵中抽取得到。
本实施例中，Hb的基矩阵的维数为mb行和nb列，mb和nb都是大于0的整数。Hb的维数为mb行和nb列。奇偶校验矩阵集合P1的基矩阵的维数为mb1行和nb1列，mb1和nb1都是大于0的整数。奇偶校验矩阵集合P2的基矩阵的行数为mb2和列数为nb2，其中mb2和nb2都是大于0的整数。
在此基础上，行索引序列的长度为mb2，并且行索引序列中的各个元素都是从集合{0,1,2...,(mb1-1)}中取值，且各个元素互不相同。行索引序列中的一个元素为0，表示从奇偶校验矩阵集合P1的基矩阵中抽取第一行。列索引序列的长度为nb2，并且列索引序列中的各个元素在集合{0,1,2...,(nb1-1)}中取值，且各个元素互不相同。列索引序列中的一个元素为0，表示要从奇偶校验矩阵集合P1的基矩阵中抽取第一列。
在一示例中，mb2是小于mb1的正整数，nb2是小于nb1的正整数。
在一实施例中，行索引序列满足以下之一：
1)行索引序列中的元素是连续的升序整数，也可以理解为，行索引序列为连续的升序整数集合；2)行索引序列中的元素包括不连续的升序整数，也可以理解为，行索引序列为不连续的升序整数集合；3)行索引序列中的元素是非升序整数，且行索引序列中的前M个元素是连续的升序整数，M是大于1且小于mb2的整数，也可以理解为，行索引序列为非升序整数集合；4)行索引序列中至少包括{0、1、2、3}。
一种示例，行索引序列中的前4个元素是{0、1、2、3}。
在一实施例中，列索引序列满足以下之一：
1)列索引序列的前E个元素是连续的升序整数，E大于1；2)列索引序列的前E个元素包括不连续的升序整数，E大于1；3)列索引序列中至少包括{0、1}；4)列索引序列中至少包括{22、23、24、25}。
一种示例，列索引序列的前2个元素是{0、1}。
在一实施例中，行索引序列和列索引序列包括以下组合之一：
1)行索引序列是连续的升序整数集合；列索引序列的前E个元素是不连续的升序整数，E是大于1的整数；2)行索引序列是不连续的升序整数集合；列索引序列的前E个元素是不连续的升序整数，E是大于1的整数；3)行索引序列是连续的升序整数集合；列索引序列的前E个元素是连续的升序整数，E是大于1的整数；4)行索引序列是不连续的升序整数集合；列索引序列的前E个元素是连续的升序整数，E是大于1的整数。
其中，E是大于1且小于或等于kb2的整数，kb2等于nb2和mb2的差值，即kb2等于奇偶校验矩阵集合P2的基矩阵的系统列数或奇偶校验矩阵集合P1中奇偶校验矩阵的系统列数。在一种示例中，E等于kb2。
在一实施例中，kb2等于第二奇偶校验矩阵集合的基矩阵的系统列数，或者等于第二奇偶校验矩阵集合的基矩阵的列数与行数的差值，或者小于或等于第一奇偶校验矩阵集合P1中的奇偶校验矩阵的系统列数。
本实施例中，奇偶校验矩阵集合P1的基矩阵的系统列数为kb1，kb1是大于0的整数，kb2小于kb1。
在一示例中，kb2为小于22的正整数。
在一示例中，kb2在集合{12、14、15、16、18、20}中取值。
在一示例中，kb2为小于kb1-4的正整数。
在一示例中，kb2在集合{12、14、15、16、17}中取值。
在一实施例中，第一奇偶校验矩阵集合中包括a1个第一奇偶校验矩阵，a1个第一奇偶校验矩阵的基矩阵相同；第二奇偶校验矩阵集合中包括a2个第二奇偶校验矩阵，a2个第二奇偶校验矩阵的基矩阵相同；第二奇偶校验矩阵集合的最大提升值Zmax2(以下记为Zmax2)为第一奇偶校验矩阵集合中第i个第一奇偶校验矩阵所支持的最大提升值(以下记为Zi)的D倍，D为2的正整数次幂，i为小于a1的非负整数，Zi是奇偶校验矩阵集合P1中第i个第一奇偶校验矩阵所支持的最大提升值。
本实施例中，a2是大于或等于1的整数，奇偶校验矩阵集合P2中所有的第二奇偶校验矩阵都具有相同的基矩阵；a1是大于或等于1的整数，奇偶校验矩阵集合P1中所有的第一奇偶校验矩阵都具有相同的基矩阵。奇偶校验矩阵集合P1中第i个第一奇偶校验矩阵所支持的最大提升值为Zi，i等于0、1、2、...或(a1-1)中的一个，奇偶校验矩阵集合P2中第i个第二奇偶校验矩阵的最大提升值 为Zi的D倍，即，等于Zi*D。
在一示例中，D是大于1的整数，D等于2的正整数次幂，如D等于2、4或8。
在一示例中，Zmax2等于以下之一：Z0、Z1、Z2、...、Z(a1-1)。
在一实施例中，奇偶校验矩阵集合P2的最大提升值Zmax2大于P1的最大提升值Zmax1。
本实施例中，奇偶校验矩阵集合P1所支持的最大提升值为Zmax1，奇偶校验矩阵集合P2所支持的最大提升值为Zmax2，其中，Zmax1和Zmax2都是大于0的整数，且Zmax2大于Zmax1。
在一示例中，Zmax1等于384，Zmax2为大于384的正整数。
在一示例中，Zmax2在集合{416、448、480、512、576、640、704、768、832、896、960、1024、1152、1280、1408、1536、1664、1792、1920、2048}中取值。
在一实施例中，第二奇偶校验矩阵集合的最大提升值Zmax2为a·2 b，其中，a是大于15的奇数，b是正整数。
本实施例中，Zmax2等于a·2 b，其中a是大于15的奇数，b是正整数。
在一示例中，a在集合{17、19、21、23、25、27、29、31、33、35、37、39、41}中取值；b在集合{4、5、6、7、8、9、10}中取值。
在一实施例中，第二奇偶校验矩阵集合支持的至少1个提升值子集合至少包括：a·2 B，其中，a是大于15的奇数，B是非负整数集合。
在一示例中，a在集合{17、19、21、23、25、27、29、31、33、35、37、39、41}中取值；B是一组连续的非负整数构成的集合。B是由B0到B1构成的集合，其中B0等于2、3、4、或者5；B1等于5、6、7、或者8。
在一示例中，所述1个提升值子集合中最小值大于384。
在一实施例中，目标提升值属于G个提升值子集合中的一个提升值子集合，其中，G大于1，G个提升值子集合中任意2个提升值子集合之间无交集。
本实施例中，存在G个提升值子集合，各提升值子集合的索引分别记为0、1、...、(G-1)，G是大于1的整数，任意2个提升值子集合之间无交集。目标提升值是G个提升值子集合中的1个元素。
在一实施例中，第一奇偶校验矩阵集合所支持的提升值子集合的索引构成集合Set1；第二奇偶校验矩阵集合所支持的提升值子集合索引构成集合Set2。 Set2是Set1的一个子集，或者Set2和Set1的交集为空集。
在一实施例中，第一奇偶校验矩阵集合支持的提升值构成第一提升值集合Zset1，第二奇偶校验矩阵集合支持的提升值构成第二提升值集合Zset2；Zset1和Zset2满足以下之一：
1)Zset1和Zset2无交集；2)Zset1是Zset2的子集；3)Zset1和Zset2的交集Zset中的元素数量小于Zset1中的元素数量，且小于Zset2中的元素数量。
在一实施例中，第二奇偶校验矩阵集合支持的最小提升值大于第一奇偶校验矩阵集合支持的最大提升值；第二奇偶校验矩阵集合支持的提升值包括以下至少之一：416、448、480、512、576、640、704、768、832、896、960、1024、1152、1280、1408、1536、1664、1792、1920、2048。
在一实施例中，第一奇偶校验矩阵集合支持的最大信息长度Kmax1小于第二奇偶校验矩阵集合支持的最大信息长度Kmax2。
在一示例中，Kmax1等于8448。
在一实施例中，第二奇偶校验矩阵集合中包括至少一个奇偶校验矩阵，该奇偶校验矩阵中包括k0个上下相邻对，k0个上下相邻对中包括k1个第一类上下相邻对和k2个第二类上下相邻对，且k1大于3*k2，k1和k2都是大于0的整数；其中，上下相邻对是指该奇偶校验矩阵中任意两个指示单位阵循环移位且位于同一列中的相邻元素；第一类上下相邻对的两个元素的差值对2取余的结果等于0；第二类上下相邻对的两个元素的差值对2取余的结果大于0。
本实施例中，上下相邻对定义为：该奇偶校验矩阵中任意2个元素{h i,j,h (i+1) mod mb,j}，这2个元素都是指示单位阵循环移位的元素(不为-1)，mb是该奇偶校验矩阵的行数，mod表示取余操作。第一类上下相邻对是指满足以下关系式的上下相邻对(表示为 hi,k和h j,k)：mod(h i,k-h j,k,2)≤a，j＝(i+1)mod mb；第二类上下相邻对是指满足以下关系式的上下相邻对(表示为 hi,k和h j,k)：mod(h i,k-h j,k,2)>a，j＝(i+1)mod mb。其中，a等于0，k0、k1和k2都是正整数，并且k1大于k2的3倍。
本实施例中，通过取余操作判断构成上下相邻对的两个元素的差为奇数还是偶数，如果对2取余的结果为0，差为偶数，则构成第一类上下相邻对，这种情况下，在译码过程中单位阵可以拆分成多组，各行的校验节点更新之间没有地址冲突，能够减少各行校验节点更新之间的等待时间，译码速度较快；如果对2取余的结果为1而不为0，差为奇数，则构成第二类上下相邻对，这种情况下各行校验节点更新之间存在地址冲突，各行的校验节点更新之间需要等待时间，译码速度较慢。因此，确定的目标奇偶校验矩阵中，第一类上下相邻对的 个数越多，译码速度越快即吞吐量越高。在确定目标奇偶校验矩阵时，可以适当增加第一类上下相邻对的数量。
在一实施例中，第二奇偶校验矩阵集合中包括至少一个奇偶校验矩阵，该奇偶校验矩阵中包括k3个指示单位阵循环移位的第一类元素和k4个指示单位阵循环移位的第二类元素，且k3大于3*k4，k3和k4都是大于0的整数；其中，第一类元素对2取余的结果等于0；第二类元素对2取余的结果大于0。
本实施例中，奇偶校验矩阵集合P2中包括至少一个奇偶校验矩阵，该奇偶校验矩阵中包括k3个指示单位阵循环移位的第一类元素和k4个指示单位阵循环移位的第二类元素，其中第一类元素满足以下关系：mod(h i,j,2)≤b，第二类元素满足以下关系：mod(h i,j,2)>b，其中，h i,j是该奇偶校验矩阵中横坐标为i且列坐标为j的指示单位阵循环移位的元素。b等于0，k3和k4都是正整数，并且k3大于k4的3倍。
本实施例中，通过取余操作判断指示单位阵循环移位的元素为奇数还是偶数。如果对2取余的结果为0，则为偶数，构成第一类元素，第一类元素所指示的单位阵，各行的校验节点更新之间没有地址冲突，能够减少各行校验节点更新之间的等待时间，译码速度较快；如果对2取余的结果不为0，则为奇数，构成第二类元素，第二类元素所指示的单位阵，各行校验节点更新之间存在地址冲突，各行的校验节点更新之间需要等待时间，译码速度较慢。因此，确定的目标奇偶校验矩阵中，第一类元素的个数越多，译码速度越高。在确定目标奇偶校验矩阵时，可以适当增加第一类元素的数量。
在一实施例中，还包括：
步骤100：根据设定信息从至少两个奇偶校验矩阵集合中确定一个奇偶校验矩阵集合作为目标奇偶校验矩阵集合；其中，设定信息包括以下至少之一：传输块尺寸(Transport Block Size，TBS)、码率、高层信令、调制阶数、调制编码方案索引、调制与编码策略(Modulation and Coding Scheme，MCS)表索引。
本实施例中，根据设定信息从至少两个奇偶校验矩阵集合中确定一个作为目标奇偶校验矩阵集合，Hb从目标奇偶校验矩阵集合中确定。在至少两个奇偶校验矩阵集合中，存在两个奇偶校验矩阵集合满足：其中一个奇偶校验矩阵集合的基矩阵是从另一个奇偶校验矩阵集合的基矩阵中抽取得到的子矩阵。
例如，相关标准协议中给定奇偶校验矩阵集合P1，根据奇偶校验矩阵集合P1确定奇偶校验矩阵集合P2，且奇偶校验矩阵集合P2的基矩阵是从奇偶校验矩阵集合P1的基矩阵中抽取得到的子矩阵。根据设定信息，可以选择奇偶校验矩阵集合P1或奇偶校验矩阵集合P2作为目标奇偶校验矩阵集合，并从中确定 一个奇偶校验矩阵作为Hb。
在一实施例中，相关标准协议中给定奇偶校验矩阵集合P1和第三奇偶校验矩阵集合(记为奇偶校验矩阵集合P2’)，并且根据奇偶校验矩阵集合P1确定奇偶校验矩阵集合P2，奇偶校验矩阵集合P2的基矩阵是从奇偶校验矩阵集合P1的基矩阵中抽取得到的子矩阵。根据设定信息，可以选择奇偶校验矩阵集合P1、奇偶校验矩阵集合P2或奇偶校验矩阵集合P2’作为目标奇偶校验矩阵集合，并从中确定一个奇偶校验矩阵作为Hb。
本实施例中，除了奇偶校验矩阵集合P1和奇偶校验矩阵集合P2，奇偶校验矩阵集合P2’也可以作为目标奇偶校验矩阵集合。奇偶校验矩阵集合P2’包括a3个第三奇偶校验矩阵，a3等于P1中第一奇偶校验矩阵的数量a1。在进行LDPC编码之前，根据设定信息从奇偶校验矩阵集合P1、奇偶校验矩阵集合P2和奇偶校验矩阵集合P2’中确定目标奇偶校验矩阵集合(或者确定目标奇偶校验矩阵集合的索引)，并从目标奇偶校验矩阵集合中确定一个奇偶校验矩阵作为Hb，然后依据Hb进行LDPC编码。
在一实施例中，步骤100包括：
在满足以下条件至少之一的情况下，将第二奇偶校验矩阵集合作为目标奇偶校验矩阵集合：
1)TBS大于或等于T0，T0为大于或等于奇偶校验矩阵集合P1支持的待传输数据的最大信息长度Kmax1的整数；2)码率大于或等于R0，R0为大于0且小于1的实数。
在一示例中，根据TBS和码率确定目标奇偶校验矩阵集合：
条件1：TBS小于或等于292比特，或者TBS小于或等于3824比特且码率小于或等于0.67，或者码率小于或等于0.25；条件2：TBS大于或等于T0，T0是大于或等于Kmax1的正整数；条件3：码率大于或等于R0，R0是大于0且小于1的实数。
如果满足条件1，则采用奇偶校验矩阵集合P2’作为目标奇偶校验矩阵集合；如果条件2和条件3中的至少之一成立，则采用奇偶校验矩阵集合P2作为目标奇偶校验矩阵集合；如果上述条件都不成立，则采用奇偶校验矩阵集合P1作为目标奇偶校验矩阵集合。
在一示例中，T0等于Kmax2的X倍，其中X是大于1的整数；R0等于1/2、2/3、3/4、5/6、6/7、7/8或者8/9；R0的数值可以采用四舍五入方法获得2位小数点的数值或者3位小数点的数值；R0等于0.5、0.67、0.75、0.83、0.86、0.88或者0.89。
在本申请实施例中，还提供一种低密度奇偶校验编码方法，利用目标基矩阵进行编码，不仅可以提高数据传输的吞吐量以及LDPC码的译码并行度，而且支持灵活的码长和码率，提高编码灵活性。本实施例中未详细描述的技术细节，可参见上述任意实施例。
图2为另一实施例提供的一种低密度奇偶校验编码方法的流程图。如图2所示，本实施例提供的方法包括步骤210和步骤220。
在步骤210中，确定目标基矩阵，所述目标基矩阵为第二奇偶校验矩阵集合的基矩阵，并且，所述第二奇偶校验矩阵集合的基矩阵从第一奇偶校验矩阵集合的基矩阵中抽取得到。
在步骤220中，根据所述目标基矩阵和目标提升值对待传输数据进行低密度奇偶校验编码。
本实施例中，从第二奇偶校验矩阵集合(即奇偶校验矩阵集合P2)的基矩阵中选定一个目标基矩阵，利用目标基矩阵和Zc对待传输数据进行编码，得到用于传输LDPC码。其中，奇偶校验矩阵集合P2与奇偶校验矩阵集合P1的基矩阵满足：奇偶校验矩阵集合P2的基矩阵是从第一奇偶校验矩阵集合(即奇偶校验矩阵集合P1)的基矩阵中抽取得到的子矩阵。奇偶校验矩阵集合P1可以采用相关标准协议中已知的奇偶校验矩阵集合。
本实施例基于奇偶校验矩阵集合P2与奇偶校验矩阵集合P1的基矩阵的关系，在奇偶校验矩阵集合P1的基矩阵已知的情况下可以确定奇偶校验矩阵集合P2的基矩阵，从奇偶校验矩阵集合P2的基矩阵中确定用于编码的目标基矩阵，目标基矩阵与目标奇偶校验矩阵相对应。由于奇偶校验矩阵集合P2的基矩阵是从奇偶校验矩阵集合P1的基矩阵中抽取得到的，在相同的目标提升值的情况下，能够减少相应的目标奇偶校验矩阵的系统列数和/或校验列数，使接收机可针对更多的奇偶校验矩阵进行并行译码，提高了译码并行度以及数据传输的吞吐量，并且这种编码方式支持针对任意码长和码率的灵活编码。
在一实施例中，步骤220包括：
根据目标基矩阵和目标提升值确定校验矩阵H(以下记为H)；基于校验矩阵H对待传输数据进行低密度奇偶校验编码。
本实施例中，先确定目标基矩阵，并根据目标基矩阵和Zc确定H，H与Hb相对应，基于H实现对待传输数据的低密度奇偶校验编码。
在一实施例中，步骤220包括：
根据目标基矩阵确定目标奇偶校验矩阵Hb；根据Hb和目标提升值对待传输数据进行低密度奇偶校验编码。
本实施例中，先确定目标基矩阵，并根据目标基矩阵和Zc确定Hb。目标基矩阵的维数为mb行和nb列，mb和nb都是大于0的整数。目标基矩阵可以为P2的基矩阵，是按行索引序列和/或列索引序列从奇偶校验矩阵集合P1的基矩阵中抽取得到的子矩阵。
在一实施例中，步骤210包括：
根据索引序列和第一奇偶校验矩阵集合的基矩阵确定第二奇偶校验矩阵集合的目标基矩阵，其中，索引序列包括行索引序列和列索引序列中的至少之一；在此基础上，步骤220包括：
根据目标基矩阵确定目标奇偶校验矩阵Hb；根据Hb和目标提升值对待传输数据进行低密度奇偶校验编码。
在一实施例中，步骤210包括：
从P1的基矩阵或P2的基矩阵中确定目标基矩阵。
在一实施例中，还包括：
步骤200：根据设定信息从至少两个奇偶校验矩阵集合中确定一个奇偶校验矩阵集合作为目标奇偶校验矩阵集合；其中，设定信息包括以下至少之一：传输块尺寸、码率、高层信令、调制阶数、调制编码方案索引、MCS表索引。
在一实施例中，步骤200包括：
在满足以下条件至少之一的情况下，将第二奇偶校验矩阵集合作为目标奇偶校验矩阵集合：
传输块尺寸大于或等于T0，T0为大于或等于第一奇偶校验矩阵集合支持的最大信息长度Kmax1的整数，或者T0等于第二奇偶校验矩阵集合支持的最大信息长度Kmax2；码率大于或等于R0，R0为大于0且小于1的实数。
本实施例中，根据设定信息从至少两个奇偶校验矩阵集合中确定一个作为目标奇偶校验矩阵集合，目标基矩阵与Hb相对应，Hb从目标奇偶校验矩阵集合中确定。
第二奇偶校验矩阵集合的基矩阵按照行索引序列和列索引序列中的至少之一从奇偶校验矩阵集合P1的基矩阵中抽取得到。
在一实施例中，行索引序列满足以下之一：
行索引序列中的元素是连续的升序整数；行索引序列中的元素包括不连续 的升序整数；行索引序列中的元素是非升序整数，且行索引序列中的前M个元素是连续的升序整数，M大于1；所述行索引序列中至少包括{0、1、2、3}。
在一实施例中，列索引序列满足以下之一：
列索引序列的前kb2个元素是连续的升序整数，kb2大于1；列索引序列的前kb2个元素包括不连续的升序整数，kb2大于1；列索引序列中至少包括{0、1}；列索引序列中至少包括{22、23、24、25}。
在一实施例中，kb2等于奇偶校验矩阵集合P2的基矩阵的系统列数，或者等于奇偶校验矩阵集合P2的基矩阵的列数与行数的差值，或者小于或等于奇偶校验矩阵集合P1中的奇偶校验矩阵的系统列数。
在一实施例中，第一奇偶校验矩阵集合中包括a1个第一奇偶校验矩阵，a1个第一奇偶校验矩阵的基矩阵相同；第二奇偶校验矩阵集合中包括a2个第二奇偶校验矩阵，a2个第二奇偶校验矩阵的基矩阵相同；第二奇偶校验矩阵集合的最大提升值Zmax2为第一奇偶校验矩阵集合中第i个第一奇偶校验矩阵所支持的最大提升值Zi的D倍，D为2的正整数次幂，i为小于a1的非负整数。
在一实施例中，第二奇偶校验矩阵集合的最大提升值Zmax2大于第一奇偶校验矩阵集合的最大提升值Zmax1。
在一实施例中，第二奇偶校验矩阵集合的最大提升值Zmax2为a·2 b，其中，a是大于15的奇数，b是正整数。
在一实施例中，目标提升值属于G个提升值子集合中的一个提升值子集合，其中，G大于1，G个提升值子集合中任意2个提升值子集合之间无交集。
在一实施例中，第一奇偶校验矩阵集合P1支持的提升值构成第一提升值集合Zset1，第二奇偶校验矩阵集合支持的提升值构成第二提升值集合Zset2；第一提升值集合Zset1和第二提升值集合Zset2满足以下之一：
第一提升值集合Zset1和第二提升值集合Zset2无交集；第一提升值集合Zset1是第二提升值集合Zset2的子集；第一提升值集合Zset1和第二提升值集合Zset2的交集Zset中的元素数量小于第一提升值集合Zset1中的元素数量，且小于第二提升值集合Zset2中的元素数量。
在一实施例中，第二奇偶校验矩阵集合支持的最小提升值大于第一奇偶校验矩阵集合支持的最大提升值；第二奇偶校验矩阵集合支持的提升值包括以下至少之一：416、448、480、512、576、640、704、768、832、896、960、1024、1152、1280、1408、1536、1664、1792、1920、2048。
在一实施例中，第一奇偶校验矩阵集合支持的最大信息长度Kmax1小于第 二奇偶校验矩阵集合支持的最大信息长度Kmax2。
在一实施例中，第二奇偶校验矩阵集合中包括至少一个奇偶校验矩阵，该奇偶校验矩阵中包括k0个上下相邻对，k0个上下相邻对中包括k1个第一类上下相邻对和k2个第二类上下相邻对，且k1大于3*k2，k1和k2都是大于0的整数；其中，上下相邻对是指该奇偶校验矩阵中任意两个指示单位阵循环移位且位于同一列中的相邻元素；第一类上下相邻对的两个元素的差值对2取余的结果等于0；第一类上下相邻对的两个元素的差值对2取余的结果大于0。
在一实施例中，第二奇偶校验矩阵集合中包括至少一个奇偶校验矩阵，该奇偶校验矩阵中包括k3个指示单位阵循环移位的第一类元素和k4个指示单位阵循环移位的第二类元素，且k3大于k4的3倍，k3和k4都是大于0的整数；
其中，第一类元素对2取余的结果等于0；第二类元素对2取余的结果大于0。
以下通过实例对编码过程进行示例性说明，在以下实例中，将第一奇偶校验矩阵集合记为奇偶校验矩阵集合P1，将第二奇偶校验矩阵集合记为奇偶校验矩阵集合P2，将第三奇偶校验矩阵集合记为奇偶校验矩阵集合P2’：
实例1
LDPC编码的输入信息比特序列(即待传输数据)表示为c 0,c 1,c 2,c 3,...,c K-1，其长度为K比特。LDPC编码后获得的编码后比特序列表示为d 0,d 1,d 2,...,d N-1，其长度为N比特。对于奇偶校验矩阵集合P1，K＝kb1·Z c，N＝(nb1-2)·Z c，即奇偶校验矩阵集合P1的系统列数为kb1以及总列数为nb1，kb1和nb1都是大于0的整数；对于奇偶校验矩阵集合P2，K＝kb2·Z c，N＝(nb2-2)·Z c，即奇偶校验矩阵集合P2的系统列数为kb2以及总列数为nb2，kb2和nb2都是大于0的整数；其中，Z c是LDPC编码的目标提升值，Z c是大于0的整数。
对输入信息比特序列进行LDPC编码，包括以下步骤：
步骤1，确定提升值子集合索引i LS。每个索引i LS定义一个提升值子集合，任意两个提升值子集合之间无交集。其中包含Z c的提升值子集合索引为i LS。该提升值子集合索引与目标奇偶校验矩阵的索引(即目标奇偶校验矩阵在奇偶校验矩阵集合中的索引)相同。
步骤2，将输入信息比特序列c 0,c 1,c 2,c 3,...,c K-1中第2·Z c比特至第K-1比特存入编码后比特序列d 0,d 1,d 2,...,d N-1中。可通过如下伪代码实现(其中“NULL”表示填充比特)：
for k＝2Z c to K-1
if c k≠＜NULL＞
Figure PCTCN2021139513-appb-000019
else
c k＝0；
Figure PCTCN2021139513-appb-000020
end if
end for
步骤3，确定奇偶校验矩阵集合P2的基矩阵H BG2；依据奇偶校验矩阵集合P2的基矩阵和提目标升值Z c确定校验矩阵H；并进行LDPC编码产生校验比特序列。产生的N+2Z c-K个校验比特构成校验比特序列
Figure PCTCN2021139513-appb-000021
且满足
Figure PCTCN2021139513-appb-000022
其中c＝[c 0,c 1,c 2,...,c K-1] T。其中所满足的关系式中的0是指全零向量，并且LDPC编码操作都在2元伽罗华域(GF(2))上进行。
校验矩阵H的确定过程包括：
对于奇偶校验矩阵集合P1，其基矩阵H BG1包括mb1行，对应行索引为i＝0,1,2,...,(mb1-1)，包括nb1列，对应列索引为j＝0,1,2,...,(nb1-1)。对于奇偶校验矩阵集合P2，其基矩阵H BG2包括mb2行，对应行索引为i＝0,1,2,...,(mb2-1)，其包括nb2列，对应列索引为j＝0,1,2,...,(nb2-1)。基矩阵中至少包括“0”和“1”两种元素。
奇偶校验矩阵集合P2的基矩阵H BG2由奇偶校验矩阵集合P1的基矩阵H BG1、行索引序列α和列索引序列β确定，此过程可表示为：H' BG＝H BG1(α,:)，H BG2＝H' BG(:,β)；或者，H" BG＝H BG1(:,β)，H BG2＝H" BG(α,:)；或者，H BG2＝H BG1(α,β)。
其中，H BG1是奇偶校验矩阵集合P1的基矩阵；H BG2是奇偶校验矩阵集合P2的基矩阵；H BG1(α,:)表示将矩阵H BG1中行索引为α的所有行取出并构成新的矩阵；类似的，H' BG(:,β)表示将矩阵H' BG中列索引为β的所有列取出并构成新的矩阵。即奇偶校验矩阵集合P2的基矩阵H BG2是奇偶校验矩阵集合P1的基矩阵H BG1的子矩阵(或抽取矩阵)。
目标奇偶校验矩阵Hb属于奇偶校验矩阵集合P2，相应的，目标基矩阵H BG属于奇偶校验矩阵集合P2的基矩阵H BG2。将目标基矩阵H BG中的所有元素置换成全零方阵或者单位阵循环移位后的矩阵，可以获得校验矩阵H。其中，全零 方阵或者单位阵的维数都是Z c×Z c。
获得校验矩阵H的过程包括：
将目标基矩阵H BG中的所有“0”元素置换成全零方阵，全零方阵的大小都是Z c×Z c。
将目标基矩阵H BG中的所有“1”元素置换成单位阵循环移位后的矩阵I(P i,j)，单位阵的大小为Z c×Z c，其中i和j分别是目标基矩阵H BG的行索引和列索引。 I( Pi,j)表示将一个大小为Z c×Z c的单位阵进行右循环移位P i,j后获得的矩阵。对于奇偶校验矩阵集合P1，P i,j＝mod(V i,j,Z c)，其中V i,j是奇偶校验矩阵集合P1中第i LS个第一奇偶校验矩阵中的第i行第j列元素，V i,j是根据索引i LS和奇偶校验矩阵集合P1确定，索引i LS是奇偶校验矩阵集合P1中的第一奇偶校验矩阵的索引；对于奇偶校验矩阵集合P2，奇偶校验矩阵集合P2的第i LS个第二奇偶校验矩阵根据奇偶校验矩阵集合P1的第i LS个第一奇偶校验矩阵、行索引序列α、和列索引序列β确定，V' i,j＝V α(i),β(j)，其中V' i,j是奇偶校验矩阵集合P2的第i LS个第二奇偶校验矩阵中的元素，V α(i),β(j)是奇偶校验矩阵集合P1的第i LS个第一奇偶校验矩阵中的元素；进而，通过计算公式P i,j＝mod(V' i,j,Z c)，获得右循环移位值P i,j。即，奇偶校验矩阵集合P2的目标奇偶校验矩阵由奇偶校验矩阵集合P1、行索引序列α和列索引序列β确定，例如，确定奇偶校验矩阵集合P2的第i LS个第二奇偶校验矩阵中指示单位阵循环移位的第i行第j列元素V' i,j为：V' i,j＝V α(i),β(j)，i LS等于0至7中的至少一个整数，α(i)是行索引序列α中的第i个元素，β(j)是列索引序列β中的第j个元素。
步骤4，将校验比特序列存入编码后比特序列，获取编码后比特序列。将产生的N+2Z c-K个校验比特
Figure PCTCN2021139513-appb-000023
存入编码后比特序列d 0,d 1,d 2,...,d N-1中，伪代码如下：
for k＝K to N+2Z c-1
Figure PCTCN2021139513-appb-000024
end for
表1为一示例中提供的提升值子集合。8个提升值子集合对应的提升值子集合索引i LS分别为0至7。
表1提升值子集合
提升值子集合索引(i LS) 提升值子集合
0 {2,4,8,16,32,64,128,256,512,1024}
1 {3,6,12,24,48,96,192,384,768}
2 {5,10,20,40,80,160,320,640}
3 {7,14,28,56,112,224,448,896}
4 {9,18,36,72,144,288,576}
5 {11,22,44,88,176,352,704}
6 {13,26,52,104,208,416,832}
7 {15,30,60,120,240,480,960}
本实例中，奇偶校验矩阵集合P1中至少包括表3所示的其中1个奇偶校验矩阵；或者，奇偶校验矩阵集合P1中至少包括表11所示的其中1个奇偶校验矩阵的子矩阵，例如表11所述的1个奇偶校验矩阵的最前mb行和最前mb+16列构成的子矩阵，mb是大于3的整数，mb等于4、6、8、10、或者18。
表2为一示例中提供的奇偶校验矩阵集合P1的基矩阵中元素等于1的位置以及元素值，其中，元素等于1的位置通过行索引(i)和列索引(j)表示，元素等于1的位置对应于指示单位阵循环移位元素的位置，并且定义了在相应的奇偶校验矩阵中该位置的元素值(V i,j)，即循环移位的位数；P1的基矩阵H BG1中，其他行索引或列索引的位置(即表2中没有定义的位置)所对应元素值等于“0”，即对应于指示全零方阵的位置。表2中，每个提升值子集合索引i LS分别对应于一个第一奇偶校验矩阵。以i LS＝0为例，表2中，i LS＝0所在的列中所有定义出的位置(i,j)对应于单位阵循环移位，其他没有定义的位置对应于全零方阵，这些单位阵循环移位和全零方阵共同构成i LS＝0对应的第一奇偶校验矩阵，i LS等于0至7共对应于8个第一奇偶校验矩阵，其中的一个或多个奇偶校验矩阵构成奇偶校验矩阵集合P1。奇偶校验矩阵集合P1所支持的最大信息长度为8448，基矩阵的维数为46行68列，从而mb1＝46，nb1＝68，kb1＝22。
奇偶校验矩阵集合P1至少包括如表2中的1个第一奇偶校验矩阵。
表2奇偶校验矩阵集合P1的基矩阵中元素等于1的位置以及元素值
Figure PCTCN2021139513-appb-000025
Figure PCTCN2021139513-appb-000026
Figure PCTCN2021139513-appb-000027
Figure PCTCN2021139513-appb-000028
Figure PCTCN2021139513-appb-000029
在一示例中，奇偶校验矩阵集合P1包括如表2中的8个第一奇偶校验矩阵，即索引为i LS等于0至7。奇偶校验矩阵集合P1的第i LS个提升值子集合对应于表1中第i LS个提升值子集合中小于或等于384的所有提升值构成的集合。表2和表1中的索引i LS是同一个，即第0个第一奇偶校验矩阵对应的提升值子集合为{2,4,8,16,32,64,128,256}，第1个第一奇偶校验矩阵对应的提升值子集合为{3,6,12,24,48,96,192,384}，第2个第一奇偶校验矩阵对应的提升值子集合为{5,10,20,40,80,160,320}，第3个第一奇偶校验矩阵对应的提升值子集合为{7,14,28,56,112,224}，第4个第一奇偶校验矩阵对应的提升值子集合为{9,18,36,72,144,288}，第5个第一奇偶校验矩阵对应的提升值子集合为{11,22,44,88,176,352}，第6个第一奇偶校验矩阵对应的提升值子集合为{13,26,52,104,208}，第7个第一奇偶校验矩阵对应的提升值子集合为{15,30,60,120,240}。即，奇偶校验矩阵集合P1所支持的最大提升值为Zmax1＝384。奇偶校验矩阵集合P1支持的所有提升值构成集合为Zset1＝{2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,18,20,22,24,26,28,30,32,36,40,44,48,52,56,60,64,72,80,88,96,104,112,120,128,144,160,176,192,208,224,240,256,288,320,352,384}。
奇偶校验矩阵集合P2包括a2个第二奇偶校验矩阵，所对应的提升值子集合至少包括表1中的1个提升值子集合。
在一示例中，奇偶校验矩阵集合P2包括a2＝8个第二奇偶校验矩阵，8个第二奇偶校验矩阵所对应的提升值子集合分别为表1中的8个提升值子集合。奇 偶校验矩阵集合P2的第i LS个第二奇偶校验矩阵所支持的提升值子集合对应于表1中第i LS个提升值子集合，即分别对应为：第0个第二奇偶校验矩阵对应的提升值子集合为{2,4,8,16,32,64,128,256,512,1024}，第1个第二奇偶校验矩阵对应的提升值子集合为{3,6,12,24,48,96,192,384,768}，第2个第二奇偶校验矩阵对应的提升值子集合为{5,10,20,40,80,160,320,640}，第3个第二奇偶校验矩阵对应的提升值子集合为{7,14,28,56,112,224,448,896}，第4个第二奇偶校验矩阵对应的提升值子集合为{9,18,36,72,144,288,576}，第5个第二奇偶校验矩阵对应的提升值子集合为{11,22,44,88,176,352,704}，第6个第二奇偶校验矩阵对应的提升值子集合为{13,26,52,104,208,416,832}，第7个第二奇偶校验矩阵对应的提升值子集合为{15,30,60,120,240,480,960}。即，奇偶校验矩阵集合P2所支持的最大提升值为Zmax2＝1024，其等于256(奇偶校验矩阵集合P1所支持的第i LS＝0个提升值子集合中的最大提升值)的4倍。以及，奇偶校验矩阵集合P2所支持的提升值构成集合为Zset2＝{2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,18,20,22,24,26,28,30,32,36,40,44,48,52,56,60,64,72,80,88,96,104,112,120,128,144,160,176,192,208,224,240,256,288,320,352,384,416,448,480,512,576,640,704,768,832,896,960,1024}，可以看出，Zset1是Zset2的子集。
本实例中，行索引序列和列索引序列满足以下组合：行索引序列是不连续的升序整数集合；列索引序列的前kb2个元素是连续的升序整数。由于列索引序列的前kb2个元素是连续的升序整数，所以奇偶校验矩阵集合P2的LDPC译码器中，变量节点更新模块(对应于奇偶校验矩阵中某一列的更新)完全兼容奇偶校验矩阵集合P1的LDPC译码器的变量节点更新；而行索引序列是不连续的升序整数集合可以保证LDPC码具有优秀的译码性能。
在一示例中，列索引序列的前kb2个元素为由0至kb2-1的所有整数构成的集合，如{0,1,2,...,(kb2-2),(kb2-1)}，其中kb2是大于1的整数，kb2是奇偶校验矩阵集合P2的基矩阵的系统列数(系统列数等于基矩阵列数与基矩阵行数的差值)。例如，行索引序列α为集合[0,1,2,3,4,5,6,7,8,10,11,12,13,19,20,24,25,26,27,29,30,31,32,33,34,35,36,37,38,39,41,42,44,45]的一个子集。
在一示例中，行索引序列α＝[0,1,2,3,4,5,6,7,8,10,11,12,13,19,20,24,25,26,27,29,30,31,32,33,34,35,36,37,38,39,41,42,44,45]。以及，列索引序列β＝[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,22,23,24,25,26,27,28,29,30,32,33,34,35,41,42,46,47,48,49,51,52,53,54,55,56,57,58,59,60,61,63,64,66,67]。即，行索引序列α的长度等于mb2＝34，列索引序列β的长度等于nb2＝50。即由行索引序列α、列索引序列β和奇偶校验矩阵集合P1的基矩阵所确定的奇偶校验矩阵集合P2的基矩阵是大小为mb2＝34行nb2＝50列的矩阵，系统列数 kb2＝16。
实例2
本实例中，行索引序列和列索引序列满足以下组合：行索引序列是连续的升序整数集合；列索引序列的前kb2个元素是不连续的升序整数集合。由于行索引序列是连续的升序整数集合，所以奇偶校验矩阵集合P2的LDPC译码器中，校验节点更新模块(对应于奇偶校验矩阵中某一行的更新)完全兼容奇偶校验矩阵集合P1的LDPC译码器的校验节点更新；而列索引序列的前kb2个元素是不连续的升序整数集合可以保证LDPC码译具有优秀的译码性能。本实例中P1的基矩阵中元素等于1的位置以及元素值可以与表2所定义的不同，表2仅为示例性的说明，在索引序列α或β不同的情况下，P1的基矩阵中元素等于1的位置以及元素值也可以不同。
在一示例中，行索引序列中包括mb2个元素，其为由0至(mb2-1)所构成的集合{0,1,2,...,(mb2-2),(mb2-1)}，其中mb2是大于1的整数，mb2为奇偶校验矩阵集合P2的基矩阵行数。行索引序列α为[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33]的一个子集。以及，列索引序列β的前kb2个元素是不连续的升序整数，列索引序列β的前kb2个元素构成的集合是[0,1,2,3,4,5,6,8,10,12,14,17,18,19,20,21]的一个子集。
在一示例中，行索引序列α＝[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33]；以及，列索引序列β＝[0,1,2,3,4,5,6,8,10,12,14,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55]。即，行索引序列α的长度等于mb＝34，列索引序列β的长度等于nb＝50。即由行索引序列α、列索引序列β和奇偶校验矩阵集合P1的基矩阵所确定的奇偶校验矩阵集合P2的基矩阵是大小为mb2＝34行nb2＝50列的矩阵，kb2＝16。
在一示例中，列索引序列β的前kb2个元素构成的集合是[0,1,2,3,4,5,6,8,10,11,13,14,16,17,19,21]的一个子集。对应的，奇偶校验矩阵集合P1包括索引i LS等于0至7所对应的第一奇偶校验矩阵中的至少一个。
在一示例中，列索引序列β＝[0,1,2,3,4,5,6,8,10,11,13,14,16,17,19,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55]。对应的，奇偶校验矩阵集合P1包括索引i LS等于0至7所对应的的8个第一奇偶校验矩阵。
在一示例中，列索引序列β的前kb2个元素构成的集合是[0,1,2,3,4,6,8,9, 10,13,14,16,17,19,20,21]的一个子集。对应的，奇偶校验矩阵集合P1包括索引i LS等于0至7所对应的第一奇偶校验矩阵中的至少一个。
在一示例中，列索引序列β＝[0,1,2,3,4,6,8,9,10,13,14,16,17,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55]。对应的，奇偶校验矩阵集合P1包括索引i LS等于0至7所对应的8个第一奇偶校验矩阵。
在一示例中，列索引序列β的前kb2个元素构成的集合是[0,1,2,3,4,6,7,8,9,11,13,16,17,18,19,21]的一个子集。对应的，奇偶校验矩阵集合P1包括索引i LS等于0至7所对应的第一奇偶校验矩阵中的至少一个。
在一示例中，列索引序列β＝[0,1,2,3,4,6,7,8,9,11,13,16,17,18,19,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55]。对应的，奇偶校验矩阵集合P1包括索引i LS等于0至7所对应的8个第一奇偶校验矩阵。
实例3
本实例中，行索引序列和列索引序列满足以下组合：行索引序列是不连续的升序整数集合；列索引序列的前kb2个元素是不连续的升序整数。由于行索引序列是不连续的升序整数集合以及列索引序列的前kb2个元素是不连续的升序整数，可以保证LDPC码译具有优秀的译码性能；并且由于奇偶校验矩阵集合P2的基矩阵依然是奇偶校验矩阵集合P1的基矩阵的一个子矩阵(即抽取矩阵)，所以在LDPC译码硬件上两者还是完全兼容，只是需要添加部分开关电路即可，开关电路用于使能或不使能部分路由电路以及对应的变量节点更新模块或校验节点更新模块电路。本实例中P1的基矩阵中元素等于1的位置以及元素值可以与表2所定义的不同，表2仅为示例性的说明，在索引序列α或β不同的情况下，P1的基矩阵中元素等于1的位置以及元素值也可以不同。
在一示例中，行索引序列α为[0,1,2,3,4,5,7,8,10,11,12,13,16,17,19,20,23,24,25,26,27,28,30,32,33,35,36,38,39,41,42,43,44,45]的一个子集。以及，列索引序列β的前kb2个元素是不连续的升序整数，列索引序列β的前kb2个元素构成的集合是[0,1,2,3,4,5,6,7,8,9,10,11,12,14,18,21]的一个子集。奇偶校验矩阵集合P1包括索引i LS等于0至7所对应的第一奇偶校验矩阵中的至少一个。
例如，行索引序列α＝[0,1,2,3,4,5,7,8,10,11,12,13,16,17,19,20,23,24,25,26,27,28,30,32,33,35,36,38,39,41,42,43,44,45]。列索引序列β＝[0,1,2,3,4,5,6,7,8,9,10,11,12,14,18,21,22,23,24,25,26,27,29,30,32,33,34,35, 38,39,41,42,45,46,47,48,49,50,52,54,55,57,58,60,61,63,64,65,66,67]。即，行索引序列α的长度等于mb＝34，列索引序列β的长度等于nb＝50。即由行索引序列α、列索引序列β和奇偶校验矩阵集合P1的基矩阵所确定的奇偶校验矩阵集合P2的基矩阵是大小为mb2＝34行nb2＝50列的矩阵，系统列数kb2＝16。本示例中，奇偶校验矩阵集合P1包括索引i LS等于0至7所对应的8个第一奇偶校验矩阵。
在一示例中，行索引序列α为[0,1,2,3,4,5,7,8,10,11,12,13,14,16,19,20,24,25,26,27,30,31,32,33,34,35,36,38,39,41,42,43,44,45]的一个子集。以及，列索引序列β的前kb2个元素是不连续的升序整数，列索引序列β的前kb2个元素构成的集合是[0,1,2,3,4,5,6,7,8,9,10,11,12,14,15,16]的一个子集。奇偶校验矩阵集合P1包括索引i LS等于0至7所对应的第一奇偶校验矩阵中的至少一个。
例如，行索引序列α＝[0,1,2,3,4,5,7,8,10,11,12,13,14,16,19,20,24,25,26,27,30,31,32,33,34,35,36,38,39,41,42,43,44,45]。列索引序列β＝[0,1,2,3,4,5,6,7,8,9,10,11,12,14,15,16,22,23,24,25,26,27,29,30,32,33,34,35,36,38,41,42,46,47,48,49,52,53,54,55,56,57,58,60,61,63,64,65,66,67]。即，行索引序列α的长度等于mb＝34，列索引序列β的长度等于nb＝50。即由行索引序列α、列索引序列β和奇偶校验矩阵集合P1的基矩阵所确定的奇偶校验矩阵集合P2的基矩阵是大小为mb2＝34行nb2＝50列的矩阵，系统列数kb2＝16。本示例中，奇偶校验矩阵集合P1包括索引i LS等于0至7所对应的8个第一奇偶校验矩阵。
实例4
本实例中，行索引序列和列索引序列满足以下组合：行索引序列是连续的升序整数集合；列索引序列的前kb2个元素是连续的升序整数。由于行索引序列是连续的升序整数集合，所以奇偶校验矩阵集合P2的LDPC译码器中，校验节点更新模块(对应于奇偶校验矩阵中某一行的更新)完全兼容奇偶校验矩阵集合P1的LDPC译码器的校验节点更新；而列索引序列的前kb2个元素是连续的升序整数，所以奇偶校验矩阵集合P2的LDPC译码器中，变量节点更新模块(对应于奇偶校验矩阵中某一列的更新)完全兼容奇偶校验矩阵集合P1的LDPC译码器的变量节点更新。本实例中P1的基矩阵中元素等于1的位置以及元素值可以与表2所定义的不同，表2仅为示例性的说明，在索引序列α或β不同的情况下，P1的基矩阵中元素等于1的位置以及元素值也可以不同。
在一示例中，行索引序列的mb2个元素为集合{0,1,2,...,(mb2-2),(mb2-1)}，其中mb2是大于1的整数。行索引序列α为集合[0,1,2,3,4,5,6,7,8,9,10,11,12, 13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33]的一个子集。以及，列索引序列β的前kb2个元素构成的集合为{0,1,2,...,(kb2-2),(kb2-1)}，其中kb2是大于1的整数。列索引序列β的前kb2个元素构成的集合[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15]的一个子集。奇偶校验矩阵集合P1包括索引i LS等于0至7所对应的第一奇偶校验矩阵中的至少一个。
例如，行索引序列α＝[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33]。以及，列索引序列β＝[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55]。即，行索引序列α的长度等于mb＝34，列索引序列β的长度等于nb＝50。即由行索引序列α、列索引序列β和奇偶校验矩阵集合P1的基矩阵所确定的奇偶校验矩阵集合P2的基矩阵是大小为mb2＝34行nb2＝50列的矩阵，系统列数kb2＝16。本示例中，奇偶校验矩阵集合P1包括索引i LS等于0至7所对应的8个第一奇偶校验矩阵。
实例5
本实例中，行索引序列满足：行索引序列中的元素是非升序整数，且行索引序列中的前M个元素是升序整数，M是大于1且小于mb2的整数。由于行索引序列是非升序整数，所以奇偶校验矩阵集合P2的基矩阵作为奇偶校验矩阵集合P1的基矩阵的一个子矩阵，则其可具有更低的错误平层性和瀑布区误块率(Block Error Rate，BLER)。本实例中奇偶校验矩阵集合P1的基矩阵中元素等于1的位置以及元素值可以与表2所定义的不同，表2仅为示例性的说明，在索引序列α或β不同的情况下，P1的基矩阵中元素等于1的位置以及元素值也可以不同。
在一示例中，行索引序列为集合[0,1,2,3,4,8,9,10,12,15,16,43,18,19,20,30,24,29,7,22,31,32,33,34,28,23,38,39,40,42,5,44,45,25]的一个子集。以及，列索引序列β的前kb2个元素构成的集合为[0,1,3,4,6,7,8,10,11,12,13,14,16,17,18,21]的一个子集。奇偶校验矩阵集合P1包括索引i LS等于0至7所对应的第一奇偶校验矩阵中的至少一个。
例如，行索引序列α＝[0,1,2,3,4,8,9,10,12,15,16,43,18,19,20,30,24,29,7,22,31,32,33,34,28,23,38,39,40,42,5,44,45,25]。以及，列索引序列β＝[0,1,3,4,6,7,8,10,11,12,13,14,16,17,18,21,22,23,24,25,26,30,31,32,34,37,38,65,40,41,42,52,46,51,29,44,53,54,55,56,50,45,60,61,62,64,27,66,67,47]。即，行索引序列α的长度等于mb＝34，列索引序列β的长度等于nb＝50。即由行索引序列α、列索引序列β和奇偶校验矩阵集合P1的基矩阵所确定的奇 偶校验矩阵集合P2的基矩阵是大小为mb2＝34行nb2＝50列的矩阵，系统列数kb2＝16。
本实例中，奇偶校验矩阵集合P1中至少包括表3所示的其中1个奇偶校验矩阵；或者，奇偶校验矩阵集合P1中至少包括表11所示的其中1个奇偶校验矩阵的子矩阵，例如表11所述的1个奇偶校验矩阵的最前mb行和最前mb+16列构成的子矩阵，mb是大于3的整数，mb等于4、6、8、10、或者18。依据行索引序列α、列索引序列β和奇偶校验矩阵集合P1的基矩阵所确定的奇偶校验矩阵集合P2的基矩阵，然后进行LDPC编码。
表3为另一示例提供的奇偶校验矩阵集合P1的基矩阵中元素等于1的位置以及元素值，其中，奇偶校验矩阵集合P1的基矩阵中元素等于1的位置通过行索引(i)和列索引(j)表示，元素等于1的位置对应于指示单位阵循环移位元素的位置，并且定义了在相应的奇偶校验矩阵中该位置的元素值(V i,j)，即循环移位的位数；P1的基矩阵中，表3中没有定义的索引或列索引位置所对应元素值等于“0”，即对应于指示全零方阵的位置。本示例中，奇偶校验矩阵集合P1至少包括表3中的1个奇偶校验矩阵。奇偶校验矩阵集合P2由奇偶校验矩阵集合P1、行索引序列α和列索引序列β确定。依据所述奇偶校验矩阵集合P2进行LDPC编码。
图3为一实施例提供的一种基于目标奇偶校验矩阵进行LDPC编码的仿真性能的示意图。如图3所示，横坐标为信噪比(Signal Noise Ratio，SNR)，单位为dB，纵坐标为BLER，对于奇偶校验矩阵集合P2，对应信息长度为16384，码率R包括{8/9,5/6,3/4,2/3,1/2,2/5,1/3}，可以看出，在不同码率的情况下，从第二奇偶校验矩阵集合中确定目标奇偶校验矩阵进行LDPC编码具有良好的性能，并且没有差错平层。
表3奇偶校验矩阵集合P1的基矩阵中元素等于1的位置以及元素值
Figure PCTCN2021139513-appb-000030
Figure PCTCN2021139513-appb-000031
Figure PCTCN2021139513-appb-000032
Figure PCTCN2021139513-appb-000033
Figure PCTCN2021139513-appb-000034
实例6
本实例中，行索引序列α是以下集合的一个子集或者等于以下集合：[0,1,2,3,4,7,8,15,9,12,6,13,19,18,22,43,29,31,30,40,32,25,10,42,23,5,36,38,41,28,34,16,20,35]；列索引序列β的前kb2个元素构成的集合是以下集合的一个子集或者等于以下集合：[0,1,3,4,7,8,10,11,12,13,14,16,17,18,19,21]。
或者，行索引序列α是以下集合的一个子集或者等于以下集合：[0,1,2,3,4,7,8,15,6,12,9,25,22,29,10,30,11,36,34,32,18,31,19,43,45,17,26,44,35,42,28,38,33,13]；列索引序列β的前kb2个元素构成的集合是以下集合的一个子集或者等于以下集合：[0,1,3,4,6,7,10,11,12,13,14,15,16,17,18,21]。
或者，行索引序列α是以下集合的一个子集或者等于以下集合：[0,1,2,3,4,7,8,15,6,12,9,25,22,13,10,30,32,38,29,18,35,31,34,44,19,5,45,41,42,43,16,36,33,23]；列索引序列β的前kb2个元素构成的集合是以下集合的一个子集或者等于以下集合：[0,1,3,4,6,7,9,10,11,12,13,14,16,17,18,21]。
或者，行索引序列α是以下集合的一个子集或者等于以下集合：[0,1,2,3,7,19,8,15,9,12,29,18,22,31,38,43,30,5,39,13,41,20,24,34,33,28,23,16,44,21,42,32,10,6]；列索引序列β的前kb2个元素构成的集合是以下集合的一个子集或者等于以下集合：[0,1,3,6,7,10,11,12,13,14,16,17,18,19,20,21]。
或者，行索引序列α是以下集合的一个子集或者等于以下集合：[0,1,2,3,4,7,8,15,9,12,19,6,10,22,18,5,30,45,34,16,31,29,24,40,20,23,41,35,44,33,38,43,42,32]；列索引序列β的前kb2个元素构成的集合是以下集合的一个子集或者等于以下集合：[0,1,3,4,6,7,8,10,11,12,13,16,17,18,20,21]。
或者，行索引序列α是以下集合的一个子集或者等于以下集合：[0,1,2,3,4,7,8,15,9,12,6,19,22,25,29,32,30,13,21,18,43,34,33,14,23,17,10,45,28,42,38,41,20,36]；列索引序列β的前kb2个元素构成的集合是以下集合的一个子集或者等于以下集合：[0,1,3,4,6,7,10,11,12,13,14,16,17,18,20,21]。
或者，行索引序列α是以下集合的一个子集或者等于以下集合：[0,1,2,3,4,7,11,15,5,8,14,24,30,35,16,21,13,32,20,17,44,39,31,28,33,10,42,22,25,19,27,38,34,43]；列索引序列β的前kb2个元素构成的集合是以下集合的一个子集或者等于以下集合：[0,1,3,4,7,8,9,10,11,12,13,14,16,18,20,21]。
实例7
本实例中，奇偶校验矩阵集合P2所支持的最大提升值Zmax2包括以下之一：416、448、480、512、576、640、704、768、832、896、960、1024、1152、1280、1408、1536、1664、1792、1920或2048。由于奇偶校验矩阵集合P2所支持的最大提升值Zmax2较大，例如大于384，所以奇偶校验矩阵集合P2的译码器可以采用更大的译码并行度，所以其译码速度更快，对应的译码吞吐量更高。
表4为一示例中提供的奇偶校验矩阵集合P2所支持的提升值。如表4所示，其中，奇偶校验矩阵集合P2所支持的最大提升值为2048。
表4奇偶校验矩阵集合P2所支持的提升值
提升值子集合索引(i LS) P2所支持的提升值
0 {2,4,8,16,32,64,128,256,512,1024,2048}
1 {3,6,12,24,48,96,192,384,768,1536}
2 {5,10,20,40,80,160,320,640,1280}
3 {7,14,28,56,112,224,448,896,1792}
4 {9,18,36,72,144,288,576,1152}
5 {11,22,44,88,176,352,704,1408}
6 {13,26,52,104,208,416,832,1664}
7 {15,30,60,120,240,480,960,1920}
表5为另一示例中提供的奇偶校验矩阵集合P2所支持的提升值。如表5所示，其中，奇偶校验矩阵集合P2所支持的最大提升值为1920。
表5奇偶校验矩阵集合P2所支持的提升值
提升值子集合索引(i LS) P2所支持的提升值
0 {2,4,8,16,32,64,128,256,512,1024}
1 {3,6,12,24,48,96,192,384,768,1536}
2 {5,10,20,40,80,160,320,640,1280}
3 {7,14,28,56,112,224,448,896,1792}
4 {9,18,36,72,144,288,576,1152}
5 {11,22,44,88,176,352,704,1408}
6 {13,26,52,104,208,416,832,1664}
7 {15,30,60,120,240,480,960,1920}
表6为又一示例中提供的奇偶校验矩阵集合P2所支持的提升值。如表6所 示，其中，奇偶校验矩阵集合P2所支持的最大提升值为1664。
表6奇偶校验矩阵集合P2所支持的提升值
提升值子集合索引(i LS) P2所支持的提升值
0 {2,4,8,16,32,64,128,256,512,1024}
1 {3,6,12,24,48,96,192,384,768,1536}
2 {5,10,20,40,80,160,320,640,1280}
3 {7,14,28,56,112,224,448,896}
4 {9,18,36,72,144,288,576,1152}
5 {11,22,44,88,176,352,704,1408}
6 {13,26,52,104,208,416,832,1664}
7 {15,30,60,120,240,480,960}
实例8
本实例中，奇偶校验矩阵集合P2的基矩阵的系统列数为kb2，kb2等于12、14、16、18或20。其中，kb2的长度等于列索引序列的长度与行索引序列的长度的差值。以及，行索引序列的长度等于4、5、6、7、8、9、10、11、12、14、16、18、20、22、23、26、29、30、32、34、38或者42。
在一示例中，奇偶校验矩阵集合P2的基矩阵的系统列数为kb2等于20，则列索引序列β的前kb2个元素构成的集合β0＝[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19]。行索引序列的长度等于42、32、22、12、9、6或5。例如，行索引序列的长度等于22，行索引序列α＝[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21]；行索引序列的长度等于12，行索引序列α＝[0,1,2,3,4,5,6,7,8,9,10,11]；行索引序列的长度等于6，行索引序列α＝[0,1,2,3,4,5]；行索引序列的长度等于5，行索引序列α＝[0,1,2,3,4]。奇偶校验矩阵集合P2所支持的最大信息长度为Kmax2，其中，Kmax2等于20480。
在一示例中，奇偶校验矩阵集合P2的基矩阵的系统列数为kb2等于18，则列索引序列β的前kb2个元素构成的集合β0＝[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17]。行索引序列的长度等于38、29、20、11、8、6或5。例如，行索引序列的长度等于29，行索引序列α＝[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28]；行索引序列的长度等于11，行索引序列α＝[0,1,2,3,4,5,6,7,8,9,10]；行索引序列的长度等于5，行索引序列α＝[0,1,2,3,4]。奇偶校验矩阵集合P2所支持的最大信息长度为Kmax2，其中，Kmax2等于18432。
在一示例中，奇偶校验矩阵集合P2的基矩阵的系统列数为kb2等于16，则列索引序列β的前kb2个元素构成的集合β0＝[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15]。行索引序列的长度等于34、26、18、10、8、6或4。例如，行索引 序列包括以下至少之一：1)行索引序列的长度等于26，行索引序列α＝[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25]；2)行索引序列的长度等于18，行索引序列α＝[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17]；3)行索引序列的长度等于10，行索引序列α＝[0,1,2,3,4,5,6,7,8,9]；4)行索引序列的长度等于8，行索引序列α＝[0,1,2,3,4,5,6,7]；5)行索引序列的长度等于6，行索引序列α＝[0,1,2,3,4,5]；6)行索引序列的长度等于4，行索引序列α＝[0,1,2,3]。奇偶校验矩阵集合P2所支持的最大信息长度为Kmax2，其中，Kmax2等于16384。
在一示例中，奇偶校验矩阵集合P2的基矩阵的系统列数为kb2等于14，则列索引序列β的前kb2个元素构成的集合β0＝[0,1,2,3,4,5,6,7,8,9,10,11,12,13]。行索引序列的长度等于30、23、16、9、7、5或4。例如，行索引序列包括以下至少之一：1)行索引序列的长度等于30，行索引序列α＝[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29]；2)行索引序列的长度等于23，行索引序列α＝[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22]；3)行索引序列的长度等于16，行索引序列α＝[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15]；4)行索引序列的长度等于9，行索引序列α＝[0,1,2,3,4,5,6,7,8]；5)行索引序列的长度等于7，行索引序列α＝[0,1,2,3,4,5,6]；6)行索引序列的长度等于5，行索引序列α＝[0,1,2,3,4]；7)行索引序列的长度等于4，行索引序列α＝[0,1,2,3]。奇偶校验矩阵集合P2所支持的最大信息长度为Kmax2，其中，Kmax2等于14336。
在一示例中，列索引序列β等于集合β0和α中每个元素加上22后获得的集合的并集，即β＝{β0,α+22}。
实例9
本实例中，只需要依据行索引序列α和奇偶校验矩阵集合P1的基矩阵确定奇偶校验矩阵集合P2的基矩阵。其中，确定奇偶校验矩阵集合P2的基矩阵过程包括如下2个公式：
H' BG＝H BG1(α,:)
H BG2＝H' BG(:,[0～(kb2-1),22+α])
本实例中，H BG1是奇偶校验矩阵集合P1的基矩阵；H BG2是奇偶校验矩阵集合P2的基矩阵；H BG1(α,:)表示将矩阵H BG1中行索引为α的所有行取出并构成新的矩阵；类似的，H' BG(:,x)表示将矩阵H' BG中列索引为x的所有列取出并构成新的矩阵。即奇偶校验矩阵集合P2的基矩阵H BG2是奇偶校验矩阵集合P1的基矩阵H BG1的子矩阵(或抽取矩阵)。其中，0～(kb2-1)表示0到kb2-1的所有整数构成的集 合，22+α表示集合α中所有元素分别与22相加后构成的集合，[0～(kb2-1),22+α]表示0到kb2-1的所有整数构成集合和集合α中所有元素分别与22相加后构成集合的并集。行索引序列α＝[0,1,2,3,4,5,6,7,8,10,11,12,13,19,20,24,25,26,27,29,30,31,32,33,34,35,36,37,38,39,41,42,44,45]。可以看出，相当于列索引序列β等于0到kb2-1所构成集合，其中kb2等于12、14、15、16、17、18、19、或20。
实例10
本实例中，只需要依据行索引序列β和奇偶校验矩阵集合P1的基矩阵确定奇偶校验矩阵集合P2的基矩阵。其中，确定奇偶校验矩阵集合P2的基矩阵过程包括如下2个公式：
H' BG＝H BG1([0～mb2-1],:)；H BG2＝H' BG(:,β)
本实例中，H BG1是奇偶校验矩阵集合P1的基矩阵；H BG2是奇偶校验矩阵集合P2的基矩阵；H BG1(x,:)表示将矩阵H BG1中行索引为x的所有行取出并构成新的矩阵；类似的，H' BG(:,x)表示将矩阵H' BG中列索引为x的所有列取出并构成新的矩阵。即奇偶校验矩阵集合P2的基矩阵H BG2是奇偶校验矩阵集合P1的基矩阵H BG1H BG1的子矩阵(或抽取矩阵)。其中，[0～mb2-1]表示大于或等于0、且小于或等于mb2-1的所有整数构成的集合。列索引序列β＝[0,1,2,3,4,5,6,8,10,12,14,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55]，mb2等于34。
实例11
本实例中，存在G个提升值子集合，其中提升值子集合索引分别为0、1、...、(G-1)，G是大于1的整数，任意2个提升值子集合之间无交集。奇偶校验矩阵集合P1所支持的提升值子集合索引构成集合Set1；奇偶校验矩阵集合P2所支持的提升值子集合索引构成集合Set2。Set2和Set1的交集为空集。
奇偶校验矩阵集合P1所支持的提升值子集合索引为：i LS＝0至7，即对应支持的所有提升值子集合索引构成集合为Set1＝{0,1,2,3,4,5,6,7}。奇偶校验矩阵集合P2所支持的提升值子集合至少包括以下特性的1个提升值子集合：1个提升值子集合的所有提升值满足a·2 b，其中a是大于15的奇数，b是一个非负整数集合。
在一示例中，a等于17、19、21、23、25、27、29、31、33、35、37、39或者41；b等于0至B所构成的集合，其中B等于2、3、4、5、6、7、8、9或10。
表7为一示例中提供的奇偶校验矩阵集合P1所支持的提升值子集合。如表 7所示，G等于12，即有12个提升值子集合。奇偶校验矩阵集合P1所支持的提升值子集合包括i LS＝0至7对应的8个提升值子集合(Set1＝{0,1,2,3,4,5,6,7})，奇偶校验矩阵集合P2所支持的提升值子集合包括i LS＝8至11的4个提升值子集合(Set2＝{8,9,10,11})，其中，Set2和Set1的交集为空集。
表7奇偶校验矩阵集合P1所支持的提升值子集合
提升值子集合索引i LS 提升值
0 {2,4,8,16,32,64,128,256}
1 {3,6,12,24,48,96,192,384}
2 {5,10,20,40,80,160,320}
3 {7,14,28,56,112,224}
4 {9,18,36,72,144,288}
5 {11,22,44,88,176,352}
6 {13,26,52,104,208}
7 {15,30,60,120,240}
8 {17,34,68,136,272,544,1088}
9 {19,38,76,152,304,608}
10 {21,42,84,168,336,672}
11 {23,46,92,184,368,736}
实例12
本实例中，存在G个提升值子集合，其中提升值子集合索引分别为0、1、...、(G-1)，G是大于1的整数，任意2个提升值子集合之间无交集。奇偶校验矩阵集合P1所支持的提升值子集合索引构成集合Set1；奇偶校验矩阵集合P2所支持的提升值子集合索引构成集合Set2。Set2是Set1的一个子集，Set2的长度小于Set1的长度。
在一示例中，Set1＝{0,1,2,3,4,5,6,7}。
表8为另一示例中提供的奇偶校验矩阵集合P1所支持的提升值子集合。如表8所示，奇偶校验矩阵集合P1支持所有小于或等于384的所有提升值构成的集合，对应索引为i LS等于Set1中的整数，即等于0至7。即，奇偶校验矩阵集合P1所支持的提升值构成集合为Zset1＝{2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,18,20,22,24,26,28,30,32,36,40,44,48,52,56,60,64,72,80,88,96,104,112,120,128,144,160,176,192,208,224,240,256,288,320,352,384}。
表8奇偶校验矩阵集合P1所支持的提升值子集合
提升值子集合索引i LS 提升值
0 {2,4,8,16,32,64,128,256,512,1024}
1 {3,6,12,24,48,96,192,384,768}
2 {5,10,20,40,80,160,320,640}
3 {7,14,28,56,112,224,448,896}
4 {9,18,36,72,144,288}
5 {11,22,44,88,176,352}
6 {13,26,52,104,208}
7 {15,30,60,120,240}
奇偶校验矩阵集合P2支持的提升值子集合索引为i LS等于0至3，即Set2＝{0、1、2、3}。其中包括奇偶校验矩阵集合P2支持的提升值包括以下之一：
1)奇偶校验矩阵集合P2支持索引i LS等于Set2＝{0、1、2、3}的提升值子集合中所有大于384的提升值，即支持的提升值等于{448,512,640,768,896,1024}。即，奇偶校验矩阵集合P2所支持的所有提升值构成集合为Zset2＝{448,512,640,768,896,1024}，Zset1和Zset2无交集。
2)奇偶校验矩阵集合P2支持索引i LS等于Set2＝{0、1、2、3}的提升值子集合中所有提升值，即，奇偶校验矩阵集合P2所支持的所有提升值构成集合为Zset2＝{2,3,4,5,6,7,8,10,12,14,16,20,24,28,32,40,48,56,64,80,96,112,128,160,192,224,256,320,384,448,512,640,768,896,1024}。即Zset1和Zset2的交集为Zset等于{2,3,4,5,6,7,8,10,12,14,16,20,24,28,32,40,48,56,64,80,96,112,128,160,192,224,256,320,384}，Zset的元素数目(29)小于Zset1的元素数目(51)，并且Zset的元素数目小于Zset2的元素数目(35)。
实例13
本实例中，奇偶校验矩阵集合P2中包括至少一个奇偶校验矩阵，该奇偶校验矩阵(是第二奇偶校验矩阵)中包括k0个上下相邻对{h i,j,h (i+1)mod mb,j}，上下相邻对中的2个元素都是指示单位阵循环移位的元素，mb是奇偶校验矩阵的行数。第一类上下相邻对是指满足以下关系式的上下相邻对(h i,k和h j,k)：mod(h i,k-h j,k,2)≤0，j＝(i+1)mod mb；第二类上下相邻对是指满足以下关系式的上下相邻对(h i,k和h j,k)：mod(h i,k-h j,k,2)>0，j＝(i+1)mod mb。其中，k0、k1和k2都是正整数，并且k1大于k2的3倍。
本实例中，奇偶校验矩阵集合P2中至少包括表9所示的其中1个奇偶校验矩阵；或者，奇偶校验矩阵集合P2中至少包括表9所示的其中1个奇偶校验矩阵的子矩阵，例如表9所示的1个奇偶校验矩阵的最前mb行和最前mb+16列构成的子矩阵，mb是大于3的整数，mb等于4、6、8、10、或者18。依据所述奇偶校验矩阵集合P2进行LDPC编码。
表9为一示例中提供的奇偶校验矩阵集合P2的基矩阵中元素等于1的位置以及元素值，其中，元素等于1的位置通过行索引(i)和列索引(j)表示，元素等于1的位置对应于指示单位阵循环移位元素的位置，并且定义了在相应的奇偶校验矩阵中该位置的元素值(V i,j)，即循环移位的位数；P2的基矩阵H BG1中，其他行索引或列索引的位置(即表9中没有定义的位置)所对应元素值等于“0”，即对应于指示全零方阵的位置。其中包括8个奇偶校验矩阵，其中：
第0个奇偶校验矩阵具有k0＝57个上下相邻对，其中k1＝51个第一类型上下相邻对和k2＝6个第二类型上下相邻对；第1个奇偶校验矩阵具有k0＝57个上下相邻对，其中k1＝50个第一类型上下相邻对和k2＝7个第二类型上下相邻对；第2个奇偶校验矩阵具有k0＝57个上下相邻对，其中k1＝50个第一类型上下相邻对和k2＝7个第二类型上下相邻对；第3个奇偶校验矩阵具有k0＝57个上下相邻对，其中k1＝52个第一类型上下相邻对和k2＝2个第二类型上下相邻对；第4个奇偶校验矩阵具有k0＝57个上下相邻对，其中k1＝53个第一类型上下相邻对和k2＝4个第二类型上下相邻对；第5个奇偶校验矩阵具有k0＝57个上下相邻对，其中k1＝52个第一类型上下相邻对和k2＝5个第二类型上下相邻对；第6个奇偶校验矩阵具有k0＝57个上下相邻对，其中k1＝50个第一类型上下相邻对和k2＝7个第二类型上下相邻对；第7个奇偶校验矩阵具有k0＝57个上下相邻对，其中k1＝51个第一类型上下相邻对和k2＝6个第二类型上下相邻对。
其中一种示例，k1大于k2的5倍。
本实例中，奇偶校验矩阵集合P2中包括如表9中所示的索引i LS等于0至7所对应的第二奇偶校验矩阵中的至少一个。
表9奇偶校验矩阵集合P2的基矩阵中元素等于1的位置以及元素值
Figure PCTCN2021139513-appb-000035
Figure PCTCN2021139513-appb-000036
Figure PCTCN2021139513-appb-000037
Figure PCTCN2021139513-appb-000038
实例14
本实例中，奇偶校验矩阵集合P2中包括至少一个奇偶校验矩阵，该奇偶校验矩阵(是第二奇偶校验矩阵)满足：该奇偶校验矩阵中包括k3个指示单位阵循环移位的第一类元素和k4个指示单位阵循环移位的第二类元素，其中指示单位阵循环移位的第一类元素满足以下关系：mod(h i,j,2)≤0，指示单位阵循环移位的第二类元素满足以下关系：mod(h i,j,2)>0，其中，h i,j是奇偶校验矩阵中横坐标为i且列坐标为j的指示单位阵循环移位的元素。其中，k3和k4都是正整数，并且k3大于k4的3倍。
本实例中P2的基矩阵中元素等于1的位置以及元素值可以与表9所定义的不同，表9仅为示例性的说明，在索引序列α或β不同的情况下，P2的基矩阵中元素等于1的位置以及元素值也可以不同。
实例15
本实施例中，根据目标基矩阵H BG确定目标奇偶校验矩阵。
LDPC编码的输入信息比特序列(即待传输数据)表示为c 0,c 1,c 2,c 3,...,c K-1，其长度为K比特。LDPC编码后获得的编码后比特序列表示为d 0,d 1,d 2,...,d N-1，其长度为N比特。对输入信息比特序列进行LDPC编码，包括以下步骤：
步骤1，确定提升值子集合索引i LS。每个索引i LS定义一个提升值子集合。其中包含目标提升值Z c的提升值子集合索引为i LS。
步骤2，将输入信息比特序列c 0,c 1,c 2,c 3,...,c K-1中第2·Z c比特至第K-1比特存入编码后比特序列d 0,d 1,d 2,...,d N-1中。
步骤3，产生N+2Z c-K个校验比特
Figure PCTCN2021139513-appb-000039
且满足
Figure PCTCN2021139513-appb-000040
其中c＝[c 0,c 1,c 2,...,c K-1] T。其中所满足的关系式中的0是指全零向量，并且LDPC编码操作都在2元伽罗华域(GF(2))上进行。目标奇偶校验矩阵Hb属于奇偶校验矩阵集合P2，相应的，目标基矩阵H BG属于奇偶校验矩阵集合P2的基矩阵。
校验矩阵H的确定过程包括：
将目标基矩阵H BG中的所有“0”元素置换成全零方阵，全零方阵的大小都是Z c×Z c。将目标基矩阵H BG中的所有“1”元素置换成单位阵循环移位后的矩阵I(P i,j)，单位阵的大小为Z c×Z c，其中i和j分别是基矩阵H BG的行索引和列索引。 I(P i,j)表示将一个大小为Z c×Z c的单位阵进行右循环移位P i,j后获得的矩阵。P i,j＝mod(V i,j,Z c)，其中V i,j是奇偶校验矩阵集合P1中第i LS个奇偶校验矩阵中的第i行第j列元素，索引i LS是奇偶校验矩阵集合P1中的奇偶校验矩阵索引。
步骤4，将产生的N+2Z c-K个校验比特
Figure PCTCN2021139513-appb-000041
存入编码后比特序列d 0,d 1,d 2,...,d N-1中。
在标准版本为Release 15中，奇偶校验矩阵集合P1中包括8个第一奇偶校验矩阵，第一奇偶校验矩阵的索引i LS等于0至7。其中第i LS个奇偶校验矩阵支持的最大提升值Z iLS，也就是，奇偶校验矩阵集合P1中第i LS＝0个奇偶校验矩阵支持的最大提升值Z 0＝256；第i LS＝1个奇偶校验矩阵支持的最大提升值Z 1＝384；第i LS＝2个奇偶校验矩阵支持的最大提升值Z 2＝320；第i LS＝3个奇偶校验矩阵支持的最大提升值Z 3＝224；第i LS＝4个奇偶校验矩阵支持的最大提升值Z 4＝288；第i LS＝5个奇偶校验矩阵支持的最大提升值Z 5＝352；第i LS＝6个奇偶校验矩阵支持的最大提升值Z 6＝208；第i LS＝7个奇偶校验矩阵支持的最大提升值Z 7＝240。
在标准版本为Release X中，存在1个奇偶校验矩阵集合P2，奇偶校验矩阵集合P2包括如下的至少一个第二奇偶校验矩阵：该第二奇偶校验矩阵对应的索引为i LS，满足
Figure PCTCN2021139513-appb-000042
其中V i,j是标准版本Release 15中奇偶校验矩阵集合P1中第i LS个奇偶校验矩阵的第i行第j列元素，V' i,j是标准版本Release X中奇偶校验矩阵集合P2中第i LS个奇偶校验矩阵的第i行第j列元素，V' i,j和V i,j都是指示单位阵循环移位的元素，以及至少存在1组V' i,j和V i,j满足V' i,j≠V i,j，第二奇偶校验矩阵索引i LS等于0至7的1个整数。其中，
Figure PCTCN2021139513-appb-000043
是在标准版本为Release15的奇偶校验矩阵集合P1中第i LS个奇偶校验矩阵所支持的最大提升值。
标准版本Release 15中的奇偶校验矩阵集合P1的基矩阵的维数为46行68列，奇偶校验矩阵集合P1中的8个第一奇偶校验矩阵索引i LS等于0至7(例如实例20中的表10所示的8个第一奇偶校验矩阵)。标准版本Release X中的奇偶校验矩阵集合P2中包括8个第二奇偶校验矩阵，第二奇偶校验矩阵索引i LS等于0至7。
本实例中P1的基矩阵中元素等于1的位置以及元素值例如为表2所示，也可以与表2所定义的不同；在索引序列α或β不同的情况下，P1的基矩阵中元素等于1的位置以及元素值也可以不同。
在一示例中，标准版本Release 15中的奇偶校验矩阵集合P1的基矩阵的维数为42行52列，奇偶校验矩阵集合P1中的8个第一奇偶校验矩阵，第一奇偶校验矩阵索引i LS等于0至7。标准版本Release X中奇偶校验矩阵集合P2中包括8个第二奇偶校验矩阵，第二奇偶校验矩阵索引i LS等于0至7。
实例16
本实例中，标准版本为Release X中，存在1个奇偶校验矩阵集合P2，奇偶校验矩阵集合P2的基矩阵是标准版本为Release 15中奇偶校验矩阵集合P1的基矩阵的一个子矩阵(抽取矩阵)。奇偶校验矩阵集合P2包括如下的至少一个第二奇偶校验矩阵：该第二奇偶校验矩阵对应的索引为i LS，满足mod(V' i,j-V a(i),b(j),Z iLS)＝0，其中V a(i),b(j)是标准版本Release 15中奇偶校验矩阵集合P1中第i LS个第二奇偶校验矩阵的第a(i)行第b(j)列元素，V' i,j是标准版本Release X中奇偶校验矩阵集合P2中第i LS个第二奇偶校验矩阵的第i行第j列元素，V' i,j和V a(i),b(j)都是指示单位阵循环移位的元素，以及至少存在1组V' i,j和V a(i),b(j)满足V' i,j≠V a(i),b(j)，第二奇偶校验矩阵的索引i LS等于0至7的1个整数，a是抽取的行索引序列，a的长度小于奇偶校验矩阵集合P1的基矩阵的行数，b是抽取的列索引序列，b的长度小于奇偶校验矩阵集合P1的基矩阵的列数。其中，Z iLS是在标准版本为Release 15的奇偶校验矩阵集合P1中第i LS个奇偶校验矩阵所支持的最大提升值。
标准版本Release 15中的奇偶校验矩阵集合P1的基矩阵的维数为46行68列，奇偶校验矩阵集合P1中包括8个第一奇偶校验矩阵(例如实例20中的表10所示的8个第一奇偶校验矩阵)，第一奇偶校验矩阵索引i LS等于0至7。标准版本Release X中，奇偶校验矩阵集合P2中包括8个第二奇偶校验矩阵PCM，第二奇偶校验矩阵索引i LS等于0至7。
在一示例中，a等于实例1～实例6中的1个行索引序列α，b等于实例1～实例6中的1个行索引序列β。
对于在一示例中，a等于{0,1,2,3,4,5,6,7,8,10,11,12,13,19,20,24,25,26,27,29,30,31,32,33,34,35,36,37,38,39,41,42,44,45}，b等于{0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,22,23,24,25,26,27,28,29,30,32,33,34,35,41,42,46,47,48,49,51,52,53,54,55,56,57,58,59,60,61,63,64,66,67}。即标准版本Release X中的奇偶校验矩阵集合P2的基矩阵的维数为34行50列。
实例17
本实例中，首先确定目标奇偶校验矩阵Hb，根据Hb和目标提升值对待传输数据进行低密度奇偶校验编码。
LDPC编码的输入信息比特序列(即待传输数据)表示为c 0,c 1,c 2,c 3,...,c K-1，其长度为K比特。LDPC编码后获得的编码后比特序列表示为d 0,d 1,d 2,...,d N-1，其长度为N比特。包括以下步骤：
步骤1，确定提升值子集合索引i LS。每个索引i LS定义一个提升值子集合。 其中包含提升值Z c的提升值子集合索引为i LS。
步骤2，将输入信息比特序列c 0,c 1,c 2,c 3,...,c K-1中第2·Z c比特至第K-1比特存入编码后比特序列d 0,d 1,d 2,...,d N-1中。
步骤3，依据行索引序列、列索引序列和奇偶校验矩阵集合P1确定奇偶校验矩阵集合P2的奇偶校验矩阵；依据奇偶校验矩阵集合P2的奇偶校验矩阵和提升值进行LDPC编码，获得编码后比特序列。产生N+2Z c-K个校验比特
Figure PCTCN2021139513-appb-000044
且满足
Figure PCTCN2021139513-appb-000045
其中c＝[c 0,c 1,c 2,...,c K-1] T。其中所满足的关系式中的0是指全零向量，并且LDPC编码操作都在2元伽罗华域(GF(2))上进行。
校验矩阵H的确定过程包括：
将奇偶校验矩阵中的所有“-1”(或NULL)元素置换成全零方阵，全零方阵的大小都是Z c×Z c；将奇偶校验矩阵中的所有非“-1”元素位置换成单位阵循环移位后的矩阵I(P i,j)，单位阵的大小为Z c×Z c，其中i和j分别是对应非“-1”元素位置的行索引和列索引。I(P i,j)表示将一个大小为Z c×Z c的单位阵进行右循环移位P i,j后获得的矩阵。P i,j＝mod(V i,j,Z c)，其中V i,j是奇偶校验矩阵中的第i行第j列元素。
步骤4，将产生的N+2Z c-K个校验比特
Figure PCTCN2021139513-appb-000046
存入编码后比特序列d 0,d 1,d 2,...,d N-1中。
本实施例中，存在1个奇偶检验矩阵集合P2和1个奇偶检验矩阵集合P1。其中，进行LDPC编码的奇偶校验矩阵来自于奇偶检验矩阵集合P2或奇偶检验矩阵集合P1。奇偶检验矩阵集合P1中包括a1个奇偶校验矩阵，其中a1＝8；奇偶检验矩阵集合P1中的所有a1个奇偶校验矩阵都具有相同的基矩阵。奇偶校验矩阵集合P1的基矩阵的行数为mb1和列数为nb1，其中mb1和nb1分别为46和68。
奇偶检验矩阵集合P2中包括a2个奇偶校验矩阵，其中a2＝8；奇偶检验矩阵集合P2中的所有a2个奇偶校验矩阵都具有相同的基矩阵。奇偶校验矩阵集合P2的基矩阵的行数为mb2和列数为nb2，其中mb2和nb2都是大于0的整数。
存在1个行索引序列和1个列索引序列。其中行索引序列的长度为mb2；列索引序列的长度等于nb2。在一示例中，mb2是小于mb1的正整数，nb2是小于nb1的正整数。
依据行索引序列α、列索引序列β和奇偶校验矩阵集合P1确定奇偶校验矩阵集合P2的奇偶校验矩阵，即确定LDPC编码的奇偶校验矩阵。其中，奇偶校 验矩阵集合P2的奇偶校验矩阵是在奇偶校验矩阵集合P1的奇偶校验矩阵中按照行索引序列中的元素依序选取对应的行和按照列索引序列中的元素依序选取对应的列后组成的子矩阵，包括：
Hb'＝Hb1(α,:)
Hb2＝Hb'(:,β)
或者，Hb'＝Hb1(:,β)
Hb2＝Hb'(α,:)
或者，Hb2＝Hb1(α,β)
其中，Hb1是奇偶校验矩阵集合P1的第i LS个奇偶校验矩阵，Hb2是奇偶校验矩阵集合P2的第i LS个奇偶校验矩阵。如上的编码过程中，如果采用奇偶校验矩阵集合P2中的第i LS个奇偶校验矩阵进行编码时，V i,j是第i LS个奇偶校验矩阵中的第i行第j列元素。
其中，行索引序列α为如实例1～实例6中的一个行索引序列，列索引序列β为如实例1～实例6中的一个列索引序列；P1的基矩阵中元素等于1的位置以及元素值例如为表2所示，也可以与表2所定义的不同；在索引序列α或β不同的情况下，P1的基矩阵中元素等于1的位置以及元素值也可以不同。
实例18
本实例中，首先确定奇偶校验矩阵集合P2的基矩阵，然后据此确定奇偶校验矩阵集合P2的目标奇偶校验矩阵。如下：
步骤1，确定提升值子集合索引i LS。
步骤2，将输入信息比特序列c 0,c 1,c 2,c 3,...,c K-1中第2·Z c比特至第K-1比特存入编码后比特序列d 0,d 1,d 2,...,d N-1中。
步骤3，确定奇偶校验矩阵集合P2的基矩阵；依据奇偶校验矩阵集合P2的基矩阵确定奇偶校验矩阵；依据奇偶校验矩阵和提升值进行LDPC编码，获得编码后比特序列。产生N+2Z c-K个校验比特
Figure PCTCN2021139513-appb-000047
且满足
Figure PCTCN2021139513-appb-000048
其中c＝[c 0,c 1,c 2,...,c K-1] T。其中所满足的关系式中的0是指全零向量，并且LDPC编码操作都在2元伽罗华域(GF(2))上进行。其中，矩阵H的确定为如下描述：
对于奇偶校验矩阵集合P1，其基矩阵H BG1包括mb1行，对应行索引为i＝0,1,2,...,(mb1-1)，包括nb1列，对应列索引为j＝0,1,2,...,(nb1-1)。对于奇偶校验矩阵集合P2，其基矩阵H BG2包括mb2行，对应行索引为i＝0,1,2,...,(mb2-1)，其包 括nb2列，对应列索引为j＝0,1,2,...,(nb2-1)。基矩阵中至少包括“0”和“1”两种元素。
奇偶校验矩阵集合P2的基矩阵由奇偶校验矩阵集合P1的基矩阵、行索引序列α和列索引序列β确定，如下公式：
H' BG＝H BG1(α,:)
H BG2＝H' BG(:,β)
或者，H" BG＝H BG1(:,β)
H BG2＝H" BG(α,:)
或者，H BG2＝H BG1(α,β)
其中，H BG1是奇偶校验矩阵集合P1的基矩阵；H BG2是奇偶校验矩阵集合P2的基矩阵；H BG1(α,:)表示将矩阵H BG1中行索引为α的所有行取出并构成新的矩阵；类似的，H' BG(:,β)表示将矩阵H' BG中列索引为β的所有列取出并构成新的矩阵。即奇偶校验矩阵集合P2的基矩阵是在奇偶校验矩阵集合P1的基矩阵中按照行索引序列中的元素依序选取对应的行和按照列索引序列中的元素依序选取对应的列后组成的子矩阵。
依据奇偶校验矩阵集合P2的基矩阵确定奇偶校验矩阵集合P2的奇偶校验矩阵Hb。如下3个过程：
1)将基矩阵H BG中的所有“0”元素置换成“-1”或“NULL”。
2)将基矩阵H BG中的所有“1”元素置换成V i,j，其中i和j分别是基矩阵H BG的行索引和列索引。对于奇偶校验矩阵集合P2，V i,j由奇偶校验矩阵索引i LS确定。对于奇偶校验矩阵集合P1，V i,j例如由实例20中表10和奇偶校验矩阵索引i LS确定。
3)基矩阵H BG中的所有元素都置换完成，即可获得第i LS个奇偶校验矩阵Hb。
获取矩阵H包括如下3个过程：
1)将奇偶校验矩阵Hb中的所有“-1”或“NULL”元素置换成全零方阵，全零方阵的大小都是Z c×Z c。
2)将奇偶校验矩阵Hb中的所有非“-1”元素置换成单位阵循环移位后的矩阵I(P i,j)，单位阵的大小为Z c×Z c，其中i和j分别是奇偶校验矩阵Hb的行索引和列索引。I(P i,j)表示将一个大小为Z c×Z c的单位阵进行右循环移位P i,j后获得的矩阵，P i,j＝mod(V i,j,Z c)，其中V i,j是奇偶校验矩阵Hb中的第i行第j列元素。
3)奇偶校验矩阵Hb中的所有元素都置换完成，即可获得矩阵H。即可进 行LDPC编码。
实例19
本实例中，从奇偶校验矩阵集合P1或奇偶校验矩阵集合P2中确定1个奇偶校验矩阵然后再进行LDPC编码的过程。如下：
步骤1，确定提升值子集合索引i LS。
步骤2，将输入信息比特序列c 0,c 1,c 2,c 3,...,c K-1中第2·Z c比特至第K-1比特存入编码后比特序列d 0,d 1,d 2,...,d N-1中。
步骤3，从奇偶校验矩阵集合P1或奇偶校验矩阵集合P2中确定确定1个奇偶校验矩阵；依据奇偶校验矩阵和提升值进行LDPC编码，获得编码后比特序列。产生N+2Z c-K个校验比特
Figure PCTCN2021139513-appb-000049
且满足
Figure PCTCN2021139513-appb-000050
其中c＝[c 0,c 1,c 2,...,c K-1] T。其中所满足的关系式中的0是指全零向量，并且LDPC编码操作都在2元伽罗华域(GF(2))上进行。其中，矩阵H的确定为如下描述：
对于奇偶校验矩阵集合P1，其基矩阵H BG包括mb1行，对应行索引为i＝0,1,2,...,(mb1-1)，包括nb1列，对应列索引为j＝0,1,2,...,(nb1-1)。对于奇偶校验矩阵集合P2，其基矩阵H BG包括mb2行，对应行索引为i＝0,1,2,...,(mb2-1)，其包括nb2列，对应列索引为j＝0,1,2,...,(nb2-1)。基矩阵H BG中至少包括“0”和“1”两种元素。
将基矩阵H BG中的所有元素置换成全零方阵或者单位阵循环移位后的矩阵，可以获得矩阵H。其中，全零方阵或者单位阵的维数都是Z c×Z c。
获取校验矩阵H包括：
1)将目标基矩阵H BG中的所有“0”元素置换成全零方阵，全零方阵的大小都是Z c×Z c。
2)将目标基矩阵H BG中的所有“1”元素置换成单位阵循环移位后的矩阵I(P i,j)，单位阵的大小为Z c×Z c，i和j分别是基矩阵H BG的行索引和列索引。I(P i,j)表示将一个大小为Z c×Z c的单位阵进行右循环移位P i,j后获得的矩阵，P i,j＝mod(V i,j,Z c)，其中V i,j是奇偶校验矩阵集合P1中第i LS个奇偶校验矩阵中的第i行第j列元素或者奇偶校验矩阵集合P2中第i LS个奇偶校验矩阵中的第i行第j列元素。
奇偶校验矩阵集合P2的基矩阵是奇偶校验矩阵集合P1的基矩阵的子矩阵(或抽取矩阵)，即奇偶校验矩阵集合P2的基矩阵等于奇偶校验矩阵集合P1的基矩阵中依据行索引序列a和列索引序列b进行抽取获得的子矩阵(或抽取矩阵)。a的长度小于奇偶校验矩阵集合P1的基矩阵的行数，b的长度小于奇偶校验矩阵集合P1的基矩阵的列数。
奇偶校验矩阵集合P1的基矩阵的维数为46行68列，奇偶校验矩阵集合P1中的8个第一奇偶校验矩阵如实例20表10所示，第一奇偶校验矩阵索引i LS等于0至7。奇偶校验矩阵集合P2中包括8个第二奇偶校验矩阵，第二奇偶校验矩阵索引i LS等于0至7。
在一示例中，a和b等于实例1～实例6中的其中1个行索引序列α和其中1个行索引序列β。
在一示例中，a等于{0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33}，b等于{0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,22,23,24,25,26,27,28,29,30,32,33,34,35,41,42,46,47,48,49,51,52,53,54,55,56,57,58,59,60,61,63,64,66,67}，奇偶校验矩阵集合P1的基矩阵的维数为34行50列。
实例20
本实例中，奇偶校验矩阵集合P1中包括索引i LS等于0至7所对应的8个奇偶校验矩阵。
表10为又一示例中提供的奇偶校验矩阵集合P1的基矩阵中元素等于1的位置以及元素值，其中，元素等于1的位置通过行索引(i)和列索引(j)表示，元素等于1的位置对应于指示单位阵循环移位元素的位置，并且定义了在相应的奇偶校验矩阵中该位置的元素值(V i,j)，即循环移位的位数；P1的基矩阵H BG1中，其他行索引或列索引的位置(即表10中没有定义的位置)所对应元素值等于“0”，即对应于指示全零方阵的位置。表10中，每个提升值子集合索引i LS分别对应于一个第一奇偶校验矩阵。
表10奇偶校验矩阵集合P1的基矩阵中元素等于1的位置以及元素值
Figure PCTCN2021139513-appb-000051
Figure PCTCN2021139513-appb-000052
Figure PCTCN2021139513-appb-000053
Figure PCTCN2021139513-appb-000054
Figure PCTCN2021139513-appb-000055
实例21
本实例中，奇偶校验矩阵集合P2中至少包括表11所示的其中1个奇偶校验矩阵；或者，奇偶校验矩阵集合P2中至少包括表11所示的其中1个奇偶校验矩阵的子矩阵，例如所述1个奇偶校验矩阵的最前mb行和最前mb+16列构成的子矩阵，mb是大于3的整数，其中mb等于4、6、8、10、或者18。依据所述奇偶校验矩阵集合P2进行LDPC编码。
表11为另一示例提供的奇偶校验矩阵集合P2的基矩阵中元素等于1的位置以及元素值，其中，元素等于1的位置通过行索引(i)和列索引(j)表示，元素等于1的位置对应于指示单位阵循环移位元素的位置，并且定义了在相应的奇偶校验矩阵中该位置的元素值(V i,j)，即循环移位的位数；表11中没有定义的行索引或列索引的位置所对应元素值等于“0”，即对应于指示全零方阵的位置。表11中，每个i LS分别对应于一个奇偶校验矩阵，i LS等于0、1、2、...、7。
表11所示的基矩阵是实例20中表10所示的基矩阵(第五代移动通信技术(5th Generation Mobile Communication Technology，5G)标准版本15或16中的基矩阵)的一个子矩阵(或抽取矩阵)，其中对应的行索引序列为：{0,1,2,3,4,8,9,10,12,15,16,43,18,19,20,30,24,29,7,22,31,32,33,34,28,23,38,39,40,42,5,44,45,25}，列索引序列为：{0,1,3,4,6,7,8,10,11,12,13,14,16,17,18,21,22,23,24,25,26,30,31,32,34,37,38,65,40,41,42,52,46,51,29,44,53,54,55,56,50,45,60,61,62,64,27,66,67,47}。最大提升值为1024。其中，从表11中确定目标奇偶校验矩阵进行LDPC编码的仿真性能如图3所示，对应信息长度为16384，码率包括{8/9,5/6,3/4,2/3,1/2,2/5,1/3}，可以看出，在不同码率的情况下，从第二奇偶校验矩阵集合中确定目标奇偶校验矩阵进行LDPC编码具有良好的性能，并且没有差错平层；并且其支持的最大提升值可以达到1024，LDPC译码并行度高，所以译码吞吐量大。
表11奇偶校验矩阵集合P2的基矩阵中元素等于1的位置以及元素值
Figure PCTCN2021139513-appb-000056
Figure PCTCN2021139513-appb-000057
Figure PCTCN2021139513-appb-000058
Figure PCTCN2021139513-appb-000059
实例22
本实例中，除了奇偶校验矩阵集合P1和奇偶校验矩阵集合P2，奇偶校验矩阵集合P2’也可以作为目标奇偶校验矩阵集合，其中，奇偶校验矩阵集合P2’包括8个奇偶校验矩阵，奇偶校验矩阵集合P2’所支持的最大信息长度为3840，基矩阵的维数为42行52列。在进行LDPC编码之前，至少由以下设定信息中的至少之一从3类奇偶校验矩阵集合{奇偶校验矩阵集合P1、奇偶校验矩阵集合P2和奇偶校验矩阵集合P2’}中确定LDPC编码的目标奇偶校验矩阵集合(或确定目标奇偶校验矩阵集合的索引)：传输块大小(TBS)、码率、高层信令、调制阶数、调制编码方案索引、MCS表。
在一示例中，依据传输块大小和码率确定目标奇偶校验矩阵集合的过程如下：
条件1：TBS小于或等于292，或者TBS小于或等于3824且码率小于或等于0.67，或者码率小于或等于0.25。
条件2：TBS大于或等于T0，T0是大于Kmax1的正整数。
条件3：码率大于或等于R0，R0是大于0且小于1的实数。
例如，如果条件1成立，则采用奇偶校验矩阵集合P2’作为目标奇偶校验矩阵集合进行LDPC编码；如果条件2成立，则采用奇偶校验矩阵集合P2作为目标奇偶校验矩阵集合进行LDPC编码；在其他情况下则采用奇偶校验矩阵集合P1作为目标奇偶校验矩阵集合进行LDPC编码。
又如，如果条件1成立，则采用奇偶校验矩阵集合P2’作为目标奇偶校验矩阵集合进行LDPC编码；如果条件3成立，则采用奇偶校验矩阵集合P2作为目标奇偶校验矩阵集合进行LDPC编码；在其他情况下则采用奇偶校验矩阵集合P1作为目标奇偶校验矩阵集合进行LDPC编码。
又如，如果条件1成立，则采用奇偶校验矩阵集合P2’作为目标奇偶校验矩阵集合进行LDPC编码；如果条件2成立并且条件3也成立，则采用奇偶校验矩阵集合P2作为目标奇偶校验矩阵集合进行LDPC编码；在其他情况下则采用奇偶校验矩阵集合P1作为目标奇偶校验矩阵集合进行LDPC编码。
在一示例中，T0等于Kmax2的X倍，其中X是大于或等于1的整数；R0等于1/2、2/3、3/4、5/6、6/7、7/8或者8/9，R0的数值可以采用四舍五入方法获得2位小数点的数值或者3位小数点的数值。X等于1、2、3、4、5、6、7、8或10。Kmax1是奇偶校验矩阵集合P1的最大信息长度，Kmax2是奇偶校验矩阵集合P2的最大信息长度。
在一示例中，依据高层信令、传输块大小、和码率确定奇偶校验矩阵集合(或确定目标奇偶校验矩阵集合的索引)的示例如下：若高层信令使能，则采用奇偶校验矩阵集合P2作为目标奇偶校验矩阵集合进行LDPC编码；否则如果上述的条件1成立，则采用奇偶校验矩阵集合P2’作为目标奇偶校验矩阵集合进行LDPC编码，否则采用奇偶校验矩阵集合P1作为目标奇偶校验矩阵集合进行LDPC编码。
在一示例中，依据调制阶数、传输块大小、和码率确定奇偶校验矩阵集合(或确定目标奇偶校验矩阵集合的索引)的示例如下：若调制阶数大于或等于参数Y，则采用奇偶校验矩阵集合P2作为目标奇偶校验矩阵集合进行LDPC编码；否则如果上述的条件1成立，则采用奇偶校验矩阵集合P2’作为目标奇偶校验矩阵集合进行LDPC编码，否则采用奇偶校验矩阵集合P1作为目标奇偶校验矩阵集合进行LDPC编码。其中参数Y等于以下之一：4、6、8、10、12、14。
在一示例中，依据调制编码方案索引、传输块大小、和码率确定奇偶校验矩阵集合(或确定目标奇偶校验矩阵集合的索引)的示例如下：若调制编码方案索引大于或等于参数I，则采用奇偶校验矩阵集合P2作为目标奇偶校验矩阵集合进行LDPC编码；否则如果上述的条件1成立，则采用奇偶校验矩阵集合P2’作为目标奇偶校验矩阵集合进行LDPC编码，否则采用奇偶校验矩阵集合P1作为目标奇偶校验矩阵集合进行LDPC编码。其中参数I等于15、18、20、21、22、23、24、25、26、27、28或者29；或者参数I等于所使用的MCS表格中最大调制阶数下的其中1个MCS索引。
在一示例中，依据MCS表确定奇偶校验矩阵集合(或确定目标奇偶校验矩 阵集合的索引)的示例如下：若MCS表为预设高速数据速率MCS表，则采用奇偶校验矩阵集合P2作为目标奇偶校验矩阵集合进行LDPC编码；否则如果上述的条件1成立，则采用奇偶校验矩阵集合P2’作为目标奇偶校验矩阵集合进行LDPC编码；否则采用奇偶校验矩阵集合P1作为目标奇偶校验矩阵集合作为目标奇偶校验矩阵集合进行LDPC编码。
在一示例中，依据MCS表和调制编码方案索引确定奇偶校验矩阵集合(或确定目标奇偶校验矩阵集合的索引)的示例如下：若MCS表为预设高速数据速率MCS表，并且调制编码方案索引大于或等于参数I，则采用奇偶校验矩阵集合P2作为目标奇偶校验矩阵集合进行LDPC编码；否则如果以上条件1成立，则采用奇偶校验矩阵集合P2’作为目标奇偶校验矩阵集合进行LDPC编码，否则采用奇偶校验矩阵集合P1作为目标奇偶校验矩阵集合进行LDPC编码。其中参数I等于10、15、18、20、21、22、23、24、25、26、27、28或者29；或者参数I等于所使用的MCS表格中最大调制阶数下的其中1个调制编码方案索引。
在一示例中，依据MCS表和调制阶数确定奇偶校验矩阵集合(或确定目标奇偶校验矩阵集合的索引)的示例如下：若MCS表为预设高速数据速率MCS表，并且调制阶数大于或等于参数Y，则采用奇偶校验矩阵集合P2作为目标奇偶校验矩阵集合进行LDPC编码；否则如果以上条件1成立，则采用奇偶校验矩阵集合P2’作为目标奇偶校验矩阵集合进行LDPC编码，否则采用奇偶校验矩阵集合P1作为目标奇偶校验矩阵集合进行LDPC编码。其中参数Y等于以下之一：6、8、10、12、14。
在一示例中，依据TBS确定奇偶校验矩阵集合(或确定目标奇偶校验矩阵集合的索引)的示例如下。至少依据以下条件之一确定：条件1：TBS小于或等于T1；条件2：TBS大于T1、且小于或等于T2；条件3：TBS大于T2。其中，T1是大于0的整数，T2是大于T1的整数。
例如，如果条件1成立，则采用奇偶校验矩阵集合P2’作为目标奇偶校验矩阵集合进行LDPC编码；如果条件2成立，则采用奇偶校验矩阵集合P1作为目标奇偶校验矩阵集合进行LDPC编码；在其他情况下(条件3成立)则采用奇偶校验矩阵集合P2作为目标奇偶校验矩阵集合进行LDPC编码。T1＝3824，T2＝8424；或者，T1＝1024，T2＝8424；或者，T1＝512，T2＝4096。
MCS表至少包括以下字段：调制编码方案索引、调制阶数和目标码率。其中，调制编码方案索引是大于或等于0且小于2 n的整数，其中n等于4、5或6。调制阶数是大于0的整数。目标码率是大于0且小于1的实数，目标码率可以采用x/1024的表示格式。
在本申请实施例中，还提供一种低密度奇偶校验译码方法，利用目标奇偶 校验矩阵进行译码，不仅可以提高数据传输的吞吐量以及LDPC码的译码并行度，而且支持灵活的码长和码率，提高译码灵活性。未在本实施例中详尽描述的技术细节可参见上述任意实施例。
图4为一实施例提供的一种低密度奇偶校验译码方法的流程图。如图4所示，本实施例提供的方法包括步骤310和步骤320。
在步骤310中，确定目标奇偶校验矩阵，所述目标奇偶校验矩阵属于第二奇偶校验矩阵集合，并且，所述第二奇偶校验矩阵集合的基矩阵从第一奇偶校验矩阵集合的基矩阵中抽取得到。
在步骤320中，根据所述目标奇偶校验矩阵和目标提升值对接收数据进行低密度奇偶校验译码。
在一实施例中，确定目标奇偶校验矩阵，包括：
根据第一奇偶校验矩阵集合确定第二奇偶校验矩阵集合的目标奇偶校验矩阵。
在一实施例中，确定目标奇偶校验矩阵，包括：
根据所述第一奇偶校验矩阵集合的基矩阵确定所述第二奇偶校验矩阵集合的基矩阵；根据所述第二奇偶校验矩阵集合的基矩阵确定所述第二奇偶校验矩阵集合的目标奇偶校验矩阵。
在一实施例中，所述第二奇偶校验矩阵集合的基矩阵按照行索引序列和列索引序列中的至少之一从第一奇偶校验矩阵集合的基矩阵中抽取得到。
在一实施例中，所述行索引序列满足以下之一：
所述行索引序列中的元素是连续的升序整数；所述行索引序列中的元素包括不连续的升序整数；所述行索引序列中的元素是非升序整数，且所述行索引序列中的前M个元素是连续的升序整数，M大于1；所述行索引序列中至少包括{0、1、2、3}。
在一实施例中，所述列索引序列满足以下之一：
所述列索引序列的前kb2个元素是连续的升序整数，kb2大于1；所述列索引序列的前kb2个元素包括不连续的升序整数，kb2大于1；所述列索引序列中至少包括{0、1}；所述列索引序列中至少包括{22、23、24、25}。
在一实施例中，kb2等于所述第二奇偶校验矩阵集合的基矩阵的系统列数，或者等于所述第二奇偶校验矩阵集合的基矩阵的列数与行数的差值，或者小于或等于所述第一奇偶校验矩阵集合中的奇偶校验矩阵的系统列数。
在一实施例中，所述第一奇偶校验矩阵集合中包括a1个第一奇偶校验矩阵，所述a1个第一奇偶校验矩阵的基矩阵相同；所述第二奇偶校验矩阵集合中包括a2个第二奇偶校验矩阵，所述a2个第二奇偶校验矩阵的基矩阵相同；所述第二奇偶校验矩阵集合的最大提升值Zmax2为所述第一奇偶校验矩阵集合中第i个第一奇偶校验矩阵所支持的最大提升值Zi的D倍，D为2的正整数次幂，i为小于a1的非负整数。
在一实施例中，所述第二奇偶校验矩阵集合的最大提升值Zmax2大于所述第一奇偶校验矩阵集合的最大提升值Zmax1。
在一实施例中，第二奇偶校验矩阵集合的最大提升值Zmax2为a·2 b，其中，a是大于15的奇数，b是正整数。
在一实施例中，所述目标提升值属于G个提升值子集合中的一个提升值子集合，其中，G大于1，G个提升值子集合中任意2个提升值子集合之间无交集。
在一实施例中，所述第一奇偶校验矩阵集合支持的提升值构成第一提升值集合Zset1，所述第二奇偶校验矩阵集合支持的提升值构成第二提升值集合Zset2；所述第一提升值集合Zset1和所述第二提升值集合Zset2满足以下之一：
所述第一提升值集合Zset1和所述第二提升值集合Zset2无交集；所述第一提升值集合Zset1是所述第二提升值集合Zset2的子集；所述第一提升值集合Zset1和所述第二提升值集合Zset2的交集Zset中的元素数量小于所述第一提升值集合Zset1中的元素数量，且小于所述第二提升值集合Zset2中的元素数量。
在一实施例中，所述第二奇偶校验矩阵集合支持的最小提升值大于所述第一奇偶校验矩阵集合支持的最大提升值；
所述第二奇偶校验矩阵集合支持的提升值包括以下至少之一：416、448、480、512、576、640、704、768、832、896、960、1024、1152、1280、1408、1536、1664、1792、1920、2048。
在一实施例中，所述第一奇偶校验矩阵集合支持的最大信息长度Kmax1小于所述第二奇偶校验矩阵集合支持的最大信息长度Kmax2。
在一实施例中，第二奇偶校验矩阵集合中包括至少一个奇偶校验矩阵，该奇偶校验矩阵中包括k0个上下相邻对，k0个上下相邻对中包括k1个第一类上下相邻对和k2个第二类上下相邻对，且k1大于3*k2，k1和k2都是大于0的整数；其中，所述上下相邻对是指该奇偶校验矩阵中任意两个指示单位阵循环移位且位于同一列中的相邻元素；所述第一类上下相邻对的两个元素的差值对2取余的结果等于0；所述第一类上下相邻对的两个元素的差值对2取余的结果大于0。
在一实施例中，第二奇偶校验矩阵集合中包括至少一个奇偶校验矩阵，该奇偶校验矩阵中包括k3个指示单位阵循环移位的第一类元素和k4个指示单位阵循环移位的第二类元素，且k3大于3*k4，k3和k4都是大于0的整数；其中，所述第一类元素对2取余的结果等于0；所述第二类元素对2取余的结果大于0。
在一实施例中，还包括：
步骤300：根据设定信息从至少两个奇偶校验矩阵集合中确定一个奇偶校验矩阵集合作为目标奇偶校验矩阵集合；其中，所述设定信息包括以下至少之一：传输块尺寸、码率、高层信令、调制阶数、调制编码方案索引、调制与编码策略MCS表索引。
在一实施例中，根据设定信息从至少两个奇偶校验矩阵集合中确定一个奇偶校验矩阵集合作为目标奇偶校验矩阵集合，包括：
在满足以下条件至少之一的情况下，将第二奇偶校验矩阵集合作为所述目标奇偶校验矩阵集合：
传输块尺寸大于或等于T0，T0为大于或等于所述第一奇偶校验矩阵集合支持的最大信息长度Kmax1的整数；码率大于或等于R0，R0为大于0且小于1的实数。
在本申请实施例中，还提供一种低密度奇偶校验译码方法，利用目标基矩阵进行编码，不仅可以提高数据传输的吞吐量以及LDPC码的译码并行度，而且支持灵活的码长和码率，提高编码灵活性。本实施例中未详细描述的技术细节，可参见上述任意实施例。
图5为另一实施例提供的一种低密度奇偶校验译码方法的流程图。如图5所示，本实施例提供的方法包括步骤410和步骤420。
在步骤410中，确定目标基矩阵，所述目标基矩阵为第二奇偶校验矩阵集合的基矩阵，并且，所述第二奇偶校验矩阵集合的基矩阵从第一奇偶校验矩阵集合的基矩阵中抽取得到。
在步骤420中，根据所述目标基矩阵和目标提升值对接收数据进行低密度奇偶校验译码。
在一实施例中，确定目标奇偶校验矩阵，包括：
根据第一奇偶校验矩阵集合确定第二奇偶校验矩阵集合的目标奇偶校验矩阵。
在一实施例中，确定目标奇偶校验矩阵，包括：
根据所述第一奇偶校验矩阵集合的基矩阵确定所述第二奇偶校验矩阵集合的基矩阵；根据所述第二奇偶校验矩阵集合的基矩阵确定所述第二奇偶校验矩阵集合的目标奇偶校验矩阵。
在一实施例中，所述第二奇偶校验矩阵集合的基矩阵按照行索引序列和列索引序列中的至少之一从第一奇偶校验矩阵集合的基矩阵中抽取得到。
在一实施例中，所述行索引序列满足以下之一：
所述行索引序列中的元素是连续的升序整数；所述行索引序列中的元素包括不连续的升序整数；所述行索引序列中的元素是非升序整数，且所述行索引序列中的前M个元素是连续的升序整数，M大于1；所述行索引序列中至少包括{0、1、2、3}。
在一实施例中，所述列索引序列满足以下之一：
所述列索引序列的前kb2个元素是连续的升序整数，kb2大于1；所述列索引序列的前kb2个元素包括不连续的升序整数，kb2大于1；所述列索引序列中至少包括{0、1}；所述列索引序列中至少包括{22、23、24、25}。
在一实施例中，kb2等于所述第二奇偶校验矩阵集合的基矩阵的系统列数，或者等于所述第二奇偶校验矩阵集合的基矩阵的列数与行数的差值，或者小于或等于所述第一奇偶校验矩阵集合中的奇偶校验矩阵的系统列数。
在一实施例中，所述第一奇偶校验矩阵集合中包括a1个第一奇偶校验矩阵，所述a1个第一奇偶校验矩阵的基矩阵相同；所述第二奇偶校验矩阵集合中包括a2个第二奇偶校验矩阵，所述a2个第二奇偶校验矩阵的基矩阵相同；所述第二奇偶校验矩阵集合的最大提升值Zmax2为所述第一奇偶校验矩阵集合中第i个第一奇偶校验矩阵所支持的最大提升值Zi的D倍，D为2的正整数次幂，i为小于a1的非负整数。
在一实施例中，所述第二奇偶校验矩阵集合的最大提升值Zmax2大于所述第一奇偶校验矩阵集合的最大提升值Zmax1。
在一实施例中，第二奇偶校验矩阵集合的最大提升值Zmax2为a·2 b，其中，a是大于15的奇数，b是正整数。
在一实施例中，所述目标提升值属于G个提升值子集合中的一个提升值子集合，其中，G大于1，G个提升值子集合中任意2个提升值子集合之间无交集。
在一实施例中，所述第一奇偶校验矩阵集合支持的提升值构成第一提升值集合Zset1，所述第二奇偶校验矩阵集合支持的提升值构成第二提升值集合Zset2；所述第一提升值集合Zset1和所述第二提升值集合Zset2满足以下之一：
所述第一提升值集合Zset1和所述第二提升值集合Zset2无交集；所述第一提升值集合Zset1是所述第二提升值集合Zset2的子集；所述第一提升值集合Zset1和所述第二提升值集合Zset2的交集Zset中的元素数量小于所述第一提升值集合Zset1中的元素数量，且小于所述第二提升值集合Zset2中的元素数量。
在一实施例中，所述第二奇偶校验矩阵集合支持的最小提升值大于所述第一奇偶校验矩阵集合支持的最大提升值；所述第二奇偶校验矩阵集合支持的提升值包括以下至少之一：416、448、480、512、576、640、704、768、832、896、960、1024、1152、1280、1408、1536、1664、1792、1920、2048。
在一实施例中，所述第一奇偶校验矩阵集合支持的最大信息长度Kmax1小于所述第二奇偶校验矩阵集合支持的最大信息长度Kmax2。
在一实施例中，第二奇偶校验矩阵集合中包括至少一个奇偶校验矩阵，该奇偶校验矩阵中包括k0个上下相邻对，k0个上下相邻对中包括k1个第一类上下相邻对和k2个第二类上下相邻对，且k1大于3*k2，k1和k2都是大于0的整数；其中，所述上下相邻对是指该奇偶校验矩阵中任意两个指示单位阵循环移位且位于同一列中的相邻元素；所述第一类上下相邻对的两个元素的差值对2取余的结果等于0；所述第一类上下相邻对的两个元素的差值对2取余的结果大于0。
在一实施例中，第二奇偶校验矩阵集合中包括至少一个奇偶校验矩阵，该奇偶校验矩阵中包括k3个指示单位阵循环移位的第一类元素和k4个指示单位阵循环移位的第二类元素，且k3大于3*k4，k3和k4都是大于0的整数；其中，所述第一类元素对2取余的结果等于0；所述第二类元素对2取余的结果大于0。
在一实施例中，还包括：
步骤400：根据设定信息从至少两个奇偶校验矩阵集合中确定一个奇偶校验矩阵集合作为目标奇偶校验矩阵集合；其中，所述设定信息包括以下至少之一：传输块尺寸、码率、高层信令、调制阶数、调制编码方案索引、调制与编码策略MCS表索引。
在一实施例中，根据设定信息从至少两个奇偶校验矩阵集合中确定一个奇偶校验矩阵集合作为目标奇偶校验矩阵集合，包括：
在满足以下条件至少之一的情况下，将第二奇偶校验矩阵集合作为所述目标奇偶校验矩阵集合：
传输块尺寸大于或等于T0，T0为大于或等于所述第一奇偶校验矩阵集合支持的最大信息长度Kmax1的整数；码率大于或等于R0，R0为大于0且小于1的实数。
本申请实施例还提供一种低密度奇偶校验编码装置。图6为一实施例提供的一种低密度奇偶校验编码装置的结构示意图。如图6所示，所述低密度奇偶校验编码装置包括：第一矩阵确定模块510和第一编码模块520。
第一矩阵确定模块510，设置为确定目标奇偶校验矩阵，所述目标奇偶校验矩阵属于第二奇偶校验矩阵集合，并且，所述第二奇偶校验矩阵集合的基矩阵从第一奇偶校验矩阵集合的基矩阵中抽取得到；第一编码模块520，设置为根据所述目标奇偶校验矩阵和目标提升值对待传输数据进行低密度奇偶校验编码。
本实施例的低密度奇偶校验编码装置，利用目标奇偶校验矩阵进行编码，不仅可以提高数据传输的吞吐量以及LDPC码的译码并行度，而且支持灵活的码长和码率，提高编码灵活性。
在一实施例中，第一矩阵确定模块510，设置为：
根据第一奇偶校验矩阵集合确定第二奇偶校验矩阵集合的目标奇偶校验矩阵。
在一实施例中，第一矩阵确定模块510，设置为：
根据所述第一奇偶校验矩阵集合的基矩阵确定所述第二奇偶校验矩阵集合的基矩阵；根据所述第二奇偶校验矩阵集合的基矩阵确定所述第二奇偶校验矩阵集合的目标奇偶校验矩阵。
在一实施例中，所述第二奇偶校验矩阵集合的基矩阵按照行索引序列和列索引序列中的至少之一从第一奇偶校验矩阵集合的基矩阵中抽取得到。
在一实施例中，所述行索引序列满足以下之一：
所述行索引序列中的元素是连续的升序整数；所述行索引序列中的元素包括不连续的升序整数；所述行索引序列中的元素是非升序整数，且所述行索引序列中的前M个元素是连续的升序整数，M大于1；所述行索引序列中至少包括{0、1、2、3}。
在一实施例中，所述列索引序列满足以下之一：
所述列索引序列的前kb2个元素是连续的升序整数，kb2大于1；所述列索引序列的前kb2个元素包括不连续的升序整数，kb2大于1；所述列索引序列中至少包括{0、1}；所述列索引序列中至少包括{22、23、24、25}。
在一实施例中，kb2等于所述第二奇偶校验矩阵集合的基矩阵的系统列数，或者等于所述第二奇偶校验矩阵集合的基矩阵的列数与行数的差值，或者小于或等于所述第一奇偶校验矩阵集合中的奇偶校验矩阵的系统列数。
在一实施例中，所述第一奇偶校验矩阵集合中包括a1个第一奇偶校验矩阵，所述a1个第一奇偶校验矩阵的基矩阵相同；所述第二奇偶校验矩阵集合中包括a2个第二奇偶校验矩阵，所述a2个第二奇偶校验矩阵的基矩阵相同；所述第二奇偶校验矩阵集合的最大提升值Zmax2为所述第一奇偶校验矩阵集合中第i个第一奇偶校验矩阵所支持的最大提升值Zi的D倍，D为2的正整数次幂，i为小于a1的非负整数。
在一实施例中，所述第二奇偶校验矩阵集合的最大提升值Zmax2大于所述第一奇偶校验矩阵集合的最大提升值Zmax1。
在一实施例中，所述第二奇偶校验矩阵集合的最大提升值Zmax2为a·2 b，其中，a是大于15的奇数，b是正整数。
在一实施例中，所述目标提升值属于G个提升值子集合中的一个提升值子集合，其中，G大于1，G个提升值子集合中任意2个提升值子集合之间无交集。
在一实施例中，所述第一奇偶校验矩阵集合支持的提升值构成第一提升值集合Zset1，所述第二奇偶校验矩阵集合支持的提升值构成第二提升值集合Zset2；所述第一提升值集合Zset1和所述第二提升值集合Zset2满足以下之一：
所述第一提升值集合Zset1和所述第二提升值集合Zset2无交集；所述第一提升值集合Zset1是所述第二提升值集合Zset2的子集；所述第一提升值集合Zset1和所述第二提升值集合Zset2的交集Zset中的元素数量小于所述第一提升值集合Zset1中的元素数量，且小于所述第二提升值集合Zset2中的元素数量。
在一实施例中，所述第二奇偶校验矩阵集合支持的最小提升值大于所述第一奇偶校验矩阵集合支持的最大提升值；所述第二奇偶校验矩阵集合支持的提升值包括以下至少之一：416、448、480、512、576、640、704、768、832、896、960、1024、1152、1280、1408、1536、1664、1792、1920、2048。
在一实施例中，所述第一奇偶校验矩阵集合支持的最大信息长度Kmax1小于所述第二奇偶校验矩阵集合支持的最大信息长度Kmax2。
在一实施例中，所述第二奇偶校验矩阵集合中包括至少一个奇偶校验矩阵，该奇偶校验矩阵中包括k0个上下相邻对，k0个上下相邻对中包括k1个第一类上下相邻对和k2个第二类上下相邻对，且k1大于3*k2，k1和k2都是大于0的整数；其中，所述上下相邻对是指该奇偶校验矩阵中任意两个指示单位阵循环移位且位于同一列中的相邻元素；所述第一类上下相邻对的两个元素的差值对2取余的结果等于0；所述第一类上下相邻对的两个元素的差值对2取余的结果大于0。
在一实施例中，所述第二奇偶校验矩阵集合中包括至少一个奇偶校验矩阵， 该奇偶校验矩阵中包括k3个指示单位阵循环移位的第一类元素和k4个指示单位阵循环移位的第二类元素，且k3大于3*k4，k3和k4都是大于0的整数；其中，所述第一类元素对2取余的结果等于0；所述第二类元素对2取余的结果大于0。
在一实施例中，还包括：
第一集合确定模块，设置为根据设定信息从至少两个奇偶校验矩阵集合中确定一个奇偶校验矩阵集合作为目标奇偶校验矩阵集合；其中，所述设定信息包括以下至少之一：传输块尺寸、码率、高层信令、调制阶数、调制编码方案索引、MCS表索引。
在一实施例中，第一集合确定模块，设置为：
在满足以下条件至少之一的情况下，将第二奇偶校验矩阵集合作为所述目标奇偶校验矩阵集合：
传输块尺寸大于或等于T0，T0为大于或等于所述第一奇偶校验矩阵集合支持的最大信息长度Kmax1的整数；码率大于或等于R0，R0为大于0且小于1的实数。
本实施例提出的低密度奇偶校验编码装置与上述实施例提出的低密度奇偶校验编码方法属于同一构思，未在本实施例中详尽描述的技术细节可参见上述任意实施例，并且本实施例具备与执行低密度奇偶校验编码方法相同的效果。
本申请实施例还提供一种低密度奇偶校验编码装置。图7为另一实施例提供的一种低密度奇偶校验编码装置的结构示意图。如图7所示，所述低密度奇偶校验编码装置包括：第二矩阵确定模块610和第二编码模块620。
第二矩阵确定模块610，设置为确定目标基矩阵，所述目标基矩阵为第二奇偶校验矩阵集合的基矩阵，并且，所述第二奇偶校验矩阵集合的基矩阵从第一奇偶校验矩阵集合的基矩阵中抽取得到；第二编码模块620，设置为根据所述目标基矩阵和目标提升值对待传输数据进行低密度奇偶校验编码。
本实施例的低密度奇偶校验编码装置，利用目标基矩阵进行编码，不仅可以提高数据传输的吞吐量以及LDPC码的译码并行度，而且支持灵活的码长和码率，提高编码灵活性。本实施例中未详细描述的技术细节，可参见上述任意实施例。
在一实施例中，第二编码模块620，设置为根据所述目标基矩阵和所述目标提升值确定校验矩阵H；基于所述校验矩阵H对待传输数据进行低密度奇偶校 验编码。
在一实施例中，第二编码模块620，设置为根据所述目标基矩阵确定目标奇偶校验矩阵；基于所述目标奇偶校验矩阵和所述目标提升值对待传输数据进行低密度奇偶校验编码。
在一实施例中，还包括：
第二集合确定模块，设置为根据设定信息从至少两个奇偶校验矩阵集合中确定一个奇偶校验矩阵集合作为目标奇偶校验矩阵集合；其中，所述设定信息包括以下至少之一：传输块尺寸、码率、高层信令、调制阶数、调制编码方案索引、MCS表索引。
本实施例提出的低密度奇偶校验编码装置与上述实施例提出的低密度奇偶校验编码方法属于同一构思，未在本实施例中详尽描述的技术细节可参见上述任意实施例，并且本实施例具备与执行低密度奇偶校验编码方法相同的效果。
本申请实施例还提供一种低密度奇偶校验译码装置。图8为一实施例提供的一种低密度奇偶校验译码装置的结构示意图。如图8所示，所述低密度奇偶校验译码装置包括：第三矩阵确定模块710和第一译码模块720。
第三矩阵确定模块710，设置为确定目标奇偶校验矩阵，所述目标奇偶校验矩阵属于第二奇偶校验矩阵集合，并且，所述第二奇偶校验矩阵集合的基矩阵从第一奇偶校验矩阵集合的基矩阵中抽取得到；第一译码模块720，设置为根据所述目标奇偶校验矩阵和目标提升值对接收数据进行低密度奇偶校验译码。
本实施例的低密度奇偶校验译码装置，利用目标奇偶校验矩阵进行编码，不仅可以提高数据传输的吞吐量以及LDPC码的译码并行度，而且支持灵活的码长和码率，提高编码灵活性。
在一实施例中，还包括：
第三集合确定模块，设置为根据设定信息从至少两个奇偶校验矩阵集合中确定一个奇偶校验矩阵集合作为目标奇偶校验矩阵集合；其中，所述设定信息包括以下至少之一：传输块尺寸、码率、高层信令、调制阶数、调制编码方案索引、MCS表索引。
在一实施例中，第三集合确定模块，设置为：
在满足以下条件至少之一的情况下，将第二奇偶校验矩阵集合作为所述目标奇偶校验矩阵集合：
传输块尺寸大于或等于T0，T0为大于或等于所述第一奇偶校验矩阵集合支 持的最大信息长度Kmax1的整数；码率大于或等于R0，R0为大于0且小于1的实数
本实施例提出的低密度奇偶校验译码装置与上述实施例提出的低密度奇偶校验译码方法属于同一构思，未在本实施例中详尽描述的技术细节可参见上述任意实施例，并且本实施例具备与执行低密度奇偶校验译码方法相同的效果。
本申请实施例还提供一种低密度奇偶校验译码装置。图9为另一实施例提供的一种低密度奇偶校验译码装置的结构示意图。如图9所示，所述低密度奇偶校验译码装置包括：第四矩阵确定模块810和第二译码模块820。
第四矩阵确定模块810，设置为确定目标基矩阵，所述目标基矩阵为第二奇偶校验矩阵集合的基矩阵，并且，所述第二奇偶校验矩阵集合的基矩阵从第一奇偶校验矩阵集合的基矩阵中抽取得到；第二译码模块820，设置为根据所述目标基矩阵和目标提升值对接收数据进行低密度奇偶校验译码。
本实施例的低密度奇偶校验译码装置，利用目标基矩阵进行编码，不仅可以提高数据传输的吞吐量以及LDPC码的译码并行度，而且支持灵活的码长和码率，提高编码灵活性。本实施例中未详细描述的技术细节，可参见上述任意实施例。
在一实施例中，还包括：
第四集合确定模块，设置为根据设定信息从至少两个奇偶校验矩阵集合中确定一个奇偶校验矩阵集合作为目标奇偶校验矩阵集合；其中，所述设定信息包括以下至少之一：传输块尺寸、码率、高层信令、调制阶数、调制编码方案索引、MCS表索引。
本实施例提出的低密度奇偶校验译码装置与上述实施例提出的低密度奇偶校验译码方法属于同一构思，未在本实施例中详尽描述的技术细节可参见上述任意实施例，并且本实施例具备与执行低密度奇偶校验译码方法相同的效果。
本申请实施例还提供了一种编码设备，图10为一实施例提供的一种编码设备的硬件结构示意图，如图10所示，本申请提供的编码设备，包括存储器12、处理器11以及存储在存储器12上并可在处理器11上运行的计算机程序，处理器11执行所述程序时实现上述的低密度奇偶校验编码方法。
编码设备可以包括存储器12；该编码设备中的处理器11可以是一个或多个，图10中以一个处理器11为例；存储器12用于存储一个或多个程序；所述一个 或多个程序被所述一个或多个处理器11执行，使得所述一个或多个处理器11实现如本申请实施例中所述的低密度奇偶校验编码方法。
编码设备还包括：通信装置13、输入装置14和输出装置15。
编码设备中的处理器11、存储器12、通信装置13、输入装置14和输出装置15可以通过总线或其他方式连接，图10中以通过总线连接为例。
输入装置14可用于接收输入的数字或字符信息，以及产生与编码设备的用户设置以及功能控制有关的按键信号输入。输出装置15可包括显示屏等显示设备。
通信装置13可以包括接收器和发送器。通信装置13设置为根据处理器11的控制进行信息收发通信。
存储器12作为一种计算机可读存储介质，可设置为存储软件程序、计算机可执行程序以及模块，如本申请实施例所述低密度奇偶校验编码方法对应的程序指令/模块(例如，低密度奇偶校验编码装置中的第一矩阵确定模块110和第一编码模块120)。存储器12可包括存储程序区和存储数据区，其中，存储程序区可存储操作系统、至少一个功能所需的应用程序；存储数据区可存储根据编码设备的使用所创建的数据等。此外，存储器12可以包括高速随机存取存储器，还可以包括非易失性存储器，例如至少一个磁盘存储器件、闪存器件或其他非易失性固态存储器件。在一些实例中，存储器12可包括相对于处理器11远程设置的存储器，这些远程存储器可以通过网络连接至编码设备。上述网络的实例包括但不限于互联网、企业内部网、局域网、移动通信网及其组合。
本申请实施例还提供了一种译码设备，图11为一实施例提供的一种译码设备的硬件结构示意图，如图11所示，本申请提供的译码设备，包括存储器22、处理器21以及存储在存储器22上并可在处理器21上运行的计算机程序，处理器21执行所述程序时实现上述的低密度奇偶校验译码方法。
译码设备可以包括存储器22；该译码设备中的处理器21可以是一个或多个，图11中以一个处理器21为例；存储器22用于存储一个或多个程序；所述一个或多个程序被所述一个或多个处理器21执行，使得所述一个或多个处理器21实现如本申请实施例中所述的低密度奇偶校验译码方法。
译码设备还包括：通信装置23、输入装置24和输出装置25。
译码设备中的处理器21、存储器22、通信装置23、输入装置24和输出装置25可以通过总线或其他方式连接，图11中以通过总线连接为例。
输入装置24可用于接收输入的数字或字符信息，以及产生与译码设备的用户设置以及功能控制有关的按键信号输入。输出装置25可包括显示屏等显示设备。
通信装置23可以包括接收器和发送器。通信装置23设置为根据处理器21的控制进行信息收发通信。
存储器22作为一种计算机可读存储介质，可设置为存储软件程序、计算机可执行程序以及模块，如本申请实施例所述低密度奇偶校验译码方法对应的程序指令/模块(例如，低密度奇偶校验译码装置中的第三矩阵确定模块710和第一译码模块720)。存储器22可包括存储程序区和存储数据区，其中，存储程序区可存储操作系统、至少一个功能所需的应用程序；存储数据区可存储根据译码设备的使用所创建的数据等。此外，存储器22可以包括高速随机存取存储器，还可以包括非易失性存储器，例如至少一个磁盘存储器件、闪存器件或其他非易失性固态存储器件。在一些实例中，存储器22可包括相对于处理器21远程设置的存储器，这些远程存储器可以通过网络连接至译码设备。上述网络的实例包括但不限于互联网、企业内部网、局域网、移动通信网及其组合。
本申请实施例还提供一种存储介质，所述存储介质存储有计算机程序，所述计算机程序被处理器执行时实现本申请实施例中任一所述的低密度奇偶校验编码方法或低密度奇偶校验译码方法。
该编码方法，包括：
确定目标奇偶校验矩阵，所述目标奇偶校验矩阵属于第二奇偶校验矩阵集合，并且，所述第二奇偶校验矩阵集合的基矩阵从第一奇偶校验矩阵集合的基矩阵中抽取得到；根据所述目标奇偶校验矩阵和目标提升值对待传输数据进行低密度奇偶校验编码。
或者，该编码方法，包括：
确定目标基矩阵，所述目标基矩阵为第二奇偶校验矩阵集合的基矩阵，并且，所述第二奇偶校验矩阵集合的基矩阵从第一奇偶校验矩阵集合的基矩阵中抽取得到；根据所述目标基矩阵和目标提升值对待传输数据进行低密度奇偶校验编码。
或者，该译码方法，包括：
确定目标奇偶校验矩阵，所述目标奇偶校验矩阵属于第二奇偶校验矩阵集合，并且，所述第二奇偶校验矩阵集合的基矩阵从第一奇偶校验矩阵集合的基矩阵中抽取得到；根据所述目标奇偶校验矩阵和目标提升值对接收数据进行低 密度奇偶校验译码。
或者，该译码方法，包括：
确定目标基矩阵，所述目标基矩阵为第二奇偶校验矩阵集合的基矩阵，并且，所述第二奇偶校验矩阵集合的基矩阵从第一奇偶校验矩阵集合的基矩阵中抽取得到；根据所述目标基矩阵和目标提升值对接收数据进行低密度奇偶校验译码。
本申请实施例的计算机存储介质，可以采用一个或多个计算机可读的介质的任意组合。计算机可读介质可以是计算机可读信号介质或者计算机可读存储介质。计算机可读存储介质例如可以是，但不限于：电、磁、光、电磁、红外线或半导体的系统、装置或器件，或者任意以上的组合。计算机可读存储介质的例子(非穷举的列表)包括：具有一个或多个导线的电连接、便携式计算机磁盘、硬盘、随机存取存储器(Random Access Memory，RAM)、只读存储器(Read Only Memory，ROM)、可擦式可编程只读存储器(Erasable Programmable Read Only Memory，EPROM)、闪存、光纤、便携式CD-ROM、光存储器件、磁存储器件或者上述的任意合适的组合。计算机可读存储介质可以是任何包含或存储程序的有形介质，该程序可以被指令执行系统、装置或者器件使用或者与其结合使用。
计算机可读的信号介质可以包括在基带中或者作为载波一部分传播的数据信号，其中承载了计算机可读的程序代码。这种传播的数据信号可以采用多种形式，包括但不限于：电磁信号、光信号或上述的任意合适的组合。计算机可读的信号介质还可以是计算机可读存储介质以外的任何计算机可读介质，该计算机可读介质可以发送、传播或者传输用于由指令执行系统、装置或者器件使用或者与其结合使用的程序。
计算机可读介质上包含的程序代码可以用任何适当的介质传输，包括但不限于：无线、电线、光缆、无线电频率(Radio Frequency，RF)等等，或者上述的任意合适的组合。
可以以一种或多种程序设计语言或其组合来编写用于执行本申请操作的计算机程序代码，所述程序设计语言包括面向对象的程序设计语言，诸如Java、Smalltalk、C++，还包括常规的过程式程序设计语言，诸如“C”语言或类似的程序设计语言。程序代码可以完全地在用户计算机上执行、部分地在用户计算机上执行、作为一个独立的软件包执行、部分在用户计算机上部分在远程计算机上执行或者完全在远程计算机或服务器上执行。在涉及远程计算机的情形中，远程计算机可以通过任意种类的网络，包括局域网(Local Area Network，LAN)或广域网(Wide Area Network，WAN)，连接到用户计算机，或者，可以连接 到外部计算机(例如利用因特网服务提供商来通过因特网连接)。
以上所述，仅为本申请的示例性实施例而已。
本领域内的技术人员应明白，术语用户终端涵盖任何适合类型的无线用户设备，例如移动电话、便携数据处理装置、便携网络浏览器或车载移动台。
一般来说，本申请的多种实施例可以在硬件或专用电路、软件、逻辑或其任何组合中实现。例如，一些方面可以被实现在硬件中，而其它方面可以被实现在可以被控制器、微处理器或其它计算装置执行的固件或软件中，尽管本申请不限于此。
本申请的实施例可以通过移动装置的数据处理器执行计算机程序指令来实现，例如在处理器实体中，或者通过硬件，或者通过软件和硬件的组合。计算机程序指令可以是汇编指令、指令集架构(Instruction Set Architecture，ISA)指令、机器指令、机器相关指令、微代码、固件指令、状态设置数据或者以一种或多种编程语言的任意组合编写的源代码或目标代码。
本申请附图中的任何逻辑流程的框图可以表示程序步骤，或者可以表示相互连接的逻辑电路、模块和功能，或者可以表示程序步骤与逻辑电路、模块和功能的组合。计算机程序可以存储在存储器上。存储器可以具有任何适合于本地技术环境的类型并且可以使用任何适合的数据存储技术实现，例如但不限于只读存储器(Read-Only Memory，ROM)、随机访问存储器(Random Access Memory，RAM)、光存储器装置和系统(数码多功能光碟(Digital Video Disc，DVD)或光盘(Compact Disk，CD))等。计算机可读介质可以包括非瞬时性存储介质。数据处理器可以是任何适合于本地技术环境的类型，例如但不限于通用计算机、专用计算机、微处理器、数字信号处理器(Digital Signal Processing，DSP)、专用集成电路(Application Specific Integrated Circuit，ASIC)、可编程逻辑器件(Field-Programmable Gate Array，FPGA)以及基于多核处理器架构的处理器。

Claims (27)

  1. 一种低密度奇偶校验编码方法，包括：
    确定目标奇偶校验矩阵，所述目标奇偶校验矩阵属于第二奇偶校验矩阵集合，并且，所述第二奇偶校验矩阵集合的基矩阵从第一奇偶校验矩阵集合的基矩阵中抽取得到；
    根据所述目标奇偶校验矩阵和目标提升值对待传输数据进行低密度奇偶校验编码。
  2. 根据权利要求1所述的方法，其中，所述确定目标奇偶校验矩阵，包括：
    根据所述第一奇偶校验矩阵集合确定所述第二奇偶校验矩阵集合的目标奇偶校验矩阵。
  3. 根据权利要求1所述的方法，其中，所述确定目标奇偶校验矩阵，包括：
    根据所述第一奇偶校验矩阵集合的基矩阵确定所述第二奇偶校验矩阵集合的基矩阵；
    根据所述第二奇偶校验矩阵集合的基矩阵确定所述第二奇偶校验矩阵集合的目标奇偶校验矩阵。
  4. 根据权利要求1所述的方法，其中，所述第二奇偶校验矩阵集合的基矩阵按照行索引序列和列索引序列中的至少之一从所述第一奇偶校验矩阵集合的基矩阵中抽取得到。
  5. 根据权利要求4所述的方法，其中，所述行索引序列满足以下之一：
    所述行索引序列中的元素是连续的升序整数；
    所述行索引序列中的元素包括不连续的升序整数；
    所述行索引序列中的元素是非升序整数，且所述行索引序列中的前M个元素是连续的升序整数，M大于1；
    所述行索引序列中至少包括{0、1、2、3}。
  6. 根据权利要求4所述的方法，其中，所述列索引序列满足以下之一：
    所述列索引序列的前kb2个元素是连续的升序整数，kb2大于1；
    所述列索引序列的前kb2个元素包括不连续的升序整数，kb2大于1；
    所述列索引序列中至少包括{0、1}；
    所述列索引序列中至少包括{22、23、24、25}。
  7. 根据权利要求6所述的方法，其中，kb2等于所述第二奇偶校验矩阵集合的基矩阵的系统列数，或者等于所述第二奇偶校验矩阵集合的基矩阵的列数 与行数的差值，或者小于或等于所述第一奇偶校验矩阵集合中的奇偶校验矩阵的系统列数。
  8. 根据权利要求1所述的方法，其中，所述第一奇偶校验矩阵集合中包括a1个第一奇偶校验矩阵，所述a1个第一奇偶校验矩阵的基矩阵相同；
    所述第二奇偶校验矩阵集合中包括a2个第二奇偶校验矩阵，所述a2个第二奇偶校验矩阵的基矩阵相同；
    所述第二奇偶校验矩阵集合的最大提升值Zmax2为所述第一奇偶校验矩阵集合中第i个第一奇偶校验矩阵所支持的最大提升值Zi的D倍，D为2的正整数次幂，i为小于a1的非负整数。
  9. 根据权利要求1所述的方法，其中，所述第二奇偶校验矩阵集合的最大提升值Zmax2大于所述第一奇偶校验矩阵集合的最大提升值Zmax1。
  10. 根据权利要求1、8或9所述的方法，其中，所述第二奇偶校验矩阵集合的最大提升值Zmax2为a·2 b，其中，a是大于15的奇数，b是正整数。
  11. 根据权利要求1所述的方法，其中，所述目标提升值属于G个提升值子集合中的一个提升值子集合，其中，G大于1，所述G个提升值子集合中每2个提升值子集合之间无交集。
  12. 根据权利要求1所述的方法，其中，
    所述第一奇偶校验矩阵集合支持的提升值构成第一提升值集合Zset1，所述第二奇偶校验矩阵集合支持的提升值构成第二提升值集合Zset2；
    所述第一提升值集合Zset1和所述第二提升值集合Zset2满足以下之一：
    所述第一提升值集合Zset1和所述第二提升值集合Zset2无交集；
    所述第一提升值集合Zset1是所述第二提升值集合Zset2的子集；
    所述第一提升值集合Zset1和所述第二提升值集合Zset2的交集Zset中的元素数量小于所述第一提升值集合Zset1中的元素数量，且小于所述第二提升值集合Zset2中的元素数量。
  13. 根据权利要求1所述的方法，其中，
    所述第二奇偶校验矩阵集合支持的最小提升值大于所述第一奇偶校验矩阵集合支持的最大提升值；
    所述第二奇偶校验矩阵集合支持的提升值包括以下至少之一：416、448、480、512、576、640、704、768、832、896、960、1024、1152、1280、1408、1536、1664、1792、1920、2048。
  14. 根据权利要求1所述的方法，其中，
    所述第一奇偶校验矩阵集合支持的最大信息长度Kmax1小于所述第二奇偶校验矩阵集合支持的最大信息长度Kmax2。
  15. 根据权利要求1所述的方法，其中，所述第二奇偶校验矩阵集合中包括至少一个奇偶校验矩阵，所述奇偶校验矩阵中包括k0个上下相邻对，所述k0个上下相邻对中包括k1个第一类上下相邻对和k2个第二类上下相邻对，且k1大于3*k2，k1和k2都是大于0的整数；
    其中，所述上下相邻对是指所述奇偶校验矩阵中两个指示单位阵循环移位且位于同一列中的相邻元素；
    所述第一类上下相邻对的两个元素的差值对2取余的结果等于0；
    所述第一类上下相邻对的两个元素的差值对2取余的结果大于0。
  16. 根据权利要求1所述的方法，其中，所述第二奇偶校验矩阵集合中包括至少一个奇偶校验矩阵，所述奇偶校验矩阵中包括k3个指示单位阵循环移位的第一类元素和k4个指示单位阵循环移位的第二类元素，且k3大于3*k4，k3和k4都是大于0的整数；
    其中，所述第一类元素对2取余的结果等于0；
    所述第二类元素对2取余的结果大于0。
  17. 根据权利要求1所述的方法，还包括：
    根据设定信息从至少两个奇偶校验矩阵集合中确定一个奇偶校验矩阵集合作为目标奇偶校验矩阵集合；
    其中，所述设定信息包括以下至少之一：传输块尺寸、码率、高层信令、调制阶数、调制编码方案索引、调制与编码策略MCS表索引。
  18. 根据权利要求17所述的方法，其中，所述根据设定信息从至少两个奇偶校验矩阵集合中确定一个奇偶校验矩阵集合作为目标奇偶校验矩阵集合，包括：
    在满足以下条件至少之一的情况下，将所述第二奇偶校验矩阵集合作为所述目标奇偶校验矩阵集合：
    传输块尺寸大于或等于T0，T0为大于或等于所述第一奇偶校验矩阵集合支持的最大信息长度Kmax1的整数；
    码率大于或等于R0，R0为大于0且小于1的实数。
  19. 一种低密度奇偶校验编码方法，包括：
    确定目标基矩阵，所述目标基矩阵为第二奇偶校验矩阵集合的基矩阵，并且，所述第二奇偶校验矩阵集合的基矩阵从第一奇偶校验矩阵集合的基矩阵中抽取得到；
    根据所述目标基矩阵和目标提升值对待传输数据进行低密度奇偶校验编码。
  20. 根据权利要求19所述的方法，其中，根据所述目标基矩阵和目标提升值对待传输数据进行低密度奇偶校验编码，包括：
    根据所述目标基矩阵和所述目标提升值确定校验矩阵H；
    基于所述校验矩阵H对所述待传输数据进行低密度奇偶校验编码。
  21. 根据权利要求19所述的方法，其中，根据所述目标基矩阵和目标提升值对待传输数据进行低密度奇偶校验编码，包括：
    根据所述目标基矩阵确定目标奇偶校验矩阵；
    基于所述目标奇偶校验矩阵和所述目标提升值对所述待传输数据进行低密度奇偶校验编码。
  22. 根据权利要求19所述的方法，还包括：
    根据设定信息从至少两个奇偶校验矩阵集合中确定一个奇偶校验矩阵集合作为目标奇偶校验矩阵集合；
    其中，所述设定信息包括以下至少之一：传输块尺寸、码率、高层信令、调制阶数、调制编码方案索引、调制与编码策略MCS表索引。
  23. 一种低密度奇偶校验译码方法，包括：
    确定目标奇偶校验矩阵，所述目标奇偶校验矩阵属于第二奇偶校验矩阵集合，并且，所述第二奇偶校验矩阵集合的基矩阵从第一奇偶校验矩阵集合的基矩阵中抽取得到；
    根据所述目标奇偶校验矩阵和目标提升值对接收数据进行低密度奇偶校验译码。
  24. 一种低密度奇偶校验译码方法，包括：
    确定目标基矩阵，所述目标基矩阵为第二奇偶校验矩阵集合的基矩阵，并且，所述第二奇偶校验矩阵集合的基矩阵从第一奇偶校验矩阵集合的基矩阵中抽取得到；
    根据所述目标基矩阵和目标提升值对接收数据进行低密度奇偶校验译码。
  25. 一种编码设备，包括存储器、处理器以及存储在所述存储器上并可在所述处理器上运行的计算机程序，其中，所述处理器执行所述程序时实现如权利 要求1-22中任一项所述的低密度奇偶校验编码方法。
  26. 一种译码设备，包括存储器、处理器以及存储在所述存储器上并可在所述处理器上运行的计算机程序，其中，所述处理器执行所述程序时实现如权利要求23-24中任一项所述的低密度奇偶校验译码方法。
  27. 一种计算机可读存储介质，存储有计算机程序，其中，所述程序被处理器执行时实现如权利要求1-22中任一项所述的低密度奇偶校验编码方法或者如权利要求23-24中任一项所述的低密度奇偶校验译码方法。
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