WO2019000763A1 - 低损耗半导体功率器件 - Google Patents

低损耗半导体功率器件 Download PDF

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WO2019000763A1
WO2019000763A1 PCT/CN2017/108956 CN2017108956W WO2019000763A1 WO 2019000763 A1 WO2019000763 A1 WO 2019000763A1 CN 2017108956 W CN2017108956 W CN 2017108956W WO 2019000763 A1 WO2019000763 A1 WO 2019000763A1
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junction
region
conductivity type
power device
disposed
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曹峰
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苏州美天网络科技有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0635—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors and diodes, or resistors, or capacitors

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  • the invention belongs to the field of semiconductor technology, and in particular to a low loss semiconductor power device.
  • Power devices include power ICs and power discrete devices.
  • Power discrete devices mainly include semiconductor devices such as power MOSFETs, high-power transistors, and IGBTs.
  • Power devices are used in almost all electronic manufacturing industries, including notebooks and PCs in the computer field. , servers, displays and various peripherals; mobile phones, telephones and other various terminal and central office equipment in the field of network communication; traditional black and white household appliances and various digital products in the field of consumer electronics; industrial PCs in industrial control, various types Instrumentation and various control equipment.
  • power devices can also effectively save energy. Due to the demand for electronic products and the continuous improvement of energy efficiency requirements, the Chinese power device market has maintained a relatively fast development speed.
  • Power semiconductor devices are an important part of power electronic circuits.
  • An ideal power semiconductor device should have good static and dynamic characteristics. It can withstand high voltage and leakage current in the off state, and can flow through in the on state. High current and very low tube voltage drop have short on and off times during switching, and on-state loss, off-state loss and switching loss are small. At the same time, it can withstand high di/dt and du/dt and has full control function.
  • the present invention proposes a low-loss semiconductor power device in which a shunt circuit is provided at the gate.
  • a shunt circuit is provided at the gate.
  • a low loss semiconductor power device comprising:
  • a drain of the MOS power device is disposed at a bottom end thereof, and an epitaxial layer of a first conductivity type is disposed at an upper end of the substrate;
  • a body region of a second conductivity type disposed at an upper portion of the channel and the epitaxial layer, wherein the body region covers at least an upper end of two adjacent channels to form an adjacent body region, wherein the body region a source of a first conductivity type is disposed, and an upper end between the adjacent body regions is configured with a gate;
  • a first PN junction is disposed on an upper portion of the first independent channel, and an upper end of the epitaxial layer is disposed
  • the insulation is configured with a first resistor, an anode of the first PN junction is connected to the gate, and a cathode of the first PN junction is connected to the source through the first resistor.
  • the upper end of the epitaxial layer is further insulated and disposed with a second resistor electrically connected to the gate.
  • a second PN junction is disposed on an upper portion of the second independent channel, and the second resistor is electrically connected to the gate through the second PN junction, the second resistor and the second PN junction The anode is connected, and the cathode of the second PN junction is connected to the gate.
  • an anode of the first PN junction is connected to a common terminal of the second PN junction and the gate.
  • an upper portion of the first independent channel is disposed with a first base region of a first conductivity type, a top portion of the first conductivity type is disposed at an upper portion thereof, and a first conductivity type is disposed at an upper end of the first base region The second district.
  • an upper portion of the second independent channel is disposed with a second base region of a first conductivity type, a top portion of the second conductivity type is disposed at an upper portion thereof, and a first conductivity type is disposed at an upper end of the second base region The fourth district.
  • the first conductivity type is an N type
  • the second conductivity type is a P type
  • the first area is an anode of the first PN junction
  • the second area is the first PN junction
  • the cathode the third region is the anode of the second PN junction
  • the fourth region is the cathode of the second PN junction.
  • the first conductivity type is a P type
  • the second conductivity type is an N type
  • the second area is an anode of the first PN junction
  • the first area is the first PN junction
  • the fourth region is the anode of the second PN junction
  • the third region is the cathode of the second PN junction.
  • the first PN junction is at least two, and each of the first PN junctions is independently disposed in one of the first independent channels, and the anode of each of the first PN junctions is connected in parallel with the anode and the cathode and the cathode are connected in parallel.
  • a low loss semiconductor power device which has a faster switching speed
  • the switch capacity is larger;
  • Figure 1 is a cross-sectional view of a low loss semiconductor power device
  • FIG. 2 is a top plan view of a low loss semiconductor power device
  • Figure 3 is a partially enlarged schematic view of Figure 2.
  • the low loss semiconductor power device proposed by the present invention includes:
  • the first conductivity type substrate 700 has a drain of a MOS power device disposed at a bottom end thereof, and an epitaxial layer 200 of a first conductivity type is disposed at an upper end of the substrate 700, and the material of the substrate epitaxial layer 200 is preferably silicon, but Not limited to silicon;
  • the second conductivity type channel 100 is disposed in the epitaxial layer at intervals. As shown in FIG. 1, only five channels 100 are shown in this embodiment, and the number thereof may be determined according to specific product design requirements.
  • the channel 100 is flush with the upper end of the epitaxial layer 200;
  • the body region 300 of the second conductivity type is disposed on the upper portion of the channel 100 and the epitaxial layer 200. Specifically, the body region 300 of the second conductivity type covers an upper portion of the plurality of channels 100 so that the second conductive portion is finally The body region 300 of the type is flush with the upper end of the epitaxial layer 200, wherein the body region 300 covers at least the upper ends of the two adjacent channels 100 to form adjacent body regions, and the body region is configured with the first a conductive source 310, an upper end between the adjacent body regions is provided with a gate 500, thereby constituting a MOS power device;
  • first independent channels 110 and second independent channels 120 are not covered by the body region 300 in the channel 100, and a first PN junction is disposed on an upper portion of the first independent channel 110.
  • the upper end of the epitaxial layer 200 is insulated and disposed with a first resistor 610.
  • the anode of the first PN junction is connected to the gate 500 through a metal line, and the cathode of the first PN junction passes through the first resistor 610.
  • the source electrodes 310 are connected in common, and the electrodes and the resistors are connected by metal wires. The prior art is not described in this embodiment.
  • the gate When the power device is turned off, the gate has an oscillating voltage. When the oscillating voltage is too high, the first PN junction is conducted to the source, and the first resistor effectively slows down the absorption of the high voltage, thereby avoiding the gate voltage oscillation. When the voltage of the gate is at a normal voltage value, the first PN junction is turned off, the current does not flow through the first PN junction, and the first resistor is not consumed, thereby reducing the loss of the power device and improving the switching of the power device. The capacity effectively eliminates the gate voltage oscillation and the switching speed is faster.
  • the gates 500 are all gated gates, that is, the gates are independently disposed at the upper end of each body region, and two adjacent body regions are not connected.
  • an insulating film 400 is formed on the upper surface of the power device, a conductive film is formed on the insulating film 400, the conductive film and the insulating film are etched, and the remaining conductive film becomes the gate and the first A resistor, a second resistor 620 is further formed on the conductive film, and the second resistor 620 is connected to the gate 500.
  • a second PN junction is disposed on an upper portion of the second independent channel 120, and the second resistor 620 is electrically connected to the gate 500 through the second PN junction, wherein the second A resistor 620 is coupled to the anode of the second PN junction, a cathode of the second PN junction is coupled to the gate 500, and the other end of the second resistor is coupled to the gate control terminal.
  • the anode of the first PN junction is connected to the common terminal of the second PN junction cathode and the gate 500.
  • the upper portion of the first independent channel 110 is configured with a first base region 111 of a first conductivity type, as shown in FIGS. 2 and 3, and the first region 112 of the second conductivity type is disposed at an upper portion thereof.
  • a second region 113 of a first conductivity type is disposed at an upper end of the first base region 111.
  • an upper portion of the second independent channel 120 is disposed with a second base region 121 of a first conductivity type, and an upper portion of the second conductive region is disposed with a third region 122 of a second conductivity type, and an upper end of the second base region A fourth region 123 of the first conductivity type is disposed.
  • the first conductivity type is an N type
  • the second conductivity type is a P type
  • the first area is an anode of the first PN junction
  • the second area is the A cathode of a PN junction
  • the third region being the anode of the second PN junction
  • the fourth region being the cathode of the second PN junction.
  • the first conductivity type is a P type
  • the second conductivity type is an N type
  • a second region is an anode of the first PN junction
  • the first region is a cathode of the first PN junction
  • the fourth region is an anode of the second PN junction
  • the third region is The cathode of the second PN junction.
  • the first PN junction is at least two, and each of the first PN junctions is independently disposed in one of the first independent channels, and the anode and anode of each of the first PN junctions are connected in parallel, the cathode and the cathode. Parallel to enhance the conduction effect of the gate overvoltage, further reduce the gate voltage oscillation, and stabilize the breaking characteristics of the power device.
  • a low-loss semiconductor power device proposed by the present invention has a faster switching speed, a larger switching capacity, and a lower switching loss of the power device.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

一种低损耗半导体功率器件包括：第一导电型的衬底（700），其底端配置有MOS晶体管的漏极，衬底上端配置有第一导电型的外延层（200）；第二导电型的沟道（100）、第二导电型的体区（300），其中，体区至少覆盖在两个相邻沟道的上端形成相邻体区，体区内配置有第一导电型的源极（310），相邻体区之间的上端配置有栅极（500）；其中，沟道中至少存在两个未被体区覆盖的第一独立沟道（110）和第二独立沟道（120），第一独立沟道上部配置有第一PN结，外延层上端绝缘配置有第一电阻（610），第一PN结的阳极与栅极连接，第一PN结的阴极通过第一电阻与源极共接。解决了功率器件开关损耗过大的技术问题。

Description

低损耗半导体功率器件 技术领域
本发明属于半导体技术领域，特别是涉及一种低损耗半导体功率器件。
背景技术
功率器件包括功率IC和功率分立器件，功率分立器件则主要包括功率MOSFET、大功率晶体管和IGBT等半导体器件，功率器件几乎用于所有的电子制造业，所应用的产品包括计算机领域的笔记本、PC、服务器、显示器以及各种外设；网络通信领域的手机、电话以及其它各种终端和局端设备；消费电子领域的传统黑白家电和各种数码产品；工业控制类中的工业PC、各类仪器仪表和各类控制设备等。除了保证这些设备的正常运行以外，功率器件还能起到有效的节能作用。由于电子产品的需求以及能效要求的不断提高，中国功率器件市场一直保持较快的发展速度。
功率半导体器件是电力电子电路的重要组成部分，一个理想的功率半导体器件应该具有好的静态和动态特性，在截止状态时能承受高电压且漏电流要小，在导通状态时，能流过大电流和很低的管压降，在开关转换时，具有短的开、关时间；通态损耗、断态损耗和开关损耗均要小。同时能承受高的di/dt和du/dt以及具有全控功能。
现有的功率器件具有极快的开关特性，实现更高的功率转换效率，但在功率器件断开和闭合过程中，栅极易产生震荡，为了抑制这种震荡，通常在功率器件中串入电阻来减小震荡，但这导致整个功率器件的损耗增大。
发明内容
针对上述技术问题，本发明中提出了一种低损耗半导体功率器件，在栅极设置有分流电路，当栅电压震荡过大时，电压通过分流电路导流，避免栅电压震荡，同时降低了功率器件的损耗。
为了实现根据本发明的这些目的和其它优点，提供了一种低损耗半导体功率器件，包括：
第一导电型的衬底，其底端配置有MOS功率器件的漏极，所述衬底上端配置有第一导电型的外延层；
第二导电型的沟道，其间隔配置在所述外延层中；
第二导电型的体区，其配置在所述沟道和外延层上部，其中，所述体区至少覆盖在两个相邻所述沟道的上端形成相邻体区，所述体区内配置有第一导电型的源极，所述相邻体区之间的上端配置有栅极；
其中，所述沟道中至少存在两个未被所述体区覆盖的第一独立沟道和第二独立沟道，所述第一独立沟道上部配置有第一PN结，所述外延层上端绝缘配置有第一电阻，所述第一PN结的阳极与所述栅极连接，所述第一PN结的阴极通过所述第一电阻与所述源极共接。
优选的，所述外延层上端还绝缘配置有第二电阻，其与所述栅极导电连接。
优选的，所述第二独立沟道上部配置有第二PN结，所述第二电阻通过所述第二PN结与所述栅极导电连接，所述第二电阻与所述第二PN结的阳极连接，所述第二PN结的阴极与所述栅极连接。
优选的，所述第一PN结的阳极连接在所述第二PN结和所述栅极的共接端。
优选的，所述第一独立沟道的上部配置有第一导电型的第一基区，其上部配置有第二导电型的第一区，所述第一基区上端配置有第一导电型的第二区。
优选的，所述第二独立沟道的上部配置有第一导电型的第二基区，其上部配置有第二导电型的第三区，所述第二基区上端配置有第一导电型的第四区。
优选的，所述第一导电型为N型，所述第二导电型为P型，所述第一区为所述第一PN结的阳极，所述第二区为所述第一PN结的阴极，所述第三区为所述第二PN结的阳极，所述第四区为所述第二PN结的阴极。
优选的，所述第一导电型为P型，所述第二导电型为N型，所述第二区为所述第一PN结的阳极，所述第一区为所述第一PN结的阴极，所述第四区为所述第二PN结的阳极，所述第三区为所述第二PN结的阴极。
优选的，所述第一PN结至少为2个，每一个第一PN结独立配置在一个所述第一独立沟道中，每一个第一PN结的阳极与阳极并联、阴极与阴极并联。
本发明至少包括以下有益效果：
1、本发明提出的一种低损耗半导体功率器件，开关速度更快；
2、开关容量更大；
3、功率器件的开关损耗更低。
本发明的其它优点、目标和特征将部分通过下面的说明体现，部分还将通过对本发明的研究和实践而为本领域的技术人员所理解。
附图说明
图1是低损耗半导体功率器件的剖视图；
图2是低损耗半导体功率器件的俯视图；
图3是图2中的局部放大示意图。
具体实施方式
下面结合附图对本发明做进一步的详细说明，以令本领域技术人员参照说明书文字能够据以实施。
应当理解，本发明所使用的诸如“具有”、“包含”以及“包括”术语并不配出一个或多个其它元件或其组合的存在或添加。
同时，为清楚地说明本发明的具体实施方式，说明书附图中所列示意图，放大了本发明所述的层和区域的厚度，且所列图形大小并不代表实际尺寸； 说明书附图是示意性的，不应限定本发明的范围。说明书中所列实施例不应仅限于说明书附图中所示区域的特定形状，而是包括所得到的形状如制造引起的偏差等，如刻蚀得到的曲线通常具有弯曲或圆润的特点，在本发明实施例中均以矩形表示。
如图1-3所示，本发明提出的低损耗半导体功率器件，包括：
第一导电型的衬底700，其底端配置有MOS功率器件的漏极，所述衬底700上端配置有第一导电型的外延层200，衬底外延层200的材质优选为硅，但不局限于为硅；
第二导电型的沟道100，其间隔配置在所述外延层中，如图1所示，本实施例中仅示出了5个沟道100，其数量多少可根据具体产品设计要求确定，沟道100与外延层200的上端齐平；
第二导电型的体区300，其配置在所述沟道100和外延层200上部，具体的，第二导电型的体区300覆盖设置在若干个沟道100的上部，使得最终第二导电型的体区300与外延层200的上端齐平，其中，所述体区300至少覆盖在两个相邻所述沟道100的上端形成相邻体区，所述体区内配置有第一导电型的源极310，所述相邻体区之间的上端配置有栅极500，从而构成了MOS功率器件；
其中，所述沟道100中至少存在两个未被所述体区300覆盖的第一独立沟道110和第二独立沟道120，所述第一独立沟道110上部配置有第一PN结，所述外延层200上端绝缘配置有第一电阻610，所述第一PN结的阳极与所述栅极500通过金属线连接，所述第一PN结的阴极通过所述第一电阻610与所述源极310共接，各极之间以及与电阻之间都是通过金属线连接的，为现有技术，本实施例中没有再叙述。
当功率器件关断时，栅极出现震荡电压，当震荡电压过高时，通过第一PN结导流到源极，通过第一电阻有效减缓吸收了高电压，避免了栅电压震荡， 栅极的电压处于正常电压值时，第一PN结截止，电流不会通过第一PN结导流，也不会经过第一电阻消耗，从而降低了功率器件的损耗，提高了功率器件的开关容量，有效消除了栅电压震荡，开关速度更快。
一种实施例中，所述栅极500都是分栅栅极，也就是栅极独立设置在每个体区上端，不连接两个相邻的体区。
一种实施例中，在功率器件的上表面上形成一层绝缘薄膜400，在绝缘薄膜400上形成一层导电膜，刻蚀导电膜和绝缘薄膜，剩余的导电膜成为所述栅极和第一电阻，同时在导电膜上还形成有第二电阻620，所述第二电阻620与所述栅极500连接。
一种实施例中，所述第二独立沟道120上部配置有第二PN结，所述第二电阻620通过所述第二PN结与所述栅极500导电连接，其中，所述第二电阻620与所述第二PN结的阳极连接，所述第二PN结的阴极与所述栅极500连接，第二电阻的另一端与栅极控制端连接。
一种实施例中，所述第一PN结的阳极连接在所述第二PN结阴极和所述栅极500的共接端。
一种实施例中，所述第一独立沟道110的上部配置有第一导电型的第一基区111，如图2和3所示，其上部配置有第二导电型的第一区112，所述第一基区111上端配置有第一导电型的第二区113。
一种实施例中，所述第二独立沟道120的上部配置有第一导电型的第二基区121，其上部配置有第二导电型的第三区122，所述第二基区上端配置有第一导电型的第四区123。
一种实施例中，所述第一导电型为N型，所述第二导电型为P型，所述第一区为所述第一PN结的阳极，所述第二区为所述第一PN结的阴极，所述第三区为所述第二PN结的阳极，所述第四区为所述第二PN结的阴极。
一种实施例中，所述第一导电型为P型，所述第二导电型为N型，所述 第二区为所述第一PN结的阳极，所述第一区为所述第一PN结的阴极，所述第四区为所述第二PN结的阳极，所述第三区为所述第二PN结的阴极。
一种实施例中，所述第一PN结至少为2个，每一个第一PN结独立配置在一个所述第一独立沟道中，每一个第一PN结的阳极与阳极并联、阴极与阴极并联，以增强栅极过电压的导流效果，进一步减少栅电压震荡，稳定功率器件的开断特性。
由上所述，本发明提出的一种低损耗半导体功率器件，开关速度更快，开关容量更大、功率器件的开关损耗更低。
尽管本发明的实施方案已公开如上，但其并不仅仅限于说明书和实施方式中所列运用，它完全可以被适用于各种适合本发明的领域，对于熟悉本领域的人员而言，可容易地实现另外的修改，因此在不背离权利要求及等同范围所限定的一般概念下，本发明并不限于特定的细节和这里示出与描述的图例。

Claims (9)

  1. 一种低损耗半导体功率器件，其特征在于，包括：
    第一导电型的衬底，其底端配置有MOS功率器件的漏极，所述衬底上端配置有第一导电型的外延层；
    第二导电型的沟道，其间隔配置在所述外延层中；
    第二导电型的体区，其配置在所述沟道和外延层上部，其中，所述体区至少覆盖在两个相邻所述沟道的上端形成相邻体区，所述体区内配置有第一导电型的源极，所述相邻体区之间的上端配置有栅极；
    其中，所述沟道中至少存在两个未被所述体区覆盖的第一独立沟道和第二独立沟道，所述第一独立沟道上部配置有第一PN结，所述外延层上端绝缘配置有第一电阻，所述第一PN结的阳极与所述栅极连接，所述第一PN结的阴极通过所述第一电阻与所述源极共接。
  2. 如权利要求1所述的低损耗半导体功率器件，其特征在于，所述外延层上端还绝缘配置有第二电阻，其与所述栅极导电连接。
  3. 如权利要求2所述的低损耗半导体功率器件，其特征在于，所述第二独立沟道上部配置有第二PN结，所述第二电阻通过所述第二PN结与所述栅极导电连接，所述第二电阻与所述第二PN结的阳极连接，所述第二PN结的阴极与所述栅极连接。
  4. 如权利要求3所述的低损耗半导体功率器件，其特征在于，所述第一PN结的阳极连接在所述第二PN结和所述栅极的共接端。
  5. 如权利要求4所述的低损耗半导体功率器件，其特征在于，所述第一独立沟道的上部配置有第一导电型的第一基区，其上部配置有第二导电型的第一区，所述第一基区上端配置有第一导电型的第二区。
  6. 如权利要求5所述的低损耗半导体功率器件，其特征在于，所述第二独立沟道的上部配置有第一导电型的第二基区，其上部配置有第二导电型的第三区，所述第二基区上端配置有第一导电型的第四区。
  7. 如权利要求6所述的低损耗半导体功率器件，其特征在于，所述第一导电型为N型，所述第二导电型为P型，所述第一区为所述第一PN结的阳极，所述第二区为所述第一PN结的阴极，所述第三区为所述第二PN结的阳极，所述第四区为所述第二PN结的阴极。
  8. 如权利要求6所述的低损耗半导体功率器件，其特征在于，所述第一导电型为P型，所述第二导电型为N型，所述第二区为所述第一PN结的阳极，所述第一区为所述第一PN结的阴极，所述第四区为所述第二PN结的阳极，所述第三区为所述第二PN结的阴极。
  9. 如权利要求7或8所述的低损耗半导体功率器件，其特征在于，所述第一PN结至少为2个，每一个第一PN结独立配置在一个所述第一独立沟道中，每一个第一PN结的阳极与阳极并联、阴极与阴极并联。
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