CN106449768A - 一种jfet管 - Google Patents

一种jfet管 Download PDF

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CN106449768A
CN106449768A CN201611051509.4A CN201611051509A CN106449768A CN 106449768 A CN106449768 A CN 106449768A CN 201611051509 A CN201611051509 A CN 201611051509A CN 106449768 A CN106449768 A CN 106449768A
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jfet
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CN106449768B (zh
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李风浪
李舒歆
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Huzhou Qiqi Electromechanical Technology Co., Ltd
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Dongguan Lianzhou Intellectual Property Operation and Management Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/808—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

本发明涉及半导体技术领域，特别涉及一种JFET管，P型衬底；N型注入区；P型注入区；P型重掺杂区；N型重掺杂的漏区和源区；所述漏区与所述P型注入区之间的第一场氧化层；所述源区与所述P型注入区之间的第二场氧化层，所述第一场氧化层下的N型注入区上部形成P型掺杂区，所述P型掺杂区靠近P型注入区一侧与栅极电性相连，构成第二JFET结构，所述第二JFET结构的夹断电压高于本征JFET结构，本发明JFET管，其耐压性能有效提高。

Description

一种JFET管
技术领域
本发明涉及半导体技术领域，特别涉及一种JFET管。
技术背景
随着半导体科技的快速演进，使得例如电脑及其周边数字产品等也日益地更新。电脑及其周边数字产品的应用集成电路半导体工艺快速发展,为能否提供高品质数字产品的重要因素。
结型场效应管(JFET)是最常见的半导体器件之一，包括N沟道结型场效应管和P沟道结型场效应管，在实践应用中，常用的是N沟道JFET。结型场效应管由于器件尺寸小，具有优于MOSFET的优点，有助于半导体器件进一步朝向高密度、小型化的方向发展。
传统的结型场效应管是通过PN结耐压，提高耐压的方式主要依靠降低结的浓度，但是当今制程下，耐压程度仍然有限，无法做成耐高压的结型场效应管，而且降低结的浓度易引起器件电流太小、稳定性差等问题。
发明内容
本发明的目的是提供一种JFET管，其耐压性能有效提高。
为实现上述目的，本发明采用以下技术方案：
一种JFET管，包括：P型衬底，所述P型衬底作为背栅；在所述P型衬底的上表层中形成N型注入区；在所述N型注入区的上表层中形成的P型注入区，所述P型注入区作为正栅；在所述P型注入区的上表层中形成的P型重掺杂区；在所述N型注入区上表层的两端形成的N型重掺杂的漏区和源区，正栅靠近所述源区；所述漏区与所述P型注入区之间的N型注入区上形成的第一场氧化层；所述源区与所述P型注入区之间的N型注入区上形成的第二场氧化层，所述第一场氧化层下的N型注入区上部形成P型掺杂区，所述P型掺杂区靠近P型注入区一侧与栅极电性相连，构成第二JFET结构，所述第二JFET结构的夹断电压高于本征JFET结构。
可选的，所述整个P型掺杂区与第一场氧化层接触。
可选的，所述P型掺杂区呈“L”型，靠近所述P型注入区一侧与所述第一场氧化层接触，且与栅极电性相连。
可选的，所述P型掺杂区与第一场氧化层之间的N型注入区靠近漏区侧与漏极电性相连。
可选的，部分所述第一场氧化层上以及与之相连的部分P型注入区上形成第一多晶硅层。
可选的，所述P型掺杂区通过第一多晶硅层与栅极电性相连。
可选的，部分所述第一场氧化层上以及与之相连的部分漏区上形成第二多晶硅层。
可选的，所述P型掺杂区与第一场氧化层之间的N型注入区通过第二多晶硅层与漏极电性相连。
可选的，所述N型注入区分为第一N型注入区和第二N型注入区，第二N型注入区形成在P型掺杂区与P型注入区之间的第一N型注入区上表层中，且所述第二N型注入区多子浓度低于第一N型注入区。
可选的，所述第二N型注入区深度大于P型掺杂区同时小于P型注入区。
相对于现有技术，本发明具有以下有益效果：
本发明JFET管所述第一场氧化层下的N型注入区上部形成P型掺杂区，所述P型掺杂区与栅极电性相连，构成第二JFET结构，JFET管工作时，栅极加负压，P型掺杂区与下面的N型注入区形成的PN结反偏，PN结耗尽加强，增加漏区侧N型注入区的抗压能力；所述第二JFET结构的夹断电压高于本征JFET结构，使得JFET管不受第二JFET结构影响正常工作。
附图说明
图1为本发明第一实施例JFET剖面结构示意图；
图2为本发明第二实施例JFET剖面结构示意图；
图3为本发明第三实施例JFET剖面结构示意图。
具体实施方式
为了更好地理解本发明，下面结合附图以及实施例对本发明作进一步介绍，实施例仅限于解释本发明，并不对本发明构成任何限定。第一实施例
如图1所示，本实施例JFET管，包括：P型衬底100，所述P型衬底100作为背栅；在所述P型衬底100的上表层中形成N型注入区200；在所述N型注入区200的上表层中形成的P型注入区300，所述P型注入区300作为正栅；在所述P型注入区300的上表层中形成的P型重掺杂区310；在所述N型注入区200上表层的两端形成的N型重掺杂的漏区210和源区220，正栅靠近所述源区220；所述漏区210与所述P型注入区300之间的N型注入区200上形成的第一场氧化层410；所述源区220与所述P型注入区300之间的N型注入区200上形成的第二场氧化层420，所述第一场氧化层410下的N型注入区200上部形成P型掺杂区500，所述P型掺杂区500靠近P型注入区300一侧与栅极电性相连，构成第二JFET结构，所述第二JFET结构的夹断电压高于本征JFET结构。
本实施例整个P型掺杂区500与第一场氧化层410接触，JFET管工作时，栅极加负压，P型掺杂区500与下面的N型注入区200形成的PN结反偏，PN结耗尽加强，增加漏区210侧N型注入区200的抗压能力；所述第二JFET结构的夹断电压高于P型注入区300、N型注入区200以及P型衬底构成的本征JFET结构，使得JFET管不受第二JFET结构影响正常工作；漏区210正电压逐步增强时，本征JFET结构先夹断，漏电流不再随着漏区220电压增加而增加，之后第二JFET结构夹断，进一步增强漏区210侧N型注入区200的抗压能力。
第二实施例
如图2所示，本实施例与第一实施例不同的是，所述P型掺杂区500呈“L”型，靠近所述P型注入区300一侧与所述第一场氧化层410接触，且与栅极电性相连，P型掺杂区500两侧均与N型注入区形成PN结耗尽，使得相同体积的P型掺杂区500，达到的抗压效果更好，或者达到相同抗压效果时所需的P型掺杂区500的体积更小，节省成本；
本实施例P型掺杂区500与第一场氧化层410之间的N型注入区200靠近漏区210侧与漏极电性相连，使得P型掺杂区500与第一场氧化层410之间的N型注入区200形成的PN结反向偏置，耗尽加强，抗压能力加强；
本实施例，部分所述第一场氧化层410上以及与之相连的部分P型注入区300上形成第一多晶硅层610，第一多晶硅层610使得P型注入区300电场均匀分布，增加耐压，且所述P型掺杂区500可通过第一多晶硅层610实现与栅极电性相连；同理，部分所述第一场氧化层410上以及与之相连的部分漏区210上形成第二多晶硅层620，使得漏区300电场均匀分布，增加耐压，且所述P型掺杂区500与第一场氧化层410之间的N型注入区200可通过第二多晶硅层620实现与漏极电性相连。
第三实施例
如图3所示，本实施例相对于第一实施例，所述N型注入区200分为第一N型注入区201和第二N型注入区202，第二N型注入区202形成在P型掺杂区500与P型注入区300之间的第一N型注入区201上表层中，且所述第二N型注入区202多子浓度低于第一N型注入区201，增加N型注入区200表层抗电压能力，所述第二N型注入区202深度大于P型掺杂区500同时小于P型注入区300，增强P型掺杂区500耗尽抗电压能力，同时减小对沟道区载流子浓度的影响，进而减小对导通电流的影响。

Claims (10)

1.一种JFET管，包括：P型衬底，所述P型衬底作为背栅；在所述P型衬底的上表层中形成N型注入区；在所述N型注入区的上表层中形成的P型注入区，所述P型注入区作为正栅；在所述P型注入区的上表层中形成的P型重掺杂区；在所述N型注入区上表层的两端形成的N型重掺杂的漏区和源区，正栅靠近所述源区；所述漏区与所述P型注入区之间的N型注入区上形成的第一场氧化层；所述源区与所述P型注入区之间的N型注入区上形成的第二场氧化层，其特征在于：所述第一场氧化层下的N型注入区上部形成P型掺杂区，所述P型掺杂区靠近P型注入区一侧与栅极电性相连，构成第二JFET结构，所述第二JFET结构的夹断电压高于本征JFET结构。
2.根据权利要求1所述的JFET管，其特征在于：所述整个P型掺杂区与第一场氧化层接触。
3.根据权利要求1所述的JFET管，其特征在于：所述P型掺杂区呈“L”型，靠近所述P型注入区一侧与所述第一场氧化层接触，且与栅极电性相连。
4.根据权利要求3所述的JFET管，其特征在于：所述P型掺杂区与第一场氧化层之间的N型注入区靠近漏区侧与漏极电性相连。
5.根据权利要求1所述的JFET管，其特征在于：部分所述第一场氧化层上以及与之相连的部分P型注入区上形成第一多晶硅层。
6.根据权利要求5所述的JFET管，其特征在于：所述P型掺杂区通过第一多晶硅层与栅极电性相连。
7.根据权利要求1所述的JFET管，其特征在于：部分所述第一场氧化层上以及与之相连的部分漏区上形成第二多晶硅层。
8.根据权利要求7所述的JFET管，其特征在于：所述P型掺杂区呈“L”型，靠近所述P型注入区一侧与所述第一场氧化层接触，且与栅极电性相连，所述P型掺杂区与第一场氧化层之间的N型注入区通过第二多晶硅层与漏极电性相连。
9.根据权利要求1所述的JFET管，其特征在于：所述N型注入区分为第一N型注入区和第二N型注入区，第二N型注入区形成在P型掺杂区与P型注入区之间的第一N型注入区上表层中，且所述第二N型注入区多子浓度低于第一N型注入区。
10.根据权利要求9所述的JFET管，其特征在于：所述第二N型注入区深度大于P型掺杂区同时小于P型注入区。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107403843A (zh) * 2017-07-22 2017-11-28 长沙方星腾电子科技有限公司 一种二极管
CN108417642A (zh) * 2018-02-27 2018-08-17 上海华虹宏力半导体制造有限公司 结型场效应晶体管

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US20160056303A1 (en) * 2012-05-25 2016-02-25 Taiwan Semiconductor Manufacturing Company, Ltd. Bootstrap MOS for High Voltage Applications
CN105810680A (zh) * 2016-03-15 2016-07-27 上海华虹宏力半导体制造有限公司 Jfet及其制造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0805499A2 (en) * 1992-08-17 1997-11-05 Fuji Electric Co., Ltd. High withstand voltage M I S field effect transistor and semiconductor integrated circuit
CN103178093A (zh) * 2011-12-26 2013-06-26 上海华虹Nec电子有限公司 高压结型场效应晶体管的结构及制备方法
US20160056303A1 (en) * 2012-05-25 2016-02-25 Taiwan Semiconductor Manufacturing Company, Ltd. Bootstrap MOS for High Voltage Applications
CN105810680A (zh) * 2016-03-15 2016-07-27 上海华虹宏力半导体制造有限公司 Jfet及其制造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107403843A (zh) * 2017-07-22 2017-11-28 长沙方星腾电子科技有限公司 一种二极管
CN108417642A (zh) * 2018-02-27 2018-08-17 上海华虹宏力半导体制造有限公司 结型场效应晶体管

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