CN107403843A - 一种二极管 - Google Patents

一种二极管 Download PDF

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Publication number
CN107403843A
CN107403843A CN201710603032.4A CN201710603032A CN107403843A CN 107403843 A CN107403843 A CN 107403843A CN 201710603032 A CN201710603032 A CN 201710603032A CN 107403843 A CN107403843 A CN 107403843A
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diode
diffusion layer
type
hole
types
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不公告发明人
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Changsha Party Xingteng Electronic Technology Co Ltd
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Changsha Party Xingteng Electronic Technology Co Ltd
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Priority to CN201710603032.4A priority Critical patent/CN107403843A/zh
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

本发明提供了一种二极管，属于半导体集成电路技术领域。包括：P+型扩散层、N+型扩散层、第一通孔CONTACT1、第二通孔CONTACT2和P‑型多晶硅；P+型扩散层和N+型扩散层分列在上下两端，P‑型多晶硅POLY将它们联系在一起，并与它们有一定的交叠；P‑型多晶硅通过第一通孔CONTACT1与P+型扩散层相连，P‑型多晶硅通过第二通孔CONTACT2与N+型扩散层相连。本发明的二极管，与传统的二极管相比，在正向导通时，由于电流通过P‑型多晶硅传输，并不会产生寄生三极管，不会导致漏电，从而有效的实现了二极管的单向导通特性。

Description

一种二极管
技术领域
本发明属于半导体集成电路技术领域，具体涉及一种二极管。
背景技术
二极管是一种能够单向传导电流的电子器件。在半导体二极管内部有一个PN结两个引线端子，这种电子器件按照外加电压的方向，具备单向电流的传导性。
二极管由于其单向导电的特性，在芯片内部起到了非常重要的作用。所以，芯片内集成二极管在实际中的应用也越来越广泛。传统的芯片内集成二极管，P型扩散层作为二极管的正端，N型阱作为二极管的负端。这种传统的二极管，在正向导通时，会触发P型扩散层、N型阱与P型衬底形成的PNP型三极管，从而引起漏电。
发明内容
为解决现有芯片内集成的二极管导通时会引起寄生三极管漏电的技术问题，本发明提供了一种芯片内集成二极管。
一种二极管，包括：P+型扩散层、N+型扩散层、第一通孔CONTACT1、第二通孔CONTACT2和P-型多晶硅；P+型扩散层和N+型扩散层分列在上下两端，P-型多晶硅POLY将它们联系在一起，并与它们有一定的交叠；P-型多晶硅通过第一通孔CONTACT1与P+型扩散层相连，P-型多晶硅通过第二通孔CONTACT2与N+型扩散层相连。
本发明的二极管，与传统的二极管相比，在正向导通时，由于电流通过P-型多晶硅传输，并不会产生寄生三极管，不会导致漏电，从而有效的实现了二极管的单向导通特性。
附图说明
图1是本发明实施方式提供的二极管结构示意图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚明了，下面结合具体实施方式并参照附图，对本发明进一步详细说明。应该理解，这些描述只是示例性的，而并非要限制本发明的范围。此外，在以下说明中，省略了对公知结构和技术的描述，以避免不必要地混淆本发明的概念。
为解决现有芯片内集成的二极管导通时会引起寄生三极管漏电的技术问题，本发明提供了一种芯片内集成二极管。
一种二极管，包括：P+型扩散层、N+型扩散层、第一通孔CONTACT1、第二通孔CONTACT2和P-型多晶硅；从剖面图上来看，P+型扩散层和N+型扩散层分列在上下两端，P-型多晶硅POLY将它们联系在一起，并与它们有一定的交叠；P-型多晶硅通过第一通孔CONTACT1与P+型扩散层相连，P-型多晶硅通过第二通孔CONTACT2与N+型扩散层相连。
本发明的二极管，与传统的二极管相比，在正向导通时，由于电流通过P-型多晶硅传输，并不会产生寄生三极管，不会导致漏电，从而有效的实现了二极管的单向导通特性。
应当理解的是，本发明的上述具体实施方式仅仅用于示例性说明或解释本发明的原理，而不构成对本发明的限制。因此，在不偏离本发明的精神和范围的情况下所做的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。此外，本发明所附权利要求旨在涵盖落入所附权利要求范围和边界、或者这种范围和边界的等同形式内的全部变化和修改例。

Claims (1)

1.一种二极管，其特征在于，包括：P+型扩散层、N+型扩散层、第一通孔CONTACT1、第二通孔CONTACT2和P-型多晶硅；P+型扩散层和N+型扩散层分列在上下两端，P-型多晶硅POLY将它们联系在一起，并与它们有一定的交叠；P-型多晶硅通过第一通孔CONTACT1与P+型扩散层相连，P-型多晶硅通过第二通孔CONTACT2与N+型扩散层相连。
CN201710603032.4A 2017-07-22 2017-07-22 一种二极管 Pending CN107403843A (zh)

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CN107403843A true CN107403843A (zh) 2017-11-28

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN201041804Y (zh) * 2007-03-05 2008-03-26 浙江大学 一种静电放电防护器件
CN105590960A (zh) * 2015-12-28 2016-05-18 电子科技大学 超高速大电流横向绝缘栅双极型晶体管
CN106449633A (zh) * 2016-09-23 2017-02-22 矽力杰半导体技术(杭州)有限公司 瞬态电压抑制器及其制造方法
CN106449768A (zh) * 2016-11-25 2017-02-22 东莞市联洲知识产权运营管理有限公司 一种jfet管

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN201041804Y (zh) * 2007-03-05 2008-03-26 浙江大学 一种静电放电防护器件
CN105590960A (zh) * 2015-12-28 2016-05-18 电子科技大学 超高速大电流横向绝缘栅双极型晶体管
CN106449633A (zh) * 2016-09-23 2017-02-22 矽力杰半导体技术(杭州)有限公司 瞬态电压抑制器及其制造方法
CN106449768A (zh) * 2016-11-25 2017-02-22 东莞市联洲知识产权运营管理有限公司 一种jfet管

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