WO2019000488A1 - 低温多晶硅阵列基板及其制作方法 - Google Patents

低温多晶硅阵列基板及其制作方法 Download PDF

Info

Publication number
WO2019000488A1
WO2019000488A1 PCT/CN2017/092507 CN2017092507W WO2019000488A1 WO 2019000488 A1 WO2019000488 A1 WO 2019000488A1 CN 2017092507 W CN2017092507 W CN 2017092507W WO 2019000488 A1 WO2019000488 A1 WO 2019000488A1
Authority
WO
WIPO (PCT)
Prior art keywords
scale
tin oxide
indium tin
low temperature
oxide layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2017/092507
Other languages
English (en)
French (fr)
Inventor
刘凤举
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wuhan China Star Optoelectronics Technology Co Ltd
Original Assignee
Wuhan China Star Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wuhan China Star Optoelectronics Technology Co Ltd filed Critical Wuhan China Star Optoelectronics Technology Co Ltd
Publication of WO2019000488A1 publication Critical patent/WO2019000488A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • the present invention relates to the field of substrate fabrication technology, and in particular, to a low temperature polysilicon array substrate and a method of fabricating the same.
  • BITO Backside Indium Tin Oxide
  • P-SiN plasma silicon nitride
  • the BITO Mask blade is prone to plasma.
  • the phenomenon of silicon nitride falling off, the falling material forms foreign matter in the box in the subsequent panel process, resulting in product scrapping.
  • the main reason is that the coverage of the plasma silicon nitride and the stepped BITO edge is poor, resulting in poor adhesion of the plasma silicon nitride.
  • the present invention provides a low temperature polysilicon array substrate and a method for fabricating the same.
  • a low temperature polysilicon array substrate comprising a low temperature polysilicon thin film transistor, a flat layer over the low temperature polysilicon thin film transistor, a back-plated indium tin oxide layer, and an insulating layer on the surface of the back-plated indium tin oxide layer; the back-plated indium tin oxide layer A scale mark is formed thereon, and the scale mark is a hollow pattern formed on the back-plated indium tin oxide layer, and the insulation layer is attached to the surface of the back-plated indium tin oxide layer and completely covers the scale mark.
  • a low temperature polysilicon array substrate comprising a low temperature polysilicon thin film transistor, a flat layer over the low temperature polysilicon thin film transistor, a back-plated indium tin oxide layer, and an insulating layer on the surface of the back-plated indium tin oxide layer;
  • a scale mark is formed on the back-plated indium tin oxide layer; the insulating layer is hollowed out to expose an intermediate portion of the scale mark.
  • the insulating layer is a ring-shaped annular structure disposed along an edge of the back-plated indium tin oxide layer.
  • the tick mark includes a first first hole extending in a first direction and a plurality of second second holes extending in a second direction, the first scale and the first scale The second scale cross setting.
  • the first scale and the second scale are perpendicular to each other.
  • the back-plated indium tin oxide layer is chamfered at the end of the second scale.
  • the back-plated indium tin oxide layer is chamfered at a sidewall of the first scale and the second scale.
  • the back-plated indium tin oxide layer is chamfered at the intersection of the first scale and the second scale.
  • Another object of the present invention is to provide a method for fabricating a low temperature polysilicon array substrate, comprising:
  • the back-plated indium tin oxide layer is formed with a scale mark, and the scale mark is a hollow pattern formed on the back-plated indium tin oxide layer, and the insulating layer is attached to the back-plated indium tin oxide layer. Surface and completely cover the tick marks.
  • a method for fabricating a low temperature polysilicon array substrate comprising:
  • the back-plated indium tin oxide layer is formed with a tick mark, and the insulating layer is hollowed out to The middle portion of the tick mark is exposed.
  • the method for fabricating the low temperature polysilicon array substrate of the invention is simple, and the special design of the scale mark on the back-plated indium tin oxide layer and the insulating layer thereon can effectively improve the phenomenon of ion silicon nitride falling off and greatly improve the substrate product. Yield.
  • FIG. 1 is a schematic structural view of a low temperature polysilicon array substrate according to the present invention.
  • FIG. 2 is a schematic structural view of a BITO layer according to Embodiment 1 of the present invention.
  • FIG. 3 is a schematic view showing a partial manufacturing process of a low temperature polysilicon array substrate according to Embodiment 1 of the present invention
  • FIG. 4 is a schematic structural view of another BITO layer according to Embodiment 1 of the present invention.
  • FIG. 5 is a schematic structural view of a BITO layer according to Embodiment 2 of the present invention.
  • FIG. 6 is a schematic view showing a partial manufacturing process of a low temperature polysilicon array substrate according to Embodiment 2 of the present invention.
  • FIG. 7 is a schematic structural view of another BITO layer according to Embodiment 2 of the present invention.
  • the low temperature polysilicon array substrate of the present invention comprises a low temperature polysilicon thin film transistor 10, a planar layer 20 over the low temperature polysilicon thin film transistor 10, a back-plated indium tin oxide layer 30, and an insulating layer 40 on the surface of the back-plated indium tin oxide layer 30.
  • the back-plated indium tin oxide layer 30 is formed with a scale mark as a mask for shielding the scale, and the scale mark of the back-plated indium tin oxide layer 30 is compared with the flat layer below the back-plated indium tin oxide layer 30.
  • the pattern formed after the upper exposure of 20 judges the exposure shift amount.
  • the scale mark of the present embodiment is a hollow pattern formed on the back-plated indium tin oxide layer 30.
  • the insulating layer 40 is attached to the surface of the back-plated indium tin oxide layer 30 and completely covers the scale mark.
  • the scale mark includes a hole-shaped first scale 31 extending in a first direction and a plurality of aperture-shaped second scales 32 extending in a second direction, the first scale 31 and the second scale 32 intersecting. Since the insulating layer 40 completely covers the scale mark, the back-plated indium tin oxide layer 30 and the insulating layer 40 have the largest contact area, and the circumference of the first scale 31 and the second scale 32 of the back-plated indium tin oxide layer 30 can be maximized. Ground-bonded to the insulation layer 40 The surface has strong adhesion.
  • first scale 31 and the second scale 32 are perpendicular to each other, and the first scale 31 serves as a long hole extending through the length direction of the back-plated indium tin oxide layer 30, and all the second scales 32 are joined together.
  • a scale 31 serves as a symmetrical centerline for each of the second scales 32, each of which extends a portion of the second scale 32.
  • the embodiment further provides a method for fabricating a low temperature polysilicon array substrate, which mainly includes:
  • the back-plated indium tin oxide layer 30 is formed with a scale mark, and the scale mark is a hollow pattern formed on the back-plated indium tin oxide layer 30.
  • the insulating layer 40 is attached to the surface of the back-plated indium tin oxide layer 30 and completely covers the tick mark.
  • the material of the insulating layer 40 is ion silicon nitride.
  • the insulating layer 40 is attached and completely covered with the scale mark of the back-plated indium tin oxide layer 30, the stepped edge at the boundary of the scale mark still has strong adhesion, and the surrounding insulating layer 40 does not easily fall off, thereby improving the low temperature. Yield of polysilicon array substrate products.
  • FIG. 4 is a schematic structural view of another back-plated indium tin oxide layer of the present embodiment.
  • the end of the second scale 32 of the elongated hole shape is chamfered.
  • the first scale 31 and the inner side wall of the second scale 32 are chamfered, and the intersection of the first scale 31 and the second scale 32 is also chamfered, wherein the chamfer is preferably rounded.
  • the end of the second scale 32, the intersection of the first scale 31 and the second scale 32 is chamfered such that the boundary contour of the first scale 31 and the second scale 32 has greater contact with the upper insulating layer 40.
  • the area is more natural and does not have a right angle, and the adhesion of the weak portion can be further improved.
  • the inner side walls of the first scale 31 and the second scale 32 are chamfered, that is, the indium tin oxide is back-plated.
  • the thickness direction of the layer 30 (especially toward the side of the insulating layer 40) is obliquely chamfered, and the oblique direction is flared toward the insulating layer 40, so that the hollow sidewall of the back-plated indium tin oxide layer 30 has an inclined upper surface.
  • the scale mark has a certain slope from the cross-sectional direction.
  • the insulating layer 40 of the present embodiment is hollowed out to expose the intermediate portion of the scale mark.
  • the back-plated indium tin oxide layer 30 is formed as a scale structure, and is formed by connecting a first first hole 31 extending in a first direction and a plurality of second second holes 32 extending in a second direction.
  • the scale 31 is disposed across the second scale 32.
  • the insulating layer 40 is a ring-shaped closed ring structure disposed along the edge of the back-plated indium tin oxide layer 30.
  • the flat layer 20 is rectangular, and the insulating layer 40 is formed as a closed frame.
  • first scale 31 and the second scale 32 are perpendicular to each other, and the first scale 31 is a strip extending through the length direction of the back-plated indium tin oxide layer 30, and all the second scales 32 are joined together.
  • a scale 31 serves as a symmetrical centerline for each of the second scales 32, each of which extends a portion of the second scale 32.
  • the embodiment further provides a method for fabricating a low temperature polysilicon array substrate, which mainly includes:
  • the back-plated indium tin oxide layer 30 is formed with a scale mark, and the insulating layer 40 is hollowed out to expose the intermediate portion of the scale mark.
  • the material of the insulating layer 40 is ion-based silicon nitride.
  • the insulating layer 40 since the insulating layer 40 only has a ring-shaped annular structure disposed along the edge of the back-plated indium tin oxide layer 30, the annular structure is pasted and covered with a scale mark on the periphery of the back-plated indium tin oxide layer 30, and the scale of the back-plated indium tin oxide layer 30 is The mark is not covered, so that the phenomenon that the insulating layer 40 falls off in the low temperature polysilicon array substrate does not occur, and thus the yield of the low temperature polysilicon array substrate product is also improved.
  • the back-plated indium tin oxide layer 30 is chamfered at the end of the second scale 32 (rounded or inverted)
  • the first scale 31 and the side surface of the second scale 32 are chamfered, and the intersection of the first scale 31 and the second scale 32 is also chamfered.
  • the end of the second scale 32, the intersection of the first scale 31 and the second scale 32 is chamfered such that the boundary contour of the first scale 31 and the second scale 32 has greater contact with the upper insulating layer 40.
  • the area is more natural and does not have a right angle, and the adhesion of the weak portion can be further improved.
  • the inner side walls of the first scale 31 and the second scale 32 are chamfered so that the scale marks are viewed from the cross section. Having a certain slope, after plating the insulating layer 40, a part of the ionized silicon nitride material can be filled on the chamfered surface, further increasing the adhesion area, and indirectly improving the adhesion strength of the back-plated indium tin oxide layer 30 and the insulating layer 40. .
  • the low-temperature polysilicon array substrate of the present invention is simple in manufacturing method, and the ion-exchanged silicon nitride falling off phenomenon can be effectively improved by specially designing the scale mark on the back-plated indium tin oxide layer and the insulating layer thereon. Significantly increase the yield of substrate products.

Landscapes

  • Thin Film Transistor (AREA)

Abstract

一种低温多晶硅阵列基板，包括低温多晶硅薄膜晶体管（10）、低温多晶硅薄膜晶体管（10）上方的平坦层（20）、背镀氧化铟锡层（30）、以及背镀氧化铟锡层（30）表面的绝缘层（40）；背镀氧化铟锡层（30）上形成有刻度标记，刻度标记为背镀氧化铟锡层（30）上开设的镂空图案，绝缘层（40）贴合在背镀氧化铟锡层（30）表面并完全覆盖刻度标记，或者绝缘层（40）镂空设置，露出刻度标记的中间区域。低温多晶硅阵列基板制作方法简单，通过将背镀氧化铟锡层（30）上的刻度标记与其上的绝缘层（40）经过特别设计后，可以有效地改善离子体氮化硅脱落现象，大幅提高基板产品的良率。

Description

低温多晶硅阵列基板及其制作方法 技术领域
本发明涉及基板制作技术领域，尤其涉及一种低温多晶硅阵列基板及其制作方法。
背景技术
LTPS(Low Temperature Poly-silicon，即低温多晶硅)制程中，在显影时为控制曝光的偏移，需要使用Mask blade(掩模板遮挡板)设计来检测曝光偏移量。
BITO(Back side Indium tin oxide，即背镀氧化铟锡)的下一制程是镀P-SiN(等离子体氮化硅)绝缘膜，在实际生产中发现镀膜制程后，BITO Mask blade容易发生等离子体氮化硅脱落的现象，脱落的材料在后续面板制程中形成盒内异物，造成产品报废。其主要原因是等离子体氮化硅和阶梯形状的BITO边缘的覆盖性不佳，造成等离子体氮化硅附着性不佳。
发明内容
鉴于现有技术存在的不足，本发明提供了一种改善离子体氮化硅脱落现象的低温多晶硅阵列基板及其制作方法。
为了实现上述的目的，本发明采用了如下的技术方案：
一种低温多晶硅阵列基板，包括低温多晶硅薄膜晶体管、低温多晶硅薄膜晶体管上方的平坦层、背镀氧化铟锡层以及所述背镀氧化铟锡层表面的绝缘层；所述背镀氧化铟锡层上形成有刻度标记，所述刻度标记为所述背镀氧化铟锡层上开设的镂空图案，所述绝缘层贴合在所述背镀氧化铟锡层表面并完全覆盖所述刻度标记。
本发明提供的另一种技术方案是：
一种低温多晶硅阵列基板，包括低温多晶硅薄膜晶体管、低温多晶硅薄膜晶体管上方的平坦层、背镀氧化铟锡层以及所述背镀氧化铟锡层表面的绝缘层； 所述背镀氧化铟锡层上形成有刻度标记；所述绝缘层镂空设置，露出所述刻度标记的中间区域。
作为其中一种实施方式，所述绝缘层为沿所述背镀氧化铟锡层边缘设置的一圈封闭的环形结构。
作为其中一种实施方式，所述刻度标记包括一条第一方向延伸的孔状的第一刻度和若干条沿第二方向延伸的孔状的第二刻度，所述第一刻度与所述第二刻度交叉设置。
作为其中一种实施方式，所述第一刻度与所述第二刻度相互垂直。
作为其中一种实施方式，所述背镀氧化铟锡层在所述第二刻度的端部倒角设置。
作为其中一种实施方式，所述背镀氧化铟锡层在所述第一刻度与所述第二刻度的侧壁倒角设置。
作为其中一种实施方式，所述背镀氧化铟锡层在所述第一刻度与所述第二刻度的交叉处倒角设置。
本发明的另一目的在于提供一种低温多晶硅阵列基板的制作方法，包括：
制作平坦层；
在所述平坦层上制作背镀氧化铟锡层；
在所述背镀氧化铟锡层上制作绝缘层；
其中，所述背镀氧化铟锡层上制作有刻度标记，所述刻度标记为所述背镀氧化铟锡层上开设的镂空图案，所述绝缘层贴合在所述背镀氧化铟锡层表面并完全覆盖所述刻度标记。
本发明提供的另一种技术方案是：
一种低温多晶硅阵列基板的制作方法，包括：
制作平坦层；
在所述平坦层上制作背镀氧化铟锡层；
在所述背镀氧化铟锡层上制作绝缘层；
其中，所述背镀氧化铟锡层上制作有刻度标记，所述绝缘层镂空设置，以 露出所述刻度标记的中间区域。
本发明的低温多晶硅阵列基板制作方法简单，通过将背镀氧化铟锡层上的刻度标记与其上的绝缘层经过特别设计后，可以有效地改善离子体氮化硅脱落现象，大幅提高基板产品的良率。
附图说明
图1为本发明的一种低温多晶硅阵列基板的结构示意图；
图2为本发明实施例1的BITO层的结构示意图；
图3为本发明实施例1的低温多晶硅阵列基板的部分制作过程示意图；
图4为本发明实施例1的另一种BITO层的结构示意图；
图5为本发明实施例2的BITO层的结构示意图；
图6为本发明实施例2的低温多晶硅阵列基板的部分制作过程示意图；
图7为本发明实施例2的另一种BITO层的结构示意图。
具体实施方式
为了使本发明的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本发明进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
参阅图1，本发明的低温多晶硅阵列基板包括低温多晶硅薄膜晶体管10、位于低温多晶硅薄膜晶体管10上方的平坦层20、背镀氧化铟锡层30以及背镀氧化铟锡层30表面的绝缘层40。其中，背镀氧化铟锡层30上形成有刻度标记，以作为掩模板遮挡板，用以作为检测曝光偏移量的标尺，通过对比背镀氧化铟锡层30的刻度标记与其下方的平坦层20上曝光后形成的图案判断曝光偏移量。
实施例1
如图2所示，本实施例的刻度标记为背镀氧化铟锡层30上开设的镂空图案，绝缘层40贴合在背镀氧化铟锡层30表面，并完全覆盖刻度标记。该刻度标记包括一条第一方向延伸的孔状的第一刻度31和若干条沿第二方向延伸的孔状的第二刻度32，第一刻度31与第二刻度32交叉设置。由于绝缘层40完全覆盖刻度标记，使得背镀氧化铟锡层30与绝缘层40具有最大的接触面积，背镀氧化铟锡层30的第一刻度31、第二刻度32的周围能最大限度地贴合在绝缘层40表 面，具有较强的附着性。
本实施例中，第一刻度31与第二刻度32相互垂直，第一刻度31作为贯穿背镀氧化铟锡层30长度方向的长孔，将所有的第二刻度32衔接在一起，第一刻度31作为每条第二刻度32的对称中心线，其每侧各延伸有第二刻度32的一部分。
如图3所示，本实施例还提供一种低温多晶硅阵列基板的制作方法，主要包括：
制作平坦层20；
在平坦层20上制作背镀氧化铟锡层30；
在背镀氧化铟锡层30上制作绝缘层40；
其中，背镀氧化铟锡层30上制作有刻度标记，刻度标记为背镀氧化铟锡层30上开设的镂空图案，绝缘层40贴合在背镀氧化铟锡层30表面并完全覆盖刻度标记，绝缘层40的材料为离子体氮化硅。
由于绝缘层40贴合并完全覆盖背镀氧化铟锡层30的刻度标记，刻度标记的边界处的阶梯状边缘仍具有较强的附着力，其周围的绝缘层40不容易脱落，因此提高了低温多晶硅阵列基板产品的良率。
如图4所示，为本实施例的另一种背镀氧化铟锡层的结构示意图，在该背镀氧化铟锡层30中，长孔形的第二刻度32的端部倒角设置。第一刻度31与第二刻度32的内侧壁倒角设置，第一刻度31与第二刻度32的交叉处也倒角设置，其中，倒角最好是倒圆角。第二刻度32的端部、第一刻度31与第二刻度32的交叉处倒角设置使得第一刻度31与第二刻度32的边界轮廓处与上方的绝缘层40具有更大的接触面积，贴合更自然而不会出现直角，可以进一步提高该受力薄弱处的附着力，另外，第一刻度31与第二刻度32的内侧壁倒角设置，即在背镀氧化铟锡层30的厚度方向上(尤其是朝向绝缘层40一侧)做倾斜的倒角，倾斜方向朝向绝缘层40呈喇叭状开口，使得背镀氧化铟锡层30的镂空侧壁具有倾斜的上表面，刻度标记从截面方向看具有一定的坡度，在镀附绝缘层40后，一部分离子体氮化硅材料可以填充在该倒角面上，进一步增加附着面积，间接提高背镀氧化铟锡层30与绝缘层40的附着强度。
实施例2
结合图5和图6所示，与实施例1不同，本实施例的绝缘层40镂空设置，露出刻度标记的中间区域。而背镀氧化铟锡层30形成为标尺结构，由一条第一方向延伸的孔状的第一刻度31和若干条沿第二方向延伸的孔状的第二刻度32连接而成，第一刻度31与第二刻度32交叉设置。绝缘层40为沿背镀氧化铟锡层30边缘设置的一圈封闭的环形结构，这里，平坦层20为矩形，绝缘层40则形成为一圈封闭的边框。
本实施例中，第一刻度31与第二刻度32相互垂直，第一刻度31作为贯穿背镀氧化铟锡层30长度方向的长条，将所有的第二刻度32衔接在一起，第一刻度31作为每条第二刻度32的对称中心线，其每侧各延伸有第二刻度32的一部分。
如图6，本实施例还提供一种低温多晶硅阵列基板的制作方法，主要包括：
制作平坦层20；
在平坦层20上制作背镀氧化铟锡层30；
在背镀氧化铟锡层30上制作绝缘层40；
其中，背镀氧化铟锡层30上制作有刻度标记，绝缘层40镂空设置，以露出刻度标记的中间区域，绝缘层40的材料为离子体氮化硅。
由于绝缘层40仅仅只有沿背镀氧化铟锡层30边缘设置的一圈环形结构，该环形结构贴合并覆盖背镀氧化铟锡层30外围的刻度标记，背镀氧化铟锡层30中部的刻度标记并不被覆盖，因此不会发生绝缘层40脱落在低温多晶硅阵列基板内的现象，因此也提高了低温多晶硅阵列基板产品的良率。
如图7所示，为本实施例的另一种背镀氧化铟锡层的结构示意图，该背镀氧化铟锡层30在第二刻度32的端部倒角设置(倒圆角或倒斜角)，第一刻度31与第二刻度32的侧壁倒角设置，第一刻度31与第二刻度32的交叉处也倒角设置。第二刻度32的端部、第一刻度31与第二刻度32的交叉处倒角设置使得第一刻度31与第二刻度32的边界轮廓处与上方的绝缘层40具有更大的接触面积，贴合更自然而不会出现直角，可以进一步提高该受力薄弱处的附着力，另外，第一刻度31与第二刻度32的内侧壁倒角设置，使得刻度标记从截面方向看具有一定的坡度，在镀附绝缘层40后，一部分离子体氮化硅材料可以填充在该倒角面上，进一步增加附着面积，间接提高背镀氧化铟锡层30与绝缘层40的附着强度。
综上所述，本发明的低温多晶硅阵列基板制作方法简单，通过将背镀氧化铟锡层上的刻度标记与其上的绝缘层经过特别设计后，可以有效地改善离子体氮化硅脱落现象，大幅提高基板产品的良率。
以上所述仅是本申请的具体实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本申请原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本申请的保护范围。

Claims (19)

  1. 一种低温多晶硅阵列基板，其中，包括低温多晶硅薄膜晶体管、低温多晶硅薄膜晶体管上方的平坦层、背镀氧化铟锡层以及所述背镀氧化铟锡层表面的绝缘层；所述背镀氧化铟锡层上形成有刻度标记，所述刻度标记为所述背镀氧化铟锡层上开设的镂空图案，所述绝缘层贴合在所述背镀氧化铟锡层表面并完全覆盖所述刻度标记。
  2. 根据权利要求1所述的低温多晶硅阵列基板，其中，所述刻度标记包括一条第一方向延伸的第一刻度和若干条沿第二方向延伸的第二刻度，所述第一刻度与所述第二刻度交叉设置。
  3. 根据权利要求2所述的低温多晶硅阵列基板，其中，所述第一刻度与所述第二刻度相互垂直。
  4. 根据权利要求2所述的低温多晶硅阵列基板，其中，所述背镀氧化铟锡层在所述第二刻度的端部倒角设置。
  5. 根据权利要求2所述的低温多晶硅阵列基板，其中，所述背镀氧化铟锡层在所述第一刻度与所述第二刻度的侧壁倒角设置。
  6. 根据权利要求2所述的低温多晶硅阵列基板，其中，所述背镀氧化铟锡层在所述第一刻度与所述第二刻度的交叉处倒角设置。
  7. 一种低温多晶硅阵列基板，其中，包括低温多晶硅薄膜晶体管、低温多晶硅薄膜晶体管上方的平坦层、背镀氧化铟锡层以及所述背镀氧化铟锡层表面的绝缘层；所述背镀氧化铟锡层上形成有刻度标记；所述绝缘层镂空设置，露出所述刻度标记的中间区域。
  8. 根据权利要求7所述的低温多晶硅阵列基板，其中，所述绝缘层为沿所述背镀氧化铟锡层边缘设置的一圈封闭的环形结构。
  9. 根据权利要求7所述的低温多晶硅阵列基板，其中，所述刻度标记包括一条第一方向延伸的孔状的第一刻度和若干条沿第二方向延伸的孔状的第二刻度，所述第一刻度与所述第二刻度交叉设置。
  10. 根据权利要求9所述的低温多晶硅阵列基板，其中，所述第一刻度与所述第二刻度相互垂直。
  11. 根据权利要求9所述的低温多晶硅阵列基板，其中，所述背镀氧化铟锡层在所述第二刻度的端部倒角设置。
  12. 根据权利要求9所述的低温多晶硅阵列基板，其中，所述背镀氧化铟锡层在所述第一刻度与所述第二刻度的侧壁倒角设置。
  13. 根据权利要求9所述的低温多晶硅阵列基板，其中，所述背镀氧化铟锡层在所述第一刻度与所述第二刻度的交叉处倒角设置。
  14. 一种低温多晶硅阵列基板的制作方法，其中，包括：
    制作平坦层；
    在所述平坦层上制作背镀氧化铟锡层；
    在所述背镀氧化铟锡层上制作绝缘层；
    其中，所述背镀氧化铟锡层上制作有刻度标记；且所述绝缘层镂空设置，以露出所述刻度标记的中间区域，或者，所述刻度标记为所述背镀氧化铟锡层上开设的镂空图案，所述绝缘层贴合在所述背镀氧化铟锡层表面并完全覆盖所述刻度标记。
  15. 根据权利要求14所述的低温多晶硅阵列基板，其中，所述刻度标记包括一条第一方向延伸的第一刻度和若干条沿第二方向延伸的第二刻度，所述第一刻度与所述第二刻度交叉设置。
  16. 根据权利要求15所述的低温多晶硅阵列基板，其中，所述第一刻度与所述第二刻度相互垂直。
  17. 根据权利要求15所述的低温多晶硅阵列基板，其中，所述背镀氧化铟锡层在所述第二刻度的端部倒角设置。
  18. 根据权利要求15所述的低温多晶硅阵列基板，其中，所述背镀氧化铟锡层在所述第一刻度与所述第二刻度的侧壁倒角设置。
  19. 根据权利要求15所述的低温多晶硅阵列基板，其中，所述背镀氧化铟锡层在所述第一刻度与所述第二刻度的交叉处倒角设置。
PCT/CN2017/092507 2017-06-28 2017-07-11 低温多晶硅阵列基板及其制作方法 Ceased WO2019000488A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201710505494.2A CN107275344B (zh) 2017-06-28 2017-06-28 低温多晶硅阵列基板及其制作方法
CN201710505494.2 2017-06-28

Publications (1)

Publication Number Publication Date
WO2019000488A1 true WO2019000488A1 (zh) 2019-01-03

Family

ID=60070793

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/092507 Ceased WO2019000488A1 (zh) 2017-06-28 2017-07-11 低温多晶硅阵列基板及其制作方法

Country Status (2)

Country Link
CN (1) CN107275344B (zh)
WO (1) WO2019000488A1 (zh)

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6307611B1 (en) * 1998-06-30 2001-10-23 Hyundai Electronics Industries Co., Ltd. Method for manufacturing pixel electrodes of liquid crystal display
CN1787153A (zh) * 2004-12-10 2006-06-14 三星Sdi株式会社 等离子体显示面板及其制造方法
CN102636962A (zh) * 2011-12-12 2012-08-15 北京京东方光电科技有限公司 一种空间成像套刻检验方法及阵列基板
CN104078423A (zh) * 2014-06-24 2014-10-01 京东方科技集团股份有限公司 一种阵列基板的制造方法、阵列基板及显示装置
CN105428332A (zh) * 2015-12-28 2016-03-23 昆山国显光电有限公司 低温多晶硅阵列基板及其制作方法
CN106169441A (zh) * 2016-08-22 2016-11-30 武汉华星光电技术有限公司 改善bito断裂的阵列基板及其制作方法与液晶显示面板
CN106229347A (zh) * 2016-08-24 2016-12-14 武汉华星光电技术有限公司 一种低温多晶硅薄膜晶体管及其制造方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4029884B2 (ja) * 2005-03-29 2008-01-09 セイコーエプソン株式会社 半導体装置の製造方法
CN102054667B (zh) * 2009-10-29 2012-11-07 北大方正集团有限公司 应用光刻胶剥离工艺保护光刻对准标记的方法
CN102931171B (zh) * 2012-11-08 2015-04-29 杭州士兰集成电路有限公司 一种外延标记及其相应的制作方法
CN106711181B (zh) * 2016-12-29 2020-02-14 固安翌光科技有限公司 一种邦定电极及其制备方法和应用
CN106898617B (zh) * 2017-03-20 2020-06-30 合肥京东方光电科技有限公司 基板及其制备方法、显示面板和显示装置

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6307611B1 (en) * 1998-06-30 2001-10-23 Hyundai Electronics Industries Co., Ltd. Method for manufacturing pixel electrodes of liquid crystal display
CN1787153A (zh) * 2004-12-10 2006-06-14 三星Sdi株式会社 等离子体显示面板及其制造方法
CN102636962A (zh) * 2011-12-12 2012-08-15 北京京东方光电科技有限公司 一种空间成像套刻检验方法及阵列基板
CN104078423A (zh) * 2014-06-24 2014-10-01 京东方科技集团股份有限公司 一种阵列基板的制造方法、阵列基板及显示装置
CN105428332A (zh) * 2015-12-28 2016-03-23 昆山国显光电有限公司 低温多晶硅阵列基板及其制作方法
CN106169441A (zh) * 2016-08-22 2016-11-30 武汉华星光电技术有限公司 改善bito断裂的阵列基板及其制作方法与液晶显示面板
CN106229347A (zh) * 2016-08-24 2016-12-14 武汉华星光电技术有限公司 一种低温多晶硅薄膜晶体管及其制造方法

Also Published As

Publication number Publication date
CN107275344B (zh) 2019-12-31
CN107275344A (zh) 2017-10-20

Similar Documents

Publication Publication Date Title
CN106158917A (zh) 发光显示背板、有机发光显示器及其制作方法
JP2008517448A5 (zh)
CN109742151A (zh) 薄膜晶体管及其制作方法、阵列基板和显示面板
WO2019184265A1 (zh) 掩模板及显示面板
WO2020077861A1 (zh) 一种阵列基板及其制备方法
CN113517180B (zh) 掩膜版版图的修正方法及掩膜版版图
WO2019000488A1 (zh) 低温多晶硅阵列基板及其制作方法
US20150044424A1 (en) Bottom electrode and manufacturing method thereof
TWI578420B (zh) 半導體結構及其製作方法
CN104091807B (zh) 一种阵列基板及其制作方法、显示装置
TWI542722B (zh) 用於濺鍍製程之夾具與濺鍍半導體封裝件之方法
JPS5661170A (en) Preparation of field effect transistor
JP2013171943A5 (zh)
KR20100078312A (ko) 네거티브 포토레지스트를 이용한 에어브릿지 제조방법
CN104425296B (zh) 半导体装置以及半导体装置的制造方法
CN104062783B (zh) 基板检测用定位图形及其制造方法
CN105977206A (zh) 一种阵列基板的制造方法及阵列基板
CN107447190A (zh) 一种金属掩膜及其制备方法
CN105390509B (zh) 一种阵列基板的制作方法、阵列基板及液晶面板
CN204315620U (zh) Led结构
CN105140240A (zh) 柔性基板及其制作方法、显示装置
TW201703301A (zh) 主動元件及其製作方法
CN106653686B (zh) 薄膜晶体管及其制备方法、阵列基板、显示设备
JP2008277637A (ja) チップ抵抗器
WO2019019728A1 (zh) 掩膜板

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17916102

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 17916102

Country of ref document: EP

Kind code of ref document: A1