WO2018227963A1 - 像素电路及其驱动方法、阵列基板以及显示装置 - Google Patents

像素电路及其驱动方法、阵列基板以及显示装置 Download PDF

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Publication number
WO2018227963A1
WO2018227963A1 PCT/CN2018/072445 CN2018072445W WO2018227963A1 WO 2018227963 A1 WO2018227963 A1 WO 2018227963A1 CN 2018072445 W CN2018072445 W CN 2018072445W WO 2018227963 A1 WO2018227963 A1 WO 2018227963A1
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Prior art keywords
transistor
coupled
circuit
pole
control
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PCT/CN2018/072445
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English (en)
French (fr)
Inventor
曲加伟
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京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Priority to US16/082,167 priority Critical patent/US11302241B2/en
Publication of WO2018227963A1 publication Critical patent/WO2018227963A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G09G3/3291—Details of drivers for data electrodes in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/043—Compensation electrodes or other additional electrodes in matrix displays related to distortions or compensation signals, e.g. for modifying TFT threshold voltage in column driver
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a pixel circuit and a driving method thereof, an array substrate, and a display device.
  • OLED Organic Light Emitting Diode
  • LCD liquid crystal display
  • Embodiments of the present disclosure provide a pixel circuit and a driving method thereof, an array substrate, and a display device.
  • a pixel circuit includes a data writing circuit, a first control circuit, a capacitor, a second control circuit, a compensation circuit, a driving circuit, and a light emitting device.
  • the data write circuit is configured to provide a data signal from the data signal terminal to the first node in accordance with a control signal from the control signal terminal.
  • the first control circuit is configured to provide a threshold compensation signal from the compensation circuit or an initialization signal from the initialization signal terminal to the second node in accordance with the control signal.
  • the capacitor is configured to store a voltage difference between the first node and the second node.
  • the second control circuit is configured to provide the first voltage signal of the first voltage signal terminal to the drive circuit in accordance with the control signal.
  • the compensation circuit is configured to provide a threshold compensation signal to the first control circuit in accordance with the first voltage signal.
  • the drive circuit is configured to provide a drive current to the light emitting device based on the voltage of the first node and the first voltage signal provided by the second control circuit.
  • the light emitting device is configured to emit light according to a driving current.
  • the first control circuit may include a first transistor and a second transistor.
  • the control electrode of the first transistor is coupled to the control signal terminal, the first pole is coupled to the compensation circuit, and the second pole is coupled to the second node.
  • the control electrode of the second transistor is coupled to the control signal terminal, the first pole is coupled to the initialization signal terminal, and the second pole is coupled to the second node.
  • the type of the first transistor is different from the type of the second transistor.
  • the driving circuit may include a third transistor.
  • the control electrode of the third transistor is coupled to the first node, the first pole is coupled to the second control circuit, and the second pole is coupled to the light emitting device.
  • the compensation circuit may include a fourth transistor.
  • the control electrode and the first pole of the fourth transistor are coupled to the first control circuit, and the second pole is coupled to the first voltage signal terminal.
  • the data write circuit may include a fifth transistor.
  • the control electrode of the fifth transistor is coupled to the control signal end, the first pole is coupled to the data signal end, and the second pole is coupled to the first node.
  • the second control circuit may include a sixth transistor.
  • the control electrode of the sixth transistor is coupled to the control signal terminal, the first pole is coupled to the first voltage signal terminal, and the second pole is coupled to the driving circuit.
  • the types of transistors in the drive circuit, the compensation circuit, and the second control circuit are different from those of the transistors in the data write circuit.
  • the pixel circuit may further include a reset circuit.
  • the reset circuit is coupled in parallel with the light emitting device and coupled to the control signal end, and configured to reset the light emitting device according to the control signal.
  • the reset circuit may include a seventh transistor.
  • the control electrode of the seventh transistor is coupled to the control signal end, and the first pole and the second pole are respectively coupled to both ends of the light emitting device.
  • the type of the seventh transistor is different from the type of transistor in the driving circuit.
  • a pixel circuit including a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a capacitor, and a light emitting device.
  • the control electrode of the first transistor is coupled to the control signal terminal, the first pole is coupled to the control electrode of the fourth transistor, and the second pole is coupled to the second node.
  • the control electrode of the second transistor is coupled to the control signal terminal, the first pole is coupled to the initialization signal terminal, and the second pole is coupled to the second node.
  • a capacitor is coupled between the first node and the second node.
  • the control electrode of the third transistor is coupled to the first node, the first pole is coupled to the second pole of the sixth transistor, and the second pole is coupled to the first end of the light emitting device.
  • the control electrode of the fourth transistor and the first pole are coupled to the first pole of the first transistor, and the second pole thereof is coupled to the first voltage signal terminal.
  • the control electrode of the fifth transistor is coupled to the control signal end, the first pole is coupled to the data signal end, and the second pole is coupled to the first node.
  • the control electrode of the sixth transistor is coupled to the control signal terminal, the first pole is coupled to the first voltage signal terminal, and the second pole is coupled to the first pole of the third transistor.
  • the first end of the light emitting device is coupled to the second electrode of the third transistor, and the second end is coupled to the second voltage signal end.
  • the first transistor is different in type from the second transistor.
  • the types of the third transistor, the fourth transistor, and the sixth transistor are different from those of the fifth transistor.
  • the pixel circuit further includes a seventh transistor.
  • the control electrode of the seventh transistor is coupled to the control signal end, the first pole is coupled to the first end of the light emitting device, and the second pole is coupled to the second voltage signal end.
  • the type of the seventh transistor is different from the type of the third transistor.
  • a method for driving the above pixel circuit is provided.
  • a data signal is supplied to the first node and an initialization signal is supplied to the second node to charge the capacitor under the action of the control signal.
  • a threshold compensation signal is supplied to the second node, maintaining a voltage difference between the first node and the second node through the capacitor to control the voltage of the first node, and according to the first The voltage of the node and the first voltage signal of the first voltage signal terminal cause the light emitting device to emit light.
  • the light emitting device is reset by the control signal during the first time period.
  • an array substrate comprising the pixel circuit as above.
  • a display device comprising the array substrate as above.
  • FIG. 1 is a schematic block diagram of a pixel circuit in accordance with a first embodiment of the present disclosure
  • FIG. 2 is an exemplary circuit diagram of the pixel circuit shown in FIG. 1;
  • FIG. 3 is another exemplary circuit diagram of the pixel circuit shown in FIG. 1;
  • FIG. 5 is a schematic block diagram of a pixel circuit in accordance with a second embodiment of the present disclosure.
  • FIG. 6 is an exemplary circuit diagram of the pixel circuit shown in FIG. 5, wherein the driving circuit employs a P-type transistor;
  • FIG. 7 is another exemplary circuit diagram of the pixel circuit shown in FIG. 5, wherein the driving circuit uses a P-type transistor;
  • Figure 8 is a simulation diagram of signals in the pixel circuit shown in Figure 2;
  • Figure 9 is a simulation diagram of signals in the pixel circuit shown in Figure 6;
  • FIG. 10 is still another exemplary circuit diagram of the pixel circuit shown in FIG. 5, wherein the driving circuit employs an N-type transistor;
  • FIG. 11 is still another exemplary circuit diagram of the pixel circuit shown in FIG. 5, wherein the driving circuit employs an N-type transistor;
  • FIG. 12 is a schematic flowchart of a method for driving a pixel circuit as shown in FIG. 1 according to an embodiment of the present disclosure.
  • element A is coupled to element B
  • element A is “directly” or “indirectly” connected to element B by one or more other elements, unless otherwise stated.
  • the magnitude of the current between the source and the drain of the driving transistor is usually controlled by changing the gate voltage of the driving transistor that directly drives the OLED to emit light to achieve a change in the luminance of the light.
  • the threshold voltage of the driving transistor at different positions may be different due to the process variation.
  • the threshold voltage of the driving transistor drifts.
  • the position of each pixel is different, which also causes a voltage drop (I-R Drop) of the power source to be different, thereby affecting the current that drives the OLED.
  • FIG. 1 shows a schematic block diagram of a pixel circuit 100 in accordance with a first embodiment of the present disclosure.
  • the pixel circuit 100 may include a data writing circuit 110, a first control circuit 120, a capacitor 130, a second control circuit 140, a compensation circuit 150, a driving circuit 160, and a light emitting device 170.
  • capacitor 130, compensation circuit 150, and light emitting device 170 each have a first end and a second end.
  • the data writing circuit 110 and the second control circuit 140 each have a control terminal, a first terminal, and a second terminal.
  • the first control circuit 120 has a third end in addition to the control end, the first end and the second end.
  • the drive circuit 160 has a first end, a second end, and a third end.
  • the control terminal of the data writing circuit 110 is coupled to the control signal terminal EM, the first terminal is coupled to the data signal terminal Vdata, and the second terminal is coupled to the first node N1 (ie, to the second terminal of the capacitor 130 and the driving The second end of the circuit 160 is coupled).
  • the data writing circuit 110 can supply the data signal from the data signal terminal Vdata to the first node N1 under the action of the control signal from the control signal terminal EM, and then supply it to the capacitor 130 and the driving circuit 160.
  • the control end of the first control circuit 120 is coupled to the control signal terminal EM, the first end is coupled to the second end of the compensation circuit 150, the second end is coupled to the initialization signal terminal Vinit, and the third end and the second node N2 are coupled. Coupling (ie, coupled to the first end of capacitor 130).
  • the first control circuit 120 may provide a threshold compensation signal from the compensation circuit 150 or an initialization signal from the initialization signal terminal Vinit to the second node N2 under the action of the control signal, and then provide the capacitor 130.
  • the first end of the capacitor 130 is coupled to the second node N2, and the second end is coupled to the first node N1.
  • the capacitor 130 can store a voltage difference between the first node N1 and the second node N2.
  • the control terminal of the second control circuit 140 is coupled to the control signal terminal EM, the first terminal is coupled to the first voltage signal terminal Vdd, and the second terminal is coupled to the first terminal of the driving circuit 160.
  • the second control circuit 140 can provide the first voltage signal of the first voltage signal terminal Vdd to the driving circuit 160 under the action of the control signal.
  • the first end of the compensation circuit 150 is coupled to the first voltage signal terminal Vdd, and the second end is coupled to the first end of the first control circuit 120.
  • the compensation circuit 150 can provide a threshold compensation signal to the first control circuit.
  • the first end of the driving circuit 160 is coupled to the second end of the second control circuit 140, and the second end is coupled to the first node N1 (ie, to the second end of the capacitor 130 and the second end of the data writing circuit 110).
  • the third end is coupled to the first end of the light emitting device 170.
  • the driving circuit 160 can supply a driving current to the light emitting device 170 according to the voltage of the first node N1 and the first voltage signal.
  • the first end of the light emitting device 170 is coupled to the third end of the driving circuit 160, and the second end is coupled to the second voltage signal terminal Vss.
  • the light emitting device 170 can emit light according to a driving current supplied from the driving circuit 160.
  • the first voltage signal from the first voltage signal terminal Vdd is a high level signal
  • the second voltage signal from the second voltage signal terminal Vss is a low level signal
  • the pixel circuit 100 may be implemented with a transistor, wherein the transistor may be an N-type transistor or a P-type transistor.
  • the transistor may be an N-type or P-type field effect transistor (MOSFET), or an N-type or P-type bipolar transistor (BJT).
  • MOSFET N-type or P-type field effect transistor
  • BJT N-type or P-type bipolar transistor
  • the gate of the transistor is referred to as a gate. Since the source and the drain of the transistor are symmetrical, the source and the drain are not distinguished, that is, the source of the transistor can be the first pole (or the second pole), and the drain can be the second pole (or the One pole).
  • any controlled switching device having a strobe signal input can be used to implement the function of the transistor, and the controlled intermediate terminal of the switching device for receiving a control signal (eg, for turning the controlled switching device on and off) is referred to as
  • the control pole has the other ends being the first pole and the second pole, respectively.
  • NMOS P-type field effect transistor
  • NMOS N-type field effect transistor
  • FIG. 2 shows an exemplary circuit diagram of the pixel circuit 100 shown in FIG. 1.
  • the data write circuit 110 may include a fifth transistor M5.
  • the control electrode of the fifth transistor M5 is coupled to the control signal terminal EM.
  • the first pole is coupled to the data signal terminal Vdata, and the second pole is coupled to the first node N1.
  • the first control circuit 120 may include a first transistor M1 and a second transistor M2.
  • the control electrode of the first transistor M1 is coupled to the control signal terminal EM, the first pole is coupled to the compensation circuit 150, and the second pole is coupled to the second node N2.
  • the control electrode of the second transistor M2 is coupled to the control signal terminal EM, the first pole is coupled to the initialization signal terminal Vinit, and the second pole is coupled to the second node N2.
  • Capacitor 130 can include a capacitor C. The first end of the capacitor C is coupled to the second node N2, and the second end is coupled to the first node N1.
  • the second control circuit 140 may include a sixth transistor M6.
  • the control electrode of the sixth transistor M6 is coupled to the control signal terminal EM.
  • the first pole is coupled to the first voltage signal terminal Vdd, and the second pole is coupled to the driving circuit 160.
  • the compensation circuit 150 can include a fourth transistor M4.
  • the control electrode and the first pole of the fourth transistor M4 are coupled to the first control circuit 120, and the second pole is coupled to the first voltage signal terminal Vdd.
  • the driving circuit 160 may include a third transistor M3.
  • the control electrode of the third transistor M3 is coupled to the first node N1, the first electrode is coupled to the second control circuit 140, and the second electrode is coupled to the light emitting device 170.
  • Light emitting device 170 can include an OLED device.
  • the first end of the OLED device is coupled to the driving circuit 160, and the second end is coupled to the second voltage signal terminal Vss. Further, the first end of the OLED device is an anode and the second end is a cathode.
  • FIG. 3 shows another exemplary circuit diagram of the pixel circuit 100 shown in FIG. 1.
  • the second pole of the fourth transistor M4 in the compensation circuit 150 is coupled to the second pole of the sixth transistor M6, that is, the second pole of the fourth transistor M4 passes through the second control circuit 140 and the first voltage.
  • the signal terminal Vdd is coupled.
  • the pixel circuit shown in Fig. 3 has the same structure as the pixel circuit shown in Fig. 2 and will not be described again.
  • the first transistor M1, the third transistor M3, the fourth transistor M4, and the sixth transistor M6 are P-type transistors
  • the second transistor M2, the fifth transistor M5, and the seventh transistor M7 are N-type. Transistor.
  • the threshold voltages of the two are approximately equal, which can be collectively referred to as the threshold voltage Vth (which indicates a transistor)
  • the threshold voltage, the threshold voltage of the PMOS is a negative value, and the threshold voltage of the NMOS is a positive value).
  • the first voltage signal provided by the first voltage signal terminal Vdd, the second voltage signal provided by the second voltage signal terminal Vss, and the data signal provided by the data signal terminal Vdata are DC signals.
  • the threshold compensation signal provided by the compensation circuit 150 is the sum of the voltage of the first voltage signal Vdd and the threshold voltage Vth of the fourth transistor M4, that is, Vdd+Vth.
  • the voltage of the initialization signal provided by the initialization signal terminal Vinit is less than the voltage of the threshold compensation signal.
  • the voltage of the initialization signal Vinit is also greater than the voltage of the data signal Vdata. Therefore, the voltage of the first voltage signal Vdd is greater than the difference between the voltage of the data signal Vdata and the threshold voltage Vth of the third transistor, that is, Vdata-Vth.
  • Fig. 4 shows a timing chart of control signals supplied from the control signal terminal EM of the pixel circuit.
  • the working process of the pixel circuit shown in FIGS. 2 and 3 will be described in detail below with reference to FIG. Specifically, the first voltage signal terminal Vdd provides a first voltage signal of a high level, and the second voltage signal terminal Vss provides a second voltage signal of a low level.
  • the control signal EM is a high level signal, and the second transistor M2, the fifth transistor M5, and the seventh transistor M7 are turned on, the first transistor M1, the third transistor M3, the fourth transistor M4, and The sixth transistor M6 is turned off.
  • the data signal Vdata is supplied to the first node N1 through the fifth transistor M5, so that the voltage of the first plate of the capacitor C becomes Vdata.
  • the initialization signal Vinit is supplied to the second node N2 through the second transistor M2, so that the voltage of the second plate of the capacitor C becomes Vinit.
  • capacitor C stores charge and the voltage difference across capacitor C is Vdata-Vinit.
  • the control signal EM is a low level signal, and the first transistor M1, the third transistor M3, the fourth transistor M4, and the sixth transistor M6 are turned on, the second transistor M2, the fifth transistor M5, and The seventh transistor M7 is turned off. Passing the first voltage signal through the diode-connected fourth transistor M4 and then providing the second transistor through the first transistor M1 to the second plate of the capacitor, that is, providing the threshold compensation signal (ie, Vdd+Vth) to the second plate of the capacitor, so that The voltage of the two nodes N2 becomes Vdd+Vth. Since the amount of charge of the capacitor C does not change, the voltage difference across the capacitor C does not change. Therefore, the voltage of the first node N1 becomes Vdd+Vth+Vdata-Vinit, and the third transistor M3 is driven to generate a driving current I that causes the OLED device to emit light.
  • the threshold compensation signal ie, Vdd+Vth
  • the drive current I can be expressed as:
  • W/L is the aspect ratio of the third transistor M3, ⁇ is the hole mobility, Cox is the gate capacitance, VGS is the gate-source voltage of the third transistor M3, and Vth is the threshold voltage of the third transistor M3. .
  • the driving current I can be expressed as:
  • the drive current I is only related to the data signal Vdata and the initial signal Vinit, regardless of the threshold voltage Vth of the third transistor M3 and the voltage of the first voltage signal Vdd. Therefore, the driving current of the OLED device is not affected by the threshold voltage Vth and the power source I-R Drop of the first voltage signal Vdd at different pixel positions.
  • FIG. 5 shows a schematic block diagram of a pixel circuit 500 in accordance with a second embodiment of the present disclosure.
  • the pixel circuit 500 in addition to the data writing circuit 110, the first control circuit 120, the capacitor 130, the second control circuit 140, the compensation circuit 150, the driving circuit 160, and the light emitting device 170, the pixel circuit 500 further includes a reset circuit 180.
  • the reset circuit 180 is coupled in parallel with the light emitting device 170 and coupled to the control signal terminal EM.
  • the reset circuit 180 can reset the light emitting device 170 under the action of the control signal.
  • Fig. 6 shows an exemplary circuit diagram of the pixel circuit 500 shown in Fig. 5, in which the third transistor M3 in the driving circuit 160 employs a P-type transistor.
  • the reset circuit 180 may include a seventh transistor M7, which is an N-type transistor.
  • the control electrode of the seventh transistor M7 is coupled to the control signal terminal EM.
  • the first pole is coupled to the first end of the light emitting device 170, and the second pole is coupled to the second voltage signal terminal.
  • the pixel circuit shown in FIG. 6 has the same structure as the pixel circuit shown in FIG. 2 and will not be described again.
  • FIG. 7 shows another exemplary circuit diagram of the pixel circuit 500 shown in FIG. 5, in which the third transistor M3 in the driving circuit 160 employs a P-type transistor. As shown in FIG. 7, the second pole of the fourth transistor M4 in the compensation circuit 150 can be coupled to the second pole of the sixth transistor M6. Except for this, the pixel circuit shown in FIG. 7 has the same structure as the pixel circuit shown in FIG. 6, and will not be described again.
  • the light-emitting device can be reset. Specifically, in the first period of time (T1), the second voltage signal Vss is also supplied to the anode of the OLED device through the seventh transistor M7, thereby resetting the OLED device to ensure the stability of the current driving the OLED device, and avoiding the OLED device. Abnormal illumination.
  • FIG. 8 is a simulation diagram of signals in the pixel circuit shown in FIG. These signals are the control signal EM, the data signal Vdata, the voltage signal of the first node N1, the voltage signal of the second node N2, and the drive current signal Ioled.
  • FIG. 9 is a simulation diagram of signals in the pixel circuit shown in FIG. 6. In addition to the above signals, a current signal Im7 flowing through the seventh transistor M7 is included.
  • the second node N2 is equivalent to an alternating current ground, and thus the gates of the first transistor M1 and the second transistor M2
  • the parasitic capacitance to the drain is the parallel value Cgd1+Cgd2 of Cgd1 and Cgd2.
  • the partial control signal EM is coupled to the second plate of the capacitor C through the gate-drain parasitic capacitances Cgd1+Cgd2 of the first transistor M1 and the second transistor M2 ( That is, the second node N2).
  • the incomplete writing of the initialization signal Vinit also causes the diode D4 connected to the compensation diode to be turned on, thereby partially writing the first voltage signal Vdd to the second node N2.
  • the partial control signal EM and the signal written by the first voltage signal terminal Vdd are then capacitively coupled to the first plate of the capacitor C (i.e., the first node N1).
  • the gate-drain capacitance Cgd of the third transistor M3 is coupled to the anode of the OLED, thereby causing the OLED to generate a pulse current, causing the OLED to emit light.
  • controlling the seventh transistor M7 by the control signal EM can filter the pulse current so that the pulse current does not pass through the OLED and avoid OLED emission abnormality.
  • the control signal EM goes high, after the second node N2 and the first node N1 reach a steady state, the voltages of the second node N2 and the first node N1 become Vinit and Vdata, and reach a steady state.
  • the voltage of the second node N2 and the first node N1 has a spike voltage which causes the OLED to have a large pulse current.
  • the second node N2 and the first node N1 also have a spike voltage, and the peak current is directed to the second voltage signal terminal Vss through the seventh transistor M7 without passing through the OLED. . Therefore, there is no pulse current flowing through the OLED current, and the OLED does not emit light in this switching state. In this way, even under the action of a single control signal, the stable current output of the OLED pixel circuit can be controlled, thereby driving the OLED to emit light.
  • FIG. 10 shows still another exemplary circuit diagram of the pixel circuit shown in FIG. 5, in which the third transistor M3 in the driving circuit 160 employs an N-type transistor.
  • the first transistor M1, the third transistor M3, and the sixth transistor M6 are N-type transistors
  • the second transistor M2, the fifth transistor M5, and the seventh transistor M7 are P-type transistors.
  • the coupling relationship between the transistor and the first and second voltage signal terminals also changes.
  • the first pole of the sixth transistor M6 is coupled to the second voltage signal terminal Vss.
  • the second electrode of the fourth transistor M4 is coupled to the second voltage signal terminal Vss.
  • the first end of the OLED device is coupled to the driving circuit 160, the second end is coupled to the first voltage signal terminal Vdd, and the first end of the OLED device is a cathode and the second end is an anode.
  • the structure of the pixel circuit shown in FIG. 10 is similar to that of the pixel circuit shown in FIG. 2, and the operation timing is similar, and will not be described in detail.
  • FIG. 11 shows still another exemplary circuit diagram of the pixel circuit shown in FIG. 5, in which the third transistor M3 in the driving circuit 160 employs an N-type transistor. Different from Fig. 10, in the pixel circuit shown in Fig. 11, the second electrode of the fourth transistor M4 of the compensation circuit 150 is coupled to the second electrode of the sixth transistor M6 of the second control circuit.
  • FIG. 12 is a schematic flowchart of a method of driving a pixel circuit as above according to an embodiment of the present disclosure.
  • the first voltage signal terminal provides a first voltage signal of a high level
  • the second voltage signal terminal provides a second voltage signal of a low level.
  • step S1210 under the action of the control signal EM, the data writing circuit 110 or the fifth transistor M5 is turned on to supply the data signal Vdata to the first node N1 through the data writing circuit 110 or the fifth transistor M5, and pass
  • the first control circuit 120 or the second transistor M2 supplies an initialization signal Vinit to the second node N2.
  • the capacitor 130 or the capacitor C stores the voltage between the first node N1 and the second node N2, that is, Vdata-Vinit.
  • step S1220 under the action of the control signal EM, the second control circuit 140 or the sixth transistor M6 and the driving circuit 160 or the third transistor M3 are turned on, through the compensation circuit 150 or the fourth transistor M4 and the first control circuit 120.
  • the first transistor M1 provides a threshold compensation signal (ie, Vdd+Vth) to the second node N2.
  • the voltage difference between the first node N1 and the second node N2 is maintained by the capacitor 130 or the capacitor C as Vdata-Vinit to control the voltage of the first node N1 to become Vdd+Vth+Vdata-Vinit.
  • the light emitting device 170 or the OLED device is caused to emit light according to the voltage of the first node N1 and the first voltage signal.
  • the light emitting device 170 can also be reset by the reset circuit 180 or the seventh transistor M7 under the action of the control signal EM to ensure driving of the light emitting device.
  • the stability of the driving current of the 170 or OLED device prevents the light emitting device 170 or the OLED device from abnormally emitting light.
  • the pixel circuit according to an embodiment of the present disclosure can perform data writing, resetting, threshold voltage, and power supply IR Drop compensation and light emission of the pixel circuit in two stages by using a single control signal, thereby improving the processing speed and stability of the circuit. Sex. With the pixel circuit according to an embodiment of the present disclosure, it is possible to reduce the number of control signals, increase the wiring margin of the internal signals, simplify the design of the peripheral signal driving circuit, and reduce crosstalk between signals.

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Abstract

一种像素电路（100）及其驱动方法、阵列基板和显示装置。像素电路（100）包括数据写入电路（110）、第一控制电路（120）、电容器（130）、第二控制电路（140）、补偿电路（150）、驱动电路（160）和发光器件（170）。数据写入电路（110）根据来自控制信号端（EM）的控制信号，将来自数据信号端（Vdata）的数据信号提供至第一节点（N1）。第一控制电路（120）根据控制信号，将来自补偿电路（150）的阈值补偿信号或者来自初始化信号端（Vinit）的初始化信号提供至第二节点（N2）。电容器（130）存储第一节点（N1）和第二节点（N2）之间的电压差。第二控制电路（140）根据控制信号，将第一电压信号端（Vdd）的第一电压信号提供至驱动电路（160）。补偿电路（150）向第一控制电路（120）提供阈值补偿信号。驱动电路（160）根据第一节点（N1）的电压和第一电压信号，向发光器件（170）提供驱动电流。发光器件（170）根据驱动电流而发光。

Description

像素电路及其驱动方法、阵列基板以及显示装置
相关申请的交叉引用
本申请要求于2017年6月16日递交的中国专利申请第201710457169.3号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开涉及显示技术领域，具体地，涉及一种像素电路及其驱动方法、阵列基板以及显示装置。
背景技术
随着显示技术的进步，相对于传统的液晶显示(Liquid Crystal Display，LCD)装置，新一代的有机发光二极管(Organic Light Emitting Diode，OLED)显示装置具有更低的制造成本，更快的反应速度，更高的对比度，更广的视角，更大的工作温度范围，不需要背光单元，色彩鲜艳及轻薄等优点。因此，OLED显示技术成为当前发展最快的显示技术。
发明内容
本公开的实施例提供了一种像素电路及其驱动方法、阵列基板以及显示装置。
根据本公开的第一方面，提供了一种像素电路。像素电路包括数据写入电路、第一控制电路、电容器、第二控制电路、补偿电路、驱动电路和发光器件。数据写入电路被配置为根据来自控制信号端的控制信号，将来自数据信号端的数据信号提供至第一节点。第一控制电路被配置为根据控制信号，将来自补偿电路的阈值补偿信号或者来自初始化信号端的初始化信号提供至第二节点。电容器被配置为存储第一节点和第二节点之间的电压差。第二控制电路被配置为根据控制信号，将所述第一电压信号端的第 一电压信号提供至驱动电路。补偿电路被配置为根据第一电压信号向第一控制电路提供阈值补偿信号。驱动电路被配置为根据第一节点的电压和由第二控制电路提供的第一电压信号，向发光器件提供驱动电流。发光器件被配置为根据驱动电流而发光。
在本公开的实施例中，第一控制电路可包括第一晶体管和第二晶体管。第一晶体管的控制极与控制信号端耦接，其第一极与补偿电路耦接，其第二极与第二节点耦接。第二晶体管的控制极与控制信号端耦接，其第一极与初始化信号端耦接，其第二极与第二节点耦接。第一晶体管的类型和第二晶体管的类型不同。
在本公开的实施例中，驱动电路可包括第三晶体管。第三晶体管的控制极与第一节点耦接，其第一极与第二控制电路耦接，其第二极与发光器件耦接。
在本公开的实施例中，补偿电路可包括第四晶体管。第四晶体管的控制极和第一极与第一控制电路耦接，其第二极与第一电压信号端耦接。
在本公开的实施例中，数据写入电路可包括第五晶体管。第五晶体管的控制极与控制信号端耦接，其第一极与数据信号端耦接，其第二极与第一节点耦接。
在本公开的实施例中，第二控制电路可包括第六晶体管。第六晶体管的控制极与控制信号端耦接，其第一极与第一电压信号端耦接，其第二极与驱动电路耦接。
在本公开的实施例中，驱动电路、补偿电路和第二控制电路中的晶体管的类型与数据写入电路中的晶体管的类型不同。
在本公开的实施例中，像素电路还可包括复位电路。复位电路与发光器件并联耦接，并与控制信号端耦接，并被配置为根据控制信号，对发光器件进行复位。
在本公开的实施例中，复位电路可包括第七晶体管。第七晶体管的控制极与控制信号端耦接，其第一极和第二极分别与发光器件的两端耦接。
在本公开的实施例中，第七晶体管的类型与驱动电路中的晶体管的类 型不同。
根据本公开的第二方面，提供了一种像素电路，其包括第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管、电容器和发光器件。第一晶体管的控制极与控制信号端耦接，其第一极与第四晶体管的控制极耦接，其第二极与第二节点耦接。第二晶体管的控制极与控制信号端耦接，其第一极与初始化信号端耦接，其第二极与第二节点耦接。电容器被耦接在第一节点和第二节点之间。第三晶体管的控制极与第一节点耦接，其第一极与第六晶体管的第二极耦接，其第二极与发光器件的第一端耦接。第四晶体管的控制极和第一极与第一晶体管的第一极耦接，其第二极与第一电压信号端耦接。第五晶体管的控制极与控制信号端耦接，其第一极与数据信号端耦接，其第二极与第一节点耦接。第六晶体管的控制极与控制信号端耦接，其第一极与第一电压信号端耦接，其第二极与第三晶体管的第一极耦接。发光器件的第一端与第三晶体管的第二极耦接，第二端与第二电压信号端耦接。第一晶体管与第二晶体管的类型不同。
在本公开的实施例中，第三晶体管、第四晶体管和第六晶体管的类型与第五晶体管的类型不同。
在本公开的实施例中，像素电路还包括第七晶体管。第七晶体管的控制极与控制信号端耦接，其第一极与发光器件的第一端耦接，第二极与第二电压信号端耦接。
在本公开的实施例中，第七晶体管的类型与第三晶体管的类型不同。
根据本公开的第三方面，提供了一种用于驱动上述像素电路的方法。在该方法中，在第一时间段，在控制信号的作用下，向第一节点提供数据信号，向第二节点提供初始化信号，以对电容器进行充电。在第二时间段，在控制信号的作用下，向第二节点提供阈值补偿信号，通过电容器保持第一节点和第二节点之间的电压差，以控制第一节点的电压，并根据第一节点的电压和第一电压信号端的第一电压信号，使发光器件发光。
在本公开的实施例中，在第一时间段，在控制信号的作用下，对发光器件进行复位。
根据本公开的第四方面，提供了一种阵列基板，其包括如上的像素电路。
根据本公开的第五方面，提供了一种显示装置，其包括如上的阵列基板。
附图说明
为了更清楚地说明本公开的技术方案，下面将对实施例的附图进行简单说明。应当知道，以下描述的附图仅仅是本公开的一些实施例，而非对本公开的限制，其中：
图1是根据本公开的第一实施例的像素电路的示意性框图；
图2是图1所示的像素电路的示例性电路图；
图3是图1所示的像素电路的另一示例性电路图；
图4示出用于像素电路的控制信号的时序图；
图5是根据本公开的第二实施例的像素电路的示意性框图；
图6是图5所示的像素电路的示例性电路图，其中，驱动电路采用P型晶体管；
图7是图5所示的像素电路的另一示例性电路图，其中，驱动电路采用P型晶体管；
图8是图2所示的像素电路中的信号的仿真图；
图9是图6所示的像素电路中的信号的仿真图；
图10是图5所示的像素电路的再一个示例性电路图，其中，驱动电路采用N型晶体管；
图11是图5所示的像素电路的再一个示例性电路图，其中，驱动电路采用N型晶体管；
图12是根据本公开的实施例的用于驱动如图1所示的像素电路的方法的示意性流程图。
具体实施方式
为了使本公开的实施例的目的、技术方案和优点更加清楚，下面将结合附图，对本公开的实施例的技术方案进行清楚、完整的描述。显然，所描述的实施例仅仅是本公开的一部分实施例，而并非全部的实施例。基于所描述的实施例，本领域的普通技术人员在无需创造性劳动的前提下所获得的所有其它实施例，也都属于本公开的范围。
在下文中，除非特别说明，表述“元件A耦接到元件B”意为元件A“直接”或通过一个或多个其它元件“间接”连接到元件B。
目前，通常通过改变直接驱动OLED发光的驱动晶体管的栅极电压，来控制驱动晶体管的源极与漏极之间电流的大小以实现发光亮度的变化。然而在制作驱动晶体管的过程中，由于工艺偏差会导致不同位置的驱动晶体管的阈值电压存在差异。此外，随着工作时间延迟及使用环境改变，驱动晶体管的阈值电压会发生漂移。另一方面，在显示器件中，各像素所处的位置不同也会导致电源的压降(I-R Drop)不同，从而对驱动OLED的电流产生影响。
图1示出了根据本公开的第一实施例的像素电路100的示意性框图。如图1所示，像素电路100可包括数据写入电路110、第一控制电路120、电容器130、第二控制电路140、补偿电路150、驱动电路160和发光器件170。在本公开的实施例中，电容器130、补偿电路150和发光器件170均具有第一端和第二端。数据写入电路110和第二控制电路140均具有控制端、第一端和第二端。第一控制电路120除控制端、第一端和第二端外，还具有第三端。驱动电路160具有第一端、第二端和第三端。
数据写入电路110的控制端与控制信号端EM耦接、第一端与数据信号端Vdata耦接、以及第二端与第一节点N1耦接(即，与电容器130的第二端和驱动电路160的第二端耦接)。数据写入电路110可在来自控制信号端EM的控制信号的作用下，将来自数据信号端Vdata的数据信号提供至第一节点N1，进而提供给电容器130和驱动电路160。
第一控制电路120的控制端与控制信号端EM耦接、第一端与补偿电路150的第二端耦接、第二端与初始化信号端Vinit耦接、以及第三端与第 二节点N2耦接(即，与电容器130的第一端耦接)。第一控制电路120可在控制信号的作用下，将来自补偿电路150的阈值补偿信号或者来自初始化信号端Vinit的初始化信号提供至第二节点N2，进而提供给电容器130。
电容器130的第一端与第二节点N2耦接、第二端与第一节点N1耦接。电容器130可存储第一节点N1和第二节点N2之间的电压差。
第二控制电路140的控制端与控制信号端EM耦接、第一端与第一电压信号端Vdd耦接、以及第二端与驱动电路160的第一端耦接。第二控制电路140可在控制信号的作用下，将第一电压信号端Vdd的第一电压信号提供至驱动电路160。
补偿电路150的第一端与第一电压信号端Vdd耦接、第二端与第一控制电路120的第一端耦接。补偿电路150可向第一控制电路提供阈值补偿信号。
驱动电路160的第一端与第二控制电路140的第二端耦接，第二端与第一节点N1耦接(即，与电容器130的第二端和数据写入电路110的第二端耦接)、以及第三端与发光器件170的第一端耦接。驱动电路160可根据第一节点N1的电压和第一电压信号，向发光器件170提供驱动电流。
发光器件170的第一端与驱动电路160的第三端耦接，第二端与第二电压信号端Vss耦接。发光器件170可根据驱动电路160提供的驱动电流而发光。
在本公开的实施例中，来自第一电压信号端Vdd的第一电压信号是高电平信号，来自第二电压信号端Vss第二电压信号是低电平信号。
在本公开的实施例中，像素电路100可采用晶体管实现，其中晶体管可以是N型晶体管或者P型晶体管。具体地，晶体管可以是N型或P型场效应晶体管(MOSFET)，或者N型或P型双极性晶体管(BJT)。在本公开的实施例中，晶体管的栅极被称为控制极。由于晶体管的源极和漏极是对称的，因此对源极和漏极不做区分，即晶体管的源极可以为第一极(或第二极)，漏极可以为第二极(或第一极)。进一步，可以采用具有选通信号输入的任何受控开关器件来实现晶体管的功能，将用于接收控制信号(例 如用于开启和关断受控开关器件)的开关器件的受控中间端称为控制极，另外两端分别为第一极和第二极。以下，以P型场效应晶体管(NMOS)和N型场效应晶体管(NMOS)为例进行详细的描述。
图2示出了图1所示的像素电路100的示例性电路图。
如图2所示，数据写入电路110可包括第五晶体管M5。第五晶体管M5的控制极与控制信号端EM耦接，第一极与数据信号端Vdata耦接，第二极与第一节点N1耦接。
第一控制电路120可包括第一晶体管M1和第二晶体管M2。第一晶体管M1的控制极与控制信号端EM耦接，第一极与补偿电路150耦接，第二极与第二节点N2耦接。第二晶体管M2的控制极与控制信号端EM耦接，第一极与初始化信号端Vinit耦接，第二极与第二节点N2耦接。
电容器130可包括电容器C。电容器C的第一端与第二节点N2耦接，第二端与第一节点N1耦接。
第二控制电路140可包括第六晶体管M6。第六晶体管M6的控制极与控制信号端EM耦接，第一极与第一电压信号端Vdd耦接，第二极与驱动电路160耦接。
补偿电路150可包括第四晶体管M4。第四晶体管M4的控制极和第一极与第一控制电路120耦接，第二极与第一电压信号端Vdd耦接。
驱动电路160可包括第三晶体管M3。第三晶体管M3的控制极与第一节点N1耦接，第一极与第二控制电路140耦接，第二极与发光器件170耦接。
发光器件170可包括OLED器件。OLED器件的第一端与驱动电路160耦接，第二端与第二电压信号端Vss耦接。此外，OLED器件的第一端是阳极，第二端是阴极。
图3示出了图1所示的像素电路100的另一示例性电路图。如图3所示，补偿电路150中的第四晶体管M4的第二极与第六晶体管M6的第二极耦接，即第四晶体管M4的第二极通过第二控制电路140与第一电压信号端Vdd耦接。除此之外，图3中所示的像素电路与图2所示的像素电路 的结构相同，不再赘述。
如图2和图3所示，第一晶体管M1、第三晶体管M3、第四晶体管M4和第六晶体管M6是P型晶体管，第二晶体管M2、第五晶体管M5和第七晶体管M7是N型晶体管。另外，在生产过程中，由于第三晶体管M3和第四晶体管M4的距离较近，工艺影响较小，可近似认为两者的阈值电压相等，下文可统一称其为阈值电压Vth(其表示晶体管的阈值电压，PMOS的阈值电压为负值，NMOS的阈值电压为正值)。
在本公开的实施例中，第一电压信号端Vdd提供的第一电压信号、第二电压信号端Vss提供的第二电压信号、以及数据信号端Vdata提供的数据信号为直流信号。
在本公开的实施例中，补偿电路150提供的阈值补偿信号是第一电压信号Vdd的电压与第四晶体管M4的阈值电压Vth之间的和，即Vdd+Vth。初始化信号端Vinit提供的初始化信号的电压小于该阈值补偿信号的电压。另外，初始化信号Vinit的电压还大于数据信号Vdata的电压。因此，第一电压信号Vdd的电压大于数据信号Vdata的电压与第三晶体管的阈值电压Vth之间的差，即Vdata-Vth。
图4示出了像素电路的控制信号端EM提供的控制信号的时序图。以下结合图4，对如图2和图3所示的像素电路的工作过程进行详细描述。具体地，第一电压信号端Vdd提供高电平的第一电压信号，第二电压信号端Vss提供低电平的第二电压信号。
在第一时间段(T1)，控制信号EM是高电平信号，第二晶体管M2、第五晶体管M5和第七晶体管M7导通，第一晶体管M1、第三晶体管M3、第四晶体管M4和第六晶体管M6截止。通过第五晶体管M5将数据信号Vdata提供至第一节点N1，使电容器C的第一极板的电压变为Vdata。通过第二晶体管M2将初始化信号Vinit提供至第二节点N2，使电容器C的第二极板的电压变为Vinit。这样，电容器C存储电荷，电容器C两端的电压差为Vdata-Vinit。
在第二时间段(T2)，控制信号EM是低电平信号，第一晶体管M1、 第三晶体管M3、第四晶体管M4和第六晶体管M6导通，第二晶体管M2、第五晶体管M5和第七晶体管M7截止。将第一电压信号通过二极管连接的第四晶体管M4后再通过第一晶体管M1提供至电容的第二极板，即将阈值补偿信号(即Vdd+Vth)提供至电容的第二极板，使第二节点N2的电压变为Vdd+Vth。由于电容器C的电荷量不变，所以电容器C两端的电压差不变。因此，第一节点N1的电压变为Vdd+Vth+Vdata-Vinit，并驱动第三晶体管M3产生使OLED器件发光的驱动电流I。
可将驱动电流I表示为下式：
Figure PCTCN2018072445-appb-000001
其中，W/L为第三晶体管M3的宽长比，μ为空穴迁移率，Cox为栅极电容，VGS为第三晶体管M3的栅源极间电压，Vth为第三晶体管M3的阈值电压。
由于第三晶体管M3的栅极电压为Vdd+Vth+Vdata-Vinit，源极电压为Vdd，可将驱动电流I表示为：
Figure PCTCN2018072445-appb-000002
由上，驱动电流I仅与数据信号Vdata和初始信号Vinit有关，与第三晶体管M3的阈值电压Vth和第一电压信号Vdd的电压无关。因此，OLED器件的驱动电流不受阈值电压Vth和第一电压信号Vdd在不同像素位置的电源I-R Drop的影响。
图5示出了根据本公开的第二实施例的像素电路500的示意性框图。如图5所示，除了数据写入电路110、第一控制电路120、电容器130、第二控制电路140、补偿电路150、驱动电路160和发光器件170外，像素电路500还包括复位电路180。复位电路180与发光器件170并联耦接，并与控制信号端EM耦接。复位电路180可在控制信号的作用下，对发光器件170进行复位。
图6示出了图5所示的像素电路500的示例性电路图，其中，驱动电 路160中的第三晶体管M3采用P型晶体管。如图6所示，复位电路180可包括第七晶体管M7，第七晶体管M7是N型晶体管。第七晶体管M7的控制极与控制信号端EM耦接，第一极与发光器件170的第一端耦接，第二极与第二电压信号端耦接。除此之外，图6所示的像素电路与图2所示的像素电路的结构相同，不再赘述。
图7示出了图5所示的像素电路500的另一示例性电路图，其中，驱动电路160中的第三晶体管M3采用P型晶体管。如图7所示，补偿电路150中的第四晶体管M4的第二极可与第六晶体管M6的第二极耦接。除此之外，图7所示的像素电路与图6所示的像素电路的结构相同，不再赘述。
在图6和图7所示的像素电路的工作过程中，除了可完成以上所述的数据写入、阈值电压及电源I-R Drop的补偿和发光外，还可对发光器件进行复位。具体地，在第一时间段(T1)，还通过第七晶体管M7向OLED器件的阳极提供第二电压信号Vss，从而对OLED器件复位，以确保驱动OLED器件的电流的稳定性，避免OLED器件异常发光。
以下结合图8和图9对本公开的两个实施例的操作效果进行描述。图8是图2所示的像素电路中的信号的仿真图。这些信号是控制信号EM、数据信号Vdata、第一节点N1的电压信号、第二节点N2的电压信号和驱动电流信号Ioled。图9是图6所示的像素电路中的信号的仿真图。除了上述信号外，还包括流过第七晶体管M7的电流信号Im7。
由于第一控制电路120中的第一晶体管M1和第二晶体管M2的栅漏极存在寄生电容Cgd1和Cgd2，第二节点N2相当于交流接地，因此第一晶体管M1和第二晶体管M2的栅极到漏极的寄生电容为Cgd1和Cgd2的并联值Cgd1+Cgd2。在控制信号EM由低电平变为高电平的瞬间，将部分控制信号EM通过第一晶体管M1和第二晶体管M2的栅漏极寄生电容Cgd1+Cgd2耦合到电容器C的第二极板(即第二节点N2)。这样，第一晶体管M1和第二晶体管M2没有完全转换到M1关断和M2导通状态。因此，初始化信号Vinit的不完全写入也会导致补偿二极管连接的晶体管M4导通，从而将第一电压信号Vdd部分地写入到第二节点N2。然后部分控制信号 EM以及第一电压信号端Vdd写入的信号通过电容耦合到电容器C的第一极板(即第一节点N1)。之后，通过第三晶体管M3的栅漏极电容Cgd耦合到OLED的阳极，进而使OLED产生一个脉冲电流，导致OLED发光。然而，通过控制信号EM控制第七晶体管M7可将脉冲电流滤去，使该脉冲电流不经过OLED，并且避免OLED发光异常。当EM变为高电平后，第二节点N2和第一节点N1达到稳定状态后，第二节点N2和第一节点N1的电压变为Vinit和Vdata，到达稳定状态。
如图8所示，在控制信号EM由低电平变为高电平时，第二节点N2和第一节点N1的电压存在尖峰脉冲电压，这个脉冲使OLED存在一个大的脉冲电流。如图9所示，在使用晶体管M7的过程中，第二节点N2和第一节点N1也存在尖峰脉冲电压，这个尖峰电流经过第七晶体管M7被导向第二电压信号端Vss，而不经过OLED。因此，OLED电流中不存在脉冲电流流过，OLED不会在这一转换状态下发光。这样，即使在单个控制信号的作用下，也能控制OLED像素电路稳定的电流输出，进而驱动OLED发光。
图10示出图5所示的像素电路的再一个示例性电路图，其中，驱动电路160中的第三晶体管M3采用N型晶体管。如图10所示，第一晶体管M1、第三晶体管M3和第六晶体管M6是N型晶体管，而第二晶体管M2、第五晶体管M5和第七晶体管M7是P型晶体管。相应地，晶体管与第一和第二电压信号端的耦接关系也发生改变。具体地，对于第二控制电路140，第六晶体管M6的第一极与第二电压信号端Vss耦接。对于补偿电路150，第四晶体管M4的第二极与第二电压信号端Vss耦接。对于发光器件170，OLED器件的第一端与驱动电路160耦接，第二端与第一电压信号端Vdd耦接，并且OLED器件的第一端是阴极，第二端是阳极。此外，图10所示的像素电路的结构与图2所示的像素电路的结构类似，工作时序也类似，不再具体描述。
图11示出图5所示的像素电路的再一个示例性电路图，其中，驱动电路160中的第三晶体管M3采用N型晶体管。与图10不同，在图11所示 的像素电路中，补偿电路150的第四晶体管M4的第二极与第二控制电路的第六晶体管M6的第二极耦接。
图12是根据本公开的实施例的驱动如上的像素电路的方法的示意性流程图。在本公开的实施例中，第一电压信号端提供高电平的第一电压信号，第二电压信号端提供低电平的第二电压信号。
在步骤S1210，在控制信号EM的作用下，使数据写入电路110或者第五晶体管M5导通，以通过数据写入电路110或者第五晶体管M5向第一节点N1提供数据信号Vdata，并通过第一控制电路120或者第二晶体管M2向第二节点N2提供初始化信号Vinit。电容器130或者电容器C存储第一节点N1和第二节点N2之间的电压，即Vdata-Vinit。
在步骤S1220，在控制信号EM的作用下，使第二控制电路140或者第六晶体管M6和驱动电路160或者第三晶体管M3导通，通过补偿电路150或者第四晶体管M4和第一控制电路120或者第一晶体管M1向第二节点N2提供阈值补偿信号(即Vdd+Vth)。通过电容器130或者电容器C保持第一节点N1和第二节点N2之间的电压差为Vdata-Vinit，以控制第一节点N1的电压变为Vdd+Vth+Vdata-Vinit。根据第一节点N1的电压和第一电压信号，使发光器件170或者OLED器件发光。
此外，对于如图5所示的像素电路500，在步骤S1210，还可在控制信号EM的作用下，通过复位电路180或者第七晶体管M7对发光器件170进行复位，以确保用于驱动发光器件170或者OLED器件的驱动电流的稳定性，避免发光器件170或者OLED器件异常发光。
根据本公开的实施例的像素电路能够采用单个控制信号，在两个阶段内完成对像素电路的数据写入、复位、阈值电压及电源I-R Drop的补偿以及发光，从而提高电路的处理速度和稳定性。采用根据本公开的实施例的像素电路，能够减少控制信号的数量，增加内部信号的布线余量，简化外围信号驱动电路的设计并减少信号间的串扰。
以上对本公开的若干实施方式进行了详细描述，但本公开的保护范围并不限于此。显然，对于本领域的普通技术人员来说，在不脱离本公开的 精神和范围的情况下，可以对本公开的实施例进行各种修改、替换或变形。本公开的保护范围由所附权利要求限定。

Claims (18)

  1. 一种像素电路，包括：数据写入电路、第一控制电路、电容器、第二控制电路、补偿电路、驱动电路和发光器件；
    其中，所述数据写入电路被配置为根据来自控制信号端的控制信号，将来自数据信号端的数据信号提供至第一节点；
    所述第一控制电路被配置为根据所述控制信号，将来自所述补偿电路的阈值补偿信号或者来自初始化信号端的初始化信号提供至第二节点；
    所述电容器被配置为存储所述第一节点和所述第二节点之间的电压差；
    所述第二控制电路被配置为根据所述控制信号，将第一电压信号端的第一电压信号提供至所述驱动电路；
    所述补偿电路被配置为根据所述第一电压信号，向所述第一控制电路提供所述阈值补偿信号；
    所述驱动电路被配置为根据所述第一节点的电压和由所述第二控制电路提供的第一电压信号，向所述发光器件提供驱动电流；
    所述发光器件被配置为根据所述驱动电流而发光。
  2. 根据权利要求1所述的像素电路，其中，所述第一控制电路包括：
    第一晶体管，其控制极与所述控制信号端耦接，其第一极与所述补偿电路耦接，其第二极与所述第二节点耦接；
    第二晶体管，其控制极与所述控制信号端耦接，其第一极与所述初始化信号端耦接，其第二极与所述第二节点耦接，
    其中，所述第一晶体管的类型和所述第二晶体管的类型不同。
  3. 根据权利要求1所述的像素电路，其中，所述驱动电路包括：
    第三晶体管，其控制极与所述第一节点耦接，其第一极与所述第二控制电路耦接，其第二极与所述发光器件耦接。
  4. 根据权利要求1所述的像素电路，其中，所述补偿电路包括：
    第四晶体管，其控制极和第一极与所述第一控制电路耦接，其第二极与所述第一电压信号端耦接。
  5. 根据权利要求1所述的像素电路，其中，所述数据写入电路包括：
    第五晶体管，其控制极与所述控制信号端耦接，其第一极与所述数据信号端耦接，其第二极与所述第一节点耦接。
  6. 根据权利要求1所述的像素电路，其中，所述第二控制电路包括：
    第六晶体管，其控制极与所述控制信号端耦接，其第一极与所述第一电压信号端耦接，其第二极与所述驱动电路耦接。
  7. 根据权利要求1所述的像素电路，其中，
    所述驱动电路、所述补偿电路和所述第二控制电路中的晶体管的类型与所述数据写入电路中的晶体管的类型不同。
  8. 根据权利要求1至7中的任一项所述的像素电路，还包括复位电路，所述复位电路与所述发光器件并联耦接，并与所述控制信号端耦接，并被配置为根据所述控制信号，对所述发光器件进行复位。
  9. 根据权利要求8所述的像素电路，其中，所述复位电路包括：
    第七晶体管，其控制极与所述控制信号端耦接，其第一极和第二极分别与所述发光器件的两端耦接。
  10. 根据权利要求9所述的像素电路，其中，
    所述第七晶体管的类型与所述驱动电路中的晶体管的类型不同。
  11. 一种像素电路，包括：第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管、电容器和发光器件；
    其中，所述第一晶体管的控制极与所述控制信号端耦接，其第一极与所述第四晶体管的控制极耦接，其第二极与第二节点耦接；
    所述第二晶体管的控制极与所述控制信号端耦接，其第一极与所述初始化信号端耦接，其第二极与所述第二节点耦接；
    所述电容器被耦接在第一节点和所述第二节点之间；
    所述第三晶体管的控制极与所述第一节点耦接，其第一极与所述第六晶体管的第二极耦接，其第二极与所述发光器件的第一端耦接；
    所述第四晶体管的控制极和第一极与所述第一晶体管的第一极耦接，其第二极与所述第一电压信号端耦接；
    所述第五晶体管的控制极与所述控制信号端耦接，其第一极与所述数据信号端耦接，其第二极与所述第一节点耦接；
    所述第六晶体管的控制极与所述控制信号端耦接，其第一极与所述第一电压信号端耦接，其第二极与所述第三晶体管的第一极耦接；
    所述发光器件的第一端与所述第三晶体管的第二极耦接，其第二端与第二电压信号端耦接，
    其中，所述第一晶体管与所述第二晶体管的类型不同。
  12. 根据权利要求11所述的像素电路，其中，
    所述第三晶体管、所述第四晶体管和所述第六晶体管的类型与所述第五晶体管的类型不同。
  13. 根据权利要求11或12所述的像素电路，还包括第七晶体管，
    所述第七晶体管的控制极与所述控制信号端耦接，其第一极与所述发光器件的第一端耦接，第二极与所述第二电压信号端耦接。
  14. 根据权利要求13所述的像素电路，其中，
    所述第七晶体管的类型与所述第三晶体管的类型不同。
  15. 一种用于驱动如权利要求1至14中的任意一项所述的像素电路的方法，包括：
    在第一时间段，在控制信号的作用下，向第一节点提供数据信号，向第二节点提供初始化信号，以对电容器进行充电；
    在第二时间段，在所述控制信号的作用下，向所述第二节点提供阈值补偿信号，通过所述电容器保持所述第一节点和所述第二节点之间的电压差，以控制所述第一节点的电压，并根据所述第一节点的电压和所述第一电压信号端的第一电压信号，使发光器件发光。
  16. 根据权利要求15所述的方法，其中，
    在所述第一时间段，在所述控制信号的作用下，对所述发光器件进行复位。
  17. 一种阵列基板，包括如权利要求1至14中的任意一项所述的像素电路。
  18. 一种显示装置，包括如权利要求17所述的阵列基板。
PCT/CN2018/072445 2017-06-16 2018-01-12 像素电路及其驱动方法、阵列基板以及显示装置 WO2018227963A1 (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114677957A (zh) * 2022-03-29 2022-06-28 京东方科技集团股份有限公司 一种像素电路、其驱动方法及显示装置

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107103880B (zh) * 2017-06-16 2018-11-20 京东方科技集团股份有限公司 像素驱动电路及其驱动方法、阵列基板以及显示装置
CN108039149B (zh) * 2017-12-07 2020-02-07 京东方科技集团股份有限公司 一种oled像素电路及其驱动方法、显示装置
US11462165B2 (en) * 2019-07-02 2022-10-04 Beijing Boe Technology Development Co., Ltd. Pixel driving circuit, related driving method, pixel circuit, and display panel
CN113112959B (zh) * 2021-04-08 2022-07-12 京东方科技集团股份有限公司 像素电路、显示面板、显示设备及像素电路的驱动方法

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1694135A (zh) * 2004-04-30 2005-11-09 Lg.菲利浦Lcd株式会社 有机发光装置
US20070040772A1 (en) * 2005-08-22 2007-02-22 Yang-Wan Kim Pixel circuit of organic electroluminescent display device and method of driving the same
CN102682706A (zh) * 2012-06-06 2012-09-19 四川虹视显示技术有限公司 一种amoled像素驱动电路
CN102682705A (zh) * 2012-06-06 2012-09-19 四川虹视显示技术有限公司 Amoled像素驱动电路
CN104409047A (zh) * 2014-12-18 2015-03-11 合肥鑫晟光电科技有限公司 像素驱动电路、像素驱动方法和显示装置
CN105096831A (zh) * 2015-08-21 2015-11-25 京东方科技集团股份有限公司 像素驱动电路、方法、显示面板和显示装置
CN105448243A (zh) * 2014-09-22 2016-03-30 Nlt科技股份有限公司 像素电路及其驱动方法以及显示装置
CN105845081A (zh) * 2016-06-12 2016-08-10 京东方科技集团股份有限公司 像素电路、显示面板及驱动方法
CN106205495A (zh) * 2016-09-09 2016-12-07 深圳市华星光电技术有限公司 Amoled像素驱动电路及像素驱动方法
CN107103880A (zh) * 2017-06-16 2017-08-29 京东方科技集团股份有限公司 像素驱动电路及其驱动方法、阵列基板以及显示装置

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4075505B2 (ja) * 2001-09-10 2008-04-16 セイコーエプソン株式会社 電子回路、電子装置、及び電子機器
JP2004054238A (ja) * 2002-05-31 2004-02-19 Seiko Epson Corp 電子回路、電気光学装置、電気光学装置の駆動方法、及び電子機器
JP4123084B2 (ja) * 2002-07-31 2008-07-23 セイコーエプソン株式会社 電子回路、電気光学装置、及び電子機器
JP4144462B2 (ja) * 2002-08-30 2008-09-03 セイコーエプソン株式会社 電気光学装置及び電子機器
JP4048969B2 (ja) * 2003-02-12 2008-02-20 セイコーエプソン株式会社 電気光学装置の駆動方法及び電子機器
TWI261213B (en) * 2003-08-21 2006-09-01 Seiko Epson Corp Optoelectronic apparatus and electronic machine
US20050258867A1 (en) * 2004-05-21 2005-11-24 Seiko Epson Corporation Electronic circuit, electro-optical device, electronic device and electronic apparatus
US8300031B2 (en) * 2005-04-20 2012-10-30 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device comprising transistor having gate and drain connected through a current-voltage conversion element
JP4753373B2 (ja) * 2005-09-16 2011-08-24 株式会社半導体エネルギー研究所 表示装置及び表示装置の駆動方法
KR101962897B1 (ko) * 2012-08-30 2019-03-29 삼성디스플레이 주식회사 화소 및 이를 이용한 유기전계발광 표시장치

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1694135A (zh) * 2004-04-30 2005-11-09 Lg.菲利浦Lcd株式会社 有机发光装置
US20070040772A1 (en) * 2005-08-22 2007-02-22 Yang-Wan Kim Pixel circuit of organic electroluminescent display device and method of driving the same
CN102682706A (zh) * 2012-06-06 2012-09-19 四川虹视显示技术有限公司 一种amoled像素驱动电路
CN102682705A (zh) * 2012-06-06 2012-09-19 四川虹视显示技术有限公司 Amoled像素驱动电路
CN105448243A (zh) * 2014-09-22 2016-03-30 Nlt科技股份有限公司 像素电路及其驱动方法以及显示装置
CN104409047A (zh) * 2014-12-18 2015-03-11 合肥鑫晟光电科技有限公司 像素驱动电路、像素驱动方法和显示装置
CN105096831A (zh) * 2015-08-21 2015-11-25 京东方科技集团股份有限公司 像素驱动电路、方法、显示面板和显示装置
CN105845081A (zh) * 2016-06-12 2016-08-10 京东方科技集团股份有限公司 像素电路、显示面板及驱动方法
CN106205495A (zh) * 2016-09-09 2016-12-07 深圳市华星光电技术有限公司 Amoled像素驱动电路及像素驱动方法
CN107103880A (zh) * 2017-06-16 2017-08-29 京东方科技集团股份有限公司 像素驱动电路及其驱动方法、阵列基板以及显示装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114677957A (zh) * 2022-03-29 2022-06-28 京东方科技集团股份有限公司 一种像素电路、其驱动方法及显示装置

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