WO2018227409A1 - 一种基于mos场效应晶体管的滤波电路及芯片 - Google Patents

一种基于mos场效应晶体管的滤波电路及芯片 Download PDF

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Publication number
WO2018227409A1
WO2018227409A1 PCT/CN2017/088201 CN2017088201W WO2018227409A1 WO 2018227409 A1 WO2018227409 A1 WO 2018227409A1 CN 2017088201 W CN2017088201 W CN 2017088201W WO 2018227409 A1 WO2018227409 A1 WO 2018227409A1
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Prior art keywords
field effect
effect transistor
mos field
mos
esd
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PCT/CN2017/088201
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English (en)
French (fr)
Inventor
陈建兴
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深圳市汇顶科技股份有限公司
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Priority to PCT/CN2017/088201 priority Critical patent/WO2018227409A1/zh
Priority to EP17905914.2A priority patent/EP3447800B1/en
Priority to CN201780000480.3A priority patent/CN107466426B/zh
Priority to US16/171,582 priority patent/US10930643B2/en
Publication of WO2018227409A1 publication Critical patent/WO2018227409A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H01L27/027—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements specially adapted to provide an electrical current path other than the field effect induced current path
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H01L27/027—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements specially adapted to provide an electrical current path other than the field effect induced current path
    • H01L27/0274—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements specially adapted to provide an electrical current path other than the field effect induced current path involving a parasitic bipolar transistor triggered by the electrical biasing of the gate electrode of the field effect transistor, e.g. gate coupled transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H01L27/0285—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements bias arrangements for gate electrode of field effect transistors, e.g. RC networks, voltage partitioning circuits
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
    • H02H9/045—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere
    • H02H9/046—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere responsive to excess voltage appearing at terminals of integrated circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00—Networks using active elements
    • H03H11/02—Multiple-port networks
    • H03H11/38—One-way transmission networks, i.e. unilines

Definitions

  • the present application relates to the field of integrated circuit technology, and in particular, to a filter circuit and a chip based on a MOS field effect transistor.
  • the selected filter capacitor can be MOS (Metal-Oxide-Semiconductor), MIM (Metal-Insulator-Metal), MOM (Metal-Oxide-Metal, Metal-oxide-metal capacitors, etc.
  • MOS capacitor Metal-Oxide-Semiconductor
  • MIM Metal-Insulator-Metal
  • MOM Metal-Oxide-Metal, Metal-oxide-metal capacitors, etc.
  • MOS capacitors are divided into PMOS capacitors and NMOS capacitors.
  • Figures 1 and 2 show the PMOS capacitors and NMOS capacitors as filter capacitors added between the power supply and ground.
  • ESD Electro-Static discharge
  • Such a filter circuit generally only has a capacitance characteristic and does not have an ESD (Electro-Static discharge) characteristic.
  • ESD Electro-Static discharge
  • an ESD event often occurs between the power source and the ground, and the internal device of the chip is always threatened. Safety. Therefore, it is very important to enhance the ESD capability of the chip.
  • the circuit and the chip enable the filter circuit to exhibit a capacitive characteristic during normal operation of the chip, and provide an ESD discharge path when an ESD event occurs between the power supply of the chip and the ground to enhance the ESD capability of the chip.
  • One embodiment of the present application provides a MOS field effect transistor based filter circuit including a first MOS field effect transistor and an electrostatic discharge unit; between the gate of the first MOS field effect transistor and the substrate during normal operation A filter capacitor is formed; when the static electricity is released, the electrostatic discharge cell and the first MOS field effect transistor form a discharge path that transfers the accumulated electrostatic charge to the ground.
  • the embodiment of the present application further provides a chip including the MOS field effect transistor based filter circuit as described above, and the filter circuit is disposed between the power source of the chip and the ground.
  • the embodiment of the present application adds an electrostatic discharge unit based on the first MOS field effect transistor, and combines the capacitance characteristics required between the power source and the ground and the characteristics of the ESD discharge path to the same circuit.
  • the circuit In the normal operation, the circuit exhibits a capacitive characteristic, which functions to filter out AC interference in the power supply; and provides an ESD discharge path when an ESD event occurs between the power supply and the ground, which serves as an ESD protection and is beneficial for enhancement.
  • the ESD capability of the chip is based on the first MOS field effect transistor, and combines the capacitance characteristics required between the power source and the ground and the characteristics of the ESD discharge path to the same circuit.
  • the circuit In the normal operation, the circuit exhibits a capacitive characteristic, which functions to filter out AC interference in the power supply; and provides an ESD discharge path when an ESD event occurs between the power supply and the ground, which serves as an ESD protection and is beneficial for enhancement.
  • the ESD capability of the chip is based on the first MOS
  • the electrostatic discharge unit includes a second MOS field effect transistor and a third MOS field effect transistor; a drain of the first MOS field effect transistor, a drain of the second MOS field effect transistor, and a drain of the third MOS field effect transistor Connecting; a gate of the first MOS field effect transistor, a gate of the second MOS field effect transistor, and a gate of the third MOS field effect transistor are grounded; a source and a substrate of the first MOS field effect transistor, and a second MOS The source of the field effect transistor and the substrate are connected to a power source; the source of the third MOS field effect transistor is grounded to the substrate.
  • a form of an electrostatic discharge unit and its connection structure with a first MOS field effect transistor are provided.
  • the first MOS field effect transistor is a PMOS field effect transistor
  • the second MOS field effect transistor is a PMOS field effect transistor
  • the third MOS field effect transistor is an NMOS field effect crystal.
  • Body tube A type of a first MOS field effect transistor, a second MOS field effect transistor, and a third MOS field effect transistor is provided.
  • the gate of the second MOS field effect transistor and the gate of the third MOS field effect transistor are connected and grounded through a resistor.
  • the series resistors in the gate make the Snap-back easier to turn on, making ESD protection easier.
  • the electrostatic discharge unit includes a second MOS field effect transistor and a third MOS field effect transistor; a drain of the first MOS field effect transistor, a drain of the second MOS field effect transistor, and a drain of the third MOS field effect transistor Connecting; the gate of the first MOS field effect transistor, the gate of the second MOS field effect transistor, and the gate of the third MOS field effect transistor are all connected to the power source; the source and the substrate of the first MOS field effect transistor, and the third The source of the MOS field effect transistor is grounded to the substrate; the source of the second MOS field effect transistor is connected to the substrate. Another connection structure of the electrostatic discharge unit and the first MOS field effect transistor is provided.
  • the first MOS field effect transistor is an NMOS field effect transistor
  • the second MOS field effect transistor is a PMOS field effect transistor
  • the third MOS field effect transistor is still an NMOS field effect transistor. Another type of first MOS field effect transistor is provided.
  • the gate of the second MOS field effect transistor and the gate of the third MOS field effect transistor are connected to each other and connected to the power supply through a resistor.
  • the series resistors in the gate make the Snap-back easier to turn on, making ESD protection easier.
  • the overall size of the first MOS field effect transistor is larger than the overall size of the second MOS field effect transistor; and the overall size of the first MOS field effect transistor is larger than the overall size of the third MOS field effect transistor.
  • the larger the size the smaller the impedance.
  • a parasitic transistor exists between the drain and the source of the third MOS field effect transistor, and a parasitic resistance exists between the base of the parasitic transistor and the substrate of the third MOS field effect transistor; wherein, when a large amount of charge is accumulated in the When the drain of the third MOS field effect transistor is described, the reverse PN junction between the drain of the third MOS field effect transistor and the substrate is broken, and the current flows to the base of the parasitic transistor and flows to the ground via the parasitic resistance. The base voltage of the parasitic transistor is raised and the parasitic transistor is turned on and forms a low impedance discharge path for providing a fast discharge of the accumulated electrostatic charge to the ground.
  • a parasitic transistor exists between the drain and the source of the second MOS field effect transistor, and a parasitic resistance exists between the base of the parasitic transistor and the substrate of the second MOS field effect transistor; wherein, when a large amount of charge is accumulated in the first When the source of the MOS field effect transistor is used, the reverse PN junction between the substrate and the drain of the second MOS field effect transistor is broken, and the current flows to the base of the parasitic transistor and flows through the parasitic resistance to the drain. The base voltage of the parasitic transistor is lowered and the parasitic transistor is turned on and forms a low impedance discharge path for providing a fast discharge of the accumulated electrostatic charge to the drain.
  • FIG. 1 is a schematic structural view of a circuit using a PMOS field effect transistor as a filter capacitor in the prior art
  • FIG. 2 is a schematic structural view of a circuit using an NMOS field effect transistor as a filter capacitor in the prior art
  • FIG. 3 is a schematic structural diagram of a MOS field effect transistor-based filter circuit according to a first embodiment of the present application
  • FIG. 4 is a cross-sectional structural view of a third MOS field effect transistor M3 according to a first embodiment of the present application
  • FIG. 5 is a schematic structural diagram of a MOS field effect transistor-based filter circuit according to a second embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of a MOS field effect transistor-based filter circuit according to a third embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of a MOS field effect transistor based filter circuit according to a fourth embodiment of the present application.
  • the first embodiment of the present application relates to a filter circuit based on a MOS field effect transistor.
  • the filter circuit includes a first MOS field effect transistor and an electrostatic discharge unit.
  • the electrostatic discharge unit may be composed of a plurality of MOS field effect transistors and matched with the first MOS field effect transistor, so that MOS capacitance can be formed between the gate of the first MOS field effect transistor and the substrate during normal operation.
  • the filter capacitor makes the filter circuit exhibit capacitive characteristics; when an ESD event occurs between the power source and the ground, the electrostatic discharge unit can provide a low-impedance discharge path to transfer the accumulated electrostatic charge to the ground for ESD protection.
  • the electrostatic discharge unit may be composed of two MOS field effect transistors, which are a second MOS field effect transistor and a third MOS field effect transistor, respectively.
  • the first MOS field effect transistor is a PMOS field effect transistor
  • the second MOS field effect transistor is a PMOS field effect transistor
  • the third MOS field effect transistor is an NMOS field effect transistor, for example, the first MOS field effect transistor is The connection structure of the electrostatic discharge unit will be specifically described.
  • the drain of the first MOS field effect transistor M1, the drain of the second MOS field effect transistor M2, and the drain of the third MOS field effect transistor M3 are connected to each other (the connection of the three is in FIG. 3).
  • the letter of the first MOS field effect transistor M1 is connected to the ground VSS
  • the gate of the second MOS field effect transistor M2 and the gate of the third MOS field effect transistor M3 are connected to each other and then grounded to VSS.
  • the source and the substrate of the first MOS field effect transistor M1, and the source and the substrate of the second MOS field effect transistor M2 are both connected to the power supply VDD, and the source and the substrate of the third MOS field effect transistor M3 are grounded. VSS.
  • the third MOS field effect transistor M3 is in an off state. At this time, the drain and the source of the third MOS field effect transistor M3 correspond to the off state.
  • the second MOS field effect transistor M2 is in an on state, and therefore, the drain of the first MOS field effect transistor M1 can be connected to the power source VDD through the second MOS field effect transistor M2.
  • the equivalent circuit in FIG. 3 is the same as that in FIG. 1, and the function is also the same as that in FIG. 1. That is, a PMOS capacitor is formed between the gate of the first MOS field effect transistor M1 and the substrate (N-type substrate), which acts as a filter capacitor for filtering out AC interference in the power supply. That is to say, in normal operation, the filter circuit provided in this embodiment exhibits a capacitance characteristic.
  • the overall size of the first MOS field effect transistor M1 is much larger than the other two MOS field effect transistors (ie, the second MOS field effect transistor M2 and the third MOS field effect transistor M3). Since the larger the size, the smaller the impedance, the impedance of the first MOS field effect transistor M1 is much smaller than that of the other two MOS field effect transistors. Therefore, when an ESD event occurs between the power source and the ground, most of the charge from the power source will reach the drain from the source of the first MOS field effect transistor M1, that is, point A, and gather there. As the electrostatic charge (ie, the charge accumulated at point A) increases, the voltage at point A is lifted.
  • the third MOS field effect transistor M3 When the voltage at this point rises to a certain value (turning on the Snap-back voltage value), the third MOS field effect transistor M3 is triggered to enter the Snap-back, that is, the parasitic transistor conduction of the third MOS field effect transistor M3 is triggered.
  • the accumulated electrostatic charge can be discharged to the ground VSS through the low-impedance discharge path (the arrow in Fig. 3 shows the transfer path of most of the charge when the electrostatic discharge is released), thereby protecting the internal components of the chip. That is to say, the filter circuit in this embodiment can provide a low impedance discharge path when an ESD event occurs between the power source and the ground.
  • the cross-sectional structure of the third MOS field effect transistor M3 is as shown in FIG. 4, and there is a parasitic transistor (NPN type) between the drain (D) and the source (S), the base of the parasitic transistor and the third MOS field effect transistor. There is a parasitic resistance R between the substrates.
  • NPN type parasitic transistor
  • R parasitic resistance
  • the conduction uniformity (also referred to as turn-on uniformity) of the third MOS field effect transistor M3 will affect its electrostatic protection performance. In design, it can pass Appropriately increasing the width of the drain (which is equivalent to increasing the resistance in the circuit to reduce the current) increases its conduction uniformity, thereby increasing its ability to discharge static electricity.
  • the present embodiment adds an electrostatic discharge unit based on the first MOS field effect transistor, and combines the capacitance characteristics required between the power source and the ground and the characteristics of the ESD discharge path into the same circuit.
  • the circuit exhibits a capacitive characteristic during normal operation, and functions to filter out AC interference in the power supply; an ESD discharge path is provided when an ESD event occurs between the power supply and the ground, which serves as an ESD protection and is beneficial to enhancing the chip. ESD capabilities.
  • the second embodiment of the present application relates to a filter circuit based on a MOS field effect transistor.
  • This embodiment further improves the structure of the filter circuit based on the first embodiment.
  • the main improvement is that in the embodiment, the gate of the second MOS field effect transistor and the gate of the third MOS field effect transistor are connected to each other and then grounded through a resistor VSS.
  • the gate of the second MOS field effect transistor M2 is connected to the gate of the third MOS field effect transistor M3, and then grounded to VSS through the resistor R0.
  • the parasitic transistor conduction of the third MOS field effect transistor can be triggered more easily and quickly to form a low-impedance discharge path (the arrows in FIG. 5 show most of the electrostatic discharge).
  • the transfer path of the charge thereby rapidly discharging the accumulated electrostatic charge to the ground, is advantageous for improving the charge discharge capability of the chip and better protecting the device inside the chip.
  • the embodiment reduces the voltage of the third MOS field effect transistor into the Snap-back, so that it is easier to trigger the parasitic transistor conduction of the third MOS field effect transistor when the ESD event occurs, forming a low impedance.
  • the discharge path is beneficial to improve the charge release capability.
  • the third embodiment of the present application relates to a filter circuit based on a MOS field effect transistor.
  • This embodiment can be used as an alternative embodiment of the first embodiment.
  • the difference between the two is that the first MOS field effect transistor is a PMOS field effect transistor as an example, and the embodiment is used.
  • the first MOS field effect transistor will be described as an NMOS field effect transistor.
  • connection structure of the three is as follows :
  • the drain of the first MOS field effect transistor M1, the drain of the second MOS field effect transistor M2, and the drain of the third MOS field effect transistor M3 are connected to each other (the connection of the three is indicated by the letter A). Out).
  • the gate of the first MOS field effect transistor M1 is connected to the power supply VDD
  • the gate of the second MOS field effect transistor M2 and the gate of the third MOS field effect transistor M3 are connected to each other and then connected to the power supply VDD.
  • the source and the substrate of the first MOS field effect transistor M1 and the source and the substrate of the third MOS field effect transistor M3 are both grounded to VSS; the source and the substrate of the second MOS field effect transistor M2 are connected to the power supply VDD. .
  • the second MOS field effect transistor M2 In normal operation, the second MOS field effect transistor M2 is in an off state. At this time, the source and the drain of the second MOS field effect transistor M2 are equivalent to being in an off state.
  • the third MOS field effect transistor M3 is in an on state, and therefore, the drain of the first MOS field effect transistor M1 can be grounded to VSS through the third MOS field effect transistor M3.
  • the equivalent circuit in Figure 5 and the phase in Figure 2 Similarly, the function is the same as in FIG. 2. That is, the gate of the first MOS field effect transistor M1 forms a NMOS capacitor with the substrate, which acts as a filter capacitor for filtering out AC interference in the power supply. That is to say, in normal operation, the filter circuit provided in this embodiment exhibits a capacitance characteristic.
  • the electrostatic charge concentrated at the source of the second MOS field effect transistor M2 raises the voltage at that point, and the voltage at that point is raised to a certain value (turning on Snap-).
  • the second MOS field effect transistor M2 is activated to turn on the Snap-back, that is, the parasitic transistor of the second MOS field effect transistor M2 is turned on to form a low impedance discharge path.
  • the accumulated electrostatic charge can be vented to point A through the low impedance discharge path.
  • a parasitic transistor exists between the drain and the source of the second MOS field effect transistor, and a parasitic resistance exists between the base of the parasitic transistor and the substrate of the second MOS field effect transistor.
  • PNP type parasitic transistor
  • a parasitic resistance exists between the base of the parasitic transistor and the substrate of the second MOS field effect transistor.
  • the overall size of the first MOS field effect transistor M1 is still much larger than the overall size of the other two MOS field effect transistors, that is, the impedance of the first MOS field effect transistor M1 is much smaller than other The impedance of two MOS field effect transistors. Therefore, after the charge is discharged to the A point, most of the charge flows to the source of the first MOS field effect transistor M1, and then flows from the source of the first MOS field effect transistor M1 to the ground VSS (the arrow in FIG.
  • This embodiment provides another type of first MOS field effect transistor M1 and a connection structure of the electrostatic discharge unit and the first MOS field effect transistor with respect to the first embodiment.
  • the fourth embodiment of the present invention relates to a filter circuit based on a MOS field effect transistor.
  • This embodiment further improves the structure of the filter circuit based on the third embodiment.
  • the main improvement is that in the embodiment, the gate of the second MOS field effect transistor is connected to the gate of the third MOS field effect transistor and is connected to the power supply VDD through a resistor.
  • the gate of the third MOS field effect transistor M3 is connected to the gate of the second MOS field effect transistor M2, and then connected to the power supply VDD through the resistor R1.
  • the second MOS field effect transistor can be in a weakly conducting state when an ESD event occurs, thereby reducing the voltage value of the second MOS field effect transistor entering the Snap-back, so that the second MOS field effect transistor Snap-back is easier to open. That is, this design structure makes it easier and faster to trigger the parasitic transistor conduction of the second MOS field effect transistor when an ESD event occurs, forming a low-impedance discharge path (the arrow in FIG. 7 shows the electrostatic discharge). , the majority of the charge transfer path), so that the electrostatic charge of the aggregate is quickly discharged to the ground, which is more conducive to improving the ESD capability of the chip to better protect the devices inside the chip.
  • the embodiment reduces the voltage of the second MOS field effect transistor into the Snap-back, so that the parasitic transistor of the second MOS field effect transistor can be triggered more easily and faster when an ESD event occurs. Turning on, forming a low-impedance discharge path, is beneficial to improve the charge discharge capability.
  • a fifth embodiment of the present application relates to a chip.
  • the chip includes the MOS field effect transistor-based filter circuit described in the above embodiment, and the filter circuit is disposed between the power supply of the chip and the ground.
  • the filter circuit When the chip is working normally, the filter circuit exhibits a capacitance characteristic; when an ESD event occurs between the power supply of the chip and the ground, the filter circuit provides a low-impedance discharge path, and discharges the accumulated electrostatic charge to the ground, thereby avoiding chip Internal components are damaged by overvoltage.
  • the present embodiment adds an electrostatic discharge unit based on the first MOS field effect transistor, and combines the capacitance characteristics required between the power source and the ground and the characteristics of the ESD discharge path into the same circuit.
  • the chip exhibits capacitive characteristics during normal operation; it provides a low-impedance ESD discharge path when an ESD event occurs between the power supply of the chip and the ground, and functions as an ESD protection.

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  • Microelectronics & Electronic Packaging (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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Abstract

一种基于MOS场效应晶体管的滤波电路及芯片，该滤波电路包括第一MOS场效应晶体管（M1）和静电释放单元；在正常工作时，第一MOS场效应晶体管（M1）的栅极（G）与衬底之间形成滤波电容；在发生ESD事件时，静电释放单元与第一MOS场效应晶体管（M1）形成将聚集的静电电荷转移至地（VSS）的放电通路。在第一MOS场效应晶体管（M1）的基础上，增设了静电释放单元，从而将电源（VDD）与地（VSS）之间同时需要的电容特性及ESD放电通路的特性结合至同一电路中，使该电路在正常工作时呈现电容特性；在电源（VDD）与地（VSS）之间发生ESD事件时提供ESD放电通路，起到ESD保护的作用，从而提升芯片的ESD能力。

Description

一种基于MOS场效应晶体管的滤波电路及芯片 技术领域
本申请涉及集成电路技术领域，特别涉及一种基于MOS场效应晶体管的滤波电路及芯片。
背景技术
在芯片设计的收尾阶段，一般会在芯片的空余部位加上从电源到地的滤波电路。选用的滤波电容可以是MOS(Metal-Oxide-Semiconductor，金属-氧化物-半导体)场效应晶体管电容、MIM(Metal-Insulator-Metal,金属-绝缘体-金属)电容、MOM(Metal-Oxide-Metal，金属-氧化物-金属)电容等。但考虑到MOS场效应晶体管电容(下文简称为MOS电容)的单位面积容值比其它电容更大，在同等面积的情况下可以获取更大的电容，因此，通常情况下，都会选择MOS电容作为滤波电容。
MOS电容分为PMOS电容与NMOS电容两种，图1、2分别示出了PMOS电容及NMOS电容作为滤波电容加在电源与地之间的示意图。这种滤波电路一般只具备电容特性，并不具备ESD(Electro-Static discharge，静电释放)特性但在实际应用中，电源与地之间还会经常发生ESD事件，并时刻威胁着芯片内部器件的安全。因此，增强芯片的ESD能力显得十分重要。
发明内容
本申请部分实施例的目的在于提供一种基于MOS场效应晶体管的滤波 电路及芯片，使得该滤波电路可在芯片正常工作时呈现电容特性，在芯片的电源与地之间发生ESD事件时提供ESD放电通路，增强芯片的ESD能力。
本申请的一个实施例提供了一种基于MOS场效应晶体管的滤波电路，包括第一MOS场效应晶体管和静电释放单元；在正常工作时，第一MOS场效应晶体管的栅极与衬底之间形成滤波电容；在静电释放时，静电释放电元与第一MOS场效应晶体管形成将聚集的静电电荷转移至地的放电通路。
本申请实施例还提供了一种芯片，包括如上所述的基于MOS场效应晶体管的滤波电路，滤波电路设置在芯片的电源与地之间。
本申请实施例相对于现有技术而言，在第一MOS场效应晶体管的基础上，增设了静电释放单元，将电源与地之间同时需要的电容特性及ESD放电通路的特性结合至同一电路中，使该电路在正常工作时呈现电容特性，起到滤除电源中的交流干扰的作用；在电源与地之间发生ESD事件时提供ESD放电通路，起到ESD保护的作用，有利于增强芯片的ESD能力。
另外，静电释放单元包括第二MOS场效应晶体管及第三MOS场效应晶体管；第一MOS场效应晶体管的漏极、第二MOS场效应晶体管的漏极及第三MOS场效应晶体管的漏极相互连接；第一MOS场效应晶体管的栅极、第二MOS场效应晶体管的栅极及第三MOS场效应晶体管的栅极均接地；第一MOS场效应晶体管的源极与衬底、第二MOS场效应晶体管的源极与衬底均连接电源；第三MOS场效应晶体管的源极与衬底接地。提供一种静电释放单元的形式以及其与第一MOS场效应晶体管的连接结构。
另外，第一MOS场效应晶体管为PMOS场效应晶体管，第二MOS场效应晶体管为PMOS场效应晶体管，第三MOS场效应晶体管为NMOS场效应晶 体管。提供一种第一MOS场效应晶体管、第二MOS场效应晶体管及第三MOS场效应晶体管的类型。
另外，第二MOS场效应晶体管的栅极及第三MOS场效应晶体管的栅极连接后通过一电阻接地。在栅极串联电阻，使得Snap-back更容易开启，从而更容易起到ESD保护作用。
另外，静电释放单元包括第二MOS场效应晶体管及第三MOS场效应晶体管；第一MOS场效应晶体管的漏极、第二MOS场效应晶体管的漏极及第三MOS场效应晶体管的漏极相互连接；第一MOS场效应晶体管的栅极、第二MOS场效应晶体管的栅极及第三MOS场效应晶体管的栅极均连接电源；第一MOS场效应晶体管的源极与衬底、第三MOS场效应晶体管的源极与衬底均接地；第二MOS场效应晶体管的源极与衬底连接电源。提供另一种静电释放单元与第一MOS场效应晶体管的连接结构。
另外，第一MOS场效应晶体管为NMOS场效应晶体管，第二MOS场效应晶体管为PMOS场效应晶体管，第三MOS场效应晶体管仍为NMOS场效应晶体管。提供另一种第一MOS场效应晶体管的类型。
另外，第二MOS场效应晶体管的栅极及第三MOS场效应晶体管的栅极连接后通过一电阻连接电源。在栅极串联电阻，使得Snap-back更容易开启，从而更容易起到ESD保护作用。
另外，第一MOS场效应晶体管的整体尺寸大于第二MOS场效应晶体管的整体尺寸；且第一MOS场效应晶体管的整体尺寸大于第三MOS场效应晶体管的整体尺寸。尺寸越大，阻抗越小，这种设计结构可使第一MOS场效应晶体管将更多的静电电荷转移至地，有助于增强ESD电荷泄放能力。
另外，第三MOS场效应晶体管的漏极与源极之间存在寄生三极管，寄生三极管的基极与第三MOS场效应晶体管的衬底之间存在寄生电阻；其中，当大量的电荷聚集在所述第三MOS场效应晶体管的漏极时，第三MOS场效应晶体管的漏极与衬底之间的反向PN结被击穿，电流流向寄生三极管的基极并经寄生电阻流到地端，而使得寄生三极管的基极电压抬升且寄生三极管导通并形成低阻抗的放电通路，放电通路用于给聚集的静电电荷提供快速泄放到地的通道。
另外，第二MOS场效应晶体管的漏极与源极之间存在寄生三极管，寄生三极管的基极与第二MOS场效应晶体管的衬底之间存在寄生电阻；其中，当大量的电荷聚集在第二MOS场效应晶体管的源极时，第二MOS场效应晶体管的衬底与漏极之间的反向PN结被击穿，电流流向寄生三极管的基极并经寄生电阻流到漏极，而使得寄生三极管的基极电压下降且寄生三极管导通并形成低阻抗的放电通路，放电通路用于给聚集的静电电荷提供快速泄放到漏极的通道。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，附图中具有相同参考数字标号的元件表示为类似的元件，除非有特别申明，附图中的图不构成比例限制。
图1是现有技术用PMOS场效应晶体管作为滤波电容的电路的结构示意图；
图2是现有技术用NMOS场效应晶体管作为滤波电容的电路的结构示意图；
图3是根据本申请第一实施例的基于MOS场效应晶体管的滤波电路的结构示意图；
图4是根据本申请第一实施例的第三MOS场效应晶体管M3的剖面结构示意图；
图5是根据本申请第二实施例的基于MOS场效应晶体管的滤波电路的结构示意图；
图6是根据本申请第三实施例的基于MOS场效应晶体管的滤波电路的结构示意图；
图7是根据本申请第四实施例的基于MOS场效应晶体管的滤波电路的结构示意图。
具体实施方式
为了使本申请的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本申请部分实施例进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本申请，并不用于限定本申请。
本申请第一实施例涉及一种基于MOS场效应晶体管的滤波电路。该滤波电路包括第一MOS场效应晶体管和静电释放单元。
该静电释放单元可由多个MOS场效应晶体管组成，并与第一MOS场效应晶体管相配合，以使在正常工作时，第一MOS场效应晶体管的栅极与衬底之间可形成MOS电容作为滤波电容，使该滤波电路呈现电容特性；在电源与地之间发生ESD事件时，静电释放单元可提供低阻抗的放电通路，将聚集的静电电荷转移至地，达到ESD保护的目的。
较佳地，静电释放单元可由两个MOS场效应晶体管组成，其分别为第二MOS场效应晶体管及第三MOS场效应晶体管。本实施例以第一MOS场效应晶体管为PMOS场效应晶体管、第二MOS场效应晶体管为PMOS场效应晶体管、第三MOS场效应晶体管为NMOS场效应晶体管为例，对第一MOS场效应晶体管与静电释放单元的连接结构作具体地说明。
如图3所示，第一MOS场效应晶体管M1的漏极、第二MOS场效应晶体管M2的漏极及第三MOS场效应晶体管M3的漏极相互连接(三者的连接处在图3中用字母A示出)；第一MOS场效应晶体管M1的栅极连接至地VSS，第二MOS场效应晶体管M2的栅极与第三MOS场效应晶体管M3的栅极相互连接后再共同接地VSS；第一MOS场效应晶体管M1的源极与衬底、以及第二MOS场效应晶体管M2的源极与衬底均连接至电源VDD，第三MOS场效应晶体管M3的源极与衬底则接地VSS。
正常工作时，第三MOS场效应晶体管M3处于截止状态。此时，第三MOS场效应晶体管M3的漏极与源极相当于断开状态。而第二MOS场效应晶体管M2处于导通状态，因此，第一MOS场效应晶体管M1的漏极可通过第二MOS场效应晶体管M2与电源VDD连接。由此可见，正常工作时，图3中的等效电路与图1中的相同，功能也与图1相同。即，第一MOS场效应晶体管M1的栅极与衬底(N型衬底)之间形成PMOS电容，其作为滤波电容用于滤除电源中的交流干扰。也就是说，正常工作时，本实施例提供的滤波电路呈现电容特性。
值得一提的是，本实施例中，第一MOS场效应晶体管M1的整体尺寸远远大于其它两个MOS场效应晶体管(即第二MOS场效应晶体管M2及第三 MOS场效应晶体管M3)。由于尺寸越大，阻抗越小，因此，第一MOS场效应晶体管M1的阻抗远远小于其它两个MOS场效应晶体管。所以，当电源与地之间发生ESD事件时，来自电源的绝大部分电荷会从第一MOS场效应晶体管M1的源极到达漏极，即A点处，并在此聚集。随着静电电荷(即聚集在A点处的电荷)的增多，A点处的电压会被抬升。当该点处的电压抬升至一定数值(开启Snap-back的电压值)时，就会触发第三MOS场效应晶体管M3进入Snap-back，即触发第三MOS场效应晶体管M3的寄生三极管导通，形成一条低阻抗的放电通路。聚集的静电电荷即可通过该低阻抗的放电通路泄放到地VSS(图3中的箭头示出了静电释放时，绝大部分电荷的转移路径)，以此保护芯片的内部器件。也就是说，在电源与地之间发生ESD事件时，本实施例中的滤波电路可提供低阻抗的放电通路。
下面将简要说明第三MOS场效应晶体管M3如何将聚集在其漏极处的静电电荷泄放至地VSS的。
第三MOS场效应晶体管M3的剖面结构如图4所示，漏极(D)与源极(S)之间存在寄生三极管(NPN型)，寄生三极管的基极与第三MOS场效应晶体管的衬底之间存在寄生电阻R。当大量的电荷聚集在漏极时，漏极与衬底(P-substrate)之间的反向PN结会被击穿。此时，电流会流向寄生三极管的基极，并经寄生电阻R流到B端(即地VSS)，使寄生三极管的基极电压抬升，使寄生三极管导通，从而开启Snap-back，形成低阻抗的放电通路。聚集的静电电荷即可通过该低阻抗的放电通路快速泄放到地。
值得一提的是，在ESD保护中，第三MOS场效应晶体管M3的导通均匀性(也可称为开启均匀性)将会影响到其静电保护的性能。在设计时，可通 过适当增加漏极的宽度(这在电路中相当于增大电阻，从而减小电流)来提高其导通均匀性，从而提高其静电释放的能力。
本实施例相对于现有技术而言，在第一MOS场效应晶体管的基础上，增设了静电释放单元，将电源与地之间同时需要的电容特性及ESD放电通路的特性结合至同一电路中，使该电路在正常工作时呈现电容特性，起到滤除电源中的交流干扰的作用；在电源与地之间发生ESD事件时提供ESD放电通路，起到ESD保护的作用，有利于增强芯片的ESD能力。
本申请第二实施例涉及一种基于MOS场效应晶体管的滤波电路。本实施例在第一实施例的基础上，对该滤波电路的结构作了进一步改进。主要改进之处在于，本实施例中，第二MOS场效应晶体管的栅极与第三MOS场效应晶体管的栅极相互连接后通过一电阻接地VSS。
如图5所示，第二MOS场效应晶体管M2的栅极与第三MOS场效应晶体管M3的栅极连接后，再通过电阻R0接地VSS。第三MOS场效应晶体管M3的栅极(G)与漏极(D)之间存在寄生电容，连接电阻R0可使静电电荷从寄生电容耦合至电阻R0，从而使第三MOS场效应晶体管M3在发生ESD事件时处于弱导通状态。这种情况下，开启Snap-back的电压会被降低，会更容易触发第三MOS场效应晶体管M3开启Snap-back。即，使得发生ESD事件时，可以更容易、更快地触发第三MOS场效应晶体管的寄生三极管导通，形成低阻抗的放电通路(图5中的箭头示出了静电释放时，绝大部分电荷的转移路径)，从而快速地将聚集地静电电荷泄放到地，有利于提升芯片的电荷泄放能力，更好地保护芯片内部的器件。
本实施例相对于第一实施例而言，降低了第三MOS场效应晶体管进入Snap-back的电压，使得发生ESD事件时更容易触发第三MOS场效应晶体管的寄生三极管导通，形成低阻抗的放电通路，有利于提高电荷泄放能力。
本申请第三实施例涉及一种基于MOS场效应晶体管的滤波电路。本实施例可作为第一实施例的替换实施例，两者的区别之处在于：第一实施例中是以第一MOS场效应晶体管为PMOS场效应晶体管为例进行说明的，而本实施例将以第一MOS场效应晶体管为NMOS场效应晶体管为例进行说明。
当第一MOS场效应晶体管M1为NMOS场效应晶体管，而第二MOS场效应晶体管M2仍为PMOS场效应晶体管、第三MOS场效应晶体管M3仍为NMOS场效应晶体管时，三者的连接结构如下：
如图6所示，第一MOS场效应晶体管M1的漏极、第二MOS场效应晶体管M2的漏极及第三MOS场效应晶体管M3的漏极相互连接(三者的连接处用字母A示出)。第一MOS场效应晶体管M1的栅极连接电源VDD，第二MOS场效应晶体管M2的栅极与第三MOS场效应晶体管M3的栅极相互连接后再共同接至电源VDD。第一MOS场效应晶体管M1的源极与衬底、以及第三MOS场效应晶体管M3的源极与衬底均接地VSS；第二MOS场效应晶体管M2的源极与衬底则连接至电源VDD。
正常工作时，第二MOS场效应晶体管M2处于截止状态。此时，第二MOS场效应晶体管M2的源极与漏极相当于处于断开状态。而第三MOS场效应晶体管M3处于导通状态，因此，第一MOS场效应晶体管M1的漏极可通过第三MOS场效应晶体管M3接地VSS。此时，图5中的等效电路与图2中相 同，功能也与图2相同。即，第一MOS场效应晶体管M1的栅极与衬底形成NMOS电容，其作为滤波电容用于滤除电源中的交流干扰。也就是说，正常工作时，本实施例提供的滤波电路呈现电容特性。
当电源与地之间发生ESD事件时，聚集在第二MOS场效应晶体管M2的源极处的静电电荷会抬升该点处的电压，当该点处的电压被抬升至一定数值(开启Snap-back的电压值)时，就会触动第二MOS场效应晶体管M2开启Snap-back，即触发第二MOS场效应晶体管M2的寄生三极管导通，形成一条低阻抗的放电通路。聚集的静电电荷即可通过该低阻抗的放电通路泄放到A点。
具体地说，第二MOS场效应晶体管的漏极与源极之间存在寄生三极管(PNP型)，该寄生三极管的基极与第二MOS场效应晶体管的衬底之间也存在寄生电阻。当大量的电荷聚集在第二MOS场效应晶体管的源极时，第二MOS场效应晶体管的衬底与漏极之间的反向PN结被击穿。此时，电流流向寄生三极管的基极并经寄生电阻流到漏极(A点)，使得寄生三极管的基极电压下降，使寄生三极管导通，从而开启Snap-back，形成低阻抗的放电通路。聚集的静电电荷即可通过该低阻抗的放电通路快速泄放到A点。
同样地，本实施例中，第一MOS场效应晶体管M1的整体尺寸仍远远大于其它两个MOS场效应晶体管的整体尺寸，也就是说，第一MOS场效应晶体管M1的阻抗远远小于其它两个MOS场效应晶体管的阻抗。因此，电荷泄放到A点后，绝大部分电荷会流向第一MOS场效应晶体管M1的源极，再从第一MOS场效应晶体管M1的源极流向地VSS(图6中的箭头示出了静电释放时，绝大部分电荷的转移路径)；仅有很少的一部分会流向第三MOS场效应晶体管M3的源极，再流向地VSS，而后一部分相当于前一部分基本可忽略不 计。
本实施例相对于第一实施例而言，提供了另一种第一MOS场效应晶体管M1的类型，以及静电释放单元与第一MOS场效应晶体管的连接结构。
本实施第四实施例涉及一种基于MOS场效应晶体管的滤波电路。本实施例在第三实施例的基础上，对该滤波电路的结构作了进一步改进。主要改进之处在于，本实施例中，第二MOS场效应晶体管的栅极与第三MOS场效应晶体管的栅极连接后通过一电阻连接至电源VDD。
如图7所示，第三MOS场效应晶体管M3的栅极与第二MOS场效应晶体管M2的栅极连接后，再通过电阻R1连接至电源VDD。同样地，连接电阻R1，可使第二MOS场效应晶体管在发生ESD事件时处于弱导通状态，从而降低第二MOS场效应晶体管进入Snap-back的电压值，使第二MOS场效应晶体管的Snap-back更容易开启。即，这种设计结构使得发生ESD事件时，可以更容易、更快地触发第二MOS场效应晶体管的寄生三极管导通，形成低阻抗的放电通路(图7中的箭头示出了静电释放时，绝大部分电荷的转移路径)，从而快速地将聚集地静电电荷泄放到地，更有利于提升芯片的ESD能力，以更好地保护芯片内部的器件。
本实施例相对于第一实施例而言，降低了第二MOS场效应晶体管进入Snap-back的电压，使得发生ESD事件时，可以更容易、更快地触发第二MOS场效应晶体管的寄生三极管导通，形成低阻抗的放电通路，有利于提高电荷泄放能力。
本申请的第五实施例涉及一种芯片。该芯片包括上述实施例所述的基于MOS场效应晶体管的滤波电路，该滤波电路设在芯片的电源与地之间。
在芯片正常工作时，该滤波电路呈现电容特性；在芯片的电源与地之间发生ESD事件时，该滤波电路提供低阻抗的放电通路，将聚集的静电电荷泄放到地，从而避免芯片的内部器件因过压而损坏。
本实施例相对于现有技术而言，在第一MOS场效应晶体管的基础上，增设了静电释放单元，将电源与地之间同时需要的电容特性及ESD放电通路的特性结合至同一电路中，使芯片在正常工作时呈现电容特性；在芯片的电源与地之间发生ESD事件时提供低阻抗的ESD放电通路，起到ESD保护的作用。
本领域的普通技术人员可以理解，上述各实施例是实现本申请的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本申请的精神和范围。
Figure PCTCN2017088201-appb-000001

Claims (6)

  1. 连接后通过一电阻接地。
  2. 根据权利要求1所述的基于MOS场效应晶体管的滤波电路，其特征在于，所述静电释放单元包括第二MOS场效应晶体管及第三MOS场效应晶体管；
    所述第一MOS场效应晶体管的漏极、所述第二MOS场效应晶体管的漏极及所述第三MOS场效应晶体管的漏极相互连接；所述第一MOS场效应晶体管的栅极、所述第二MOS场效应晶体管的栅极及所述第三MOS场效应晶体管的栅极均连接电源；所述第一MOS场效应晶体管的源极与衬底、所述第三MOS场效应晶体管的源极与衬底均接地；所述第二MOS场效应晶体管的源极与衬底连接所述电源。
  3. 根据权利要求5所述的基于MOS场效应晶体管的滤波电路，其特征在于，所述第一MOS场效应晶体管为NMOS场效应晶体管，所述第二MOS场效应晶体管为PMOS场效应晶体管，所述第三MOS场效应晶体管仍为NMOS场效应晶体管。
  4. 根据权利要求5所述的基于MOS场效应晶体管的滤波电路，其特征在于，所述第二MOS场效应晶体管的栅极与所述第三MOS场效应晶体管的栅极连接后通过一电阻连接所述电源。
  5. 根据权利要求2至7中任一项所述的基于MOS场效应晶体管的滤波电路，其特征在于，所述第一MOS场效应晶体管的整体尺寸大于所述第二MOS场效应晶体管的整体尺寸；且所述第一MOS场效应晶体管的整体尺寸大于所述第三MOS场效应晶体管的整体尺寸。
  6. 根据权利要求2至4中任一项所述的基于MOS场效应晶体管的滤波电路，其特征在于，所述第三MOS场效应晶体管的漏极与源极之间存在寄生三
PCT/CN2017/088201 2017-06-14 2017-06-14 一种基于mos场效应晶体管的滤波电路及芯片 WO2018227409A1 (zh)

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EP17905914.2A EP3447800B1 (en) 2017-06-14 2017-06-14 Mos field effect transistor-based filter circuit and chip
CN201780000480.3A CN107466426B (zh) 2017-06-14 2017-06-14 一种基于mos场效应晶体管的滤波电路及芯片
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