WO2018223642A1 - 阵列基板及其制造方法、显示面板以及显示装置 - Google Patents

阵列基板及其制造方法、显示面板以及显示装置 Download PDF

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WO2018223642A1
WO2018223642A1 PCT/CN2017/115424 CN2017115424W WO2018223642A1 WO 2018223642 A1 WO2018223642 A1 WO 2018223642A1 CN 2017115424 W CN2017115424 W CN 2017115424W WO 2018223642 A1 WO2018223642 A1 WO 2018223642A1
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Prior art keywords
electrode
source
substrate
projection
gate electrode
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PCT/CN2017/115424
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English (en)
French (fr)
Chinese (zh)
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李子华
刘静
刘祺
马群
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京东方科技集团股份有限公司
鄂尔多斯市源盛光电有限责任公司
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Application filed by 京东方科技集团股份有限公司, 鄂尔多斯市源盛光电有限责任公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/065,224 priority Critical patent/US20210193694A9/en
Priority to EP17899227.7A priority patent/EP3640985A4/en
Priority to JP2018548446A priority patent/JP7403225B2/ja
Publication of WO2018223642A1 publication Critical patent/WO2018223642A1/zh

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    • H—ELECTRICITY
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile

Definitions

  • the present disclosure relates to the field of display technology. More specifically, it relates to an array substrate and a method of manufacturing the same, a display panel, and a display device.
  • TFTs Thin film transistors
  • MOS metal oxide semiconductor
  • An aging process has been proposed to reduce leakage current in the TFT.
  • the Aging process can have new adverse effects, such as burns, added highlights, anomalous displays, and the like.
  • LDD lightly doped drain region
  • a first aspect of the present disclosure provides an array substrate.
  • the array substrate includes: an active layer disposed on a substrate, the active layer including a channel region, source/drain regions disposed on both sides of the channel region, and a channel region disposed in the channel region a lightly doped drain region between the source/drain regions; a gate electrode and a first electrode disposed on the active layer; a first insulating layer disposed on the gate electrode and the first electrode; a blocking portion disposed on the first insulating layer and a second electrode, wherein a projection of the second electrode on the substrate at least partially overlaps a projection of the first electrode on the substrate, a projection coverage of the barrier on the substrate Projection of the lightly doped drain region on the substrate, the projection of the barrier on the substrate does not overlap with the projection of the source/drain region on the substrate, and Wherein, the blocking portion and the second electrode are disposed in the same layer.
  • the barrier has an opening, the projection of the opening on the substrate at least partially overlapping the projection of the gate electrode on the substrate.
  • the width of the lightly doped drain region ranges from about 0.5 um to 1 um.
  • the array substrate further includes: a second insulating layer disposed between the active layer and the gate electrode; passing through the first insulating layer and the second insulating layer a via hole; a source/drain electrode disposed on the first insulating layer, the source/drain electrode being in contact with the source/drain region via the via.
  • the source/drain regions have a doping concentration greater than a doping concentration of the lightly doped drain region, and wherein the source/drain regions have a doping concentration range of about 4.5 ⁇ 10 15 to 6 ⁇ 10 15 ions/cm 3 , and the doping concentration of the lightly doped drain region ranges from about 5 ⁇ 10 12 to 4.5 ⁇ 10 15 ions/cm 3 .
  • a second aspect of the present disclosure provides a display panel.
  • the display panel includes the array substrate as described above.
  • a third aspect of the present disclosure provides a display device.
  • the display device includes a display panel as described above.
  • a fourth aspect of the present disclosure provides a method of fabricating an array substrate.
  • the manufacturing method of the array substrate includes: forming an active layer on a substrate; forming a gate electrode and a first electrode on the active layer; forming a first on the gate electrode and the first electrode An insulating layer; forming a barrier material layer on the insulating layer; processing the barrier material layer by a patterning process to form a barrier portion and a second electrode, wherein a projection of the second electrode on the substrate At least partially overlapping a projection of the first electrode on the substrate, the barrier being remote from the gate a projection of a portion of the electrode electrode extending outwardly on the substrate is located within a projection of a portion of the active layer that extends outward from a side of the gate electrode on a substrate;
  • the blocking portion is used as a mask, and the active layer is first doped to form source/drain regions on both sides of the channel region of the active layer and disposed in the channel region and the source/ A lightly doped drain region between the
  • the barrier has an opening, the projection of the opening on the substrate at least partially overlapping the projection of the gate electrode on the substrate.
  • the width of the lightly doped drain region ranges from about 0.5 um to 1 um.
  • the doping energy of the first doping is between about 30 KeV and 40 KeV.
  • a doping concentration of the source/drain regions is greater than a doping concentration of the lightly doped drain region, and wherein a doping concentration of the source/drain regions of the source/drain regions The range is about 4.5 x 10 15 to 6 x 10 15 ions/cm 3 , and the doping concentration of the lightly doped drain (LDD) region ranges from about 5 x 10 12 to 4.5 x 10 15 ions/cm 3 .
  • the conductivity type of the channel region is N-type
  • the conductivity type of the lightly doped drain region and the conductivity type of the doped region of the source/drain region are P-type.
  • the method of fabricating the array substrate further includes: forming a second insulating layer on the active layer before forming the gate electrode and the first electrode; forming the source/ After the drain region, a via hole is formed through the first insulating layer and the second insulating layer; a source/drain electrode is formed on the first insulating layer, and the source/drain electrode passes through the via hole Contacting the source/drain regions.
  • forming the gate electrode and the first electrode includes: forming a gate electrode material layer on the second insulating layer; patterning the gate electrode material layer to form the a gate electrode and the first electrode.
  • the method of fabricating the array substrate further includes: doping the active layer with the gate electrode as a mask after forming the gate electrode and the first electrode, To define a channel region of the active layer.
  • FIG. 1(a) is a schematic illustration of an array substrate in accordance with an embodiment of the present disclosure
  • FIG. 1(b) is a schematic illustration of an array substrate in accordance with an embodiment of the present disclosure
  • FIG. 2 is a schematic diagram of an array substrate in accordance with an embodiment of the present disclosure
  • FIG. 3 is a schematic diagram of an array substrate in accordance with an embodiment of the present disclosure.
  • FIG. 4 is a flow chart showing a method of fabricating an array substrate according to an embodiment of the present disclosure
  • FIG. 5 is a schematic flow chart of a method of fabricating an array substrate according to an embodiment of the present disclosure
  • 6(A)-6(F) are process flow diagrams of a method of fabricating an array substrate in accordance with an embodiment of the present disclosure.
  • the terms “upper”, “lower”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom” and Its derivatives should involve the public Open the text.
  • the terms “overlay”, “on top of”, “positioned on” or “positioned on top of” mean that a first element, such as a first structure, exists in a second element, such as a second structure. Above, wherein an intermediate element such as an interface structure may exist between the first element and the second element.
  • the term “contacting” means connecting a first element such as a first structure and a second element such as a second structure, with or without other elements at the interface of the two elements.
  • An embodiment of the present disclosure provides an array substrate comprising: an active layer disposed on a substrate, the active layer including a channel region, source/drain regions disposed on both sides of the channel region, and a trench disposed a lightly doped drain region between the track region and the source/drain region; a gate electrode and a first electrode disposed on the active layer; and a first insulating layer disposed on the gate electrode and the first electrode a barrier portion and a second electrode disposed on the first insulating layer, wherein a projection of the second electrode on the substrate at least partially overlaps with a projection of the first electrode on the substrate, the barrier portion being on the substrate a projection overlying the projection of the lightly doped drain region on the substrate, a projection of the barrier on the substrate and a projection of the source/drain region on the substrate Overlap, and wherein the barrier portion and the second electrode layer are disposed in the same layer.
  • the same layer arrangement means that it is formed of the same film layer.
  • FIG. 1(a) is a schematic diagram of an array substrate in accordance with an embodiment of the present disclosure.
  • an array substrate according to an embodiment of the present disclosure includes an active layer 11 disposed on a substrate 10, the active layer 11 including a channel region 11C, and two disposed in the channel region 11C.
  • the projection at least partially overlaps the projection of the first electrode 122 on the substrate 10, the projection of the barrier portion 141 on the substrate 10 covers the projection of the lightly doped drain region 11L on the substrate 10, and the blocking portion 141 is on the substrate 10.
  • the projection on the substrate and the projection of the source/drain region 11SD on the substrate 10 do not overlap (in other words, the edge of the barrier portion 141 away from the gate electrode 121 and the gate electrode of the lightly doped drain region 11L
  • the edge of 121 is relatively aligned, and wherein the blocking portion 141 and the second electrode 142 are disposed in the same layer and are of the same material.
  • the edge of the blocking portion away from the gate electrode and the lightly doped drain region are remote from the gate.
  • the extreme edge of the pole means that the outer boundary of the projection of the barrier on the substrate substantially overlaps the outer boundary of the projection of the lightly doped drain region on the substrate.
  • the first electrode and the second electrode form a capacitance to maintain a stable voltage.
  • the capacitance including the first electrode and the second electrode can maintain the stability of the voltage of the driving transistor in one cycle, the current of the OLED in one cycle is also stabilized, thereby ensuring Luminous uniformity and stability of OLEDs.
  • a lightly doped drain region 11L is provided on both sides of the channel region as an example.
  • the position of the lightly doped drain region can be set according to actual needs.
  • the lightly doped drain region may be located only on one side of the channel region.
  • 1(b) shows a case where a region away from the first electrode in the source/drain region is used as a drain, in which case a lightly doped drain may be provided only on a side of the channel region away from the first electrode. Polar zone.
  • the lightly doped drain region only on the side of the channel region close to the first electrode.
  • the leakage current of the thin film transistor can be reduced by providing a lightly doped drain region. Due to the same layer arrangement of the second electrode and the barrier, the two can be formed by a single patterning process. Thus, when the second electrode and the barrier portion are formed, only one mask is used, so that the manufacturing process of the array substrate can be simplified, the yield of production is improved, and the cost is also saved.
  • the blocking portion may have an opening P.
  • the projection of the opening P on the substrate 10 at least partially overlaps the projection of the gate electrode 121 on the substrate 10.
  • the width of the lightly doped drain region (also corresponding to the projection of the edge of the barrier portion 141 away from the gate electrode 121 on the substrate 10 to the projection of the channel region 11C on the substrate 10)
  • the range of d is about 0.5 um to 1 um.
  • the array substrate according to an embodiment of the present disclosure further includes: a second insulating layer 15 disposed between the active layer 11 and the gate electrode 121; passing through the first insulating layer 13 and the second insulating layer Via hole V of layer 15; The source/drain electrodes 16 are disposed on the first insulating layer 13, and the source/drain electrodes 16 are in contact with the source/drain regions 11SD through the vias V.
  • the conductivity type of the channel region may be N-type
  • the doping type of the lightly doped drain region and the conductivity type of the doped region of the source/drain region may be P-type. It can be understood that the doping concentration of the source/drain regions is greater than the doping concentration of the lightly doped drain regions. In one embodiment, the doping concentration of the source/drain regions may range from about 4.5 ⁇ 10 15 to 6 ⁇ 10 15 ions/cm 3 , and the doping concentration range of the lightly doped drain (LDD) region may be about 5 ⁇ 10 12 to 4.5 ⁇ 10 15 ions / cm 3 .
  • Another aspect of the present disclosure provides a method of fabricating an array substrate.
  • a method of fabricating an array substrate according to an embodiment of the present disclosure includes:
  • S111 using a blocking portion as a mask, performing first doping on the active layer to form source/drain regions on both sides of the channel region of the active layer and disposed in the channel region and the source/drain regions Lightly doped drain region.
  • the barrier may have an opening.
  • the projection of the opening on the substrate at least partially overlaps the projection of the gate electrode on the substrate.
  • the lightly doped drain region (corresponding to the distance d from the projection of the barrier away from the gate electrode on the substrate onto the projection of the channel region on the substrate) is in the range of about 0.5 Um ⁇ 1um.
  • the doping energy of the first doping may be about 30 KeV to 40 KeV.
  • the conductivity type of the channel region may be N-type, and the doping type of the lightly doped drain region and the conductivity type of the doped region of the source/drain region may be P-type.
  • the doping concentration of the source/drain regions may range from about 4.5 ⁇ 10 15 to 6 ⁇ 10 15 ions/cm 3
  • the doping concentration of the lightly doped drain (LDD) region may range from about 5 ⁇ 10 12 to 4.5. ⁇ 10 15 ions/cm 3 .
  • the material of the second conductive layer may include at least one of the following materials: molybdenum (Mo), molybdenum-niobium alloy (MoNb), aluminum (Al), aluminum-niobium alloy (AlNd), titanium (Ti), and copper (Cu), and combination.
  • Mo molybdenum
  • MoNb molybdenum-niobium alloy
  • Al aluminum
  • AlNd aluminum-niobium alloy
  • Ti titanium
  • Cu copper
  • FIG. 5 is a flow diagram of a method of fabricating an array substrate in accordance with an embodiment of the present disclosure. As shown in FIG. 5, in an embodiment, the method of manufacturing the array substrate further includes:
  • forming the gate electrode and the first electrode includes: forming a gate electrode material layer on the second insulating layer; patterning the gate electrode material layer to form the gate electrode and the first electrode.
  • 6(A)-6(F) are process flow diagrams of a method of fabricating an array substrate in accordance with an embodiment of the present disclosure. A method of fabricating an array substrate according to an embodiment of the present disclosure will be further described below with reference to FIG.
  • a method of fabricating an array substrate according to an embodiment of the present disclosure includes:
  • the substrate may include a glass substrate, and may also include any material suitable for use as a substrate, such as a high molecular polymer, a metal foil, or the like.
  • the active layer may include a silicon material. Since the electron mobility of the low temperature polysilicon material is superior to the electron mobility of the amorphous silicon material, the active layer may be disposed to include a polysilicon material.
  • an amorphous silicon layer may be formed on the substrate, and then the amorphous silicon is subjected to an excimer laser annealing (ELA) process to cause the amorphous silicon to become polycrystalline silicon, and then the polycrystalline silicon is first.
  • ELA excimer laser annealing
  • the first conductivity type is N-type
  • a doping amount of 1 ⁇ 10 12 to 2 ⁇ 10 12 ions/cm 3 can be employed.
  • P-type silicon can be provided and then an N-well can be formed on the P-type silicon.
  • the upper surface of the N well is on the same surface as the upper surface of the P-type silicon.
  • the active layer having the first conductivity type can also be directly provided without the above doping step.
  • a second insulating layer 15 is formed on the active layer 11.
  • the material of the second insulating layer may include at least one of silicon oxide (SiOx), silicon nitride (SiNx), germanium oxide (HfOx), silicon oxynitride (SiON), AlOx and combination.
  • a gate electrode 121 and a first electrode 122 are formed on the second insulating layer 15.
  • a gate electrode material layer may be formed on the second insulating layer, and then the gate electrode material layer is patterned to form the gate electrode 121 and the first electrode 122.
  • the gate electrode material layer may include at least one of the following materials: molybdenum (Mo), molybdenum-niobium alloy (MoNb), aluminum (Al), aluminum-niobium alloy (AlNd), titanium (Ti), and copper (Cu), and combinations thereof . Doping of the second conductivity type is then performed using the gate electrode and the first electrode as a mask.
  • the second conductivity type is P-type.
  • a doping amount of 5 ⁇ 10 12 to 4.5 ⁇ 10 15 ions/cm 3 may be employed.
  • a first insulating layer 13 is further formed on the gate electrode 121 and the first electrode 122.
  • the material of the first insulating layer may include at least one of silicon oxide (SiOx), silicon nitride (SiNx), germanium oxide (HfOx), silicon oxynitride (SiON), AlOx and combination.
  • a barrier material layer 14 is further formed on the first insulating layer 13.
  • the barrier material layer may include at least one of the following materials: molybdenum (Mo), molybdenum-niobium alloy (MoNb), aluminum (Al), aluminum-niobium alloy (AlNd), titanium (Ti), and copper (Cu), and combinations thereof.
  • the barrier material layer 14 is processed by one patterning process to form the barrier portion 141 and the second electrode 142.
  • the specific step may be: forming a photoresist on the barrier material layer, exposing the photoresist with a mask including a pattern of the barrier portion and the second electrode, then performing development, and then using light
  • the resist acts as a protective layer to etch the resistor Block the material layer and finally remove the photoresist.
  • the projection of the second electrode on the substrate at least partially overlaps the projection of the first electrode on the substrate, and the portion of the barrier extending outward from the side of the gate electrode is lining
  • the projection on the bottom is located within the projection of the portion of the active layer that extends outwardly from the side of the gate electrode (in other words, the projection of the edge of the barrier away from the gate electrode on the substrate)
  • the blocking portion may have an opening P.
  • the projection of the opening P on the substrate 10 at least partially overlaps the projection of the gate electrode 121 on the substrate 10.
  • the extent of the distance of the edge of the barrier away from the gate electrode on the substrate projected onto the projection of the channel region on the substrate may be about 0.5 um ⁇ 1um.
  • the active layer 11 is first doped using the blocking portion as a mask 141 to form source/drain regions on both sides of the channel region 11C of the active layer 11.
  • 11SD and a lightly doped drain region 11L disposed between the channel region 11C and the source/drain region 11SD.
  • the conductivity type of the active layer is N-type
  • P-type doping may be employed, so that the conductivity type of the conductive region of the lightly doped drain region and the doped region of the source/drain region formed after the current doping is P type.
  • the doping energy of the doping may be about 30 KeV to 40 KeV.
  • the doping concentration of the source/drain regions is greater than the doping concentration of the lightly doped drain regions.
  • the formed source/drain regions may have a doping concentration ranging from about 4.5 ⁇ 10 15 to 6 ⁇ 10 15 ions/cm 3
  • the lightly doped drain regions may have a doping concentration range of about 5 ⁇ 10 12 to 4.5 ⁇ 10 15 ions / cm 3 .
  • via holes V are formed through the first insulating layer 13 and the second insulating layer 15, and source/drain electrodes 16 are formed on the first insulating layer 13. It can be seen that the source/drain electrodes 16 are in contact with the source/drain regions 11SD via vias V.
  • Embodiments of the present disclosure also provide a display panel and a display device.
  • the display panel in the embodiment of the present disclosure includes the array substrate as described above.
  • Appearance in an embodiment of the present disclosure The display device can be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a notebook computer, a digital photo frame, a navigator, and the like.

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  • Crystallography & Structural Chemistry (AREA)
  • Thin Film Transistor (AREA)
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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Electroluminescent Light Sources (AREA)
PCT/CN2017/115424 2017-06-08 2017-12-11 阵列基板及其制造方法、显示面板以及显示装置 WO2018223642A1 (zh)

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US16/065,224 US20210193694A9 (en) 2017-06-08 2017-12-11 Array substrate and display panel comprising barrier as doping mask overlapping gate electrode
EP17899227.7A EP3640985A4 (en) 2017-06-08 2017-12-11 NETWORK SUBSTRATE AND ITS MANUFACTURING PROCESS, DISPLAY PANEL, AND DISPLAY DEVICE
JP2018548446A JP7403225B2 (ja) 2017-06-08 2017-12-11 アレイ基板及びその製造方法、表示パネルと表示装置

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CN104916584A (zh) * 2015-04-30 2015-09-16 京东方科技集团股份有限公司 一种制作方法、阵列基板及显示装置

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KR102081283B1 (ko) * 2013-02-14 2020-04-16 삼성디스플레이 주식회사 박막 반도체 장치, 유기 발광 표시 장치, 및 이의 제조 방법

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CN104681628A (zh) * 2015-03-17 2015-06-03 京东方科技集团股份有限公司 多晶硅薄膜晶体管和阵列基板及制造方法与一种显示装置
CN104916584A (zh) * 2015-04-30 2015-09-16 京东方科技集团股份有限公司 一种制作方法、阵列基板及显示装置

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US20190355759A1 (en) 2019-11-21
EP3640985A1 (en) 2020-04-22
JP2020522875A (ja) 2020-07-30
US20210193694A9 (en) 2021-06-24
EP3640985A4 (en) 2021-04-21

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