WO2018214946A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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Publication number
WO2018214946A1
WO2018214946A1 PCT/CN2018/088257 CN2018088257W WO2018214946A1 WO 2018214946 A1 WO2018214946 A1 WO 2018214946A1 CN 2018088257 W CN2018088257 W CN 2018088257W WO 2018214946 A1 WO2018214946 A1 WO 2018214946A1
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Prior art keywords
signal lead
display panel
heavily doped
semiconductor material
line
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PCT/CN2018/088257
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English (en)
French (fr)
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樊浩原
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BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
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Priority to US16/317,840 priority Critical patent/US10818699B2/en
Publication of WO2018214946A1 publication Critical patent/WO2018214946A1/zh
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13458—Terminal pads
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a display panel and a display device.
  • the exposed signal lead wires may be easily corroded, and the corrosion may extend along the signal lead wires to the inside of the display panel, causing the display panel to display abnormally.
  • An embodiment of the present disclosure provides a display panel, including:
  • a signal lead-out line on the substrate at least one end of the signal lead-out line is exposed, a material of the signal lead-out line includes a metal, and the signal lead-out line has a disconnected region;
  • the conductive portion of the semiconductor material is heavily doped, and the conductive portion of the heavily doped semiconductor material is connected to the signal lead line located in the disconnected region.
  • the material of the conductive portion of the heavily doped semiconductor material is heavily doped polysilicon.
  • the conductive portion of the heavily doped semiconductor material is located on a side of the film layer where the signal lead line is located away from the substrate.
  • the conductive portion of the heavily doped semiconductor material is located between the film layer where the signal lead line is located and the substrate.
  • the conductive portion of the heavily doped semiconductor material and the signal lead-out line belong to the same film layer.
  • the method further includes: a first insulating layer between the conductive portion of the heavily doped semiconductor material and the signal lead-out line;
  • the signal lead lines located in the disconnected region are respectively connected to the heavily doped semiconductor material conductive portion through a first via hole penetrating the first insulating layer.
  • the method further includes: a buffer layer between the substrate and the conductive portion of the heavily doped semiconductor material.
  • the exposed end of the signal lead line is located at a side of the substrate.
  • the exposed end of the signal lead line is located at an outermost film layer of the substrate.
  • the method further includes: a second insulation located on a side of the signal lead-out line and the conductive portion of the heavily doped semiconductor material away from the substrate a layer, and a binding terminal located on a side of the second insulating layer away from the substrate;
  • the binding terminal is connected to the signal lead line outside the disconnection region through a second via hole penetrating the second insulation layer; and the second via hole is away from the disconnection region The exposed end of the signal lead.
  • the method further includes: a second insulation located on a side of the signal lead-out line and the conductive portion of the heavily doped semiconductor material away from the substrate a layer, and a binding terminal located at a side of the second insulating layer away from the substrate;
  • the bonding terminal is connected to the heavily doped semiconductor material conductive portion through a second via hole penetrating the second insulating layer.
  • the unexposed portion of the signal lead line is connected to the signal line.
  • the conductive portion of the heavily doped semiconductor material is connected to the signal line.
  • an embodiment of the present disclosure further provides a display device, which includes the above display panel provided by the embodiment of the present disclosure.
  • FIG. 1 is a schematic structural view of a display panel before corrosion in the related art
  • FIG. 2 is a schematic structural view of a display panel after corrosion in the related art
  • FIG. 3 is a schematic structural view of a display panel before corrosion in the related art
  • FIG. 4 is a schematic structural diagram of a display panel according to some embodiments of the present disclosure.
  • FIG. 5 is a schematic structural diagram of a display panel according to some embodiments of the present disclosure.
  • FIG. 6 is a schematic structural diagram of a display panel according to some embodiments of the present disclosure.
  • FIG. 7 is a schematic structural diagram of a display panel according to some embodiments of the present disclosure.
  • FIG. 8 is a schematic structural diagram of a display panel according to some embodiments of the present disclosure.
  • FIG. 9 is a schematic structural diagram of a display panel according to some embodiments of the present disclosure.
  • the test circuit In the production process of the display panel, the test circuit is usually connected with the display panel circuit to detect the display panel. After the display panel test is finished, the test circuit needs to be cut off, and the signal lead-out line connected to the test line remains. The end of the part will be exposed at the section, and the exposed signal lead is susceptible to corrosion, and the corrosion will extend inward along the signal lead-out line until the bound area or even the display area, causing the transmission of the display panel to be interrupted. , causing the display panel to display an abnormality.
  • the display panel includes: a substrate 01, a signal lead line 02 on the substrate 01, and one end of the signal lead line 02 is exposed (shown by a broken line in FIG.
  • the signal The lead wire 02 is provided with an insulating layer 03, and the insulating layer 03 is provided with a binding terminal 04.
  • the bonding terminal 04 is connected to the signal lead-out line 02 through a via 05 penetrating the insulating layer 03; after the signal lead-out line 02 is corroded, Its structure is shown in Figure 2.
  • the display panel includes: a substrate 01, a signal lead-out line 02 on the substrate 01, one end of the signal lead-out line 02 is exposed (as indicated by a broken line in FIG. 3), and the signal lead-out line 02 is provided with insulation.
  • the layer 03, the signal lead line 02 is connected to a signal line 06, and the signal lead line 02 is disposed in the same layer as the signal line 06.
  • an embodiment of the present disclosure provides a display panel and a display device for preventing display failure of the display panel due to corrosion of the exposed end of the signal lead-out line.
  • a display panel includes: a substrate 1; a signal lead line 2 located on the substrate 1 , at least one end of the signal lead line 2 being exposed (shown by a broken line in the figure)
  • the material of the signal lead line 2 includes a metal, the signal lead line 2 has a broken region A, the heavily doped semiconductor material conductive portion 3, and the heavily doped semiconductor material conductive portion 3 is connected to the signal lead line 2 located at the disconnected region A.
  • the material of the signal lead line 2 contains a metal, specifically, a laminated structure of an alloy or a multilayer metal, etc.
  • the bare metal is susceptible to corrosion in an environment containing air and moisture, and the semiconductor material is not easily corroded. That is, it has a very good insulating effect on corrosion, and the heavily doped semiconductor material has good electrical conductivity. Therefore, the embodiment of the present disclosure provides the disconnection region A in the signal lead line 2, and connects the signal lead-out line 2 located in the disconnected region A by the heavily doped semiconductor material conductive portion 3, so that the signal lead-out line 2 can be ensured in the disconnected region A. In the case of conduction, corrosion is effectively prevented from extending to other portions of the signal lead-out line 2, thereby preventing display failure of the display panel due to corrosion of the exposed end of the signal lead-out line 2.
  • the material of the heavily doped semiconductor material conductive portion 3 is generally heavily doped polysilicon, and of course other semiconductor materials, such as amorphous silicon, etc., Not limited.
  • heavily doped polysilicon means that the polysilicon is heavily doped with, for example, phosphorus ions or boron ions.
  • the formation of heavily doped polysilicon specifically may include:
  • the amorphous silicon film layer is crystallized by an excimer laser annealing process to convert the amorphous silicon film layer into a polysilicon film layer;
  • the polysilicon film layer is heavily doped by ion implantation to form a heavily doped polysilicon film layer;
  • the heavily doped polysilicon film layer is formed into a heavily doped polysilicon by a patterning process.
  • the heavily doped semiconductor material conductive portion 3 may be located on a side of the film layer where the signal lead line 2 is located away from the substrate 1 .
  • the signal lead-out line 2 is formed on the substrate 1 before the conductive portion 3 of the heavily doped semiconductor material is fabricated, and the impurity in the substrate 1 can be insulated from contaminating the heavily doped semiconductor material conductive portion 3 to ensure the heavily doped semiconductor material.
  • the conductive portion 3 has good electrical conductivity.
  • the heavily doped semiconductor material conductive portion 3 may be located between the film layer where the signal lead line 2 is located and the substrate 1 .
  • the heavily doped semiconductor material conductive portion 3 may belong to the same film layer as the signal lead line 2 .
  • the heavily doped semiconductor material conductive portion 3 may be disposed at a position of the disconnection region A of the signal lead-out line 2, and connected to a portion at both ends of the disconnected portion of the signal lead-out line 2.
  • the method may further include: a first insulating layer 7 between the conductive portion 3 of the heavily doped semiconductor material and the signal lead-out line 2;
  • the signal lead wires 2 located in the disconnection region A are respectively connected to the heavily doped semiconductor material conductive portion 3 through the first via holes 8 penetrating the first insulating layer 7.
  • the first insulating layer 7 is disposed between the heavily doped semiconductor material conductive portion 3 and the signal lead-out line 2, and on the one hand, the heavily doped semiconductor material conductive portion 3 and the signal lead-out line 2 are not affected by each other during fabrication.
  • the signal lead line 2 can be simultaneously fabricated with the gate metal or the data line metal of the display area.
  • the heavily doped semiconductor material conductive portion 3 can be fabricated simultaneously with the active layer of the display region, thereby simplifying the fabrication process.
  • no signal extraction is provided between the heavily doped semiconductor material conductive portion 3 and the substrate 1.
  • the film layer 2 is equal to the film layer, that is, the heavily doped semiconductor material conductive portion 3 and the signal lead line 2 belong to the same film layer, or the heavily doped semiconductor material conductive portion 3 is located between the film layer where the signal lead line 2 is located and the substrate 1 It may further include: a buffer layer 9 between the substrate 1 and the heavily doped semiconductor material conductive portion 3.
  • the buffer layer 9 can insulate the impurities in the substrate 1 from contaminating the heavily doped semiconductor material conductive portion 3, ensuring that the heavily doped semiconductor material conductive portion 3 has good electrical conductivity.
  • the exposed end of the signal lead line 2 may be located at the side of the substrate 1 .
  • the test line needs to be cut off.
  • the end of the residual portion of the signal lead line 2 connected to the test line is exposed at the cross section, that is, the exposed end of the signal lead line 2 is located.
  • the exposed end of the signal lead line 2 may be located at the outermost film layer of the substrate 1 .
  • the method may further include: a signal located on the side of the signal lead-out line 2 and the heavily doped semiconductor material conductive portion 3 away from the substrate 1 a second insulating layer 4, and a binding terminal 5 on the side of the second insulating layer 4 away from the substrate 1;
  • the binding terminal 5 may be connected to the signal lead line 2 outside the disconnection area A through the second via hole 6 penetrating the second insulating layer 4; and the second via hole 6 is exposed away from the signal lead line 3 with respect to the disconnection area A One end.
  • the second insulating layer 4 may be subjected to a planarization process.
  • the binding terminal 5 can be used, for example, to connect a flexible printed circuit (FPC) or an IC, which is not limited herein.
  • the display panel may further include: a second insulating layer 4 located on a side of the signal lead-out line 2 and the heavily doped semiconductor material conductive portion 3 away from the substrate 1 , and located at The second insulating layer 4 is away from the binding terminal 5 on the side of the substrate 1;
  • the bonding terminal 5 can be connected to the heavily doped semiconductor material conductive portion 3 through the second via 6 penetrating the second insulating layer 4, such that the bonding terminal 5 is guided by the heavily doped semiconductor material conductive portion 3 and the signal lead line 2 Pass to transmit an electrical signal to the signal lead line 2.
  • the unexposed portion of the signal lead line 2 may be connected to the signal line 10 to pass the signal lead line 2 to the signal line 10 .
  • the signal line 10 can be disposed in the same layer as the signal lead line 2, and the signal line 10 can also be disposed in a different layer from the signal lead line 2.
  • an insulating layer and a signal lead line are disposed between the signal line 10 and the signal lead line 2. 2 is connected to the signal line 10 through a via hole penetrating the insulating layer, which is not limited herein.
  • the signal line 10 may be a gate line or a data line or the like.
  • the heavily doped semiconductor material conductive portion 3 may also be connected to the signal line 10, such that the signal lead line 3 passes through the heavily doped semiconductor material conductive portion 3 and The signal line 10 is turned on to transmit an electrical signal to the signal line 10.
  • an embodiment of the present disclosure further provides a display device, which is provided by any embodiment of the present disclosure, and the display device may be: a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, Any product or part that has a display function, such as a navigator.
  • the display panel includes: a substrate, a signal lead line disposed on the substrate, at least one end of the signal lead line is exposed, the material of the signal lead line includes metal, and the signal lead line has a break An open region; a conductive portion of the heavily doped semiconductor material that is connected to the signal lead of the disconnected region. Since the conductive portion of the heavily doped semiconductor material has very good electrical conductivity, it can ensure the conduction of both ends of the disconnected region of the signal lead line, and at the same time, since the conductive portion of the heavily doped semiconductor material is a semiconductor material, the corrosion is very good.
  • the isolation effect can effectively prevent the corrosion from extending to the inside of the signal lead-out line, so the corrosion will not cause the transmission of the display panel working signal to be interrupted, thereby preventing the display panel from being poorly displayed due to corrosion of the exposed end of the signal lead-out line.

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Abstract

一种显示面板及显示装置，该显示面板包括：基板（1）；设置于基板上的信号引出线（2），信号引出线的至少一端裸露，信号引出线的材料包括金属，且信号引出线具有断开区域（A）；连接位于断开区域的信号引出线的重掺杂半导体材料导电部（3）。防止了因信号引出线的裸露端被腐蚀而造成的显示面板显示不良。

Description

显示面板及显示装置
相关申请的交叉引用
本公开要求在2017年05月26日提交中国专利局、申请号为201710385962.7、发明名称为“一种显示面板及显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及显示技术领域，特别是涉及一种显示面板及显示装置。
背景技术
在显示面板中会存在一些信号引出线的一端裸露，即无任何遮挡保护，裸露的信号引出线容易受到腐蚀，而且腐蚀会沿着信号引出线向显示面板内部延伸，导致显示面板的显示异常。
发明内容
本公开实施例提供了一种显示面板，包括：
基板；
位于所述基板上的信号引出线，所述信号引出线的至少一端裸露，所述信号引出线的材料包括金属，所述信号引出线具有断开区域；
重掺杂半导体材料导电部，所述重掺杂半导体材料导电部连接位于所述断开区域的所述信号引出线。
在一种可能的实现方式中，在本发明实施例提供的上述显示面板中，所述重掺杂半导体材料导电部的材料为重掺杂的多晶硅。
在一种可能的实现方式中，在本发明实施例提供的上述显示面板中，所述重掺杂半导体材料导电部位于所述信号引出线所在膜层远离所述基板的一侧。
在一种可能的实现方式中，在本发明实施例提供的上述显示面板中，所述重掺杂半导体材料导电部位于所述信号引出线所在膜层与所述基板之间。
在一种可能的实现方式中，在本发明实施例提供的上述显示面板中，所述重掺杂半导体材料导电部与所述信号引出线属于同一膜层。
在一种可能的实现方式中，在本发明实施例提供的上述显示面板中，还包括：位于所述重掺杂半导体材料导电部与所述信号引出线之间的第一绝缘层；
位于所述断开区域的所述信号引出线分别通过贯穿所述第一绝缘层的第一过孔与所述重掺杂半导体材料导电部连接。
在一种可能的实现方式中，在本发明实施例提供的上述显示面板中，还包括：位于所述基板与所述重掺杂半导体材料导电部之间的缓冲层。
在一种可能的实现方式中，在本发明实施例提供的上述显示面板中，所述信号引出线裸露的一端位于所述基板的侧边。
在一种可能的实现方式中，在本发明实施例提供的上述显示面板中，所述信号引出线裸露的一端位于所述基板的最外膜层。
在一种可能的实现方式中，在本发明实施例提供的上述显示面板中，还包括：位于所述信号引出线和所述重掺杂半导体材料导电部远离所述基板一侧的第二绝缘层，以及位于所述第二绝缘层远离所述基板一侧的绑定端子；
所述绑定端子通过贯穿所述第二绝缘层的第二过孔与在所述断开区域以外的所述信号引出线连接；且所述第二过孔相对于所述断开区域远离所述信号引出线裸露的一端。
在一种可能的实现方式中，在本发明实施例提供的上述显示面板中，还包括：位于所述信号引出线和所述重掺杂半导体材料导电部远离所述基板一侧的第二绝缘层，以及位于所述第二绝缘层远所述离基板一侧的绑定端子；
所述绑定端子通过贯穿所述第二绝缘层的第二过孔与所述重掺杂半导体材料导电部连接。
在一种可能的实现方式中，在本发明实施例提供的上述显示面板中，所 述信号引出线的未裸露部分与信号线连接。
在一种可能的实现方式中，在本发明实施例提供的上述显示面板中，所述重掺杂半导体材料导电部与信号线连接。
另一方面，本公开实施例还提供了一种显示装置，其中，包括本公开实施例提供的上述显示面板。
附图说明
图1为相关技术中腐蚀前的显示面板的结构示意图；
图2为相关技术中腐蚀后的显示面板的结构示意图；
图3为相关技术中腐蚀前的显示面板的结构示意图；
图4为本公开一些实施例提供的显示面板的结构示意图；
图5为本公开一些实施例提供的显示面板的结构示意图；
图6为本公开一些实施例提供的显示面板的结构示意图；
图7为本公开一些实施例提供的显示面板的结构示意图；
图8为本公开一些实施例提供的显示面板的结构示意图；
图9为本公开一些实施例提供的显示面板的结构示意图。
具体实施方式
在显示面板的生产过程中，通常会设置测试线路与显示面板电路连接以对显示面板进行检测，在显示面板测试结束后，需将测试线路切掉，这时连接测试线路的信号引出线的残留部分的末端就会在断面处裸露出来，而裸露的信号引出线容易受到腐蚀，而且腐蚀会沿着信号引出线向内延伸，直至绑定区域，甚至显示区域，造成显示面板工作信号的传输中断，从而导致显示面板显示异常。例如，如图1所示，切掉测试线路后，显示面板包括：基板01，位于基板01上的信号引出线02，信号引出线02的一端裸露(如图1中虚线框所示)，信号引出线02上设有绝缘层03，绝缘层03上设有绑定端子 04，绑定端子04通过贯穿绝缘层03的过孔05与信号引出线02连接；在信号引出线02受到腐蚀后，其结构示意图如图2所示。
此外，有些显示面板上设置有用于连接显示面板的信号线的信号引出线，该信号引出线末端也是裸露的，因此也容易受到腐蚀，造成显示面板工作信号的传输中断，从而导致显示面板显示异常。例如，如图3所示，显示面板包括：基板01，位于基板01上的信号引出线02，信号引出线02一端裸露(如图3中虚线框所示)，信号引出线02上设有绝缘层03，信号引出线02连接一根信号线06，信号引出线02与信号线06同层设置。
基于此，本公开实施例提供了一种显示面板及显示装置，用以防止因信号引出线的裸露端被腐蚀而造成显示面板的显示不良。
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
需要说明的是，本公开附图中各层的厚度和形状不反映真实比例，目的只是示意说明本公开内容。
参见图4至图9，本公开实施例提供的一种显示面板，包括：基板1；位于基板1上的信号引出线2，信号引出线2的至少一端裸露(如图中虚线框所示)，信号引出线2的材料包括金属，信号引出线2具有断开区域A；重掺杂半导体材料导电部3，重掺杂半导体材料导电部3连接位于断开区域A的信号引出线2。
具体地，由于信号引出线2的材料包含金属，具体可以是合金或多层金属的叠层结构等，金属裸露在包含空气和水汽等的环境中容易受到腐蚀，而半导体材料不容易受到腐蚀，即对腐蚀有非常好的隔绝效果，且重掺杂的半导体材料具有良好的导电性能。因此，本公开实施例在信号引出线2设置断开区域A，并通过重掺杂半导体材料导电部3连接位于断开区域A的信号引出线2，能保证信号引出线2在断开区域A导通的情况下，有效防止腐蚀向 信号引出线2的其他部分延伸，从而防止因信号引出线2的裸露端被腐蚀而造成显示面板的显示不良。
可选地，在本公开实施例提供的上述显示面板中，重掺杂半导体材料导电部3的材料一般为重掺杂的多晶硅，当然也可以是其他半导体材料，例如非晶硅等，在此不做限定。具体地，重掺杂的多晶硅是指在多晶硅中重掺杂有例如磷离子或硼离子。
在生产过程中，形成重掺杂的多晶硅，具体可以包括：
形成非晶硅膜层；
利用准分子激光退火工艺对非晶硅膜层进行晶化处理，使得非晶硅膜层转变成多晶硅膜层；
采用离子注入法对多晶硅膜层进行重掺杂，形成重掺杂的多晶硅膜层；
对重掺杂的多晶硅膜层通过构图工艺形成重掺杂的多晶硅。
具体地，在本公开实施例提供的上述显示面板中，重掺杂半导体材料导电部3与信号引出线2之间可以存在多种层级位置关系的可能性，下面举例介绍。
可选地，在本公开实施例提供的上述显示面板中，如图5和图8所示，重掺杂半导体材料导电部3可以位于信号引出线2所在膜层远离基板1的一侧。
具体地，在基板1上在先制作信号引出线2，之后再制作重掺杂半导体材料导电部3，可以隔绝基板1中的杂质污染重掺杂半导体材料导电部3，保证重掺杂半导体材料导电部3具有良好的导电性能。
可选地，在本公开实施例提供的上述显示面板中，如图4和图7所示，重掺杂半导体材料导电部3可以位于信号引出线2所在膜层与基板1之间。
可选地，在本公开实施例提供的上述显示面板中，如图6和图9所示，重掺杂半导体材料导电部3可以与信号引出线2属于同一膜层。
具体地，重掺杂半导体材料导电部3可以设置在信号引出线2的断开区域A位置处，且与信号引出线2的断开区域两端的部分连接。
可选地，在本公开实施例提供的上述显示面板中，如图4、图5、图7和图8所示，在重掺杂半导体材料导电部3与信号引出线2异层设置时，还可以包括：位于重掺杂半导体材料导电部3与信号引出线2之间的第一绝缘层7；
位于断开区域A的信号引出线2分别通过贯穿第一绝缘层7的第一过孔8与重掺杂半导体材料导电部3连接。
具体地，在重掺杂半导体材料导电部3与信号引出线2之间设置第一绝缘层7，一方面可以便于重掺杂半导体材料导电部3与信号引出线2在制作时互不影响，另一方面，也便于重掺杂半导体材料导电部3与信号引出线2和显示面板显示区的膜层图案同时制作，例如信号引出线2可以和显示区的栅极金属或数据线金属同时制作，重掺杂半导体材料导电部3可以与显示区的有源层同时制作，从而可以简化制作工艺。
可选地，在本公开实施例提供的上述显示面板中，如图4、图6、图7和图9所示，在重掺杂半导体材料导电部3与基板1之间没有设置诸如信号引出线2等膜层时，即重掺杂半导体材料导电部3与信号引出线2属于同一膜层，或，重掺杂半导体材料导电部3位于信号引出线2所在膜层与基板1之间时，还可以包括：位于基板1与重掺杂半导体材料导电部3之间的缓冲层9。
具体地，缓冲层9可以隔绝基板1中的杂质污染重掺杂半导体材料导电部3，保证重掺杂半导体材料导电部3具有良好的导电性能。
可选地，在本公开实施例提供的上述显示面板中，如图4至图6所示，信号引出线2裸露的一端可以位于基板1的侧边。通常情况下是在显示面板测试结束后，需将测试线路切掉，这时连接测试线路的信号引出线2的残留部分的末端就会在断面处裸露出来，即信号引出线2裸露的一端位于基板1的侧边。
可选地，在本公开实施例提供的上述显示面板中，如图7至图9所示，信号引出线2裸露的一端可以位于基板1的最外膜层。
可选地，在本公开实施例提供的上述显示面板中，如图4至图6所示，还可以包括：位于信号引出线2和重掺杂半导体材料导电部3远离基板1一 侧的第二绝缘层4，以及位于第二绝缘层4远离基板1一侧的绑定端子5；
绑定端子5可以通过贯穿第二绝缘层4的第二过孔6与在断开区域A以外的信号引出线2连接；且第二过孔6相对于断开区域A远离信号引出线3裸露的一端。
具体地，第二绝缘层4可以经过平坦化处理。并且，绑定端子5例如可以用于连接柔性电路板(Flexible Printed Circuit,FPC)或者IC，在此不做限定。
或者，可选地，在本公开实施例提供的上述显示面板中，还可以包括：位于信号引出线2和重掺杂半导体材料导电部3远离基板1一侧的第二绝缘层4，以及位于第二绝缘层4远离基板1一侧的绑定端子5；
绑定端子5可以通过贯穿第二绝缘层4的第二过孔6与重掺杂半导体材料导电部3连接，这样，绑定端子5通过重掺杂半导体材料导电部3与信号引出线2导通，以向信号引出线2传输电信号。
可选地，在本公开实施例提供的上述显示面板中，如图7至图9所示，信号引出线2的未裸露部分可以与信号线10连接，以通过信号引出线2向信号线10提供电信号。
具体地，信号线10可以与信号引出线2同层设置，信号线10也可以与信号引出线2不同层设置，例如，信号线10与信号引出线2之间设有绝缘层，信号引出线2通过贯穿绝缘层的过孔与信号线10连接，在此不做限定。具体地，信号线10可以为栅线或数据线等。
或者，可选地，在本公开实施例提供的上述显示面板中，重掺杂半导体材料导电部3也可以与信号线10连接，这样，信号引出线3通过重掺杂半导体材料导电部3与信号线10导通，以向信号线10传输电信号。
基于同一发明构思，本公开实施例还提供了一种显示装置，包括本公开任意实施例提供的显示面板，该显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
综上，本公开实施例提供的技术方案中，显示面板包括：基板，设置于基板上的信号引出线，信号引出线的至少一端裸露，信号引出线的材料包括金属，且信号引出线具有断开区域；连接位于断开区域的信号引出线的重掺杂半导体材料导电部。由于重掺杂半导体材料导电部具有非常好的导电性能，故能保证信号引出线的断开区域的两端导通，同时，由于重掺杂半导体材料导电部是半导体材料，对腐蚀有非常好的隔绝效果，故能有效防止腐蚀向信号引出线内部延伸，因此腐蚀就不会造成显示面板工作信号的传输中断，从而防止了因信号引出线裸露端被腐蚀而造成的显示面板显示不良。
显然，本领域的技术人员可以对本公开进行各种改动和变型而不脱离本公开的精神和范围。这样，倘若本公开的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (14)

  1. 一种显示面板，其中，包括：
    基板；
    位于所述基板上的所述信号引出线，所述信号引出线的至少一端裸露，所述信号引出线的材料包括金属，所述信号引出线具有断开区域；
    重掺杂半导体材料导电部，所述重掺杂半导体材料导电部连接位于所述断开区域的所述信号引出线。
  2. 根据权利要求1所述的显示面板，其中，所述重掺杂半导体材料导电部的材料为重掺杂的多晶硅。
  3. 根据权利要求1所述的显示面板，其中，所述重掺杂半导体材料导电部位于所述信号引出线所在膜层远离所述基板的一侧。
  4. 根据权利要求1所述的显示面板，其中，所述重掺杂半导体材料导电部位于上所述信号引出线所在膜层与所述基板之间。
  5. 根据权利要求1所述的显示面板，其中，所述重掺杂半导体材料导电部与所述信号引出线属于同一膜层。
  6. 根据权利要求3或4所述的显示面板，其中，还包括：位于所述重掺杂半导体材料导电部与所述信号引出线之间的第一绝缘层；
    位于所述断开区域的所述信号引出线分别通过贯穿所述第一绝缘层的第一过孔与所述重掺杂半导体材料导电部连接。
  7. 根据权利要求4或5所述的显示面板，其中，还包括：位于所述基板与所述重掺杂半导体材料导电部之间的缓冲层。
  8. 根据权利要求1～4任一项所述的显示面板，其中，所述信号引出线裸露的一端位于所述基板的侧边。
  9. 根据权利要求1～4任一项所述的显示面板，其中，所述信号引出线裸露的一端位于所述基板的最外膜层。
  10. 根据权利要求1～4任一项所述的显示面板，其中，还包括：位于所 述信号引出线和所述重掺杂半导体材料导电部远离所述基板一侧的第二绝缘层，以及位于所述第二绝缘层远离所述基板一侧的绑定端子；
    所述绑定端子通过贯穿所述第二绝缘层的第二过孔与在所述断开区域以外的所述信号引出线连接；且所述第二过孔相对于所述断开区域远离所述信号引出线裸露的一端。
  11. 根据权利要求1～4任一项所述的显示面板，其中，还包括：位于所述信号引出线和所述重掺杂半导体材料导电部远离所述基板一侧的第二绝缘层，以及位于所述第二绝缘层远离所述基板一侧的绑定端子；
    所述绑定端子通过贯穿所述第二绝缘层的第二过孔与所述重掺杂半导体材料导电部连接。
  12. 根据权利要求1～4任一项所述的显示面板，其中，所述信号引出线的未裸露部分与信号线连接。
  13. 根据权利要求1～4任一项所述的显示面板，其中，所述重掺杂半导体材料导电部与信号线连接。
  14. 一种显示装置，其中，包括如权利要求1～13任一项所述的显示面板。
PCT/CN2018/088257 2017-05-26 2018-05-24 显示面板及显示装置 Ceased WO2018214946A1 (zh)

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