WO2019214004A1 - 阵列基板、液晶显示器及电子设备 - Google Patents

阵列基板、液晶显示器及电子设备 Download PDF

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Publication number
WO2019214004A1
WO2019214004A1 PCT/CN2018/090443 CN2018090443W WO2019214004A1 WO 2019214004 A1 WO2019214004 A1 WO 2019214004A1 CN 2018090443 W CN2018090443 W CN 2018090443W WO 2019214004 A1 WO2019214004 A1 WO 2019214004A1
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end point
metal line
line
metal
array substrate
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PCT/CN2018/090443
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English (en)
French (fr)
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罗平
罗东
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深圳市华星光电技术有限公司
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Priority to US16/109,476 priority Critical patent/US10600820B2/en
Publication of WO2019214004A1 publication Critical patent/WO2019214004A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13452—Conductors connecting driver circuitry and terminals of panels

Definitions

  • the present application relates to the field of liquid crystal panels, and in particular, to an array substrate of double-layer metal traces in a fan-out area, and a liquid crystal display equipped with the array substrate, and an electronic device equipped with the liquid crystal display.
  • an array substrate of an important component of the liquid crystal display has become a main object of research.
  • the array substrate is provided with a fan-out area at the frame, and the timing controller transmits the scanning signal and the data signal to each pixel through the routing of the fan-out area to realize the display function of the liquid crystal display.
  • a part of the array substrate adopts a double-layer metal wire routing method to reduce the total area of the wire in the fan-out area. That is, two metal wires are stacked and connected to the same pixel unit.
  • the double-layer wiring may cause a short circuit between the metal line and the surface common electrode due to the manufacturing precision of the line width or poor cutting, and cause damage to the array substrate.
  • the present application proposes a circuit optimized array substrate, which can effectively prevent the short circuit from being formed by providing a double metal wire.
  • This application includes the following technical solutions:
  • An array substrate comprising a fan-out region, wherein the fan-out region is laminated with a first metal wire, a second metal wire and a common electrode wire insulated from each other, and the second metal wire is located at the first metal wire and the Between the common electrode lines, on any section perpendicular to the extending path of the first metal line, the first metal line includes a first end point and a second end point in a first direction, the second metal line The common electrode line does not exceed the first end point in the first direction, and the common electrode line does not exceed the second end point in the first direction.
  • the length dimension of the second metal line in the first direction is the same as the length dimension of the first metal line in the first direction.
  • the length dimension of the common electrode line in the first direction is the same as the length dimension of the first metal line in the first direction.
  • the first metal line is trapezoidal in a section perpendicular to the extending path of the first metal line, and the first end of the long side of the pair of trapezoidal parallel sides is the first end point and the a second end point, the two ends of the short side corresponding to the long side are respectively a third end point and a fourth end point, wherein the third end point is located on a side of the first end point, and the second metal line is in the The third endpoint is not exceeded in the first direction.
  • the second metal line is a fifth end point closest to the third end point in the first direction, and the fifth end point and the third end point are spaced apart in the first direction.
  • the common electrode line is a sixth end point closest to the fourth end point in the first direction, and the sixth end point and the fourth end point are spaced apart in the first direction.
  • a laminated insulating layer and a semiconductor layer are disposed between the first metal line and the second metal line, and the insulating layer is located between the first metal line and the semiconductor layer.
  • a protective layer is laminated between the second metal line and the common electrode line.
  • the present application also relates to a liquid crystal display and an electronic device including the above array substrate and equipped in the electronic device.
  • the data transmission function to the pixel unit is realized by the first metal line and the second metal line which are insulated and laminated, and the second metal is passed through
  • the common electrode line of the wire insulation stack balances an electric field formed between the first metal wire and the second metal wire to avoid a loading effect.
  • the first metal line is marked along the two ends of the first direction, that is, the first end point and the second end point, on an arbitrary cross section perpendicular to the extending path of the first metal line. And controlling the second metal line to not exceed the first end point in the first direction while controlling the common electrode line not to exceed the second end point in the first direction.
  • the arrangement can ensure that the second metal line and the common electrode line form a staggered stacked structure in the first direction, and if the cutting defect occurs in the process of the fan-out area, the second metal lines are staggeredly stacked. And the common electrode lines can avoid each other to ensure that the array substrate does not have a short circuit fault. Thereby, the yield of the array substrate is improved.
  • FIG. 1 is a schematic view of an array substrate according to the present application.
  • Figure 2 is a schematic cross-sectional view of the fan-out line of the present application.
  • FIG. 3 is a cross-sectional view showing another embodiment of the fan-out line of the present application.
  • the array substrate 100 includes a fan-out region 10.
  • the fan-out area 10 is located at an edge of the display area of the array substrate 100.
  • the fan-out area 10 is provided with a plurality of fan-out lines 11 for connecting the timing controller 20 and the pixel unit 30.
  • the timing controller 20 controls transmission of scan signals and data signals of the pixel unit 30.
  • the fan-out line 11 includes a first metal line 101, a second metal line 102, and a common electrode line 103 which are internally laminated and insulated from each other.
  • the first metal line 101 and the second metal line 102 are connected in parallel to realize a transmission function of the fan-out line 11.
  • FIG. 1 In the embodiment of FIG.
  • a laminated insulating layer 104 and a semiconductor layer 105 are disposed between the first metal line 101 and the second metal line 102, wherein the insulating layer 104 is located at the first metal line. Between 101 and the semiconductor layer 105. The second metal line 102 is located between the first metal line 101 and the common electrode line 103. An insulating protective layer 106 is disposed between the second metal line 102 and the common electrode line 103. It can be understood that the array substrate 100 is provided with the fan-out area 10 at the edge of the display area, and the timing controller 20 transmits the scan signal and the data signal to each of the pixel units 30 through the fan-out line 11. Realize the display function of the liquid crystal display.
  • first metal line 101 and the second metal line 102 may also be stacked
  • the first metal line 101 includes a first end point 01 and a second end point 02 in a first direction 001. That is, the length dimension of the first metal line 101 in the first direction 001 has two endpoints 01 and 02.
  • the second metal line 102 and the common electrode line 103 are alternately stacked on the first metal line 101, wherein the second metal line 102 faces the first metal line 101 in the first direction 001
  • the coverage of the first electrode line 103 does not exceed the first end point 01
  • the common electrode line 103 covers the first metal line 101 in the first direction 001 does not exceed the second end point 02.
  • the second metal line 102 is laminated on the insulating layer 104 and the semiconductor layer 105. Due to the thickness of the first metal line 101, the second metal line 102 and the insulating layer 104 and the semiconductor layer 105 will have at least one slope.
  • the second metal line 102 needs to be patterned by a photolithography process. Since the precision control of the lithography process is difficult, when the second metal line 102 is patterned, the second metal line 102 on the slope segment may be cut due to insufficient control precision of the patterning process. Deeper, the semiconductor layer 105 and even the insulating layer 104 are damaged. A similar cut in the industry is called "undercut".
  • a vertical gap is formed between the second metal line 102, the semiconductor layer 105, and the insulating layer 104.
  • the protective layer 106 is used to cover the second metal line 102 during the fabrication of the protective layer 106.
  • the protective layer 106 often cannot protect the second metal line 102.
  • the common electrode line 103 is fabricated, if the common electrode line 103 forms a cover for the second metal line 102 in the first direction 001, the common electrode line 103 enters the vertical direction. The position of the direction notch is caused to cause conduction with the second metal line 102. A failure of the short circuit may occur throughout the array substrate 100.
  • the second metal line 102 and the common electrode line 103 are alternately stacked, so that the second metal line 102 is at the first end point 01, Because the first end point 01 is not exceeded in the first direction 001, the second metal line 102 does not have a slope at a position exceeding the first end point 01, and thus does not approach the An undercut phenomenon occurs at the position of the first end point 01; on the other hand, at the position of the second end point 02, the second metal line 102 may also have an undercut defect, but since the common electrode line 103 is in the The second end point 02 is not exceeded in the first direction 001, so the common electrode line 103 is also not associated with the undercut occurring at the second end point 02, and the common electrode line is physically avoided.
  • the array substrate 100 of the present application obtains higher reliability due to the alternate stacking between the second metal line 102 and the common electrode line 103, and avoids short-circuit defects caused by undercut.
  • the length dimension of the second metal line 102 in the first direction 001 is the same as the dimension of the first metal line 101 in the first direction 001.
  • the first metal line 101 and the second metal line 102 are connected in parallel between the timing controller 20 and the pixel unit 30. Such an arrangement is to reduce the resistance of the fan-out line 11 by the parallel connection of two layers of metal. It can be understood that in order to minimize the size of the first metal line 101 and the second metal line 102, it is necessary to place the first metal line 101 and the second metal line 102 under the extreme conditions of the fabrication process.
  • the line width is controlled to the narrowest. That is, the length dimension of the first metal line 101 and the second metal line 102 in the first direction 001 is the smallest.
  • the minimum resistance value of the parallel circuit should appear in the resistance values of the first metal line 101 and the second metal line 102.
  • the first metal wire 101 and the second metal wire 102 have the same size in the first direction 001.
  • the common electrode line 103 also needs to be associated with the first metal line 101 and the The second metal wires 102 are disposed to have the same width. That is, the length dimension of the common electrode line 103 in the first direction 001 is also the same as the dimension of the first metal line 101 in the first direction 001.
  • the common electrode line 103 is formed in the same manner as the pixel electrode on the pixel unit 30 in the array substrate 100, the scanning line and the data line in the array substrate 100. Specifically, the common electrode line 103 is formed during development of a developer.
  • the width dimension of the common electrode line 103 is also the same as the width of the first metal line 101 and the second metal line 102.
  • the first metal wire 101 and the second metal wire 102 should be made rectangular in any section on an extending path perpendicular to the fan-out line 11, so that the fan-out line 11 can obtain the most Good conduction effect.
  • the first metal line 101 and the second metal line 102 tend to be trapezoidal in a section perpendicular to the extended path of the fan-out line 11 (see FIG. 3).
  • the trapezoid there are two opposite parallel sides. It can be understood that the two sides of the long side of the parallel side are the first end point 01 and the second end point 02, respectively.
  • the short side of the parallel side also has two endpoints, a third endpoint 03 and a fourth endpoint 04.
  • the third endpoint 03 is located on the side of the first endpoint 01, that is, the third endpoint 03 is closer to the first endpoint 01 than the fourth endpoint 04.
  • the fourth endpoint 04 is located on the side of the second endpoint 02.
  • the first metal line 101 and the second metal line 102 whose actual shape is trapezoidal, it is necessary to adjust the staggered stacking starting points of the second metal line 102 and the common electrode line 103 accordingly. That is, the second metal line 102 does not exceed the third end point 03 in the first direction 001, and the common electrode line 103 exceeds the fourth end point 04 in the upper portion of the first direction 001. This arrangement ensures that the second metal line 102 and the common electrode line 103 can be strictly staggered.
  • the second metal line 102 is the fifth end point 05 closest to the third end point 03 in the first direction 001. It can be understood that the fifth end point 05 is on the second metal line 102. In order to prevent the fifth endpoint 05 from overlapping with the third endpoint 03, an undercut may occur at the fifth endpoint 05, and the common electrode line 103 may be electrically connected to the fifth endpoint 05. The fifth endpoint 05 needs to be disposed at a distance a from the third endpoint 03 in the first direction 001.
  • the common electrode line 103 is the sixth end point 06 closest to the fourth end point 04 in the first direction 001.
  • the sixth end point 06 is also an end point on the common electrode line 103.
  • the sixth end point 06 and the fourth end point 04 are also spaced apart in the first direction 001 by a distance b. It can be understood that if the undercut occurs at the fourth endpoint 04 position, if the sixth endpoint 06 coincides with the fourth endpoint 04, the common electrode 103 and the second metal line 102 still exist. The hidden danger of the sixth endpoint 06 is turned on. The sixth endpoint 06 can avoid such extreme situations after being disposed at a distance from the fourth endpoint 04.
  • the present application also relates to a liquid crystal display including an array substrate 100 of the present application, and the electronic device including the liquid crystal display equipped with the array substrate 100. It can be understood that, because the liquid crystal display device is equipped with the array substrate 100, the short circuit problem of the fan-out line 11 caused by undercut in the fan-out area 10 is controlled, and thus the liquid crystal display and the equipment are equipped.
  • the electronic devices of the liquid crystal display have higher reliability and service life due to the array substrate 100.
  • the electronic device may be any device having communication and storage functions, such as a tablet computer, a mobile phone, an e-reader, a remote controller, a personal computer (PC), a notebook computer, an in-vehicle device. , network TV, wearable devices and other smart devices with network capabilities.

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  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
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Abstract

一种阵列基板、液晶显示器及电子装置，阵列基板的扇出区内依次层叠有相互绝缘的第一金属线、第二金属线和公共电极线，在第一金属线延伸路径的任意截面上，该第一金属线包含第一方向上的第一端点和第二端点，第二金属线在第一方向上不超过第一端点，公共电极线在第一方向上不超过第二端点。该第二金属线和公共电极线在第一方向上形成交错层叠的结构。

Description

阵列基板、液晶显示器及电子设备
本申请要求2018年5月8日提交中国专利局的，申请号为201810432405.0，发明名称为“阵列基板、液晶显示器及电子设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及液晶面板领域，尤其涉及一种扇出区双层金属走线的阵列基板，以及装备所述阵列基板的液晶显示器，和装备所述液晶显示器的电子设备。
背景技术
在当前液晶显示器行业普遍追求窄边框、大屏占比的环境下，液晶显示器的一个重要组成部分的阵列基板成为大家研究的主要对象。阵列基板在边框处设有扇出区，时序控制器通过扇出区的走线将扫描信号和数据信号传递给各个像素，实现液晶显示器的显示功能。
为减小扇出区的尺寸，部分阵列基板采取双层金属线走线的方式，来缩减走线在扇出区中的总面积。即两根金属线层叠设置，且均连接于同一像素单元。但双层走线会因为线宽的制造精度，或切割不良等原因，造成金属线与表层公共电极之间的短路，对阵列基板造成损害。
发明内容
本申请提出一种电路优化的阵列基板，能够有效防止因设置双层金属线而形成短路的问题。本申请包括如下技术方案：
一种阵列基板，包括扇出区，所述扇出区内层叠有相互绝缘的第一金属线、第二金属线和公共电极线，所述第二金属线位于所述第一金属线和所述公共电极线之间，在垂直于所述第一金属线延伸路径的任意截面上，所述第一金属线包含第一方向上的第一端点和第二端点，所述第二金属线在所述第一方向上不超过所述第一端点，所述公共电极线在所述第一方向上不超过所述第二端点。
其中，所述第二金属线在所述第一方向的长度尺寸与所述第一金属线在所述第一方向上的长度尺寸相同。
其中，所述公共电极线在所述第一方向的长度尺寸与所述第一金属线在所述第一方向上 的长度尺寸相同。
其中，在垂直于所述第一金属线延伸路径的截面上，所述第一金属线呈梯形，所述梯形一对平行边中的长边两端分别为所述第一端点和所述第二端点，与所述长边对应的短边两端分别为第三端点和第四端点，其中所述第三端点位于所述第一端点一侧，所述第二金属线在所述第一方向上不超过所述第三端点。
其中，所述第二金属线在所述第一方向上最靠近所述第三端点处为第五端点，所述第五端点与所述第三端点在所述第一方向上为间隔设置。
其中，所述公共电极线在所述第一方向上最靠近所述第四端点处为第六端点，所述第六端点与所述第四端点在所述第一方向上为间隔设置。
其中，所述第一金属线与所述第二金属线之间设有层叠的绝缘层和半导体层，所述绝缘层位于所述第一金属线和所述半导体层之间。
其中，所述第二金属线与所述公共电极线之间层叠有保护层。
本申请还涉及一种液晶显示器以及一种电子设备，所述液晶显示器包括上述的阵列基板，并装备于所述电子设备之中。
在本申请所述阵列基板的所述扇出区内，通过相互绝缘且层叠的所述第一金属线和所述第二金属线实现对像素单元的数据传输功能，通过与所述第二金属线绝缘层叠的所述公共电极线来平衡所述第一金属线和所述第二金属线之间形成的电场，避免出现负载效应(loading effect)。同时，在垂直于所述第一金属线延伸路径的任意截面上，将所述第一金属线沿所述第一方向的两端点，即所述第一端点和所述第二端点进行标记，控制所述第二金属线在所述第一方向上不超过所述第一端点，同时控制所述公共电极线在所述第一方向上不超过所述第二端点。这样设置可以保证所述第二金属线和公共电极线在所述第一方向上形成交错层叠的结构，在所述扇出区的制程中若出现切割不良，交错层叠的所述第二金属线和所述公共电极线可以相互避开，保证所述阵列基板不会因此出现短路故障。从而提高了所述阵列基板的良品率。
附图说明
图1是本申请所述阵列基板的示意图；
图2是本申请所述扇出线的剖面示意图；
图3是本申请所述扇出线另一实施例的剖面示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请的一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动的前提下所获得的所有其它实施例，都属于本申请保护的范围。
请参阅图1所示的阵列基板100。所述阵列基板100包括有扇出区10。所述扇出区10位于所述阵列基板100显示区的边缘处，所述扇出区10内设多条扇出线11，所述扇出线11用于连接时序控制器20和像素单元30，实现所述时序控制器20对所述像素单元30的扫描信号和数据信号的传输控制。具体的，对于单个所述扇出线11，见图2，所述扇出线11包括内层叠并相互绝缘的第一金属线101、第二金属线102和公共电极线103。所述第一金属线101和所述第二金属线102并联以实现所述扇出线11的传输功能。在图2的实施例中，所述第一金属线101与所述第二金属线102之间设有层叠的绝缘层104和半导体层105，其中所述绝缘层104位于所述第一金属线101和所述半导体层105之间。所述第二金属线102位于所述第一金属线101和所述公共电极线103之间。所述第二金属线102与所述公共电极线103之间设有绝缘的保护层106。可以理解的，所述阵列基板100在显示区边缘设置了所述扇出区10，所述时序控制器20通过所述扇出线11将扫描信号和数据信号传递给各个所述像素单元30，进而实现液晶显示器的显示功能。
可以理解的，在另一些实施例中，所述第一金属线101与所述第二金属线102之间，或所述第二金属线102与所述公共电极线103之间，还可以层叠有其他的层结构，或者对所述绝缘层104、所述半导体层105以及所述保护层106进行等效替换等。只要在所述扇出区10内所述第一金属线101和所述第二金属线102之间，或所述第二金属线102与所述公共电极线103之间为绝缘设置，均属于本申请所述阵列基板100所要求保护的技术范围。
图2为垂直于所述扇出线11的延伸路径的任意截面。在图2所示截面中，所述第一金属线101包含第一方向001上的第一端点01和第二端点02。即所述第一金属线101在所述第一方向001上的长度尺寸存在01和02两个端点。所述第二金属线102和所述公共电极线103交错层叠于所述第一金属线101上，其中所述第二金属线102在所述第一方向001上对所述第一金属线101的覆盖不超过所述第一端点01，所述公共电极线103在所述第一方向001上对所述第一金属线101的覆盖不超过所述第二端点02。
从图2可知，所述第二金属线102层叠于所述绝缘层104和所述半导体层105之上。由于所述第一金属线101存在厚度，所述第二金属线102和所述绝缘层104、所述半导体层105将至少存在一段坡度段。所述第二金属线102需要通过光刻制程来进行图形化的制作。由于光刻工艺的精度控制难度较大，在对所述第二金属线102进行图案化时，可能因为图案化制 程的控制精度不足，造成对坡度段上的所述第二金属线102的切割较深，伤及所述半导体层105甚至所述绝缘层104。行业内称类似的切割不良为“undercut”。在所述扇出线11出现undercut之后，会在所述第二金属线102、所述半导体层105和所述绝缘层104之间形成一个竖直方向的缺口。在所述保护层106的制作过程中，所述保护层106用于覆盖所述第二金属线102。但对于竖直方向的缺口，所述保护层106往往无法对所述第二金属线102进行保护。由此，当制作所述公共电极线103时，如果所述公共电极线103在所述第一方向001上对所述第二金属线102形成了覆盖，所述公共电极线103会进入竖直方向缺口的位置，从而与所述第二金属线102造成导通。整个所述阵列基板100会因此出现短路的故障。
采用本申请所述阵列基板100的设置后，由于所述第二金属线102与所述公共电极线103的交替层叠设置，使得所述第二金属线102在所述第一端点01处，因为在所述第一方向001上未超过所述第一端点01，使得所述第二金属线102不会在超过所述第一端点01的位置出现坡度，进而不会在靠近所述第一端点01的位置上发生undercut现象；另一方面，在所述第二端点02的位置，所述第二金属线102可能也会出现undercut缺陷，但由于所述公共电极线103在所述第一方向001上未超过所述第二端点02，因此所述公共电极线103也不会同发生在所述第二端点02处的undercut发生关联，从物理结构上避免了所述公共电极线103与所述第二金属线102之间的短路问题。由此，本申请所述阵列基板100因为所述第二金属线102与所述公共电极线103之间的交替层叠设置，而获得了更高的可靠性，避免undercut造成的短路缺陷。
一种实施例，所述第二金属线102在所述第一方向001上的长度尺寸与所述第一金属线101在所述第一方向001上的尺寸相同。所述第一金属线101和所述第二金属线102为并联方式连通于所述时序控制器20和所述像素单元30之间。这样的设置是为了通过两层金属的并联来减小所述扇出线11的电阻。可以理解的，为了最小化所述第一金属线101和所述第二金属线102的尺寸，需要在制作工艺的极限条件下将所述第一金属线101和所述第二金属线102的线宽控制到最窄。也即在所述第一方向001上所述第一金属线101和所述第二金属线102的长度尺寸均为最小。另一方面，当所述第一金属线101和所述第二金属线102并联时，其并联电路的最小电阻值应该出现在所述第一金属线101和所述第二金属线102阻值相同的情况下。也即所述第一金属线101与所述第二金属线102在所述第一方向001上的尺寸相同。
进一步的，为了最小化所述第一金属线101和所述第二金属线102之间的过载效应(loading effect)，所述公共电极线103也需要与所述第一金属线101和所述第二金属线102设置为宽度相同。即所述公共电极线103在所述第一方向001上的长度尺寸也与所述第一金属线101在所述第一方向001上的尺寸相同。另一方面，所述公共电极线103是与所述阵列 基板100内的所述像素单元30上的像素电极、所述阵列基板100内的扫描线以及数据线等同一道工序制成。具体的，所述公共电极线103是在显影液显影过程中制成。为了保证所述阵列基板100中显影液在显影过程中的浓度值平均，以获得宽度尺寸相同的扫描线和数据线等，需要在所述扇出区10中制作出同等宽度的所述扇出线11，以防止所述扇出区10内的显影液浓度过高而影响所述阵列基板100的制作精度。因此，在所述扇出区10内，所述公共电极线103的宽度尺寸也与所述第一金属线101和所述第二金属线102的宽度相同。
理论上，在垂直于所述扇出线11的延伸路径任意截面上，所述第一金属线101和所述第二金属线102都应被制造为矩形，以使得所述扇出线11能获得最佳的传导效果。但是由于工艺制程的限制，在垂直于所述扇出线11的延伸路径的截面上，所述第一金属线101和所述第二金属线102往往均呈现为梯形(见图3)。对于所述梯形，存在两相对的平行边。可以理解的，其中平行边的长边两端分别为所述第一端点01和所述第二端点02。而平行边中的短边也存在两个端点，分别为第三端点03和第四端点04。其中，所述第三端点03位于所述第一端点01一侧，也即所述第三端点03相对于所述第四端点04更靠近所述第一端点01。相应的，所述第四端点04位于所述第二端点02一侧。对于实际形状为梯形的所述第一金属线101和所述第二金属线102，需要将所述第二金属线102和所述公共电极线103的交错层叠设置起点进行相应的调整。即所述第二金属线102在所述第一方向001上不超过所述第三端点03，所述公共电极线103在所述第一方向001上部超过所述第四端点04。这样设置后才能保证所述第二金属线102和所述公共电极线103能够严格实现交错层叠。
进一步的，所述第二金属线102在所述第一方向001上最靠近所述第三端点03处为第五端点05。可以理解的，所述第五端点05在所述第二金属线102上。为了避免所述第五端点05与所述第三端点03重合时，在所述第五端点05处出现undercut仍可能存在所述公共电极线103与所述第五端点05导通的情况，所述第五端点05需要与所述第三端点03在所述第一方向001上设置为间隔一段距离a。
相应的，所述公共电极线103在所述第一方向001上最靠近所述第四端点04处为第六端点06。所述第六端点06也为所述公共电极线103上的一个端点。所述第六端点06与所述第四端点04在所述第一方向001上也为间隔设置，隔开一段距离b。可以理解的，在所述第四端点04位置如果出现undercut，所述第六端点06如果恰好与所述第四端点04重合，仍存在所述公共电极103与所述第二金属线102在所述第六端点06处导通的隐患。而所述第六端点06在与所述第四端点04间隔一段距离设置后，能够避免此类极端情况的发生。
本申请还涉及一种液晶显示器以及一种电子设备，其中所述液晶显示器包括本申请所述阵列基板100，所述电子设备包括有装备所述阵列基板100的所述液晶显示器。可以理解的， 所述液晶显示器因为装备了所述阵列基板100，其在所述扇出区10内因为undercut而造成的所述扇出线11短路问题得以控制，因而所述液晶显示器以及装备了所述液晶显示器的电子设备均因为所述阵列基板100而具备了更高的可靠性和使用寿命。
可以理解的，本申请实施方式涉及的电子设备可以是任何具备通信和存储功能的设备，例如：平板电脑、手机、电子阅读器、遥控器、个人计算机(PersonalComputer，PC)、笔记本电脑、车载设备、网络电视、可穿戴设备等具有网络功能的智能设备。
以上所述的实施方式，并不构成对该技术方案保护范围的限定。任何在上述实施方式的精神和原则之内所作的修改、等同替换和改进等，均应包含在该技术方案的保护范围之内。

Claims (20)

  1. 一种阵列基板，其中，包括扇出区，所述扇出区内层叠有相互绝缘的第一金属线、第二金属线和公共电极线，所述第二金属线位于所述第一金属线和所述公共电极线之间，在垂直于所述第一金属线延伸路径的任意截面上，所述第一金属线包含第一方向上的第一端点和第二端点，所述第二金属线在所述第一方向上不超过所述第一端点，所述公共电极线在所述第一方向上不超过所述第二端点。
  2. 如权利要求1所述的阵列基板，其中，所述第二金属线在所述第一方向的长度尺寸与所述第一金属线在所述第一方向上的长度尺寸相同。
  3. 如权利要求1所述的阵列基板，其中，所述第一金属线与所述第二金属线之间设有层叠的绝缘层和半导体层，所述绝缘层位于所述第一金属线和所述半导体层之间。
  4. 如权利要求2所述的阵列基板，其中，所述公共电极线在所述第一方向的长度尺寸与所述第一金属线在所述第一方向上的长度尺寸相同。
  5. 如权利要求2所述的阵列基板，其中，所述第一金属线与所述第二金属线之间设有层叠的绝缘层和半导体层，所述绝缘层位于所述第一金属线和所述半导体层之间。
  6. 如权利要求4所述的阵列基板，其中，所述第一金属线与所述第二金属线之间设有层叠的绝缘层和半导体层，所述绝缘层位于所述第一金属线和所述半导体层之间。
  7. 如权利要求1所述的阵列基板，其中，在垂直于所述第一金属线延伸路径的截面上，所述第一金属线呈梯形，所述梯形一对平行边中的长边两端分别为所述第一端点和所述第二端点，与所述长边对应的短边两端分别为第三端点和第四端点，其中所述第三端点位于所述第一端点一侧，所述第二金属线在所述第一方向上不超过所述第三端点。
  8. 如权利要求7所述的阵列基板，其中，所述第二金属线在所述第一方向上最靠近所述第三端点处为第五端点，所述第五端点与所述第三端点在所述第一方向上为间隔设置。
  9. 如权利要求7所述的阵列基板，其中，所述公共电极线在所述第一方向上最靠近所述第四端点处为第六端点，所述第六端点与所述第四端点在所述第一方向上为间隔设置。
  10. 如权利要求7所述的阵列基板，其中，所述第一金属线与所述第二金属线之间设有层叠的绝缘层和半导体层，所述绝缘层位于所述第一金属线和所述半导体层之间。
  11. 如权利要求3所述的阵列基板，其中，所述第二金属线与所述公共电极线之间层叠有保护层。
  12. 一种液晶显示器，其中，包括阵列基板，所述阵列基板包括扇出区，所述扇出区内层叠有相互绝缘的第一金属线、第二金属线和公共电极线，所述第二金属线位于所述第一金属 线和所述公共电极线之间，在垂直于所述第一金属线延伸路径的任意截面上，所述第一金属线包含第一方向上的第一端点和第二端点，所述第二金属线在所述第一方向上不超过所述第一端点，所述公共电极线在所述第一方向上不超过所述第二端点。
  13. 如权利要求12所述的液晶显示器，其中，所述第二金属线在所述第一方向的长度尺寸与所述第一金属线在所述第一方向上的长度尺寸相同。
  14. 如权利要求13所述的液晶显示器，其中，所述公共电极线在所述第一方向的长度尺寸与所述第一金属线在所述第一方向上的长度尺寸相同。
  15. 如权利要求12所述的液晶显示器，其中，在垂直于所述第一金属线延伸路径的截面上，所述第一金属线呈梯形，所述梯形一对平行边中的长边两端分别为所述第一端点和所述第二端点，与所述长边对应的短边两端分别为第三端点和第四端点，其中所述第三端点位于所述第一端点一侧，所述第二金属线在所述第一方向上不超过所述第三端点。
  16. 如权利要求15所述的液晶显示器，其中，所述第二金属线在所述第一方向上最靠近所述第三端点处为第五端点，所述第五端点与所述第三端点在所述第一方向上为间隔设置。
  17. 如权利要求15所述的液晶显示器，其中，所述公共电极线在所述第一方向上最靠近所述第四端点处为第六端点，所述第六端点与所述第四端点在所述第一方向上为间隔设置。
  18. 如权利要求1所述的液晶显示器，其中，所述第一金属线与所述第二金属线之间设有层叠的绝缘层和半导体层，所述绝缘层位于所述第一金属线和所述半导体层之间。
  19. 如权利要求18所述的液晶显示器，其中，所述第二金属线与所述公共电极线之间层叠有保护层。
  20. 一种电子设备，其中，包括权利要求12所述的液晶显示器。
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