WO2018214409A1 - 一种显示基板及其制备方法、显示装置 - Google Patents

一种显示基板及其制备方法、显示装置 Download PDF

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Publication number
WO2018214409A1
WO2018214409A1 PCT/CN2017/109739 CN2017109739W WO2018214409A1 WO 2018214409 A1 WO2018214409 A1 WO 2018214409A1 CN 2017109739 W CN2017109739 W CN 2017109739W WO 2018214409 A1 WO2018214409 A1 WO 2018214409A1
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Prior art keywords
pattern
conductive pattern
display
insulation
insulating
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Ceased
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PCT/CN2017/109739
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English (en)
French (fr)
Inventor
杨凡
郭坤
蒲杰
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BOE Technology Group Co Ltd
Ordos Yuansheng Optoelectronics Co Ltd
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BOE Technology Group Co Ltd
Ordos Yuansheng Optoelectronics Co Ltd
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Priority to US15/777,704 priority Critical patent/US10777635B2/en
Publication of WO2018214409A1 publication Critical patent/WO2018214409A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/60—Forming conductive regions or layers, e.g. electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/10—Deposition of organic active material
    • H10K71/16—Deposition of organic active material using physical vapour deposition [PVD], e.g. vacuum deposition or sputtering
    • H10K71/166—Deposition of organic active material using physical vapour deposition [PVD], e.g. vacuum deposition or sputtering using selective deposition, e.g. using a mask

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a display substrate, a method for fabricating the same, and a display device.
  • GOA Gate Driver on Array
  • COF Chip On Film
  • Embodiments of the present disclosure provide a display substrate and a method of fabricating the same, and a display device that can increase a contact area of a first conductive pattern and a second conductive pattern.
  • a first aspect provides a display substrate including a display area and a peripheral area surrounding the display area, the peripheral area including: a first conductive pattern, the first conductive pattern including at least two first hollow areas, The first hollow region is used as a registration mark pattern; an insulating layer disposed on the first conductive pattern, the insulating layer includes a first insulation pattern, and the first insulation pattern covers the first hollow region, And the first insulation The pattern does not completely cover a portion between adjacent first hollow regions; a second conductive pattern disposed on the insulating layer, the second conductive pattern being electrically connected to the first conductive pattern.
  • the shape of the first insulation pattern is in a zigzag shape.
  • the first insulation pattern includes a plurality of mutually independent sub-insulation patterns, each of the sub-insulation patterns covering one of the first hollow regions.
  • the projection of the boundary of the sub-insulation pattern on the first conductive pattern coincides with the boundary of the first hollow region.
  • the first conductive pattern surrounds the display area along an entire circumference of the display area.
  • the first conductive pattern further includes a second hollow region; the second hollow region and the first hollow region are located at different sides of the display region; the insulating layer further includes a second insulation pattern The second insulation pattern covers the second hollow region.
  • the display area includes: a pixel defining layer disposed on the base substrate, a first electrode and a light emitting layer disposed in the pixel defining layer opening, and a second electrode covering the display area;
  • the first conductive pattern is disposed in the same layer as the first electrode, and the second conductive pattern is disposed in the same layer as the second electrode.
  • the first insulation pattern is disposed in the same layer as the pixel defining layer.
  • the display area further includes a spacer disposed between the pixel defining layer and the second electrode and disposed on the pixel defining layer; the first insulating pattern and the spacer The same layer is set.
  • the second insulating pattern is disposed in the same layer as the pixel.
  • the display area further includes a spacer, the spacer being located between the pixel defining layer and the second electrode.
  • a display device including the above display substrate is provided.
  • a method for preparing a display substrate including a display area and a peripheral area surrounding the display area, including: forming a third conductive pattern on the base substrate, the third conductive pattern Including a first conductive pattern located in the peripheral region;
  • the first conductive pattern includes at least two first hollow regions, the first hollow region is used as a registration mark pattern; and a third insulation pattern is formed on the third conductive pattern, the third insulation pattern includes a first insulation pattern located in the peripheral region; the first insulation pattern covers the first hollow region, and the first insulation pattern does not completely cover a portion between adjacent first hollow regions;
  • the third conductive pattern further includes a first electrode located in the display area; the third insulation pattern further includes a pixel defining layer or a spacer located in a pixel defining area of the display area; The conductive pattern also includes a second electrode located in the display area.
  • the shape of the first insulation pattern is in a zigzag shape.
  • the first insulation pattern includes a plurality of mutually independent sub-insulation patterns, each of the sub-insulation patterns covering one of the first hollow regions.
  • the projection of the boundary of the sub-insulation pattern on the first conductive pattern coincides with the boundary of the first hollow region.
  • the first conductive pattern surrounds the display area along an entire circumference of the display area.
  • FIG. 1 is a schematic structural view of a display substrate divided into a display area and a peripheral area according to the prior art
  • FIG. 2 is an enlarged schematic view of a portion of FIG. 1 provided by the prior art
  • Figure 3 (a) is an enlarged schematic view of a portion A of Figure 1 provided by an embodiment of the present disclosure
  • Figure 3 (b) is a cross-sectional view taken along line BB' of Figure 3 (a);
  • Figure 3 (c) is an enlarged schematic view of the second portion of Figure 1 provided in the embodiment of the present disclosure
  • Figure 3 (d) is an enlarged schematic view 3 of A in Figure 1 provided by an embodiment of the present disclosure
  • FIG. 4 is an enlarged schematic view 4 of FIG. 1 in FIG. 1 according to an embodiment of the present disclosure
  • Figure 5 is an enlarged schematic view 5 of A in Figure 1 provided by an embodiment of the present disclosure
  • FIG. 6 is a schematic structural diagram of a display substrate according to an embodiment of the present disclosure.
  • FIG. 7 is a schematic structural diagram 1 of a display substrate display area according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic structural diagram 2 of a display substrate display area according to an embodiment of the present disclosure.
  • FIG. 9 is a schematic flow chart of a method for preparing a display substrate provided by the implementation of the present disclosure.
  • the term “upper”, “Bottom”, “Left”, “Right”, “Vertical”, “Horizontal”, “Top”, “Bottom” and their derivatives shall refer to the public text.
  • the terms “overlay”, “on top of”, “positioned on” or “positioned on top of” mean that a first element, such as a first structure, exists in a second element, such as a second structure. Above, wherein an intermediate element such as an interface structure may exist between the first element and the second element.
  • the term “contacting” means connecting a first element such as a first structure and a second element such as a second structure, with or without other elements at the interface of the two elements.
  • a display substrate such as an OLED (Organic Electro-Luminescence Display) is divided into a display area (also referred to as an AA area, ie, an Active Area) 01 and a peripheral area 02 surrounding the display area 01.
  • the peripheral area 02 is used to provide a driver IC (Integrated Circuit), a GOA circuit, or the like.
  • the peripheral area 02 includes a GOA circuit
  • the peripheral area 02 includes a first conductive pattern 10 and a second conductive pattern which are disposed in a stacked manner.
  • the first conductive pattern 10 and the second conductive pattern are electrically connected as A portion of the GOA circuit (the second conductive pattern is not illustrated in Figure 2 of the present disclosure).
  • the first conductive pattern 10 is provided with a plurality of first hollow regions 101 for use as a mark pattern (Mark) for facilitating alignment in subsequent processes. Since the edge of the first hollow region 101 is easily oxidized to form a burr, in order to prevent edge oxidation of the first hollow region 101, a first insulating pattern 20 is generally formed on the first conductive pattern 10 in the prior art, and the first insulating pattern 20 covers the first Hollow area 101.
  • Mark mark pattern
  • the first insulating pattern 20 in the prior art covers not only the first hollow region 101 but also a portion between adjacent first hollow regions 101 (as shown by the dotted circle in FIG. 2).
  • the second conductive pattern is formed on the first insulating pattern 20, the overlapping area of the first conductive pattern 10 and the second conductive pattern is reduced, so that the first conductive pattern 10 and the second conductive pattern are The resistance between the two is large, resulting in poor display.
  • the embodiment of the present disclosure provides a display substrate, as shown in FIGS. 1 and 6, including a display area 01 and a peripheral area 02, wherein the peripheral area 02 may be provided with a driving circuit, a Gate-Reset GOA, or an EM GOA Etc., this is not limited.
  • the peripheral area 02 includes: a first conductive pattern 10, the first conductive pattern 10 includes at least two first hollow areas 101, and the first hollow area 101 is used as a registration mark pattern; An insulating layer on the first conductive pattern 10, the insulating layer includes a first insulating pattern 20, the first insulating pattern 20 covers the first hollow region 101, and the first insulating pattern 20 does not completely cover the gap between the adjacent first hollow regions 101. a second conductive pattern 30 disposed on the insulating layer, the second conductive pattern 30 being electrically connected to the first conductive pattern 10.
  • the first conductive pattern 10, the first insulating pattern 20, and the second conductive pattern 30 are illustrated in FIGS. 3(a) and 3(b), and FIG. 3(c), FIG. 3(d), and FIG. Only the first conductive pattern 10 and the first insulating pattern 20 are illustrated, and the second conductive pattern 30 is not illustrated.
  • the shape of the first hollow region 101 on the first conductive pattern 10 is not limited. Since the first hollow region 101 is used as a registration mark pattern, the first hollow region 101 is generally set in the shape of a "+" "-" symbol. On the basis of this, the number of the first hollow areas 101 is not limited, and may be set as needed. Two first hollow areas 101 may be provided, or a plurality of first hollow areas 101 may be provided.
  • the display substrate has an area dedicated to setting the alignment mark pattern (as shown at position A in FIG. 1), which is referred to as a registration mark area, and the first hollow area 101 is used as a registration mark pattern, and thus the first The cutout area 101 is set in the registration mark area.
  • a registration mark area an area dedicated to setting the alignment mark pattern (as shown at position A in FIG. 1)
  • the first hollow area 101 is used as a registration mark pattern, and thus the first The cutout area 101 is set in the registration mark area.
  • the embodiment of the present disclosure is illustrated by taking an alignment mark area as an example.
  • the first insulating pattern 20 does not completely cover the portion between the adjacent first hollow regions 101, and may be a partial hollow of the first insulating pattern 20 between the adjacent first hollow regions 101, or may be the first insulation.
  • the pattern 20 is located adjacent to the first hollow region 101 and is disconnected from each other.
  • the shape of the first insulating pattern 20 is not limited as long as the first insulating pattern 20 covers the first hollow region 101 and does not completely cover the portion between the adjacent first hollow regions 101.
  • first conductive pattern 10 and the second conductive pattern 30 in the peripheral region 02 may be simultaneously formed with the film layer in the display region 01, or may be separately fabricated.
  • First conductive pattern 10 The shape and size of the second conductive pattern 30 may be the same or different. In the embodiment of the present disclosure, it is preferable that the first conductive pattern 10 and the second conductive pattern 30 have the same shape and size, and the second conductive pattern 30 covers the first conductive pattern 10.
  • the first conductive pattern 10 and the second conductive pattern 30 are disposed in the peripheral region 02, and the first conductive pattern 10 and the second conductive pattern 30 are electrically connected, so that the signal of the display area 01 can be derived through layers.
  • the first conductive pattern 10 and the second conductive pattern 30 are electrically connected and can be used as part of the GOA circuit.
  • Embodiments of the present disclosure provide a display substrate that covers both a first hollow region 101 and a portion between adjacent first hollow regions 101 as compared with the prior art display substrate.
  • the first insulating pattern 20 of the peripheral region 02 of the embodiment does not completely cover the portion between the adjacent first hollow regions 101, and thus the embodiment of the present disclosure may increase the contact between the first conductive pattern 10 and the second conductive pattern 30.
  • the pressure drop solves the technical problems of optical defects and uneven brightness caused by voltage drop.
  • the shape of the first insulating pattern 20 is zigzag.
  • one tooth covers one first hollow region 101.
  • the serrated teeth may face the display area 01 as shown in FIG. 3(a), FIG. 3(c), and FIG. 6, or may face away from the display area 01 as shown in FIG. 3(d).
  • the top end of the tooth may be a point (not shown in the drawings of the present disclosure), or may be as shown in FIG. 3(a) and FIG. 3(c).
  • the top end of the tooth shown in Fig. 3(d) and Fig. 6 is a line.
  • the first insulation pattern 20 covers the first hollow region 101, and when the shape of the first insulation pattern 20 is zigzag, when forming on the first insulation pattern 20 When the second conductive pattern 30 is formed, the contact area of the first conductive pattern 10 and the second conductive pattern 30 can be increased.
  • the first insulation pattern 20 includes a plurality of mutually independent sub-insulation patterns 201, and each sub-insulation pattern 201 covers a first hollow area 101.
  • the shape and size of the sub-insulation pattern 201 are not limited as long as each sub-insulation pattern 201 can cover one first hollow region 101. In order to make the contact area of the first conductive pattern 10 and the second conductive pattern 30 as large as possible, the sub-insulation pattern 201 should be as small as possible.
  • each of the sub-insulating patterns 201 covers a first hollow region 101, and as shown in FIG. 4, the boundary of the projection of the sub-insulating pattern 201 on the first conductive pattern 10 surrounds the boundary of the first hollow region 101; As shown in FIG. 5, the boundary of the sub-insulation pattern 201 projected on the first conductive pattern 10 overlaps with the boundary of the first hollow region 101.
  • the first insulation pattern 20 includes a plurality of mutually independent sub-insulation patterns 201, each of the sub-insulation patterns 201 covers one first hollow region 101, such that when the second conductive pattern is formed on the first insulation pattern 20 At 30 o'clock, the contact area of the first conductive pattern 10 and the second conductive pattern 30 can be increased.
  • the present disclosure further selects As shown in FIG. 5, the projection of the boundary of the sub-insulation pattern 201 on the first conductive pattern 10 coincides with the boundary of the first hollow region 101. At this time, the shape and size of the sub-insulation pattern 201 are exactly the same as the size and shape of the first hollow region 101, and the sub-insulation pattern 201 is filled in the first hollow region 101.
  • the first conductive pattern 10 surrounds the display area 01 along the entire periphery of the display area 01 .
  • first conductive pattern 10 since the first conductive pattern 10 surrounds the display region 01 along the entire periphery of the display region 01, the area of the first conductive pattern 10 is increased, so that the first conductive pattern 10 and the second conductive pattern 30 are in contact, which can be lowered.
  • First conductive pattern 10 and second The voltage drop of the conductive pattern 30.
  • the first conductive pattern 10 further includes a second hollow region 102; the second hollow region 102 and the first hollow region 101 are located at different sides of the display region 01; and the insulating layer further includes a second insulation The pattern 50 and the second insulation pattern 50 cover the second hollow region 102.
  • the material of the first insulating pattern 20 and the material of the second insulating pattern 50 may be the same or different. When the material of the first insulating pattern 20 and the material of the second insulating pattern 50 are different, the first insulating pattern 20 may be formed first, and then the second insulating pattern 50 may be formed; or the second insulating pattern 50 may be formed first, and then the first insulating pattern 50 may be formed. An insulating pattern 20.
  • the second conductive pattern 30 covers not only the first insulating pattern 20 but also the second insulating pattern 50.
  • the second conductive pattern 30 is electrically connected to the first conductive pattern 10 through a hollow region on the insulating layer. .
  • the second hollow region 102 may be disposed on one side of the display region 01, or the second hollow region 102 may be disposed on both sides or three sides of the display region 01.
  • the display area 01 has different sides, and the second hollow area 102 and the first hollow area 101 are located on different sides of the display area 01.
  • the display area 01 has four sides of up, down, left and right, The first hollow area 101 is located on the upper side of the display area 01, and the second hollow area 102 is located on the left and right sides of the display area 01.
  • the first conductive pattern 10 further includes a second hollow region 102.
  • the second hollow region 102 and the first hollow region 101 are located on different sides of the display region 01, and a second hollow is disposed on the first conductive pattern 10.
  • the first conductive pattern 10 can be prevented from bubbling. Covering the second insulating pattern 50 on the second hollow region 102 prevents the edge of the second hollow region 102 from being oxidized to form a burr.
  • the display area 01 includes: a pixel defining layer (PDL) 60 disposed on the substrate substrate 40 , a first electrode 70 and a light emitting layer disposed in sequence in the opening of the pixel defining layer 60 . 80.
  • the second electrode 90 covering the display area 01; the first conductive pattern 10 is disposed in the same layer as the first electrode 70, and the second conductive pattern 30 is disposed in the same layer as the second electrode 90.
  • “same layer setting" means forming from the same film layer.
  • the first electrode 70 may be an anode, and the second electrode 90 may be a cathode; or the first electrode 70 may be a cathode, and the second electrode 90 may be an anode.
  • the second electrode 90 can form a full vapor-deposited film layer using an Open Mask.
  • the light emitted from the light-emitting layer 80 can be emitted from the first electrode 70 or from the second electrode 90, and of course, can be emitted from both the first electrode 70 and the second electrode 90.
  • the materials of the first electrode 70 and the second electrode 90 are not limited.
  • the material of the first electrode 70 may be ITO ( Atdium Tin Oxide, at least one of IZO (Indium Zinc Oxide) or FTO (Fluorine-Doped Tin Oxide); when the light emitted from the luminescent layer 80 is not
  • the first electrode 70 is a reflective electrode, and the material of the first electrode 70 may be Ag (silver), Mg (magnesium), Al (aluminum), Pt (platinum), Au (gold) or One or more of their compounds.
  • the second electrode 90 is the same as the first electrode 70 described above, and will not be described herein.
  • lines or thin film transistors or the like may be disposed between the base substrate 40 and the first electrode 70, and an electron transport layer and an electron may be disposed between the first electrode 70 and the second electrode 90.
  • the evaporation of the light-emitting layer is performed by FMM (Fine Metal Mask), so that the alignment mark pattern needs to be provided on the display substrate.
  • the alignment mark pattern may be an alignment mark pattern used by the FMM to detect PPA (pixel possition accuracy).
  • the first conductive pattern 10 is disposed in the same layer as the first electrode 70, so that the first conductive pattern 10 can be formed while the first electrode 70 is being formed; the second conductive pattern 30 is in the same layer as the second electrode 90.
  • the arrangement makes it possible to fabricate the second conductive pattern 30 while the second electrode 90 is being formed, thereby simplifying the manufacturing process of the display substrate.
  • the first insulation pattern 20 is disposed in the same layer as the pixel defining layer 60.
  • the first insulating pattern 20 since the first insulating pattern 20 is disposed in the same layer as the pixel defining layer 60, the first insulating pattern 20 may be formed while the pixel defining layer 60 is formed to simplify the manufacturing process of the display substrate.
  • the display area 01 further includes a spacer 100 ((Photo Spacer, PS for short) disposed between the pixel defining layer 60 and the second electrode 90 and disposed on the pixel defining layer 60;
  • the first insulation pattern 20 is disposed in the same layer as the spacer 100.
  • the material of the spacer 100 and the material of the pixel defining layer 60 may be the same or different.
  • the first insulating pattern 20 is disposed in the same layer as the spacer 100, the first insulating pattern 20 can be formed while the spacer 100 is formed to simplify the manufacturing process of the display substrate.
  • the second insulating pattern 50 is disposed in the same layer as the pixel defining layer 60.
  • the first insulating pattern 20 may also be disposed in the same layer as the pixel defining layer 60, so that the first insulating pattern 20 and the second insulating pattern 50 can be simultaneously fabricated. .
  • the second insulating pattern 50 since the second insulating pattern 50 is disposed in the same layer as the pixel defining layer 60, the second insulating pattern 50 may be simultaneously formed when the pixel defining layer 60 is formed to simplify the manufacturing process of the display substrate.
  • the display area 01 further includes a spacer disposed between the pixel defining layer 60 and the second electrode 90 and disposed on the pixel defining layer 60.
  • the insulating layer further includes a second insulating pattern. At 50 o'clock, the second insulation pattern 50 is disposed in the same layer as the spacer 100.
  • the first insulation pattern 20 may also be disposed in the same layer as the spacer 100, so that the first insulation pattern 20 and the second insulation pattern 50 can be simultaneously fabricated.
  • the second insulation pattern 50 since the second insulation pattern 50 is disposed in the same layer as the spacer 100, the second insulation pattern 50 can be simultaneously formed when the spacer 100 is formed to simplify the manufacturing process of the display substrate.
  • Embodiments of the present disclosure provide a display device including the above display substrate.
  • the display device provided by the embodiment of the present disclosure may be an image that displays whether it is motion (eg, video) or fixed (eg, still image) and whether it is a text or a picture. Any device. More specifically, it is contemplated that the described embodiments can be implemented in or associated with a variety of electronic devices such as, but not limited to, mobile phones, wireless devices, personal data assistants (PDAs).
  • PDAs personal data assistants
  • handheld or portable computer GPS receiver/navigator, camera, MP4 video player, video camera, game console, watch, clock, calculator, TV monitor, flat panel display, computer monitor, car monitor (for example, Odometer display, etc.), navigator, cockpit controller and/or display, camera view display (eg, rear view camera display in vehicle), electronic photo, electronic billboard or signage, projector, building structure, packaging And the aesthetic structure (for example, a display for an image of a piece of jewelry), etc.
  • the display device may also be a display panel.
  • the display device may be an LCD display device or an OLED display device.
  • the embodiment of the present disclosure provides a display device including the above display substrate, wherein the first insulation pattern 20 in the display substrate covers both the first hollow region 101 and the portion between the adjacent first hollow regions 101. Since the first insulating pattern 20 of the peripheral region 02 of the present disclosure does not completely cover the portion between the adjacent first hollow regions 101, the present disclosure embodiment may increase the first conductive pattern 10 and the second conductive pattern 30 The contact area between the two, so that the contact resistance between the first conductive pattern 10 and the second conductive pattern 30 is reduced, the problem of local resistance unevenness caused by the first insulating pattern 20 is reduced, and the pressure of the display substrate is lowered. The technical problem of optical defects and uneven brightness caused by pressure drop is solved.
  • the embodiment of the present disclosure further provides a method for preparing a display substrate.
  • the display substrate includes a display area 01 and a peripheral area 02 surrounding the display area 01.
  • the preparation method includes:
  • the third conductive pattern includes a first conductive pattern 10 located in the peripheral region 02, the first conductive pattern 10 includes at least two first hollow regions 101, and the first hollow region 101 Used as a registration mark pattern. Further, the third conductive pattern further includes a first electrode 70 located in the display area 01
  • the shape of the first hollow region 101 on the first conductive pattern 10 is not limited. set. Since the first hollow region 101 is used as a registration mark pattern, the first hollow region 101 is generally set in the shape of a "+" "-" symbol.
  • the third insulation pattern includes a first insulation pattern 20 in the peripheral region 02, the first insulation pattern 20 covers the first hollow region 101, and the first insulation pattern 20 is incomplete A portion between adjacent first hollow regions 101 is covered. Further, the third insulation pattern further includes a pixel defining layer or a spacer located at a pixel defining area of the display area 01.
  • the first insulating pattern 20 does not completely cover the portion between the adjacent first hollow regions 101, and may be a partial hollow of the first insulating pattern 20 between the adjacent first hollow regions 101, or may be the first insulating pattern. 20 is located adjacent to the first hollow region 101 and is disconnected from each other.
  • the first insulating pattern 20 may be formed simultaneously with the pixel defining layer 60 of the display substrate, or may be formed simultaneously with the spacer 100 of the display substrate.
  • the spacer 100 may be formed on the pixel defining layer 60 after forming the third insulating pattern; when the first insulating pattern 20 and the spacer 100 are simultaneously formed, The pixel defining layer 60 is formed before the third insulating pattern is formed.
  • the fourth conductive pattern includes a second conductive pattern 30 located in the peripheral region 02, the second conductive pattern 30 is electrically connected to the first conductive pattern 10, and the second electrode 90 covers the display The region 01 second conductive pattern 30 covers the first conductive pattern 10. Further, the fourth conductive pattern further includes a second electrode 90 located in the display area 01.
  • the method further includes forming an organic layer in the opening region of the pixel defining layer 60, and the organic layer includes the light emitting layer 80.
  • the shape of the first conductive pattern 10 and the second conductive pattern 30 may be the same or different.
  • the embodiment of the present disclosure preferably has the same shape and size of the first conductive pattern 10 and the second conductive pattern 30, and the second conductive The pattern 30 covers the first conductive pattern 10.
  • the first conductive pattern 10 and the second conductive pattern 30 are electrically connected, so that the signal of the display area 01 can be derived layer by layer to transmit the signal of the display area 01.
  • the display substrate is a COA substrate
  • the first conductive pattern 10 and the second conductive pattern 30 are electrically connected and can be used as part of the GOA circuit.
  • Embodiments of the present disclosure provide a method of fabricating a display substrate, in which a first insulating pattern 20 in a display substrate covers both a first hollow region 101 and a portion between adjacent first hollow regions 101,
  • the first insulating pattern 20 of the peripheral region 02 of the present disclosure does not completely cover the portion between the adjacent first hollow regions 101, and thus the present disclosure may increase the first conductive pattern 10 and the second conductive pattern 30
  • the contact area between the first conductive pattern 10 and the second conductive pattern 30 is reduced, the problem of local resistance unevenness caused by the first insulating pattern 20 is reduced, and the voltage drop of the display substrate is lowered. It solves the technical problems of optical defects and uneven brightness caused by voltage drop.
  • the shape of the first insulating pattern 20 is zigzag.
  • one tooth covers one first hollow region 101.
  • the serrated teeth may face the display area 01 as shown in FIG. 3(a), FIG. 3(c), and FIG. 6, or may face away from the display area 01 as shown in FIG. 3(d).
  • the top end of the tooth may be a point (not shown in the drawings of the present disclosure), or may be as shown in FIG. 3(a) and FIG. 3(c).
  • the top end of the tooth shown in Fig. 3(d) and Fig. 6 is a line.
  • the first insulating pattern 20 covers the first hollow region 101, and since the shape of the first insulating pattern 20 is zigzag, when the second conductive pattern 30 is formed on the first insulating pattern 20, The contact area of the first conductive pattern 10 and the second conductive pattern 30 is increased.
  • the first insulation pattern 20 includes a plurality of mutually independent sub-insulation patterns 201, and each sub-insulation pattern 201 covers a first hollow area 101.
  • the shape and size of the sub-insulation pattern 201 are not limited as long as each The sub-insulation pattern 201 may cover a first hollow region 101. In order to make the contact area of the first conductive pattern 10 and the second conductive pattern 30 as large as possible, the sub-insulation pattern 201 should be as small as possible.
  • each of the sub-insulating patterns 201 covers a first hollow region 101, and as shown in FIG. 4, the boundary of the projection of the sub-insulating pattern 201 on the first conductive pattern 10 surrounds the boundary of the first hollow region 101; As shown in FIG. 5, the boundary of the sub-insulation pattern 201 projected on the first conductive pattern 10 overlaps with the boundary of the first hollow region 101.
  • the first insulation pattern 20 includes a plurality of mutually independent sub-insulation patterns 201, each of the sub-insulation patterns 201 covers one first hollow region 101, such that when the second conductive pattern is formed on the first insulation pattern 20 At 30 o'clock, the contact area of the first conductive pattern 10 and the second conductive pattern 30 can be increased.
  • the present disclosure further selects As shown in FIG. 5, the projection of the boundary of the sub-insulation pattern 201 on the first conductive pattern 10 coincides with the boundary of the first hollow region 101. At this time, the shape and size of the sub-insulation pattern 201 are exactly the same as the size and shape of the first hollow region 101, and the sub-insulation pattern 201 is filled in the first hollow region 101.
  • the first conductive pattern 10 surrounds the entire peripheral display area 01 along the display area 01 .
  • the first conductive pattern 10 surrounds the display region 01 along the entire periphery of the display region 01, the area of the first conductive pattern 10 is increased, so that the first conductive pattern 10 and the second conductive pattern 30 are in contact, which can be lowered.
  • the voltage drop of the first conductive pattern 10 and the second conductive pattern 30 since the first conductive pattern 10 surrounds the display region 01 along the entire periphery of the display region 01, the area of the first conductive pattern 10 is increased, so that the first conductive pattern 10 and the second conductive pattern 30 are in contact, which can be lowered.
  • the voltage drop of the first conductive pattern 10 and the second conductive pattern 30 since the first conductive pattern 10 surrounds the display region 01 along the entire periphery of the display region 01, the area of the first conductive pattern 10 is increased, so that the first conductive pattern 10 and the second conductive pattern 30 are in contact, which can be lowered. The voltage drop of the first conductive pattern 10 and the second conductive pattern 30.

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Abstract

提供一种显示基板及其制备方法、显示装置，涉及显示技术领域，可增加第一导电图案（10）和第二导电图案的接触面积。该显示基板包括显示区域（01）和包围显示区域（01）的周边区域（02），周边区域（02）包括：第一导电图案（10），第一导电图案（10）包括至少两个第一镂空区域（101），第一镂空区域（101）用于作为对位标记图案；设置在第一导电图案（10）上的绝缘层，绝缘层包括第一绝缘图案（20），第一绝缘图案（20）覆盖第一镂空区域（101），且第一绝缘图案（20）不完全覆盖相邻第一镂空区域（101）之间的部分；设置在绝缘层上的第二导电图案，第二导电图案贯穿第一绝缘图案（20）上的镂空区域与所述第一导电图案（10）电连接。

Description

一种显示基板及其制备方法、显示装置
相关申请的交叉引用
本申请要求于2017年05月26日递交的中国专利申请第201710386834.4号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开文本涉及显示技术领域，尤其涉及一种显示基板及其制备方法、显示装置。
背景技术
随着显示技术的快速发展，近些年来显示器的发展呈现了高集成度、低成本的发展趋势。目前，越来越多的显示器采用阵列基板栅极驱动(Gate Driver on Array，简称GOA)技术，GOA技术是将栅极驱动电路集成在阵列基板上，以省略在阵列基板的边缘再设置如柔性电路薄膜(Chip On Film，简称COF)等附加驱动，从而有利于阵列基板的小型化，且从材料成本和制作工艺两方面降低产品成本。
发明内容
本公开文本的实施例提供一种显示基板及其制备方法、显示装置，可增加第一导电图案和第二导电图案的接触面积。
为达到上述目的，本公开文本的实施例采用如下技术方案：
第一方面，提供一种显示基板，包括显示区域和包围所述显示区域的周边区域，所述周边区域包括：第一导电图案，所述第一导电图案包括至少两个第一镂空区域，所述第一镂空区域用于作为对位标记图案；设置在所述第一导电图案上的绝缘层，所述绝缘层包括第一绝缘图案，所述第一绝缘图案覆盖所述第一镂空区域，且所述第一绝缘 图案不完全覆盖相邻所述第一镂空区域之间的部分；设置在所述绝缘层上的第二导电图案，所述第二导电图案与所述第一导电图案电连接。
可选的，所述第一绝缘图案的形状为锯齿状。
可选的，所述第一绝缘图案包括多个相互独立的子绝缘图案，每个所述子绝缘图案覆盖一个所述第一镂空区域。
进一步可选的，所述子绝缘图案的边界在所述第一导电图案上的投影与所述第一镂空区域的边界重合。
可选的，所述第一导电图案沿所述显示区域的整个周边包围所述显示区域。
可选的，所述第一导电图案还包括第二镂空区域；所述第二镂空区域与所述第一镂空区域位于所述显示区域的不同侧边；所述绝缘层还包括第二绝缘图案，所述第二绝缘图案覆盖所述第二镂空区域。
可选的，所述显示区域包括：设置在衬底基板上像素界定层、位于所述像素界定层开口中依次设置的第一电极和发光层、以及、覆盖所述显示区域的第二电极；所述第一导电图案与所述第一电极同层设置，所述第二导电图案与所述第二电极同层设置。
可选的，所述第一绝缘图案与所述像素界定层同层设置。
可选的，所述显示区域还包括位于所述像素界定层和所述第二电极之间，且设置在所述像素界定层上的隔垫物；所述第一绝缘图案与所述隔垫物同层设置。
可选的，在所述绝缘层还包括第二绝缘图案时，所述第二绝缘图案与所述像素界定同层设置。
可选的，所述显示区域还包括隔垫物，所述隔垫物位于所述像素界定层和所述第二电极之间。
第二方面，提供一种显示装置，包括上述的显示基板。
第三方面，还提供一种显示基板的制备方法，所述显示基板包括显示区域和包围所述显示区域的周边区域，包括：在衬底基板上形成第三导电图案，所述第三导电图案包括位于周边区域的第一导电图案； 所述第一导电图案包括至少两个第一镂空区域，所述第一镂空区域用于作为对位标记图案；在所述第三导电图案上形成第三绝缘图案，所述第三绝缘图案包括位于周边区域的第一绝缘图案；所述第一绝缘图案覆盖所述第一镂空区域，且所述第一绝缘图案不完全覆盖相邻所述第一镂空区域之间的部分；在所述第三绝缘图案上形成第四导电图案，所述第四导电图案包括位于周边区域的第二导电图案；所述第二导电图案与所述第一导电图案电连接，所述第二电极覆盖所述显示区域。
可选的，所述第三导电图案还包括位于显示区域的第一电极；所述第三绝缘图案还包括位于所述显示区域的像素界定区域的像素界定层或隔垫物；所述第四导电图案还包括位于所述显示区域的第二电极。
可选的，所述第一绝缘图案的形状为锯齿状。
可选的，所述第一绝缘图案包括多个相互独立的子绝缘图案，每个所述子绝缘图案覆盖一个所述第一镂空区域。
进一步可选的，所述子绝缘图案的边界在所述第一导电图案上的投影与所述第一镂空区域的边界重合。
可选的，所述第一导电图案沿所述显示区域的整个周边包围所述显示区域。
附图说明
为了更清楚地说明本公开文本实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开文本的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为现有技术提供的一种显示基板划分为显示区域和周边区域的结构示意图；
图2为现有技术提供的图1中A处的放大示意图；
图3(a)为本公开文本实施例提供的图1中A处的放大示意图一；
图3(b)为图3(a)中BB′向的剖视示意图；
图3(c)为本公开文本实施例提供的图1中A处的放大示意图二；
图3(d)为本公开文本实施例提供的图1中A处的放大示意图三；
图4为本公开文本实施例提供的图1中A处的放大示意图四；
图5为本公开文本实施例提供的图1中A处的放大示意图五；
图6为本公开文本实施例提供的一种显示基板的结构示意图；
图7为本公开文本实施例提供的一种显示基板显示区域的结构示意图一；
图8为本公开文本实施例提供的一种显示基板显示区域的结构示意图二；
图9为本公开文本实施提供的一种显示基板的制备方法的流程示意图。
附图标记：
01-显示区域；02-周边区域；10-第一导电图案；101-第一镂空区域；102-第二镂空区域；20-第一绝缘图案；201-子绝缘图案；30-第二导电图案；40-衬底基板；50-第二绝缘图案；60-像素界定层；70-第一电极；80-发光层；90-第二电极；100-隔垫物。
具体实施方式
下面将结合本公开文本实施例中的附图，对本公开文本实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开文本一部分实施例，而不是全部的实施例。基于本公开文本中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开文本保护的范围。
当介绍本公开文本的元素及其实施例时，冠词“一”、“一个”、“该”和“所述”旨在表示存在一个或者多个要素。用语“包含”、“包括”、“含有”和“具有”旨在包括性的并且表示可以存在除所列要素之外的另外的要素。
出于下文表面描述的目的，如其在附图中被标定方向那样，术语“上”、 “下”、“左”、“右”“垂直”、“水平”、“顶”、“底”及其派生词应涉及公开文本。术语“上覆”、“在……顶上”、“定位在……上”或者“定位在……顶上”意味着诸如第一结构的第一要素存在于诸如第二结构的第二要素上，其中，在第一要素和第二要素之间可存在诸如界面结构的中间要素。术语“接触”意味着连接诸如第一结构的第一要素和诸如第二结构的第二要素，而在两个要素的界面处可以有或者没有其它要素。
如图1所示，诸如OLED(Organic Electro-luminescent Display，有机电致发光显示装置)的显示基板划分为显示区域(也称为AA区，即Active area)01和包围显示区域01的周边区域02，周边区域02用于设置驱动IC(Integrated Circuit，集成电路)或GOA电路等。当周边区域02包括GOA电路时，如图2所示，周边区域02包括层叠设置的第一导电图案10和第二导电图案，示例的，第一导电图案10和第二导电图案电连接可以作为GOA电路的一部分(本公开文本说明书附图2中未示意出第二导电图案)。其中，第一导电图案10上设置有多个第一镂空区域101，用于作为对位标记图案(Mark)，便于在后续制程中用于对位。由于第一镂空区域101边缘易于氧化形成毛刺，因而为了防止第一镂空区域101边缘氧化，现有技术中通常在第一导电图案10上形成第一绝缘图案20，第一绝缘图案20覆盖第一镂空区域101。
然而，如图2所示，现有技术中的第一绝缘图案20不仅覆盖第一镂空区域101，还覆盖相邻第一镂空区域101之间的部分(如图2中虚线圈所示的部分)，这样当在第一绝缘图案20上形成第二导电图案时，就会减小第一导电图案10和第二导电图案的搭接面积，从而使得第一导电图案10和第二导电图案之间的电阻较大，进而导致显示不良。
本公开文本实施例提供一种显示基板，如图1和图6所示，包括显示区域01和周边区域02，其中，周边区域02可以设置有驱动电路、Gate-Reset GOA，或者设置有EM GOA等，对此不进行限定。
如图3-图6所示，周边区域02包括：第一导电图案10，第一导电图案10包括至少两个第一镂空区域101，第一镂空区域101用于作为对位标记图案；设置在第一导电图案10上的绝缘层，绝缘层包括第一绝缘图案20，第一绝缘图案20覆盖第一镂空区域101，且第一绝缘图案20不完全覆盖相邻第一镂空区域101之间的部分；设置在绝缘层上的第二导电图案30，第二导电图案30与第一导电图案10电连接。
附图3(a)和图3(b)中示意出第一导电图案10、第一绝缘图案20和第二导电图案30，附图3(c)、图3(d)以及图4-图6仅示意出第一导电图案10和第一绝缘图案20，未示意出第二导电图案30。
需要说明的是，第一，对于第一导电图案10上第一镂空区域101的形状不进行限定。由于第一镂空区域101用于作为对位标记图案，因而第一镂空区域101一般设置成“+”“-”符号的形状。在此基础上，对于第一镂空区域101的个数不进行限定，可以根据需要进行相应设置，可以设置两个第一镂空区域101，也可以设置多个第一镂空区域101。
其中，显示基板具有专门用于设置对位标记图案的区域(如图1中位置A处所示)，称为对位标记区，第一镂空区域101用于作为对位标记图案，因此第一镂空区域101设置在对位标记区。显示基板上可以具有一个、两个或多个对位标记区。本公开文本实施例中以具有一个对位标记区为例进行示意。
第二，第一绝缘图案20不完全覆盖相邻第一镂空区域101之间的部分，可以是第一绝缘图案20位于相邻第一镂空区域101之间的部分镂空，也可以是第一绝缘图案20位于相邻第一镂空区域101是相互断开的。对于第一绝缘图案20的形状不进行限定，只要第一绝缘图案20覆盖第一镂空区域101，且不完全覆盖相邻第一镂空区域101之间的部分即可。
第三，周边区域02中第一导电图案10和第二导电图案30可以和显示区域01中的膜层同时制作，也可以单独制作。第一导电图案10 和第二导电图案30的形状大小可以相同，也可以不相同。本公开文本实施例优选第一导电图案10和第二导电图案30的形状大小相同，且第二导电图案30覆盖第一导电图案10。
在此基础上，在周边区域02设置第一导电图案10和第二导电图案30，第一导电图案10和第二导电图案30电连接，这样可以将显示区域01的信号通过一层一层导出，以将显示区域01的信号传输至周边区域02的驱动IC或其它电路。或者，当显示基板为COA基板时，第一导电图案10和第二导电图案30电连接，可以用于作为GOA电路的一部分。
本公开文本实施例提供一种显示基板，相对现有技术显示基板中的第一绝缘图案20既覆盖第一镂空区域101，又覆盖相邻第一镂空区域101之间的部分，由于本公开文本实施例周边区域02的第一绝缘图案20不完全覆盖相邻第一镂空区域101之间的部分，因而本公开文本实施例可以增大第一导电图案10和第二导电图案30之间的接触面积，从而使得第一导电图案10和第二导电图案30之间的接触电阻减小，减小了第一绝缘图案20带来的局部电阻不均匀的问题，降低诸如OLED显示基板的显示基板的压降，解决了压降导致的光学不良、亮度不均等技术问题。
可选的，如图3(a)、图3(c)、图3(d)以及图6所示，第一绝缘图案20的形状为锯齿状。
此处，当第一绝缘图案20的形状为锯齿状时，一个齿覆盖一个第一镂空区域101。此外，锯齿状的齿可以如图3(a)、图3(c)以及图6所示朝向显示区域01，也可以如图3(d)所示背离显示区域01。
在此基础上，当第一绝缘图案20的形状为锯齿状时，齿的顶端可以是点(本公开文本说明书附图未示意出)，也可以如图3(a)、图3(c)、图3(d)以及图6所示齿的顶端是线。
本公开文本实施例，第一绝缘图案20覆盖第一镂空区域101，由于第一绝缘图案20的形状为锯齿状，因而当在第一绝缘图案20上形 成第二导电图案30时，这样便可以增加第一导电图案10和第二导电图案30的接触面积。
可选的，如图4和图5所示(附图4和图5中未示意出第二导电图案30)，第一绝缘图案20包括多个相互独立的子绝缘图案201，每个子绝缘图案201覆盖一个第一镂空区域101。
其中，对于子绝缘图案201的形状和大小不进行限定，只要每个子绝缘图案201可以覆盖一个第一镂空区域101即可。为了使第一导电图案10和第二导电图案30的接触面积尽可能地大，因而子绝缘图案201应尽可能地小。
此处，每个子绝缘图案201覆盖一个第一镂空区域101，可以是如图4所示，子绝缘图案201在第一导电图案10上的投影的边界包围第一镂空区域101的边界；也可以是如图5所示，子绝缘图案201在第一导电图案10上投影的边界与第一镂空区域101的边界重叠。
本公开文本实施例，由于第一绝缘图案20包括多个相互独立的子绝缘图案201，每个子绝缘图案201覆盖一个第一镂空区域101，这样当在第一绝缘图案20上形成第二导电图案30时，便可以增加第一导电图案10和第二导电图案30的接触面积。
为了使第一导电图案10和第二导电图案30的接触面积达到最大，且防止第一导电图案10中的第一镂空区域101的边缘不被氧化形成毛刺，因而本公开文本实施例进一步可选的，如图5所示，子绝缘图案201的边界在第一导电图案10上的投影与第一镂空区域101的边界重合。此时，子绝缘图案201的形状和大小与第一镂空区域101的大小和形状完全相同，子绝缘图案201填充在第一镂空区域101内。
可选的，如图6所示，第一导电图案10沿显示区域01的整个周边包围显示区域01。
本公开文本实施例，由于第一导电图案10沿显示区域01的整个周边包围显示区域01，因而第一导电图案10的面积增加，从而第一导电图案10和第二导电图案30接触，可以降低第一导电图案10和第二 导电图案30的压降。
可选的，如图6所示，第一导电图案10还包括第二镂空区域102；第二镂空区域102与第一镂空区域101位于显示区域01的不同侧边；绝缘层还包括第二绝缘图案50，第二绝缘图案50覆盖第二镂空区域102。
其中，第一绝缘图案20的材料和第二绝缘图案50的材料可以相同，也可以不同。当第一绝缘图案20的材料和第二绝缘图案50的材料不相同时，可以先形成第一绝缘图案20，再形成第二绝缘图案50；也可以先形成第二绝缘图案50，再形成第一绝缘图案20。
需要说明的是，第二导电图案30不仅覆盖在第一绝缘图案20上，还覆盖在第二绝缘图案50上，第二导电图案30贯穿绝缘层上的镂空区域与第一导电图案10电连接。
此处，可以在显示区域01的一侧设置第二镂空区域102，也可以在显示区域01的两侧或三侧设置第二镂空区域102。
在此基础上，显示区域01有不同侧边，第二镂空区域102与第一镂空区域101位于显示区域01的不同侧边，以图6为例，显示区域01有上下左右四个侧边，第一镂空区域101位于显示区域01的上侧，第二镂空区域102位于显示区域01的左右两侧。
本公开文本实施例，第一导电图案10还包括第二镂空区域102，第二镂空区域102与第一镂空区域101位于显示区域01的不同侧边，在第一导电图案10上设置第二镂空区域102，可以防止第一导电图案10鼓泡。在第二镂空区域102上覆盖第二绝缘图案50，可以防止第二镂空区域102的边缘被氧化形成毛刺。
可选的，如图7和图8所示，显示区域01包括：设置在衬底基板40上像素界定层(PDL)60、位于像素界定层60开口中依次设置的第一电极70和发光层80、以及覆盖显示区域01的第二电极90；第一导电图案10与第一电极70同层设置，第二导电图案30与第二电极90同层设置。在本公开文本中，“同层设置”是指由同一膜层形成。
其中，在显示基板中，可以是第一电极70为阳极，第二电极90为阴极；也可以是第一电极70为阴极，第二电极90为阳极。第二电极90可以利用Open Mask(开口掩膜板)形成全面的蒸镀膜层。
在此基础上，发光层80发出的光可以从第一电极70出射，或者从第二电极90出射，当然也可以从第一电极70和第二电极90均出射。对于第一电极70和第二电极90的材料不进行限定，当发光层80发出的光从第一电极70出射，即第一电极70是透射电极时，第一电极70的材料可以是ITO(Indium Tin Oxide，氧化铟锡)、IZO(Indium Zinc Oxide，氧化铟锌)或FTO(Fluorine-Doped Tin Oxide，氟掺杂二氧化锡)中的至少一种；当发光层80发出的光不从第一电极70出射时，此时第一电极70为反射电极，第一电极70的材料可以是Ag(银)、Mg(镁)、Al(铝)、Pt(铂)、Au(金)或它们化合物中的一种或多种。第二电极90与上述第一电极70的情况相同，此处不再赘述。
此处，需要说明的是，还可以在衬底基板40和第一电极70之间设置其它线路或薄膜晶体管等，在第一电极70和第二电极90之间还可以设置电子传输层、电子注入层、空穴传输层、空穴注入层等。
显示基板在制作过程中例如蒸镀发光层会利用FMM(精细金属掩膜板，Fine Metal Mask)进行蒸镀，因此显示基板上需设置对位标记图案。对位标记图案可以为FMM用于检测PPA(pixel possition accuracy，像素位置准确度)的对位标记图案。
本公开文本实施例中，第一导电图案10与第一电极70同层设置，因而可以在制作第一电极70的同时制作第一导电图案10；第二导电图案30与第二电极90同层设置，因而可以在制作第二电极90的同时制作第二导电图案30，从而简化了显示基板的制作工艺。
可选的，第一绝缘图案20与像素界定层60同层设置。
本公开文本实施例，由于第一绝缘图案20与像素界定层60同层设置，因而可以在制作像素界定层60的同时制作第一绝缘图案20，以简化显示基板的制作工艺。
可选的，如图8所示，显示区域01还包括位于像素界定层60和第二电极90之间，且设置在像素界定层60上的隔垫物100((Photo Spacer，简称PS)；第一绝缘图案20与隔垫物100同层设置。
其中，隔垫物100的材料和像素界定层60的材料可以相同，也可以不同。
本公开文本实施例，由于第一绝缘图案20与隔垫物100同层设置，因而可以在制作隔垫物100的同时制作第一绝缘图案20，以简化显示基板的制作工艺。
可选的，在绝缘层还包括第二绝缘图案50时，第二绝缘图案50与像素界定层60同层设置。
其中，当第二绝缘图案50与像素界定层60同层设置时，第一绝缘图案20也可以与像素界定层60同层设置，这样第一绝缘图案20和第二绝缘图案50便可以同时制作。
本公开文本实施例，由于第二绝缘图案50与像素界定层60同层设置，因而可以在制作像素界定层60时，同时制作第二绝缘图案50，以简化显示基板的制作工艺。
可选的，如图8所示，显示区域01还包括位于像素界定层60和第二电极90之间，且设置在像素界定层60上的隔垫物；在绝缘层还包括第二绝缘图案50时，第二绝缘图案50与隔垫物100同层设置。
其中，当第二绝缘图案50与隔垫物100同层设置时，第一绝缘图案20也可以与隔垫物100同层设置，这样第一绝缘图案20和第二绝缘图案50便可以同时制作。
本公开文本实施例，由于第二绝缘图案50与隔垫物100同层设置，因而可以在制作隔垫物100时，同时制作第二绝缘图案50，以简化显示基板的制作工艺。
本公开文本实施例提供一种显示装置，包括上述的显示基板。
其中，本公开文本实施例提供的显示装置可以是显示不论运动(例如，视频)还是固定(例如，静止图像)的且不论文字还是图画的图像的 任何装置。更明确地说，预期所述实施例可实施在多种电子装置中或与多种电子装置关联，所述多种电子装置例如(但不限于)移动电话、无线装置、个人数据助理(PDA)、手持式或便携式计算机、GPS接收器/导航器、相机、MP4视频播放器、摄像机、游戏控制台、手表、时钟、计算器、电视监视器、平板显示器、计算机监视器、汽车显示器(例如，里程表显示器等)、导航仪、座舱控制器和/或显示器、相机视图的显示器(例如，车辆中后视相机的显示器)、电子相片、电子广告牌或指示牌、投影仪、建筑结构、包装和美学结构(例如，对于一件珠宝的图像的显示器)等，此外，显示装置还可以是显示面板。
此处，显示装置可以是LCD显示装置，也可以是OLED显示装置。
本公开文本实施例提供一种显示装置，显示装置包括上述的显示基板，显示基板中的第一绝缘图案20既覆盖第一镂空区域101，又覆盖相邻第一镂空区域101之间的部分，由于本公开文本实施例周边区域02的第一绝缘图案20不完全覆盖相邻第一镂空区域101之间的部分，因而本公开文本实施例可以增大第一导电图案10和第二导电图案30之间的接触面积，从而使得第一导电图案10和第二导电图案30之间的接触电阻减小，减小了第一绝缘图案20带来的局部电阻不均匀的问题，降低显示基板的压降，解决了压降导致的光学不良、亮度不均等技术问题。
本公开文本实施例还提供一种显示基板的制备方法，如图1所示，显示基板包括显示区域01和包围显示区域01的周边区域02，如图9所示，所述制备方法包括：
S100、在衬底基板40上形成第三导电图案，第三导电图案包括位于周边区域02的第一导电图案10，第一导电图案10包括至少两个第一镂空区域101，第一镂空区域101用于作为对位标记图案。进一步地，第三导电图案还包括位于显示区域01的第一电极70
其中，对于第一导电图案10上第一镂空区域101的形状不进行限 定。由于第一镂空区域101用于作为对位标记图案，因而第一镂空区域101一般设置成“+”“-”符号的形状。
S101、在第三导电图案上形成第三绝缘图案，第三绝缘图案包括位于周边区域02的第一绝缘图案20，第一绝缘图案20覆盖第一镂空区域101，且第一绝缘图案20不完全覆盖相邻第一镂空区域101之间的部分。进一步地，第三绝缘图案还包括位于显示区域01的像素界定区域的像素界定层或隔垫物。
其中，第一绝缘图案20不完全覆盖相邻第一镂空区域101之间的部分，可以是第一绝缘图案20位于相邻第一镂空区域101之间的部分镂空，也可以是第一绝缘图案20位于相邻第一镂空区域101是相互断开的。
此处，第一绝缘图案20可以和显示基板的像素界定层60同时形成，也可以和显示基板的隔垫物100同时形成。当第一绝缘图案20和像素界定层60同时形成，则在形成第三绝缘图案之后还可以在像素界定层60上形成隔垫物100；当第一绝缘图案20和隔垫物100同时形成，则在形成第三绝缘图案之前，需先形成像素界定层60。
S102、在第三绝缘图案上形成第四导电图案，第四导电图案包括位于周边区域02的第二导电图案30，第二导电图案30与第一导电图案10电连接，第二电极90覆盖显示区域01第二导电图案30覆盖第一导电图案10。进一步地，第四导电图案还包括位于显示区域01的第二电极90。
需要说明的是，在形成第四导电图案之前，所述方法还包括在像素界定层60的开口区域形成有机层，有机层包括发光层80。
其中，第一导电图案10和第二导电图案30的形状大小可以相同，也可以不相同，本公开文本实施例优选第一导电图案10和第二导电图案30的形状大小相同，且第二导电图案30覆盖第一导电图案10。
此处，第一导电图案10和第二导电图案30电连接，这样可以将显示区域01的信号通过一层一层导出，以将显示区域01的信号传输 至周边区域02的驱动IC或其它电路。或者，当显示基板为COA基板时，第一导电图案10和第二导电图案30电连接，可以用于作为GOA电路的一部分。
本公开文本实施例提供一种显示基板的制备方法，相对现有技术显示基板中的第一绝缘图案20既覆盖第一镂空区域101，又覆盖相邻第一镂空区域101之间的部分，由于本公开文本实施例周边区域02的第一绝缘图案20不完全覆盖相邻第一镂空区域101之间的部分，因而本公开文本实施例可以增大第一导电图案10和第二导电图案30之间的接触面积，从而使得第一导电图案10和第二导电图案30之间的接触电阻减小，减小了第一绝缘图案20带来的局部电阻不均匀的问题，降低显示基板的压降，解决了压降导致的光学不良、亮度不均等技术问题。
可选的，如图3(a)、图3(c)、图3(d)以及图6所示，第一绝缘图案20的形状为锯齿状。
此处，当第一绝缘图案20的形状为锯齿状时，一个齿覆盖一个第一镂空区域101。此外，锯齿状的齿可以如图3(a)、图3(c)以及图6所示朝向显示区域01，也可以如图3(d)所示背离显示区域01。
在此基础上，当第一绝缘图案20的形状为锯齿状时，齿的顶端可以是点(本公开文本说明书附图未示意出)，也可以如图3(a)、图3(c)、图3(d)以及图6所示齿的顶端是线。
本公开文本实施例，第一绝缘图案20覆盖第一镂空区域101，由于第一绝缘图案20的形状为锯齿状，因而当在第一绝缘图案20上形成第二导电图案30时，这样便可以增加第一导电图案10和第二导电图案30的接触面积。
可选的，如图4和图5所示(附图4和图5中未示意出第二导电图案30)，第一绝缘图案20包括多个相互独立的子绝缘图案201，每个子绝缘图案201覆盖一个第一镂空区域101。
其中，对于子绝缘图案201的形状和大小不进行限定，只要每个 子绝缘图案201可以覆盖一个第一镂空区域101即可。为了使第一导电图案10和第二导电图案30的接触面积尽可能地大，因而子绝缘图案201应尽可能地小。
此处，每个子绝缘图案201覆盖一个第一镂空区域101，可以是如图4所示，子绝缘图案201在第一导电图案10上的投影的边界包围第一镂空区域101的边界；也可以是如图5所示，子绝缘图案201在第一导电图案10上投影的边界与第一镂空区域101的边界重叠。
本公开文本实施例，由于第一绝缘图案20包括多个相互独立的子绝缘图案201，每个子绝缘图案201覆盖一个第一镂空区域101，这样当在第一绝缘图案20上形成第二导电图案30时，便可以增加第一导电图案10和第二导电图案30的接触面积。
为了使第一导电图案10和第二导电图案30的接触面积达到最大，且防止第一导电图案10中的第一镂空区域101的边缘不被氧化形成毛刺，因而本公开文本实施例进一步可选的，如图5所示，子绝缘图案201的边界在第一导电图案10上的投影与第一镂空区域101的边界重合。此时，子绝缘图案201的形状和大小与第一镂空区域101的大小和形状完全相同，子绝缘图案201填充在第一镂空区域101内。
可选的，如图6所示，第一导电图案10包围沿显示区域01的整个周边显示区域01。
本公开文本实施例，由于第一导电图案10沿显示区域01的整个周边包围显示区域01，因而第一导电图案10的面积增加，从而第一导电图案10和第二导电图案30接触，可以降低第一导电图案10和第二导电图案30的压降。
以上所述，仅为本公开文本的具体实施方式，但本公开文本的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开文本揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开文本的保护范围之内。因此，本公开文本的保护范围应以所述权利要求的保护范围为准。

Claims (16)

  1. 一种显示基板，包括显示区域和包围所述显示区域的周边区域，其中，所述周边区域包括：
    第一导电图案，所述第一导电图案包括至少两个第一镂空区域，所述第一镂空区域用于作为对位标记图案；
    设置在所述第一导电图案上的绝缘层，所述绝缘层包括第一绝缘图案，所述第一绝缘图案覆盖所述第一镂空区域，且所述第一绝缘图案不完全覆盖相邻所述第一镂空区域之间的部分；
    设置在所述绝缘层上的第二导电图案，所述第二导电图案与所述第一导电图案电连接。
  2. 根据权利要求1所述的显示基板，其中，所述第一绝缘图案的形状为锯齿状。
  3. 根据权利要求1所述的显示基板，其中，所述第一绝缘图案包括多个相互独立的子绝缘图案，每个所述子绝缘图案覆盖一个所述第一镂空区域。
  4. 根据权利要求3所述的显示基板，其中，所述子绝缘图案的边界在所述第一导电图案上的投影与所述第一镂空区域的边界重合。
  5. 根据权利要求1所述的显示基板，其中，所述第一导电图案沿所述显示区域的整个周边包围所述显示区域。
  6. 根据权利要求1所述的显示基板，其中，所述第一导电图案还包括第二镂空区域；所述第二镂空区域与所述第一镂空区域位于所述显示区域的不同侧边；
    所述绝缘层还包括第二绝缘图案，所述第二绝缘图案覆盖所述第二镂空区域。
  7. 根据权利要求1-6任一项所述的显示基板，其中，所述显示区域包括：设置在衬底基板上像素界定层、位于所述像素界定层开口中依次设置的第一电极和发光层、以及覆盖所述显示区域的第二电极；
    所述第一导电图案与所述第一电极同层设置，所述第二导电图案与所 述第二电极同层设置。
  8. 根据权利要求7所述的显示基板，其中，所述第一绝缘图案与所述像素界定层同层设置。
  9. 根据权利要求7所述的显示基板，其中，所述显示区域还包括位于所述像素界定层和所述第二电极之间，且设置在所述像素界定层上的隔垫物；
    所述第一绝缘图案与所述隔垫物同层设置。
  10. 根据权利要求7所述的显示基板，其中，所述绝缘层还包括第二绝缘图案，所述第二绝缘图案与所述像素界定层同层设置。
  11. 根据权利要求7或10所述的显示基板，其中，所述显示区域还包括隔垫物，所述隔垫物位于所述像素界定层和所述第二电极之间。
  12. 一种显示装置，其中，包括权利要求1-11任一项所述的显示基板。
  13. 一种显示基板的制备方法，所述显示基板包括显示区域和包围所述显示区域的周边区域，其中，所述方法包括：
    在衬底基板上形成第三导电图案，所述第三导电图案包括位于周边区域的第一导电图案，其中，所述第一导电图案包括至少两个第一镂空区域，所述第一镂空区域用于作为对位标记图案；
    在所述第三导电图案上形成第三绝缘图案，所述第三绝缘图案包括位于周边区域的第一绝缘图案，所述第一绝缘图案覆盖所述第一镂空区域，且所述第一绝缘图案不完全覆盖相邻所述第一镂空区域之间的部分；
    在所述第三绝缘图案上形成第四导电图案，所述第四导电图案包括位于周边区域的第二导电图案，所述第二导电图案与所述第一导电图案电连接，所述第二电极覆盖所述显示区域。
  14. 根据权利要求13所述的制备方法，其中，所述第三导电图案还包括位于显示区域的第一电极；
    所述第三绝缘图案还包括位于所述显示区域的像素界定区域的像素界定层或隔垫物；
    所述第四导电图案还包括位于所述显示区域的第二电极。
  15. 根据权利要求13所述的制备方法，其中，所述第一绝缘图案的形状为锯齿状。
  16. 根据权利要求13所述的制备方法，其中，所述第一绝缘图案包括多个相互独立的子绝缘图案，每个所述子绝缘图案覆盖一个所述第一镂空区域。
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CN107170785B (zh) 2017-05-26 2019-06-25 京东方科技集团股份有限公司 一种oled显示基板及其制备方法、显示装置
CN108376698B (zh) * 2018-03-02 2020-06-23 京东方科技集团股份有限公司 一种显示基板及其制作方法、显示装置
CN109212920B (zh) * 2018-10-18 2020-06-02 京东方科技集团股份有限公司 显示基板及其对位标记的制作方法、显示面板和显示装置
CN110943109A (zh) * 2019-11-22 2020-03-31 武汉华星光电半导体显示技术有限公司 显示面板及显示面板的制备方法
WO2022067581A1 (zh) * 2020-09-29 2022-04-07 京东方科技集团股份有限公司 显示面板及显示装置
CN112505964B (zh) * 2020-11-20 2022-08-30 合肥鑫晟光电科技有限公司 发光基板及其制备方法、显示装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102707486A (zh) * 2012-05-31 2012-10-03 深圳市华星光电技术有限公司 彩色滤光片基板及其制造方法
CN104868058A (zh) * 2015-03-27 2015-08-26 上海天马微电子有限公司 一种显示面板、显示装置和显示面板母板
TW201602851A (zh) * 2014-07-03 2016-01-16 勝華科技股份有限公司 觸控面板與觸控顯示裝置及其製作方法
CN107170785A (zh) * 2017-05-26 2017-09-15 京东方科技集团股份有限公司 一种oled显示基板及其制备方法、显示装置

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6136662A (en) * 1999-05-13 2000-10-24 Lsi Logic Corporation Semiconductor wafer having a layer-to-layer alignment mark and method for fabricating the same
US20180190672A1 (en) * 2017-01-03 2018-07-05 Innolux Corporation Display device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102707486A (zh) * 2012-05-31 2012-10-03 深圳市华星光电技术有限公司 彩色滤光片基板及其制造方法
TW201602851A (zh) * 2014-07-03 2016-01-16 勝華科技股份有限公司 觸控面板與觸控顯示裝置及其製作方法
CN104868058A (zh) * 2015-03-27 2015-08-26 上海天马微电子有限公司 一种显示面板、显示装置和显示面板母板
CN107170785A (zh) * 2017-05-26 2017-09-15 京东方科技集团股份有限公司 一种oled显示基板及其制备方法、显示装置

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