WO2018209753A1 - 薄膜晶体管制作方法、阵列基板制作方法及显示装置 - Google Patents

薄膜晶体管制作方法、阵列基板制作方法及显示装置 Download PDF

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Publication number
WO2018209753A1
WO2018209753A1 PCT/CN2017/089459 CN2017089459W WO2018209753A1 WO 2018209753 A1 WO2018209753 A1 WO 2018209753A1 CN 2017089459 W CN2017089459 W CN 2017089459W WO 2018209753 A1 WO2018209753 A1 WO 2018209753A1
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layer
substrate
thin film
film transistor
active layer
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French (fr)
Inventor
谢华飞
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Priority to US15/576,836 priority Critical patent/US10818856B2/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/10—Deposition of organic active material
    • H10K71/12—Deposition of organic active material using liquid deposition, e.g. spin coating
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
    • H10K10/40—Organic transistors
    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462—Insulated gate field-effect transistors [IGFETs]
    • H10K10/484—Insulated gate field-effect transistors [IGFETs] characterised by the channel regions
    • H10K10/488—Insulated gate field-effect transistors [IGFETs] characterised by the channel regions the channel region comprising a layer of composite material having interpenetrating or embedded materials, e.g. a mixture of donor and acceptor moieties, that form a bulk heterojunction
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K19/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00
    • H10K19/10—Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00 comprising field-effect transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K19/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00
    • H10K19/20—Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00 comprising components having an active region that includes an inorganic semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K85/00—Organic materials used in the body or electrodes of devices covered by this subclass
    • H10K85/20—Carbon compounds, e.g. carbon nanotubes or fullerenes
    • H10K85/221—Carbon nanotubes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a method for fabricating a thin film transistor, a method for fabricating an array substrate, and a display device.
  • QLED quantum dot light-emitting device
  • OLED organic light-emitting display
  • the light-emitting layer of QLED adopts quantum dots with wider spectral tunability, higher luminescence intensity, higher color purity, longer fluorescence lifetime and better environmental stability than organic fluorescent dyes, so it has a broader development than OLED. prospect.
  • TAOS transparent amorphous oxide semiconductor
  • TFTs transparent amorphous oxide semiconductor thin film transistors
  • Traditional amorphous silicon Due to the low mobility and the severe threshold voltage drift, TFTs cannot meet the current-mode OLED/QLED display; Although TFTs have high mobility and good stability, their high-temperature process and excessive process steps make their production cost extremely high, and the existence of grain boundaries makes the uniformity worse, which affects its large Application in the size display.
  • TAOS TFTs not only have extremely low leakage current, but also have visible light, good uniformity and good stability. Especially, they can be prepared at low temperature, and it is expected to realize low-cost flexible display.
  • the mobility of oxide TFTs is lower than that of polysilicon, so increasing the mobility of oxide thin film transistors has great practical significance for improving its performance.
  • Carbon nanotubes have become more and more intensive in their application in the field of electronic devices due to their excellent and unique electrical and optical properties.
  • Semiconductor single-walled carbon nanotubes are considered to be one of the most valuable electrical materials due to their excellent mechanical, thermal, electrical and chemical stability, which can be used in high-frequency devices and improve the frequency response range of devices.
  • SWCNTs Semiconductor single-walled carbon nanotubes
  • doping can be used to prepare n-type or p-type transistors for integrated circuits. It is possible to replace silicon-based semiconductors.
  • the mobility of SWCNTs or nanotube arrays is basically above 1000cm2/(Vs), which can meet the high mobility of transistors. It is required, therefore, how to improve the mobility of the thin film transistor and drive the quantum dot light-emitting device by the high mobility thin film transistor to improve the display light-emitting performance, which has become an urgent problem to be solved in the industry.
  • the technical problem to be solved by the present invention is to provide a method for fabricating a thin film transistor, a method for fabricating an array substrate, and a display device for improving mobility of a thin film transistor, and driving the quantum dot light-emitting device by the high mobility thin film transistor to improve display The luminescence properties exhibited by the device.
  • a technical solution adopted by the present invention is to provide a method for fabricating a thin film transistor, comprising the following steps:
  • the active layer precursor solution being formed by compounding a metal oxide and a carbon nanotube;
  • the active layer film is divided into small module active layers.
  • another technical solution adopted by the present invention is to provide a method for fabricating an array substrate, a method for fabricating a thin film transistor for each pixel unit, and a method for fabricating a quantum dot light emitting device;
  • the method of fabricating the thin film transistor is fabricated by any of the methods described above.
  • a display device including an array substrate, a color filter substrate disposed opposite to the array substrate, and the array substrate and the color filter substrate.
  • the array substrate includes a thin film transistor including a substrate, an isolation layer disposed on the substrate, and an active layer disposed on the isolation layer, the active layer being oxidized by a metal
  • the material and the carbon nanotubes are compositely formed.
  • the invention has the beneficial effects that the thin film transistor manufacturing method, the array substrate manufacturing method and the display device of the present invention are combined as a thin film transistor by mixing single-walled carbon nanotubes and metal oxides.
  • the layer is used to increase the mobility, and the quantum dot light-emitting device is driven by the high mobility thin film transistor to improve the luminescence performance of the display device.
  • FIG. 1 is a schematic flow chart of a method of fabricating a thin film transistor of the present invention
  • Figure 2 is a schematic view of a precursor solution and an active layer of the present invention
  • FIG. 3 is a perspective schematic view of the active layer of FIG. 1 in a thin film transistor
  • FIG. 4 is a schematic structural view of a thin film transistor of the present invention.
  • FIG. 5 is a schematic flow chart of a method for fabricating a quantum dot light-emitting device in an array substrate of the present invention
  • FIG. 6 is a schematic structural view of a quantum dot light-emitting device in an array substrate of the present invention.
  • Figure 7 is a schematic cross-sectional view of the quantum dot light-emitting device of Figure 6;
  • FIG. 8 is a schematic diagram of a driving circuit of the quantum dot light emitting device of FIG. 6;
  • Fig. 9 is a schematic structural view of a display device of the present invention.
  • the method for fabricating a thin film transistor of the present invention comprises the following steps:
  • Step S1 providing a substrate 11.
  • the substrate 11 may be glass, plastic, quartz or silicon wafer. In other embodiments, the material of the substrate is not limited thereto.
  • Step S2 covering the isolation layer 12 on the substrate 11.
  • covering the isolation layer 12 on the substrate 11 is specifically: covering the isolation layer 12 on the substrate 11 by chemical vapor deposition.
  • the material of the isolation layer 12 may be one or a mixture of Al 2 O 3 , HfO 2 , ZrO 2 , SiO 2 , SiN x , or an organic compound.
  • Step S3 coating an active layer precursor solution on the isolation layer 12, the active layer precursor solution being formed by compounding a metal oxide and a carbon nanotube.
  • the coating of the active layer precursor solution on the isolation layer is specifically: adding single-walled carbon nanotubes to ethylene glycol monomethyl ether, and ultrasonically forming a uniformly dispersed solution of nail solution; Indium chloride, gallium nitrate hydrate, zinc chloride and ethanolamine are all dissolved in ethylene glycol monomethyl ether, wherein the ratio of ethanolamine to indium, gallium and zinc is 10:1:1:1, respectively, in air environment 50 After stirring for 1 hour at °C, it was allowed to form a solution of B after standing for 24 hours; the solution of the solution was added to the solution of ethylene in different mass ratios of single-walled carbon nanotubes/metal oxides (SWCNTs/IGZO), and ultrasonically dispersed for 2 hours to form a uniform mixture.
  • Source layer precursor solution is specifically: adding single-walled carbon nanotubes to ethylene glycol monomethyl ether, and ultrasonically forming a uniformly dispersed solution of nail solution; Indium chloride, gall
  • the material of the metal oxide is one or a mixture of ZnO, IZO, IGZO, ZTO, HIZO or In2O3.
  • Step S4 forming the active layer precursor solution into the active layer film 13.
  • the active layer precursor solution is formed into an active layer film, specifically: the substrate 11 covered with the isolation layer 12 is immersed with acetone, methanol and isopropanol; and the substrate 11 is ultrasonically cleaned. High-purity nitrogen is blown dry; the active layer precursor solution is spin-coated on the separator 12, pre-baked in air at 80 ° C for 5 minutes, and then heated to 350 ° C for 40 minutes to remove the organic solvent, and rapidly annealed to obtain Source layer 13 film.
  • Step S5 dividing the thin film of the active layer 13 into a small module active layer.
  • the film of the active layer 13 is divided into small module active layers, specifically: coating a photoresist on the active layer 13 film; exposing, developing, and wet etching the photoresist to activate the active layer
  • the layer 13 film is divided into small module active layers corresponding to each thin film transistor.
  • the method for fabricating the thin film transistor further includes a process of fabricating the source and the drain, and specifically:
  • a source 14 and a drain 15 are formed on the isolation layer 12, and the source 14 and the drain 15 are respectively located on both sides of the active layer 13 and connected to the active layer 13, specifically Depositing a metal layer on the isolation layer 12 by physical vapor deposition, coating a photoresist on the metal layer, and then exposing, developing, and wet etching to form a source 14 and a drain 15;
  • the thin film transistor further includes a gate electrode 17 and a gate insulating layer 16, and the manufacturing method further includes the steps of fabricating the gate electrode 17 and the gate insulating layer 16, in the active layer 13 and the source electrode 14
  • the drain 15 is covered with a gate insulating layer 16, specifically covering the gate insulating layer 16 by chemical vapor deposition;
  • a gate electrode 17 is formed on the gate insulating layer 16, specifically, a metal layer is deposited on the gate insulating layer 16 in a physical gas phase, and a photoresist is coated on the metal layer, and then exposed, developed, and wet etched.
  • the gate electrode 17 is formed, and the thin film transistor formed at this time is a top gate type thin film transistor.
  • the material of the gate 17, the source 14 and the drain 15 is Mo/Ti a mixture of one or more of Mo/Cu, Mo/Au, Mo/Al, Cr/Au, Cr/Cu.
  • the gate insulating layer 16 is made of Al2O3, HfO2, ZrO2, SiO2. A mixture of one or more of SiNx or an organic compound.
  • the bottom gate type thin film transistor When the thin film transistor is of a bottom gate type, the bottom gate type thin film transistor has a gate insulating layer above the gate, an active layer above the gate insulating layer, and a source above the active layer. Drain.
  • the method for fabricating the thin film transistor further includes the steps of: forming a passivation layer and forming a contact hole (not shown) on the passivation layer, specifically covering the gate insulating layer and the gate. a passivation layer, specifically covering the passivation layer by chemical vapor deposition, and coating a photoresist on the passivation layer, exposing, developing, dry etching the passivation layer and the gate insulating layer to prepare A contact hole in a region corresponding to the drain pattern.
  • the material of the passivation layer is Al2O3, HfO2, ZrO2 A mixture of one or more of SiO2, SiNx or an organic compound.
  • FIG. 5 is a schematic flow chart of a method for fabricating a quantum dot light-emitting device in an array substrate of the present invention.
  • the array substrate is similar to the prior art, and includes a substrate and a plurality of pixel units arranged in a matrix on the substrate.
  • Each of the pixel units includes at least one thin film transistor, and the thin film transistor is the above embodiment.
  • a thin film transistor is provided, the array substrate further comprising a quantum dot light emitting device located in each pixel unit.
  • the substrate in the array substrate may be a glass substrate or a flexible substrate.
  • the flexible substrate is made of a polyvinyl alcohol film, polyimide Made of polymer materials such as films and polyester films.
  • the method for fabricating an array substrate includes a method for fabricating a thin film transistor in a pixel unit and a method for fabricating a quantum dot light emitting device.
  • the method for fabricating the thin film transistor is the method for fabricating the thin film transistor provided in the above embodiment, and the method for fabricating the quantum dot light emitting device will be specifically described below.
  • a quantum dot light emitting device can be formed on the basis of the thin film transistor provided in the above embodiment.
  • the method for fabricating the quantum dot light emitting device specifically includes the following steps:
  • Step S1 forming an anode pattern 10 on a substrate on which the thin film transistor is formed, and the anode 10 is connected to a drain of the thin film transistor.
  • Forming an anode pattern on the substrate on which the thin film transistor is formed is specifically: a transparent conductive film is formed by sputtering on a substrate on which the thin film transistor is formed, and transparent conductive is applied to each thin film transistor by photolithography and wet etching.
  • the film pattern was isolated to form a transparent pixel anode; it was ultrasonically cleaned with deionized water, acetone and isopropanol for 15 minutes, dried at 100 ° C, and treated with an ultraviolet ozone machine for 30 minutes to clean and improve the hydrophilicity of the surface of the transparent conductive film.
  • the material of the anode 10 is doped graphene, metal thin film (Al, Ag, Pt, Au, etc.), oxide (ITO, AZO, CTO, etc.), composite film (TiO2-Ag-TiO2, SiO2-Au). -ZrO2, etc.), a mixture of one or more of a transparent conductive polymer (polyaniline, etc.).
  • Step S2 A pattern of the hole injection layer 20 is formed on the substrate on which the pattern of the anode 10 is formed.
  • the hole injection layer pattern is formed on the substrate on which the anode 10 pattern is formed, specifically: the aqueous dispersion solution of poly 3,4-ethylenedioxythiophene and polystyrene sulfonate is rotated at 3000 rpm.
  • the substrate on which the anode 10 pattern was formed was spin-coated for 60 seconds, and further heated at 200 ° C for 10 minutes in a glove box to remove moisture and thermal crosslinking to obtain a hole injecting layer 20.
  • the material of the hole injection layer 20 is one or a mixture of PEDOT (PSS), 2T-NATA or m-MTDATA.
  • Step S3 A pattern of the hole transport layer 30 is formed on the substrate on which the pattern of the hole injection layer 20 is formed.
  • Forming a hole transport layer pattern on the substrate on which the hole injection layer pattern is formed is specifically: spin coating a polymer triphenyldiamine derivative solution on the hole injection layer 20 to form a hole transport layer 30. .
  • the material of the hole transport layer 30 is one or a mixture of TFB, PVK, CBP, NPB or Poly-TPD.
  • Step S4 forming a pattern of the light-emitting layer 40 on the substrate on which the pattern of the hole transport layer 30 is formed.
  • Forming the light-emitting layer pattern on the substrate on which the hole transport layer pattern is formed is specifically: spin-coating the CdSe/ZnS quantum dots dissolved in toluene on the hole transport layer 30 at a rotation speed of 2000 revolutions per minute. In seconds, a quantum dot light-emitting layer was formed and dried in a vacuum oven at 150 ° C for 10 minutes to form a pattern of the light-emitting layer 40.
  • the material of the light-emitting layer 40 is a carbon quantum dot, a graphene quantum dot, a cadmium quantum dot (CdSn/ZnS, CdTe, etc.), a cadmium-free quantum dot (InP, a perovskite quantum dot, etc.) or a silicon quantum. A mixture of one or more of the points.
  • Step S5 forming an electron transport layer 50 pattern on the substrate on which the pattern of the light emitting layer 40 is formed.
  • Forming an electron transport layer pattern on the substrate on which the light emitting layer pattern is formed is specifically: placing the substrate on which the light emitting layer 40 is formed in an evaporation machine, and thermally depositing a hole blocking layer formed by a thickness of 40 nm. Electron transport layer 50.
  • the material of the electron transport layer 50 is TPBi, BBOT, BCP, Alq3 or A mixture of one or more of BNDs.
  • Step S6 forming a cathode 60 pattern on the substrate on which the pattern of the electron transport layer 50 is formed.
  • Forming a cathode pattern on the substrate on which the electron transport layer pattern is formed is specifically: covering with a metal mask, and vapor-depositing aluminum on the substrate on which the electron transport layer 50 is formed by vacuum evaporation to obtain a dot pattern as the cathode 60 .
  • the cathode 60 is connected to the cathode ground power source (not shown) via a via (not shown) to form an electric field with the anode to drive the light-emitting layer to emit light.
  • the material of the cathode 60 is doped graphene, single layer metal (Al, Ag, Mg, etc.), alloy (Mg: Ag, Li: Al, etc.) or double layer (thin insulating layer + metal, such as LiF a mixture of one or more of MgO, Al2O3+Al, and the like.
  • the method for fabricating the quantum dot light emitting device may further include: coating a peripheral protective layer covering the entire substrate on the cathode 60, for example, coating a layer of resin using a resin coating technique, and then performing a patterning process to form a corresponding
  • the outer protective layer of the area prevents damage to the pixel electrode and/or the luminescent organic substance by impurities such as air moisture.
  • the method for fabricating the thin film transistor provided by the embodiment of the invention mainly forms the film layers by sputtering or coating, and the patterning process, the process flow is simple, the requirements for the device are low, and the device for preparing the amorphous silicon thin film transistor can be used. Making thin film transistors with higher carrier mobility can reduce the manufacturing cost of the product.
  • the patterning process may include only a photolithography process or a photolithography process and an etching step, and may also include other processes for forming a predetermined pattern such as printing, inkjet, etc.;
  • the photolithography process includes film formation, A process of forming a pattern by using a photoresist, a mask, an exposure machine, or the like in a process such as exposure and development.
  • the corresponding patterning process can be selected in accordance with the structure formed in the present invention.
  • the driving circuit of the quantum dot light emitting device includes a first controllable switch T1, a second controllable switch T2, and a quantum dot light emitting device.
  • the control end of the first controllable switch T1 receives the scan signal Vscan from the scan line of the scan driving circuit, and the first end of the first controllable switch T1 receives the data signal Vdata from the data line, the first The second end of the control switch T1 is connected to the control end of the second controllable switch T2, and the first end of the second controllable switch T2 is connected to the anode 10 of the quantum dot light emitting device, the second controllable switch The second end of T2 receives the voltage signal VDD.
  • the first controllable switch T1 and the second controllable switch T2 are N-type thin film transistors, and the control end, the first end and the second end of the first and second controllable switches respectively correspond to the N-type film The gate, drain and source of the transistor.
  • the scan signal Vscan is at a high level
  • the first controllable switch T1 is turned on, a high level of the data signal Vdata is provided to a control end of the second controllable switch T2, and the second The control switch T2 is turned on, and the voltage signal VDD supplies a voltage to the quantum dot light emitting device to cause it to emit light.
  • FIG. 9 is a schematic structural view of a display device of the present invention.
  • the display device includes the above array substrate, a color film substrate disposed opposite to the array substrate, and a liquid crystal disposed between the array substrate and the color filter substrate, and other devices and functions of the display device The devices and functions of the display device are the same and will not be described here.
  • the method for fabricating a thin film transistor and the method for fabricating an array substrate improve mobility by mixing single-walled carbon nanotubes with a metal oxide as an active layer of a thin film transistor, and driving the quantum dot light-emitting device by a high mobility thin film transistor This improves the luminescence properties of the display.

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Abstract

一种薄膜晶体管制作方法、阵列基板制作方法及显示装置。薄膜晶体管制作方法包括：提供一基板(11)；在所述基板(11)上覆盖隔离层(12)；在所述隔离层(12)上涂布有源层前驱体溶液；将所述有源层前驱体溶液形成有源层薄膜(13)；将所述有源层薄膜(13)分割成小模块有源层，以通过薄膜晶体管的有源层来提高迁移率，并通过高迁移率的薄膜晶体管来驱动阵列基板的量子点发光器件以此提高显示装置显示的发光性能。

Description

薄膜晶体管制作方法、阵列基板制作方法及显示装置
【技术领域】
本发明涉及显示技术领域，特别是涉及一种薄膜晶体管制作方法、阵列基板制作方法及显示装置。
【背景技术】
QLED（量子点发光器件）是一种与OLED（有机发光显示器）原理和结构相似的新型的显示器件，即量子点和有机/无机半导体在外加直流电场驱动下，激子复合发光的一种平板显示器件。QLED的发光层采用比有机荧光染料具有光谱可调性更宽、发光强度更大、色纯度更高、荧光寿命更长、环境稳定性更好的量子点，因此相较OLED具有更广阔的发展前景。
近年来，透明非晶氧化物半导体（TAOS）薄膜晶体管(TFTs)由其在有源矩阵发光二极管显示中的潜在应用而受到了广泛的关注。传统的非晶硅 TFTs 由于迁移率较低、阈值电压漂移较严重，无法满足电流型驱动方式的 OLED/QLED 显示屏；而多晶硅 TFTs虽然具有较高的迁移率和较好的稳定性，但是其高温制程及过多的工艺步骤使其生产成本极高，且其晶界的存在使得均匀性较差，从而影响了其在大尺寸显示屏中的应用。TAOS TFTs不但具有极低的漏电流，而且可见光透明、均匀性好、稳定性好，特别是可以低温制备，有望实现低成本的柔性显示。但氧化物TFTs的迁移率较多晶硅低，因此提高氧化物薄膜晶体管的迁移率对完善其性能具有重大的现实意义。
碳纳米管（CNTs）由于其优异和独特的电学和光学性能，近年来对其在电子器件领域的应用研究越来越深入。半导体单壁碳纳米管（SWCNTs）因优良的力学、热学、电学性能和化学稳定性，可以用于高频器件，提高器件的频率响应范围等，被认为是最有应用价值的电学材料之一；另外随着传统Si半导体器件的尺寸不断缩小，一些不可避免的制约因素不断显现出来，如短沟道效应、小尺寸下掺杂浓度的统计涨落造成器件性质不均匀性，而SWCNTs由于免掺杂可制备出n型或p型晶体管应用于集成电路，有可能取代硅基半导体，SWCNTs或纳米管阵列其迁移率基本都在1000cm2/(V.s)以上，可以满足晶体管中对高迁移率的要求，因此如何提高薄膜晶体管的迁移率，并通过所述高迁移率的薄膜晶体管驱动量子点发光器件来提高显示的发光性能，已成为业界亟待解决的问题。
【发明内容】
本发明主要解决的技术问题是提供一种薄膜晶体管制作方法、阵列基板制作方法及显示装置，以提高薄膜晶体管的迁移率，并通过所述高迁移率的薄膜晶体管驱动量子点发光器件来提高显示装置显示的发光性能。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种薄膜晶体管制作方法，包括以下步骤：
提供一基板；
在所述基板上覆盖隔离层；
在所述隔离层上涂布有源层前驱体溶液，所述有源层前驱体溶液由金属氧化物和碳纳米管复合形成；
将所述有源层前驱体溶液形成有源层薄膜；及
将所述有源层薄膜分割成小模块有源层。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种阵列基板制作方法，包括每一像素单元的薄膜晶体管制作方法以及量子点发光器件制作方法；
所述薄膜晶体管制作方法由上述任一所述的方法制作而成。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种显示装置，包括阵列基板、与所述阵列基板相对设置的彩膜基板及设置在所述阵列基板与所述彩膜基板之间的液晶，所述阵列基板包括薄膜晶体管，所述薄膜晶体管包括基板、设置在所述基板上的隔离层及设置在所述隔离层上的有源层，所述有源层由金属氧化物和碳纳米管复合形成。
本发明的有益效果是：区别于现有技术的情况，本发明的所述薄膜晶体管制作方法、阵列基板制作方法及显示装置通过将单壁碳纳米管与金属氧化物混合作为薄膜晶体管的有源层来提高迁移率，并通过高迁移率的薄膜晶体管来驱动量子点发光器件以此提高显示装置显示的发光性能。
【附图说明】
图1是本发明的薄膜晶体管制作方法的流程示意图；
图2是本发明前驱体溶液和有源层示意图；
图3是图1中有源层在薄膜晶体管中的透视示意图；
图4是本发明的薄膜晶体管的结构示意图；
图5是本发明的阵列基板中量子点发光器件制作方法的流程示意图；
图6是本发明的阵列基板中量子点发光器件的结构示意图；
图7是图6中量子点发光器件的横截面示意图；
图8是图6中量子点发光器件的驱动电路示意图；
图9是本发明的显示装置的结构示意图。
【具体实施方式】
请参阅图1及图4，本发明的薄膜晶体管制作方法包括以下步骤：
步骤S1：提供一基板11。
具体地，所述基板11可以为玻璃、塑料、石英或者硅片，在其他实施例中所述基板的材料并不限于此。
步骤S2：在所述基板11上覆盖隔离层12。
其中，在所述基板11上覆盖隔离层12具体为：用化学气相沉积法在所述基板11上覆盖隔离层12。
在其他实施中，所述隔离层12的材料可以为Al2O3、HfO2、ZrO2、SiO2、SiNx或者有机化合物中的一种或者混合物。
步骤S3：在所述隔离层12上涂布有源层前驱体溶液，所述有源层前驱体溶液由金属氧化物和碳纳米管复合形成。
其中，请参阅图2，所述在所述隔离层上涂布有源层前驱体溶液具体为：将单壁碳纳米管加入到乙二醇单甲醚中，超声形成分散均匀的甲溶液；将氯化铟、硝酸镓水合物、氯化锌和乙醇胺均溶解于乙二醇单甲醚中，其中乙醇胺与铟、镓、锌的比例分别为10：1：1：1，空气环境中50℃搅拌1小时，放置24小时后形成乙溶液；将甲溶液以不同的单壁碳纳米管/金属氧化物（SWCNTs/IGZO）质量比加入到乙溶液中，超声分散2小时形成混合均匀的有源层前驱体溶液。
其中，金属氧化物的材料为ZnO、IZO、IGZO、ZTO、HIZO或In2O3中的一种或者几种的混合物。
步骤S4：将所述有源层前驱体溶液形成有源层薄膜13。
其中，请参阅图3，将所述有源层前驱体溶液形成有源层薄膜具体为：用丙酮、甲醇和异丙醇浸泡覆盖有隔离层12的基板11；超声清洗所述基板11后用高纯氮气吹干；将有源层前驱体溶液旋涂到隔离层12上，空气中80℃预烘烤5分钟，随后加热到350℃烘烤40分钟，去除有机溶剂，快速退火，得到有源层13薄膜。
步骤S5：将所述有源层13薄膜分割成小模块有源层。
其中，将所述有源层13薄膜分割成小模块有源层具体为：在所述有源层13薄膜上涂布光阻；曝光、显影、湿蚀刻所述光阻以将所述有源层13薄膜分割成对应每一薄膜晶体管的小模块有源层。
当所述薄膜晶体管包括源极14和漏极15时，上述薄膜晶体管制作方法还包括制作所述源极和漏极的过程，具体可以为：
在所述隔离层12上形成源极14和漏极15，且所述源极14和漏极15分别位于所述有源层13的两侧并与所述有源层13连接，具体为在所述隔离层12上以物理气相沉积金属层，在所述金属层上涂布光阻，再曝光、显影、湿蚀刻形成源极14和漏极15；
所述薄膜晶体管还包括栅极17和栅极绝缘层16，上述的制作方法中还包括制作栅极17和栅极绝缘层16的步骤，在所述有源层13及所述源极14和漏极15上覆盖栅极绝缘层16，具体为用化学气相沉积法覆盖栅极绝缘层16；
在所述栅极绝缘层16上形成栅极17，具体为以物理气相在所述栅极绝缘层16上沉积金属层，在所述金属层上涂布光阻，再曝光、显影、湿蚀刻形成栅极17，此时形成的薄膜晶体管为顶栅型薄膜晶体管。
其中，所述栅极17、源极14及漏极15材料为Mo/Ti 、Mo/Cu、Mo/Au、Mo/Al、Cr/Au、Cr/Cu中的一种或者几种的混合物。
所述栅极绝缘层16材料为Al2O3、HfO2、ZrO2、 SiO2、 SiNx或有机化合物中的一种或者几种的混合物。
当所述薄膜晶体管为底栅型时，底栅型的薄膜晶体管具体结构是栅极上方为栅极绝缘层，位于栅极绝缘层上方的为有源层，位于有源层上方的源极和漏极。
需要说明的是，所述薄膜晶体管制作方法还包括制作钝化层和在钝化层上制作接触孔（图未示）的步骤，具体为在所述栅极绝缘层及所述栅极上覆盖钝化层，具体为用化学气相沉积法覆盖钝化层，以及在所述钝化层上涂布光阻，再曝光、显影、干蚀刻所述钝化层和所述栅极绝缘层制备出与漏极图形对应区域的接触孔。
其中，所述钝化层的材料为Al2O3、HfO2、ZrO2、 SiO2、SiNx或有机化合物中的一种或几种的混合物。
请参阅图5，是本发明的阵列基板中量子点发光器件制作方法的流程示意图。其中，所述阵列基板与现有技术类似，包括基板及设置于所述基板上呈矩阵分布的多个像素单元，所述每一像素单元至少包括一个薄膜晶体管，所述薄膜晶体管为上述实施例提供的薄膜晶体管，所述阵列基板还包括位于每一像素单元的量子点发光器件。
其中，所述阵列基板中的基板可以为玻璃基板，也可以为柔性基板。当所述基板为柔性基板时，所述柔性基板由聚乙烯醇薄膜、聚酰亚胺 薄膜、聚酯薄膜等高分子材料制作而成。
所述阵列基板制作方法包括制作像素单元中薄膜晶体管制作方法以及量子点发光器件制作方法。其中薄膜晶体管制作方法为上述实施例提供的薄膜晶体管制作方法，以下具体说明量子点发光器件制作方法。
请参阅图6及图7，可在上述实施例提供的薄膜晶体管的基础上形成量子点发光器件，所述量子点发光器件制作方法具体包括以下步骤：
步骤S1：在形成有所述薄膜晶体管的基板上形成阳极图形10，且所述阳极10与所述薄膜晶体管的漏极相连。
在形成有所述薄膜晶体管的基板上形成阳极图形具体为：透明导电膜通过溅射在形成有所述薄膜晶体管的基板上成膜，通过光刻、湿刻将每一薄膜晶体管对应的透明导电膜图形隔离开形成透明像素阳极；再用去离子水、丙酮和异丙醇超声清洗15分钟，100℃烘干，用紫外臭氧机处理30分钟进行清洁和提高透明导电膜表面亲水性。
其中，所述阳极10的材料为掺杂石墨烯、金属薄膜（Al、Ag、Pt、Au等）、氧化物（ITO、AZO、CTO等）、复合膜（TiO2-Ag-TiO2、SiO2-Au-ZrO2等）、透明导电聚合物（聚苯胺等）的一种或者几种的混合物。
步骤S2：在形成有所述阳极10图形的基板上形成空穴注入层20图形。
在形成有所述阳极10图形的基板上形成空穴注入层图形具体为：将聚3，4-乙烯基二氧噻吩与聚苯乙烯磺酸盐的水性分散体溶液以每分钟3000转的转速在形成有阳极10图形的基板上旋涂60秒，再在手套箱中200℃下加热10分钟去除水分和热交联，得到空穴注入层20。
其中，所述空穴注入层20的材料为PEDOT(PSS)、2T-NATA或m-MTDATA中的一种或者几种的混合物。
步骤S3： 在形成有所述空穴注入层20图形的基板上形成空穴传输层30图形。
在形成有所述空穴注入层图形的基板上形成空穴传输层图形具体为：将聚合物三苯基二胺衍生物溶液旋涂在所述空穴注入层20上形成空穴传输层30。
其中，所述空穴传输层30的材料为TFB、PVK、CBP、NPB或Poly-TPD中的一种或者几种的混合物。
步骤S4：在形成有所述空穴传输层30图形的基板上形成发光层40图形。
在形成有所述空穴传输层图形的基板上形成发光层图形具体为：将溶解于甲苯中的CdSe/ZnS量子点以每分钟2000转的转速在所述空穴传输层30上旋涂20秒，形成量子点发光层，放在150℃的真空干燥箱中干燥10分钟，形成发光层40图形。
其中，所述发光层40的材料为碳量子点、石墨烯量子点、镉系量子点（CdSn/ZnS、CdTe等）、无镉系量子点（InP，钙钛矿量子点等）或硅量子点中的一种或者几种的混合物。
步骤S5：在形成有所述发光层40图形的基板上形成电子传输层50图形。
在形成有所述发光层图形的基板上形成电子传输层图形具体为：将形成有所述发光层40的基板置于蒸镀机中，热蒸镀一层厚40纳米的空穴阻挡层形成电子传输层50。
其中，所述电子传输层50的材料为TPBi、BBOT、BCP、Alq3或 BND中的一种或者几种的混合物。
步骤S6：在形成有所述电子传输层50图形的基板上形成阴极60图形。
在形成有所述电子传输层图形的基板上形成阴极图形具体为：使用金属掩膜版覆盖，以真空蒸镀法在形成有电子传输层50的基板上蒸镀铝得到点阵图案作为阴极60。阴极60经由过孔（图中未标示）与阴极接地电源相连（图中未标示）与阳极形成电场，驱动发光层发光。
其中，所述阴极60的材料为掺杂石墨烯、单层金属（Al、Ag、Mg等）、合金（Mg：Ag，Li：Al等）或双层状（薄绝缘层+金属，如LiF、MgO、Al2O3+Al等）中的一种或者几种的混合物。
需要说明的是，所述量子点发光器件制作方法还可以包括：在形成所述阴极60上覆盖整个基板的外围保护层，例如使用树脂涂覆技术涂覆一层树脂，然后进行构图工艺形成对应区域的外围保护层，防止空气水分等杂质对像素电极和/或发光有机物的破坏。
并且本发明实施例提供的薄膜晶体管制作方法，主要通过溅射或涂覆、以及构图工艺形成各膜层，工艺流程简单，对设备的要求较低，采用制备非晶硅薄膜晶体管的设备就可以制作具有较高载流子迁移率的薄膜晶体管，可以降低产品的制作成本。
在本发明中构图工艺，可只包括光刻工艺或包括光刻工艺以及刻蚀步骤，同时还可以包括打印、喷墨等其他用于形成预定图形的工艺；光刻工艺是指包括成膜、曝光、显影等工艺过程的利用光刻胶、掩模板、曝光机等形成图形的工艺。可根据本发明中所形成的结构选择相应的构图工艺。
请参阅图8，所述量子点发光器件的驱动电路包括第一可控开关T1、第二可控开关T2及量子点发光器件。其中，所述第一可控开关T1的控制端从扫描驱动电路的扫描线接收扫描信号Vscan，所述第一可控开关T1的第一端从数据线接收数据信号Vdata，所述第一可控开关T1的第二端连接所述第二可控开关T2的控制端，所述第二可控开关T2的第一端连接所述量子点发光器件的阳极10，所述第二可控开关T2的第二端接收电压信号VDD。所述第一可控开关T1及第二可控开关T2均为N型薄膜晶体管，所述第一及第二可控开关的控制端、第一端及第二端分别对应所述N型薄膜晶体管的栅极、漏极及源极。当所述扫描信号Vscan为高电平时，所述第一可控开关T1导通，所述数据信号Vdata的高电平提供给所述第二可控开关T2的控制端，所述第二可控开关T2导通，所述电压信号VDD提供电压给所述量子点发光器件以使其发光。
请参阅图9，是本发明的显示装置的结构示意图。所述显示装置包括上述的阵列基板、与所述阵列基板相对设置的彩膜基板及设置在所述阵列基板与所述彩膜基板之间的液晶，所述显示装置的其他器件及功能与现有显示装置的器件及功能相同，在此不再赘述。
所述薄膜晶体管制作方法及阵列基板制作方法通过将单壁碳纳米管与金属氧化物混合作为薄膜晶体管的有源层来提高迁移率，并通过高迁移率的薄膜晶体管来驱动量子点发光器件以此提高显示的发光性能。
以上仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

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  1. 一种薄膜晶体管制作方法，其中，包括以下步骤：
    提供一基板；
    在所述基板上覆盖隔离层；
    在所述隔离层上涂布有源层前驱体溶液，所述有源层前驱体溶液由金属氧化物和碳纳米管复合形成；
    将所述有源层前驱体溶液形成有源层薄膜；及
    将所述有源层薄膜分割成小模块有源层。
  2. 根据权利要求1所述的薄膜晶体管制作方法，其中，所述在所述隔离层上涂布有源层前驱体溶液，所述有源层前驱体溶液由金属氧化物和碳纳米管复合形成包括：
    将单壁碳纳米管加入到乙二醇单甲醚中，超声形成分散均匀的甲溶液；
    将氯化铟、硝酸镓水合物、氯化锌和乙醇胺均溶解于乙二醇单甲醚中，其中乙醇胺与铟、镓、锌的比例分别为10：1：1：1，空气环境中50℃搅拌1小时，放置24小时后形成乙溶液；及
    将甲溶液与乙溶液以不同的质量比混合，超声分散2小时形成混合均匀的有源层前驱体溶液。
  3. 根据权利要求1所述的薄膜晶体管制作方法，其中，所述将所述有源层前驱体溶液形成有源层薄膜包括：
    用丙酮、甲醇和异丙醇浸泡覆盖有隔离层的基板；
    超声清洗所述基板后用高纯氮气吹干；及
    将有源层前驱体溶液旋涂到隔离层上，空气中80℃预烘烤5分钟，随后加热到350℃烘烤40分钟，去除有机溶剂，快速退火，得到有源层薄膜；
    将所述有源层薄膜分割成小模块有源层包括：
    在所述有源层薄膜上涂布光阻；及
    曝光、显影、湿蚀刻所述光阻以将所述有源层薄膜分割成对应每一薄膜晶体管的小模块有源层。
  4. 根据权利要求1所述的薄膜晶体管制作方法，其中，所述方法还包括：
    在所述隔离层上形成源极和漏极，且所述源极和漏极与所述有源层连接，具体为在所述隔离层上以物理气相沉积金属层，在所述金属层上涂布光阻，再曝光、显影、湿蚀刻形成源极和漏极；
    在所述有源层及所述源极和漏极上覆盖栅极绝缘层，具体为用化学气相沉积法覆盖栅极绝缘层；
    在所述栅极绝缘层上形成栅极，具体为以物理气相在所述栅极绝缘层上沉积金属层，在所述金属层上涂布光阻，再曝光、显影、湿蚀刻形成栅极；
    在所述栅极绝缘层及所述栅极上覆盖钝化层，具体为用化学气相沉积法覆盖钝化层；及
    形成接触孔，具体为在所述钝化层上涂布光阻，再曝光、显影、干蚀刻形成接触孔。
  5. 一种阵列基板制作方法，其中，包括每一像素单元的薄膜晶体管制作方法以及量子点发光器件制作方法；
    所述薄膜晶体管制作方法由权利要求1-6任一所述的方法制作而成。
  6. 根据权利要求5所述的阵列基板制作方法，其中，所述量子点发光器件制作方法包括：
    在形成有所述薄膜晶体管的基板上形成阳极图形，且所述阳极与所述薄膜晶体管的漏极相连；
    在形成有所述阳极图形的基板上形成空穴注入层图形；
    在形成有所述空穴注入层图形的基板上形成空穴传输层图形；
    在形成有所述空穴传输层图形的基板上形成发光层图形；
    在形成有所述发光层图形的基板上形成电子传输层图形；及
    在形成有所述电子传输层图形的基板上形成阴极图形。
  7. 根据权利要求6所述的阵列基板制作方法，其中，所述在形成有所述薄膜晶体管的基板上形成阳极图形包括：
    透明导电膜通过溅射在形成有所述薄膜晶体管的基板上成膜，通过光刻、湿刻将每一薄膜晶体管对应的透明导电膜图形隔离开形成透明像素阳极；及
    再用去离子水、丙酮和异丙醇超声清洗15分钟，100℃烘干，用紫外臭氧机处理30分钟进行清洁和提高透明导电膜表面亲水性；
    所述在形成有所述阳极图形的基板上形成空穴注入层图形包括：
    将聚3，4-乙烯基二氧噻吩与聚苯乙烯磺酸盐的水性分散体溶液以每分钟3000转的转速在形成有阳极图形的基板上旋涂60秒，再在手套箱中200℃下加热10分钟去除水分和热交联，得到空穴注入层；
    所述在形成有所述空穴注入层图形的基板上形成空穴传输层图形包括：
    将聚合物三苯基二胺衍生物溶液旋涂在所述空穴注入层上形成空穴传输层；
    所述在形成有所述空穴传输层图形的基板上形成发光层图形包括：
    将溶解于甲苯中的CdSe/ZnS量子点以每分钟2000转的转速在所述空穴传输层上旋涂20秒，形成量子点发光层，放在150℃的真空干燥箱中干燥10分钟，形成发光层图形；
    所述在形成有所述发光层图形的基板上形成电子传输层图形包括：
    将形成有所述发光层的基板置于蒸镀机中，热蒸镀一层厚40纳米的空穴阻挡层形成电子传输层；
    所述在形成有所述电子传输层图形的基板上形成阴极图形包括：
    使用金属掩膜版覆盖，以真空蒸镀法在形成有电子传输层的基板上蒸镀铝得到点阵图案作为阴极。
  8. 一种显示装置，包括阵列基板、与所述阵列基板相对设置的彩膜基板及设置在所述阵列基板与所述彩膜基板之间的液晶，其中，所述阵列基板包括薄膜晶体管，所述薄膜晶体管包括基板、设置在所述基板上的隔离层及设置在所述隔离层上的有源层，所述有源层由金属氧化物和碳纳米管复合形成。
  9. 根据权利要求8所述的显示装置，其中，所述有源层是将单壁碳纳米管加入到乙二醇单甲醚中，超声形成分散均匀的甲溶液；
    将氯化铟、硝酸镓水合物、氯化锌和乙醇胺均溶解于乙二醇单甲醚中，其中乙醇胺与铟、镓、锌的比例分别为10：1：1：1，空气环境中50℃搅拌1小时，放置24小时后形成乙溶液；及
    将甲溶液与乙溶液以不同的质量比混合，超声分散2小时形成混合均匀的有源层前驱体溶液，将所述有源层前驱体溶液涂布在所述隔离层上形成有源层薄膜，并将所述有源层薄膜分割成小模块有源层。
  10. 根据权利要求8所述的显示装置，其中，所述阵列基板还包括量子点发光器件，所述量子点发光器件包括依次设置的阳极、空穴注入层、空穴传输层、发光层、电子传输层及阴极，其中所述阳极设置在有所述薄膜晶体管的基板上，且所述阳极与所述薄膜晶体管的漏极相连。
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