WO2018206163A1 - Transistor de puissance vertical présentant une conductivité améliorée et des performances de blocage élevées - Google Patents

Transistor de puissance vertical présentant une conductivité améliorée et des performances de blocage élevées Download PDF

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Publication number
WO2018206163A1
WO2018206163A1 PCT/EP2018/053278 EP2018053278W WO2018206163A1 WO 2018206163 A1 WO2018206163 A1 WO 2018206163A1 EP 2018053278 W EP2018053278 W EP 2018053278W WO 2018206163 A1 WO2018206163 A1 WO 2018206163A1
Authority
WO
WIPO (PCT)
Prior art keywords
trenches
semiconductor material
power transistor
trench
vertical power
Prior art date
Application number
PCT/EP2018/053278
Other languages
German (de)
English (en)
Inventor
Alberto MARTINEZ-LIMIA
Holger Bartolf
Alfred Goerlach
Wolfgang Feiler
Stephan Schwaiger
Original Assignee
Robert Bosch Gmbh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Robert Bosch Gmbh filed Critical Robert Bosch Gmbh
Priority to EP18708340.7A priority Critical patent/EP3646386A1/fr
Publication of WO2018206163A1 publication Critical patent/WO2018206163A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide

Definitions

  • the invention relates to a vertical power transistor with a
  • Trench structure wherein diode junctions and heterojunction transitions between the trenches and at least one epitaxial layer form.
  • the shielding of the gate oxide from high field strengths at high positive voltage between drain and source is problematic both in the blocking operation and in the case of short circuits. Furthermore, limiting the short-circuit current is difficult.
  • Shielding of the gate oxide make.
  • One possibility is to insert or bury p-doped regions in an epitaxial layer below the trench structure of the power transistor. These p-doped regions are electrically connected to the source region of the power transistor. By their position below the MOS head they shield high field strengths from the MOS head and contribute significantly to the limitation of
  • Another possibility is to create deep-reaching p + regions by implantation laterally of the MOS head. The implantation of these areas is deeper as the implantation of the MOS head, so that the MOS head is shielded from high field strengths.
  • the object of the invention is the performance of a vertical
  • the vertical power transistor has at least one epitaxial layer comprising a first semiconductor material doped with first carriers and a plurality of first trenches and second trenches.
  • the first trenches and the second trenches are arranged alternately and extend from the surface of the epitaxial layer into the interior of the
  • the trench bottoms of the first trenches and the second trenches are arranged in the epitaxial layer or of the
  • the second trenches are at least partially filled with a second semiconductor material which is doped with second charge carriers.
  • the first charge carriers and the second charge carriers are different.
  • a first well layer is a first well layer
  • the trench surface of the second trenches includes the trench bottom of the respective second trench and sidewalls of the respective second trench.
  • Transistor higher field strengths can be exposed.
  • higher reverse voltages can be applied to the transistor or at the same
  • the first semiconductor material has a larger bandgap than the second semiconductor material.
  • the second semiconductor material can be used as a terminal and a p / n transition between the first
  • Semiconductor material and the third semiconductor material is generated, so that the p / n junction is generated in the semiconductor materials with the larger band gap.
  • the first trenches have a smaller depth than the second trenches.
  • the advantage here is that the MOS heads are better protected against high field strengths.
  • the first trenches each have an area that extends from the trench bottom to a certain height.
  • the region is at least partially filled with a fourth semiconductor material which is doped with second charge carriers.
  • the region is electrically connected to a source region.
  • the advantage here is that the areas produce a shielding effect.
  • the reverse operation can advantageously be done via the second trenches, since they can be connected directly to the source in each cell.
  • the term reverse operation the operating mode of the transistor as
  • Freewheeling diode understood, d. H. the current flow of the transistor is reversed to the normal current flow direction. In other words, the reverse conductivity is increased.
  • a second well layer is arranged between a trench surface of the region and the epitaxial layer, which is a fifth
  • the Trench surface of the region includes the trench bottom of the respective first trench and sidewalls of the respective first trench.
  • the second well layer forms a kind of well between the trench surface and the epitaxial layer.
  • the determined height comprises ten to ninety percent of a depth of the respective first trench.
  • the first charge carriers are n-conducting and the second charge carriers are p-conducting.
  • the vertical power transistor has lower conductivities due to a higher mobility of the electrons.
  • the first semiconductor material SiC and the second semiconductor material comprises polycrystalline silicon.
  • the third semiconductor material comprises SiC.
  • the epitaxial layer is on a
  • Semiconductor substrate arranged comprising SiC.
  • the vertical power transistor is a MOSFET.
  • the advantage here is that low conduction losses at the same
  • Blocking resistance for example, compared to the bipolar IGBT occur.
  • FIG. 2 shows an example of a vertical power transistor
  • Figure 3 shows another example of the vertical power transistor.
  • FIG. 1 shows a vertical power transistor 100 of the prior art.
  • the vertical power transistor 100 comprises a semiconductor substrate 101 on the front side of which an epitaxial layer 103 is arranged.
  • the vertical power transistor 100 comprises a semiconductor substrate 101 on the front side of which an epitaxial layer 103 is arranged.
  • Epitaxial layer 103 comprises a first semiconductor material, which is provided with first
  • Charge carriers doped, for example, n-doped SiC.
  • p-doped ions are implanted, for example of Al.
  • a channel layer is formed in the upper region of the epitaxial layer 103
  • the vertical power transistor 100 has a trench structure, i. H. a plurality or plurality of trenches. In each trench 107 is a
  • Gate dielectric 110 and a gate electrode 111 arranged. On every
  • Insulation layer 112 is arranged, the gate electrode 111 from the source region
  • the deep-reaching p + regions 106 are arranged.
  • the deep-reaching p + regions 106 are arranged in a structured manner on the side of the MOS head.
  • the p + regions 106 have a greater depth than the trenches 107, d. H. they are held lower than the MOS head and shield the MOS head from high field strengths.
  • a metal layer 113 is arranged on the structured insulating layer 112 .
  • a drain metallization 114 is disposed on the back side of the semiconductor substrate 101.
  • FIG. 2 shows an example of a vertical power transistor 200.
  • the vertical power transistor 200 includes a semiconductor substrate 201 on the same
  • the epitaxial layer 203 comprises a first semiconductor material which is doped with first charge carriers, for example, n-doped SiC.
  • first charge carriers for example, n-doped SiC.
  • p-doped ions are implanted, for example of Al.
  • a channel layer 204 which functions as a channel region, is formed in the upper region of the epitaxial layer 203.
  • Epitaxial layer that forms the channel area On the channel layer 204, a further semiconductor layer is arranged, which n + the doped
  • Source regions 205 includes.
  • the vertical power transistor 200 has a trench structure.
  • the trench structure includes first trenches 207 and second trenches 220.
  • the first trenches 207 and the second trenches 220 are alternately arranged in the trench structure.
  • a second trench 220 is arranged laterally spaced apart.
  • the terms first trench 207 and second trench 220 are not understood here to mean the number of trenches, but the fact that the trench structure comprises two different types of trenches.
  • the second trenches 220 have a greater depth than the first trenches 207.
  • a gate dielectric 210 and a gate electrode 211 are arranged in each first trench 207.
  • each first trench 207 Arranged on each first trench 207 is a structured insulation layer 212 which electrically isolates the gate electrode 211 from the source region 205.
  • the second trenches 220 are filled with a second semiconductor material, wherein the second semiconductor material is doped with second charge carriers.
  • a first well layer 219 comprising a third semiconductor material doped with second carriers.
  • the first well layer 219 forms a well around the backfill of the second trenches.
  • On the channel layer 204 is a
  • a drain metallization 214 is disposed on the back side of the semiconductor substrate 201.
  • the depth of the first trenches 207 and the depth of the second trenches 220 is 0.5 ⁇ to 10 ⁇ , wherein the depth of the first trenches 207 is less than the depth of the second trenches 220.
  • the distances between the first trenches 207 and the second trenches 220 are substantially the same size and are in the range between 0.1 ⁇ and 10 ⁇ , the lower limit is process-related and the upper limit by an otherwise inadequate shielding of the MOS Complex is conditional.
  • the area laterally between the first trenches 207 and the second trenches 220, ie the horizontal area between the first trenches 207 and the second trenches 220, ie a part of the epitaxial layer 203, may deviate from the remaining part of the epitaxial layer 203
  • the depth of the first trenches 207 may be greater than the depth of the second trenches 220.
  • a further epitaxial layer can be arranged between the at least one epitaxial layer 203 and the MOS head or MOS complex.
  • the first semiconductor material and the second semiconductor material are different.
  • the second semiconductor material comprises
  • the third semiconductor material comprises highly p-doped SiC.
  • the gate dielectric 210 comprises S1O2 and the gate electrode 211 poly-silicon.
  • the semiconductor substrate 201 and the epitaxial layer 203 comprise GaN.
  • FIG. 3 shows another example of the vertical power transistor 300.
  • the vertical power transistor 300 includes the structure of the vertical
  • first trenches 307 each have a region 308 that extends from the trench bottom to a certain height of the first trenches 307. These regions 308 are at least partially or completely filled with a fourth semiconductor material 309.
  • the fourth semiconductor material 309 is at least one
  • Source region 305 electrically connected. Above the regions 308, the gate dielectric 310 and the gate electrode 311 are respectively arranged.
  • the second well layer 315 includes a fifth semiconductor material doped with second carriers.
  • the fourth semiconductor material is, in particular, in situ p-doped polycrystalline silicon.
  • the fifth semiconductor material includes, for example, SiC.
  • the effective dopant dose is usually more than 1E13 ⁇ ⁇ -3.
  • the high effective dopant dose improves the shielding of the MOS head.
  • the thickness of the layer 315 is in the range between 0.01 ⁇ and 4 ⁇ .
  • the third semiconductor material and the fifth semiconductor material may be configured the same, whereby a process step can be saved.
  • the vertical power transistors 200 and 300 are preferably MOSFETs. However, they can also be designed or realized as HEMT.
  • the vertical power transistors 200 and 300 are, for example, in
  • Vehicle inverters photovoltaic inverters, traction drives or
  • High voltage rectifiers can be used.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

L'invention concerne un transistor de puissance vertical (200, 300) comprenant au moins une couche épitaxiale (203, 303) qui comprend un premier matériau semi-conducteur qui est dopé avec des premiers porteurs de charge, le transistor comprenant en outre une pluralité de premières tranchées (207, 307) et de deuxièmes tranchées (220, 320) qui sont disposées en alternance et s'étendent à l'intérieur de la couche épitaxiale (203, 303) à partir d'une surface de ladite couche épitaxiale (203, 303). L'invention est caractérisée en ce que les deuxièmes tranchées (220, 320) sont remplies d'un deuxième matériau semi-conducteur (218, 318) qui est dopé avec des deuxièmes porteurs de charge, les premiers porteurs de charge et les deuxièmes porteurs de charge étant différents, et en ce qu'une première couche de cuvelage (219, 319) est disposée entre une surface des deuxièmes tranchées (220, 320) et la couche épitaxiale (203, 303), cette couche comprenant un troisième matériau semi-conducteur qui est dopé avec les deuxièmes porteurs de charge, et la surface de chaque deuxième tranchée comprenant le fond de la tranchée (207, 307) et les parois latérales de la tranchée (207, 307).
PCT/EP2018/053278 2017-05-10 2018-02-09 Transistor de puissance vertical présentant une conductivité améliorée et des performances de blocage élevées WO2018206163A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP18708340.7A EP3646386A1 (fr) 2017-05-10 2018-02-09 Transistor de puissance vertical présentant une conductivité améliorée et des performances de blocage élevées

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102017207847.2 2017-05-10
DE102017207847.2A DE102017207847A1 (de) 2017-05-10 2017-05-10 Vertikaler Leistungstransistor mit verbesserter Leitfähigkeit und hohem Sperrverhalten

Publications (1)

Publication Number Publication Date
WO2018206163A1 true WO2018206163A1 (fr) 2018-11-15

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PCT/EP2018/053278 WO2018206163A1 (fr) 2017-05-10 2018-02-09 Transistor de puissance vertical présentant une conductivité améliorée et des performances de blocage élevées

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EP (1) EP3646386A1 (fr)
DE (1) DE102017207847A1 (fr)
TW (1) TW201901811A (fr)
WO (1) WO2018206163A1 (fr)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117673082A (zh) * 2022-08-23 2024-03-08 艾科微电子(深圳)有限公司 半导体装置及其制造方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120261676A1 (en) * 2009-12-24 2012-10-18 Rohn Co., Ltd. SiC FIELD EFFECT TRANSISTOR
DE102013105060A1 (de) * 2012-05-18 2013-11-21 Infineon Technologies Austria Ag Halbleitervorrichtungen mit Superjunction-Struktur und Verfahren zur Herstellung
WO2017071855A1 (fr) * 2015-10-28 2017-05-04 Robert Bosch Gmbh Transistor mosfet de puissance et son procédé de production

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120261676A1 (en) * 2009-12-24 2012-10-18 Rohn Co., Ltd. SiC FIELD EFFECT TRANSISTOR
DE102013105060A1 (de) * 2012-05-18 2013-11-21 Infineon Technologies Austria Ag Halbleitervorrichtungen mit Superjunction-Struktur und Verfahren zur Herstellung
WO2017071855A1 (fr) * 2015-10-28 2017-05-04 Robert Bosch Gmbh Transistor mosfet de puissance et son procédé de production

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Publication number Publication date
EP3646386A1 (fr) 2020-05-06
DE102017207847A1 (de) 2018-11-15
TW201901811A (zh) 2019-01-01

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