WO2018205692A1 - 薄膜晶体管及其制造方法、阵列基板以及显示装置 - Google Patents

薄膜晶体管及其制造方法、阵列基板以及显示装置 Download PDF

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WO2018205692A1
WO2018205692A1 PCT/CN2018/074438 CN2018074438W WO2018205692A1 WO 2018205692 A1 WO2018205692 A1 WO 2018205692A1 CN 2018074438 W CN2018074438 W CN 2018074438W WO 2018205692 A1 WO2018205692 A1 WO 2018205692A1
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layer
film transistor
thin film
wiring
active layer
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PCT/CN2018/074438
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English (en)
French (fr)
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陈江博
宋泳锡
孙宏达
王国英
刘威
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京东方科技集团股份有限公司
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Priority to US16/077,846 priority Critical patent/US10644160B2/en
Publication of WO2018205692A1 publication Critical patent/WO2018205692A1/zh

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    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/44—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/38 - H01L21/428
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
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    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
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    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
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    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Definitions

  • the present disclosure relates to the field of display technology. More specifically, it relates to a thin film transistor and a method of fabricating the same, an array substrate, and a display device.
  • Thin film transistors are important components of driving circuits and are widely used in display devices. As a technology hotspot at this stage, oxide transistor technology has the characteristics of high mobility and good uniformity, and has received widespread attention. However, in the prior art, there are still some process difficulties to be solved for the thin film transistor.
  • Embodiments of the present disclosure provide a thin film transistor, a method of fabricating the same, an array substrate, and a display device.
  • a first aspect of the present disclosure provides a thin film transistor.
  • the thin film transistor includes: an active layer disposed on a base substrate; a gate stack disposed on the active layer, wherein the gate stack includes: disposed on the active layer a gate insulating layer; a gate electrode disposed on the gate insulating layer; a capping layer disposed on the gate electrode, the cap layer being more likely to trap oxygen atoms than the gate electrode.
  • the cover layer comprises a gallium-containing oxide.
  • the gallium-containing oxide comprises at least one of the following materials: IGZO, GZO, IGO, gallium oxide, or a combination thereof.
  • the gallium-containing oxide is oxygen deficient.
  • the material of the cover layer is the same as the material of the active layer.
  • the thin film transistor further includes: a dielectric layer disposed on the cover layer, wherein the dielectric layer covers an upper surface of the active layer.
  • the thin film transistor further includes: a first contact portion disposed on the dielectric layer; and a first hole located in the dielectric layer, wherein the first contact is via the A hole is connected to the source/drain regions of the thin film transistor.
  • a second aspect of the present disclosure provides an array substrate.
  • the array substrate includes a thin film transistor as described above.
  • the array substrate further includes: a first wiring located in the dielectric layer, the first wiring having the same structure as the gate stack, a top surface of the first wiring is high a top surface of the active layer; a second contact portion disposed on the dielectric layer; a second hole disposed in the dielectric layer, wherein the second contact portion is connected via the second hole To the first wiring.
  • the array substrate further includes: a light shielding layer disposed between the active layer and the substrate substrate to block light from under the active layer from entering the active layer; a second wiring, the second wiring being in the same layer as the light shielding layer; a third contact portion disposed on the dielectric layer; a third hole extending through the dielectric layer and extending into the substrate substrate Wherein the third contact is connected to the second wiring via the third via.
  • the array substrate further includes: a buffer layer disposed between the active layer and the base substrate, wherein the buffer layer covers an upper surface of the light shielding layer, the first An upper surface of the second wiring and an exposed upper surface of the base substrate; and a passivation layer disposed on the first contact portion, the second contact portion, and the third contact portion.
  • a third aspect of the present disclosure provides a display device.
  • the display device includes the array substrate as described above.
  • a fourth aspect of the present disclosure provides a method of fabricating a thin film transistor.
  • the manufacturing method of the thin film transistor includes: forming an active layer on a base substrate; forming a gate stack on the active layer, wherein the gate stack includes: being disposed on the active layer a gate insulating layer; a gate electrode disposed on the gate insulating layer; a capping layer disposed on the gate electrode, the cap layer being more likely to trap oxygen atoms than the gate electrode.
  • the cover layer comprises a gallium-containing oxide.
  • the gallium-containing oxide comprises at least one of the following materials: IGZO, GZO, IGO, gallium oxide, or a combination thereof.
  • forming the gate stack includes: forming an insulating material layer on the active layer; forming a conductive layer on the insulating material layer; forming a cover material layer on the conductive layer; Patterning to form the gate stack.
  • a fifth aspect of the present disclosure provides a method of fabricating an array substrate.
  • the method of manufacturing the array substrate includes the method of manufacturing a thin film transistor as described above.
  • the method of fabricating the array substrate further includes: forming a light shielding layer and a second wiring on the base substrate before forming the active layer, wherein the second wiring and the light shielding layer are simultaneously Forming, the light shielding layer is capable of blocking light from under the active layer from entering the active layer; after forming the active layer, forming a first wiring on the base substrate, wherein the a wiring and the gate stack are simultaneously formed, and the first wiring has the same structure as the gate stack; after the gate stack is formed and before the dielectric layer is formed, The upper surface of the cover layer and the upper surface of the active layer are subjected to plasma treatment.
  • the method of fabricating the array substrate further includes: forming a buffer layer on the light shielding layer after forming the light shielding layer and the second wiring and before forming the active layer, wherein The buffer layer covers an upper surface of the light shielding layer, an upper surface of the second wiring, and an exposed upper surface of the substrate substrate;
  • first hole Forming a first hole, a second hole, and a third hole in the dielectric layer, wherein the first hole reaches an upper surface of the active layer, and the second hole reaches an upper surface of the first wiring
  • the third hole reaches an upper surface of the second wiring, and wherein the third hole is formed at a time;
  • first contact portion Forming a first contact portion, a second contact portion, and a third contact portion on the dielectric layer, wherein the first contact portion is connected to a source/drain region of the thin film transistor via the through first hole, a second contact portion is connected to the first wiring via the second hole, and the third contact portion is connected to the second wiring via the third hole;
  • a passivation layer is formed on the first contact portion, the second contact portion, and the third contact portion.
  • FIG. 1 is a schematic diagram of a thin film transistor in accordance with an embodiment of the present disclosure
  • FIG. 2 is a schematic diagram of a thin film transistor in accordance with an embodiment of the present disclosure
  • FIG. 3 is a schematic diagram of a thin film transistor in accordance with an embodiment of the present disclosure.
  • FIG. 4 is a schematic diagram of a thin film transistor in accordance with an embodiment of the present disclosure.
  • FIG. 5 is a schematic diagram of a thin film transistor in accordance with an embodiment of the present disclosure.
  • FIG. 6 is a schematic diagram of a thin film transistor in accordance with an embodiment of the present disclosure.
  • FIG. 7 is a flow chart showing a method of fabricating a thin film transistor according to an embodiment of the present disclosure
  • FIG. 8 is a flow diagram of a method of fabricating a gate stack in accordance with an embodiment of the present disclosure
  • FIG. 9 is a flow chart showing a method of fabricating an array substrate according to an embodiment of the present disclosure.
  • FIG. 10 is a flow chart showing a method of fabricating an array substrate according to an embodiment of the present disclosure.
  • 11(A)-11(K) are process flow diagrams of a method of fabricating an array substrate in accordance with an embodiment of the present disclosure.
  • the terms “upper”, “lower”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom” and The derivative should refer to the public text.
  • the terms “overlay”, “on top of”, “positioned on” or “positioned on top of” mean that a first element, such as a first structure, exists in a second element, such as a second structure. Above, wherein an intermediate element such as an interface structure may exist between the first element and the second element.
  • the term “contacting” means connecting a first element such as a first structure and a second element such as a second structure, with or without other elements at the interface of the two elements.
  • FIG. 1 is a schematic diagram of a thin film transistor in accordance with an embodiment of the present disclosure.
  • a thin film transistor according to an embodiment of the present disclosure includes a base substrate 1, an active layer 2 disposed on the base substrate 1, and a gate stack 3 disposed on the active layer.
  • the gate stack 3 includes: a gate insulating layer 301 disposed on the active layer 2, a gate electrode 302 disposed on the gate insulating layer 301, and a gate electrode A cover layer 303 on the electrode 302.
  • the cap layer 303 is more likely to trap oxygen atoms than the gate electrode 302.
  • the gate insulating layer 301 defines a gate region and source/drain regions on both sides of the gate region.
  • embodiments of the present disclosure are capable of solving the problem of oxidation of the gate electrode under the cap layer.
  • the cover layer is more likely to trap oxygen atoms than the gate electrode
  • the material of the cover layer is more likely to bond and fix oxygen atoms than the material of the gate electrode.
  • the cap layer 303 comprises a gallium-containing oxide.
  • Gallium-containing oxides have a stronger oxygen atom trapping ability than common gate electrodes. Since Ga-O has a large bond energy, Ga can better bind O, so that the oxidation problem of the gate electrode under the cap layer can be solved. For example, when the gate electrode includes copper, since O of the Ga-O-Cu interface is bound by Ga, the problem of Cu oxidation can be solved.
  • the thin film transistor of the embodiment of the present disclosure can also solve the side edge oxidation problem of the gate electrode.
  • the gallium-containing oxide comprises at least one of the following materials: IGZO (indium gallium zinc oxide), GZO (Ga-doped ZnO, gallium-doped zinc oxide), IGO (Indium Gallium) Oxide, indium gallium oxide), gallium oxide or a combination thereof.
  • IGZO indium gallium zinc oxide
  • the gallium-containing oxide is oxygen deficient.
  • oxygen deficiency means that the oxygen content of the gallium-containing oxide is lower than the normal stoichiometric ratio.
  • the material of the active layer and the material of the cover layer may be the same. In this way, manufacturing costs can be saved.
  • the thin film transistor according to an embodiment of the present disclosure may further include a dielectric layer 4 disposed on the cover layer 303, wherein the dielectric layer 4 covers the exposed upper surface of the active layer 2 and the cover layer 303 Upper surface.
  • FIG. 3 is a schematic diagram of a thin film transistor in accordance with an embodiment of the present disclosure.
  • the thin film transistor according to an embodiment of the present disclosure may further include: a first contact portion C1 disposed on the dielectric layer 4 and a first hole V1 located in the dielectric layer 4, wherein the first contact Portion C1 is connected to the source/drain regions of the thin film transistor via the first hole V1.
  • the array substrate according to an embodiment of the present disclosure may further include: a first wiring W1 located in the dielectric layer 4, a second contact portion C2 disposed on the dielectric layer 4, and a dielectric layer 4 disposed on the dielectric layer 4.
  • This first wiring W1 has the same structure as the gate stack 3, and the top surface of the first wiring W1 is higher than the top surface of the active layer 2.
  • the second contact portion C2 is connected to the first wiring W1 via the second hole V2.
  • FIG. 5 is a schematic diagram of an array substrate in accordance with an embodiment of the present disclosure.
  • the array substrate according to an embodiment of the present disclosure may further include: a light shielding layer 5 disposed between the active layer 2 and the base substrate 1 to block light from entering under the active layer 2 An active layer 2; a second wiring W2 located in the same layer as the light shielding layer 5; a third contact portion C3 disposed on the dielectric layer 4; passing through the dielectric layer 4 and extending to the base substrate 1 The third hole V3 in the middle, wherein the third contact portion C3 is connected to the second wiring W2 via the third hole V3.
  • the second wiring W2 in FIG. 5 is merely exemplary and is not intended to limit the present disclosure.
  • FIG. 6 is a schematic diagram of an array substrate in accordance with an embodiment of the present disclosure.
  • the thin film transistor according to an embodiment of the present disclosure may further include: a buffer layer 6 disposed between the active layer 2 and the substrate 1 and a first contact C1 and a second contact The passivation layer 7 on the portion C2 and the third contact portion C3.
  • the buffer layer 6 covers the upper surface of the light shielding layer 5, the upper surface of the second wiring W2, and the exposed upper surface of the base substrate 1.
  • the material and thickness of each layer can be selected according to actual needs.
  • the base substrate 1 may include glass.
  • the light shielding layer 5 and the second wiring W2 may include a metal having a thickness ranging from about 50 to 400 nm (for example, 100 nm).
  • the thickness of the buffer layer 6 may range from about 100 to 500 nm (eg, about 300 nm).
  • the thickness of the active layer 2 may range from about 10 to 100 nm (for example, about 40 nm).
  • the gate insulating layer 301 may include silicon oxide (SiOx), and the gate insulating layer may have a thickness of about 100 to 500 nm (for example, about 150 nm).
  • the gate electrode 302 may comprise copper, which may range in thickness from about 50 to 1000 nm (eg, about 420 nm).
  • the dielectric layer 4 may also include silicon oxide (SiOx) having a thickness ranging from about 100 to 500 nm (e.g., about 300 nm).
  • the passivation layer 7 may include at least one of silicon oxide (SiOx) and silicon nitride (SiNx), and may have a thickness ranging from about 200 to 400 nm (for example, about 300 nm).
  • the first contact portion, the second contact portion, and the third contact portion may be formed by a sputtering method, and the first contact portion, the second contact portion, and the third contact portion may have a thickness ranging from 50 to 400 nm.
  • Another aspect of the present disclosure provides a method of fabricating a thin film transistor.
  • the description of the steps of the method herein is merely exemplary and does not represent a limitation of the order of the steps.
  • FIG. 7 is a flow chart showing a method of fabricating a thin film transistor according to an embodiment of the present disclosure. As shown in FIG. 7, a method of fabricating a thin film transistor according to an embodiment of the present disclosure includes:
  • the gate stack comprises: a gate insulating layer disposed on the active layer, a gate electrode disposed on the gate insulating layer, and a gate electrode disposed on the gate A cover layer on the electrode, and the cover layer is more likely to trap oxygen atoms than the gate electrode.
  • embodiments of the present disclosure are capable of solving the problem of oxidation of the gate electrode under the cap layer.
  • the cap layer 303 comprises a gallium-containing oxide.
  • Gallium-containing oxides have a stronger oxygen atom trapping ability than common gate electrodes. Since Ga-O has a large bond energy, Ga can better bind O, so that the oxidation problem of the gate electrode under the cap layer can be solved. For example, when the gate electrode includes copper, since O of the Ga-O-Cu interface is bound by Ga, the problem of Cu oxidation can be solved.
  • the thin film transistor of the embodiment of the present disclosure can also solve the side oxidation problem of the gate electrodes.
  • the gallium-containing oxide comprises at least one of the following materials: IGZO (indium gallium zinc oxide), GZO (Ga-doped ZnO, gallium-doped zinc oxide), IGO ( Indium Gallium Oxide, indium gallium oxide, gallium oxide or a combination thereof.
  • IGZO indium gallium zinc oxide
  • FIG. 8 is a flow diagram of a method of fabricating a gate stack in accordance with an embodiment of the present disclosure. As shown in FIG. 8, a method of fabricating a gate stack according to an embodiment of the present disclosure includes:
  • the method of fabricating a thin film transistor further includes plasma processing the upper surface of the cap layer and the upper surface of the active layer after patterning to form the gate stack.
  • the problem of oxidation of the gate electrode can be further solved by plasma treatment, which will be described in detail below.
  • the present disclosure also provides a method of fabricating an array substrate, including the method of fabricating a thin film transistor as described above.
  • FIG. 9 is a flow diagram of a method of fabricating an array substrate in accordance with an embodiment of the present disclosure. As shown in FIG. 9, the method for manufacturing an array substrate according to an embodiment of the present disclosure further includes:
  • FIG. 10 is a flow diagram of a method of fabricating an array substrate in accordance with an embodiment of the present disclosure. As shown in FIG. 10, the method of manufacturing a thin film transistor according to an embodiment of the present disclosure may further include:
  • 11(A)-11(K) are process flow diagrams of a method of fabricating an array substrate in accordance with an embodiment of the present disclosure.
  • a method of manufacturing a thin film transistor according to an embodiment of the present disclosure will be further described below with reference to FIG.
  • a method of manufacturing an array substrate includes forming a light shielding layer 5 and a second wiring W2 on a substrate 1, wherein a second wiring and a light shielding layer are simultaneously formed.
  • the metal layer may be deposited by sputtering or evaporation, and then the metal layer is patterned to form a light shielding layer and a second wiring.
  • the thickness of the metal layer may range from about 50 to 400 nm (eg, about 100 nm).
  • the method of manufacturing an array substrate according to an embodiment of the present disclosure further includes forming a buffer layer 6 on the light shielding layer and the second wiring.
  • the buffer layer 6 covers the upper surface of the light shielding layer 5, the upper surface of the second wiring W2, and the exposed upper surface of the base substrate 1.
  • a buffer layer may be deposited using PECVD (Plasma Enhanced Chemical Vapor Deposition). The thickness of the buffer layer may range from about 100 to 500 nm (eg, about 300 nm).
  • the method of manufacturing an array substrate according to an embodiment of the present disclosure further includes forming the active layer 2 on the buffer layer 6.
  • a semiconductor layer may be deposited on the buffer layer by sputtering, and then the semiconductor layer is patterned to form an active layer.
  • the thickness of the active layer 2 may range from about 10 to 100 nm (for example, about 40 nm).
  • the method of manufacturing an array substrate according to an embodiment of the present disclosure further includes forming an insulating material layer 301' on the active layer, the insulating material layer 301' covering the active layer The upper surface of 2 and the exposed upper surface of the buffer layer 6; a conductive layer 302' is formed on the insulating material layer 301'; and a cover material layer 303' is formed on the conductive layer 302'.
  • PECVD may be used to form the insulating material layer 301'.
  • the insulating material layer 301' may include silicon oxide (SiOx).
  • the thickness of the insulating material layer 301' may range from about 100 to 500 nm (e.g., about 150 nm).
  • a sputtering method may be employed to form a conductive layer 302' on the insulating material layer 301'.
  • Conductive layer 302' can comprise copper having a thickness ranging from about 50 to 1000 nm (e.g., about 420 nm).
  • the cover material layer 303' includes a gallium-containing oxide.
  • the gallium-containing oxide comprises at least one of the following materials: IGZO (indium gallium zinc oxide), GZO (Ga-doped ZnO, gallium-doped zinc oxide), IGO (Indium) Gallium Oxide, indium gallium oxide, gallium oxide or a combination thereof.
  • the method of fabricating the array substrate according to the embodiment of the present disclosure further includes patterning the conductive layer 302' and the cover material layer 303' to form the gate electrode 302 and the cover.
  • Layer 303 For example, the conductive layer 302' and the cover material layer 303' may be patterned by wet etching. Since the cover material layer 303' includes a gallium-containing oxide, the etching speed thereof is slower than the etching speed of the gate electrode below it, and thus the problem of oxidation of the side edge including the gate electrode such as copper can be solved.
  • the conductive layer 302' includes a material such as copper, the etching liquid for the conductive layer can also etch the etching including the gallium-containing oxide, and therefore, does not add an additional process burden.
  • the method of manufacturing an array substrate according to an embodiment of the present disclosure further includes patterning the insulating material layer 301' to form a gate insulating layer 301. It can be seen that, according to the method of manufacturing the thin film transistor of the embodiment of the present disclosure, the gate stack 3 and the first wiring W1 can be simultaneously formed.
  • the method of manufacturing an array substrate according to an embodiment of the present disclosure further includes plasma processing the upper surface of the cover layer and the upper surface of the active layer.
  • a plasma including at least one of the following materials may be applied: NH 3 , He, Ar, H 2 , and N 2 .
  • the method of manufacturing an array substrate according to an embodiment of the present disclosure further includes forming a dielectric layer 4 on the cover layer 303 and the first wiring W1.
  • the dielectric layer 4 covers the upper surface of the active layer 2 and the upper surface of the buffer layer 6 which is not covered by the active layer 2.
  • PECVD can be used to form the dielectric layer 4.
  • the dielectric layer 4 may also include silicon oxide (SiOx) having a thickness ranging from about 100 to 500 nm (e.g., about 300 nm).
  • SiOx silicon oxide
  • the use of a material such as a gallium-containing oxide as a cover layer can withstand higher temperatures, so that the deposition of the dielectric layer can be performed at a higher temperature to ensure the stability of the device.
  • the method of manufacturing an array substrate according to an embodiment of the present disclosure further includes: forming a first hole V1, a second hole V2, and a third hole V3 in the dielectric layer 4, wherein The first hole V1 reaches the upper surface of the active layer 2, the second hole V2 reaches the upper surface of the first wiring W1, the third hole V3 reaches the upper surface of the second wiring W2, and wherein the third hole V3 is formed once .
  • the cover layer of the embodiment of the present disclosure uses a material such as a gallium oxide-containing material to have better adhesion to the photoresist, thereby achieving a better etching effect.
  • the method of manufacturing an array substrate according to an embodiment of the present disclosure further includes forming a first contact portion C1, a second contact portion C2, and a third contact portion on the dielectric layer 4. C3, wherein the first contact portion C1 is connected to the source/drain region via the first hole C1, the second contact portion C2 is connected to the first wire W1 via the second hole V2, and the third contact portion C3 is via the third hole V3 Connected to the second wiring W2.
  • the first hole C1, the second hole C2, and the third hole C3 may be filled by sputtering metal and cover the dielectric layer 4, and then patterned to form the first contact portion C1, the second contact portion C2, and the third contact. Department C3.
  • the thickness of the first contact portion, the second contact portion, and the third contact portion may range from 50 to 400 nm.
  • the method of manufacturing the thin array substrate according to the embodiment of the present disclosure further includes forming blunt on the first contact portion C1, the second contact portion C2, and the third contact portion C3. Layer.
  • the passivation layer 7 also covers the exposed surface of the dielectric layer 4.
  • PECVD can be used to deposit the passivation layer 7.
  • the passivation layer 7 may include at least one of silicon oxide (SiOx) and silicon nitride (SiNx), and may have a thickness ranging from about 200 to 400 nm (for example, about 300 nm).
  • Embodiments of the present disclosure also provide a method of fabricating a display device.
  • the display device in the embodiment of the present disclosure includes the array substrate as described above.
  • the display device in the embodiment of the present disclosure may be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a notebook computer, a digital photo frame, a navigator, and the like.

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Abstract

一种薄膜晶体管及其制造方法、阵列基板及其制造方法以及显示装置。薄膜晶体管包括：设置在衬底基板（1）上的有源层（2）和设置在有源层（2）上的栅极叠层（3），其中，栅极叠层（3）为从下到上依次层叠的栅极绝缘层（301）、栅极电极（302）和覆盖层（303），覆盖层（303）比栅极电极（302）更容易捕获氧原子，从而解决覆盖层（303）下的栅极电极（302）的氧化问题。覆盖层（303）可为含镓的氧化物，如为IGZO、GZO、IGO、氧化镓，或其组合，含镓的氧化物可进一步为氧缺乏的。

Description

薄膜晶体管及其制造方法、阵列基板以及显示装置
相关申请的交叉引用
本申请要求于2017年05月11日递交的中国专利申请第201710330483.5号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开文本涉及显示技术领域。更具体地，涉及一种薄膜晶体管及其制造方法、阵列基板以及显示装置。
背景技术
薄膜晶体管是驱动电路的重要组成器件，其在显示装置中被广泛应用。氧化物晶体管技术作为现阶段的一个技术热点具有迁移率高、均匀性好等特点，受到人们的广泛关注。然而，在现有技术中，对于薄膜晶体管，还存在一些工艺难点需要解决。
发明内容
本公开文本的实施例提供一种薄膜晶体管及其制造方法、阵列基板以及显示装置。
本公开文本的第一方面提供了一种薄膜晶体管。所述薄膜晶体管包括：设置在衬底基板上的有源层；设置在所述有源层上的栅极叠层，其中，所述栅极叠层包括：设置在所述有源层上的栅极绝缘层；设置在所述栅极绝缘层上的栅极电极；设置在所述栅极电极上的覆盖层，所述覆盖层比所述栅极电极更容易捕获氧原子。
在一个实施例中，所述覆盖层包括含镓氧化物。
在一个实施例中，所述含镓氧化物包括下列材料的至少一种：IGZO、GZO、IGO、氧化镓或其组合。
在一个实施例中，所述含镓氧化物是氧缺乏的。
在一个实施例中，所述覆盖层的材料和所述有源层的材料相同。
在一个实施例中，所述薄膜晶体管还包括：设置在所述覆盖层上的介质层，其中，所述介质层覆盖所述有源层的上表面。
在一个实施例中，所述薄膜晶体管还包括：设置在所述介质层上的第一接触部；以及位于所述介质层中的第一孔，其中，所述第一接触经由所述过第一孔连接到薄膜晶体管的源/漏极区域。
本公开文本的第二方面提供了一种阵列基板。所述阵列基板包括如上所述的薄膜晶体管。
在一个实施例中，所述阵列基板还包括：位于所述介质层中的第一布线，所述第一布线具有与所述栅极叠层相同的结构，所述第一布线的顶表面高于所述有源层的顶表面；设置在所述介质层上的第二接触部；设置在所述介质层中的第二孔，其中，所述第二接触部经由所述第二孔连接到所述第一布线。
在一个实施例中，所述阵列基板还包括：设置在所述有源层和所述衬底基板之间的遮光层，以阻挡来自所述有源层下方的光进入所述有源层；第二布线，所述第二布线与所述遮光层位于同一层；设置在所述介质层上的第三接触部；穿过所述介质层且延伸到所述衬底基板中的第三孔，其中，所述第三接触部经由所述过第三孔连接到所述第二布线。
在一个实施例中，所述阵列基板还包括：设置在所述有源层和所述衬底基板之间的缓冲层，其中，所述缓冲层覆盖所述遮光层的上表面、所述第二布线的上表面和所述衬底基板的暴露的上表面；设置在第一接触部、第二接触部和第三接触部上的钝化层。
本公开文本的第三方面提供了一种显示装置。所述显示装置包括如上所述的阵列基板。
本公开文本的第四方面提供了一种薄膜晶体管的制造方法。所述薄膜晶体管的制造方法包括：在衬底基板上形成有源层；在所述有源层上形成栅极叠层，其中，所述栅极叠层包括：设置在所述有源层上的栅极绝缘层； 设置在所述栅极绝缘层上的栅极电极；设置在所述栅极电极上的覆盖层，所述覆盖层比所述栅极电极更容易捕获氧原子。
在一个实施例中，所述覆盖层包括含镓氧化物。
在一个实施例中，所述含镓氧化物包括下列材料的至少一种：IGZO、GZO、IGO、氧化镓或其组合。
在一个实施例中，形成所述栅极叠层包括：在所述有源层上形成绝缘材料层；在所述绝缘材料层上形成导电层；在所述导电层上形成覆盖材料层；进行构图，以形成所述栅极叠层。
本公开文本的第五方面提供了一种阵列基板的制造方法。所述阵列基板的制造方法包括如上所述的薄膜晶体管的制造方法。
在一个实施例中，所述阵列基板的制造方法还包括：在形成所述有源层之前，在所述衬底基板上形成遮光层和第二布线，其中，第二布线和遮光层被同时形成，所述遮光层能够阻挡来自所述有源层下方的光进入所述有源层；在形成所述有源层之后，在所述衬底基板上形成第一布线，其中，所述第一布线与所述栅极叠层被同时形成，并且所述第一布线具有与所述栅极叠层相同的结构；形成所述栅极叠层之后且形成所述介质层之前，对所述覆盖层的上表面和所述有源层的上表面进行等离子体处理。
在一个实施例中，所述阵列基板的制造方法进一步包括：在形成所述遮光层和所述第二布线之后且在形成所述有源层之前，在所述遮光层上形成缓冲层，其中，所述缓冲层覆盖所述遮光层的上表面、所述第二布线的上表面和所述衬底基板的暴露上表面；
在形成所述栅极叠层和所述第一布线之后，在所述覆盖层和所述第一布线上形成介质层，其中，所述介质层覆盖所述有源层的上表面以及所述缓冲层的未被所述有源层覆盖的上表面；
在所述介质层中形成第一孔、第二孔和第三孔，其中，所述第一孔到达所述有源层的上表面，所述第二孔到达所述第一布线的上表面，所述第三孔到达所述第二布线的上表面，并且其中，所述第三孔被一次形成；
在所述介质层上形成第一接触部、第二接触部和第三接触部，其中， 所述第一接触部经由所述过第一孔连接到薄膜晶体管的源/漏极区域，所述第二接触部经由所述第二孔连接到所述第一布线，所述第三接触部经由所述第三孔连接到所述第二布线；
在所述第一接触部、第二接触部和第三接触部上形成钝化层。
附图说明
为了更清楚地说明本公开文本的实施例的技术方案，下面将对实施例的附图进行简要说明，应当知道，以下描述的附图仅仅涉及本公开文本的一些实施例，而非对本公开文本的限制，其中：
图1为根据本公开文本的一个实施例的薄膜晶体管的示意图；
图2为根据本公开文本的一个实施例的薄膜晶体管的示意图；
图3为根据本公开文本的一个实施例的薄膜晶体管的示意图；
图4为根据本公开文本的一个实施例的薄膜晶体管的示意图；
图5为根据本公开文本的一个实施例的薄膜晶体管的示意图；
图6为根据本公开文本的一个实施例的薄膜晶体管的示意图；
图7为根据本公开文本的一个实施例的薄膜晶体管的制造方法的流程示意图；
图8为根据本公开文本的一个实施例的栅极叠层的制造方法的流程示意图；
图9为根据本公开文本的一个实施例的阵列基板的制造方法的流程示意图；
图10为根据本公开文本的一个实施例的阵列基板的制造方法的流程示意图；
图11(A)-11(K)为根据本公开文本的一个实施例的阵列基板的制造方法的工艺流程图。
具体实施方式
为了使本公开文本的实施例的目的、技术方案和优点更加清楚，下面 将接合附图，对本公开文本的实施例的技术方案进行清楚、完整的描述。显然，所描述的实施例是本公开文本的一部分实施例，而不是全部的实施例。基于所描述的本公开文本的实施例，本领域技术人员在无需创造性劳动的前提下所获得的所有其他实施例，也都属于本公开文本保护的范围。
当介绍本公开文本的元素及其实施例时，除非上下文中另外明确地指出，否则在本文和所附权利要求中所使用的词语的单数形式包括复数，反之亦然。因而，当提及单数时，通常包括相应术语的复数。冠词“一”、“一个”、“该”和“所述”旨在表示存在一个或者多个要素。用语“包含”、“包括”、“含有”和“具有”旨在包括性的并且表示可以存在除所列要素之外的另外的要素。
出于下文表面描述的目的，如其在附图中被标定方向那样，术语“上”、“下”、“左”、“右”“垂直”、“水平”、“顶”、“底”及其派生词应涉及公开文本。术语“上覆”、“在……顶上”、“定位在……上”或者“定位在……顶上”意味着诸如第一结构的第一要素存在于诸如第二结构的第二要素上，其中，在第一要素和第二要素之间可存在诸如界面结构的中间要素。术语“接触”意味着连接诸如第一结构的第一要素和诸如第二结构的第二要素，而在两个要素的界面处可以有或者没有其它要素。
本公开文本的一个方面提供了一种薄膜晶体管。图1为根据本公开文本的一个实施例的薄膜晶体管的示意图。如图1所示，根据本公开文本的一个实施例的薄膜晶体管包括衬底基板1、设置在衬底基板1上的有源层2；设置在所述有源层上的栅极叠层3。从图1还可以看出，该栅极叠层3包括：设置在所述有源层2上的栅极绝缘层301、设置在栅极绝缘层301上的栅极电极302、设置在栅极电极302上的覆盖层303。该覆盖层303比栅极电极302更容易捕获氧原子。可以理解，在图1所示出的实施例中，栅极绝缘层301限定栅极区域以及位于栅极区域两侧的源/漏极区域。
由于在本公开文本的实施例中，覆盖层比栅极电极更容易捕获氧原子，因此，本公开文本的实施例能够解决覆盖层下的栅极电极的氧化的问题。这里的“覆盖层比栅极电极更容易捕获氧原子”是指与栅极电极的材料相比， 覆盖层的材料更易于结合并固定氧原子。从而，能够解决覆盖层下的栅极电极的氧化的问题。
在一种实施方式中，该覆盖层303包括含镓氧化物。含镓氧化物比常见的栅极电极具有更强的氧原子捕获能力。由于Ga-O具有大的键能，Ga可以更好的束缚O，从而能够解决覆盖层下的栅极电极的氧化问题。例如，当栅极电极包括铜时，由于Ga-O-Cu界面的O会被Ga束缚，所以能够解决Cu氧化的问题。
此外，由于在制备过程中，经常需要对覆盖层和栅极电极进行刻蚀，而含镓氧化物的刻蚀速度比其下方的栅极电极的刻蚀速度要慢。因此，本公开文本的实施例的薄膜晶体管还可以解决栅极电极的侧边缘氧化问题。
在一个实施例中，含镓氧化物包括下列材料的至少一种：IGZO(indium gallium zinc oxide，铟镓锌氧化物)、GZO(Ga-doped ZnO，镓掺杂氧化锌)、IGO(Indium Gallium Oxide，氧化铟镓)、氧化镓或其组合。在一个实施例中，对于含镓氧化物包括铟镓锌氧化物(IGZO)的情况，可以将其中的铟镓锌的原子比例设置为In：Ga：Zn＝2：2：1，也可以根据需要来将原子比设置为In：Ga：Zn＝1：1：4。
在一种实施方式中，含镓氧化物是氧缺乏的。这里的“氧缺乏”是指其氧含量比正常的化学计量比时的含镓氧化物的氧含量低。
在一个实施例中，有源层的材料和覆盖层的材料可以相同。通过这样的方式可以节约制造成本。
图2为根据本公开文本的一个实施例的薄膜晶体管的示意图。如图2所示，根据本公开文本的一个实施例的薄膜晶体管还可以包括设置在覆盖层303上的介质层4，其中，介质层4覆盖有源层2的暴露的上表面和覆盖层303的上表面。
图3为根据本公开文本的一个实施例的薄膜晶体管的示意图。如图3所示，根据本公开文本的一个实施例的薄膜晶体管还可以包括：设置在介质层4上的第一接触部C1以及位于介质层4中的第一孔V1，其中，第一接触部C1经由第一孔V1连接到薄膜晶体管的源/漏极区域。
图4为根据本公开文本的一个实施例的阵列基板的示意图。如图4所示，根据本公开文本的一个实施例的阵列基板还可以包括：位于介质层4中的第一布线W1、设置在介质层4上的第二接触部C2和设置在介质层4中的第二孔V2。该第一布线W1具有与栅极叠层3相同的结构，并且第一布线W1的顶表面高于有源层2的顶表面。第二接触部C2经由第二孔V2连接到所述第一布线W1。
图5为根据本公开文本的一个实施例的阵列基板的示意图。如图5所示，根据本公开文本的一个实施例的阵列基板还可以包括：设置在有源层2和衬底基板1之间的遮光层5，以阻挡来自有源层2下方的光进入有源层2；第二布线W2，该第二布线W2与遮光层5位于同一层；设置在介质层4上的第三接触部C3；穿过介质层4且延伸到所述衬底基板1中的第三孔V3，其中，第三接触部C3经由第三孔V3连接到第二布线W2。需要指出，图5中的第二布线W2仅是示例性的，而非对本公开文本的限制。
图6为根据本公开文本的一个实施例的阵列基板的示意图。如图6所示，根据本公开文本的一个实施例的薄膜晶体管还可以包括：设置在有源层2和衬底基板1之间的缓冲层6以及设置在第一接触部C1、第二接触部C2和第三接触部C3上的钝化层7。其中，该缓冲层6覆盖遮光层5的上表面、第二布线W2的上表面和衬底基板1的暴露的上表面。
可以根据实际需要来选择各层的材质和厚度。衬底基板1可以包括玻璃。遮光层5和第二布线W2可以包括金属，其厚度范围可以为约50～400nm(例如，100nm)。缓冲层6的厚度范围可以为约100～500nm(例如，约300nm)。有源层2的厚度范围可以为约10～100nm(例如，约40nm)。栅极绝缘层301可以包括硅氧化物(SiOx)，栅极绝缘层的厚度可以为约100～500nm(例如，约150nm)。栅极电极302可以包括铜，其厚度范围可以为约50～1000nm(例如，约420nm)。介质层4也可以包括硅氧化物(SiOx)，其厚度范围可以为约100～500nm(例如，约300nm)。钝化层7可以包括硅氧化物(SiOx)和硅氮化物(SiNx)中的至少一种，其厚度范围可以为约200～400nm(例如，约300nm)。可以采用溅射法来形成第一 接触部、第二接触部和第三接触部，第一接触部、第二接触部和第三接触部的厚度范围可以为50～400nm。
本公开文本的另一方面提供了一种薄膜晶体管的制造方法。以下将结合不同实施例进行说明，需要指出，本文中的方法的步骤的标号仅仅是示例性的，并不代表着对步骤先后顺序的限制。
图7为根据本公开文本的一个实施例的薄膜晶体管的制造方法的流程示意图。如图7所示，根据本公开文本的一个实施例的薄膜晶体管的制造方法包括：
S1、在衬底基板上形成有源层；
S3、在有源层上形成栅极叠层，其中，该栅极叠层包括：设置在有源层上的栅极绝缘层、设置在栅极绝缘层上的栅极电极以及设置在栅极电极上的覆盖层，并且该覆盖层比所述栅极电极更容易捕获氧原子。
由于在本公开文本的实施例中，覆盖层比栅极电极更容易捕获氧原子，因此，本公开文本的实施例能够解决覆盖层下的栅极电极的氧化的问题。
在一种实施方式中，该覆盖层303包括含镓氧化物。含镓氧化物比常见的栅极电极具有更强的氧原子捕获能力。由于Ga-O具有大的键能，Ga可以更好的束缚O，从而能够解决覆盖层下的栅极电极的氧化问题。例如，当栅极电极包括铜时，由于Ga-O-Cu界面的O会被Ga束缚，所以能够解决Cu氧化的问题。
此外，由于在制备过程中，经常需要对覆盖层和栅极电极进行刻蚀，而含镓氧化物的刻蚀速度比其下方的栅极电极的刻蚀速度要慢。因此，本公开文本的实施例的薄膜晶体管还可以解决诸栅极电极的侧面氧化问题。
在一个实施例中，所述含镓氧化物包括下列材料的至少一种：IGZO(indium gallium zinc oxide，铟镓锌氧化物)、GZO(Ga-doped ZnO，镓掺杂氧化锌)、IGO(Indium Gallium Oxide，氧化铟镓)、氧化镓或其组合。在一个实施例中，对于含镓氧化物包括铟镓锌氧化物(IGZO)的情况，可以将其中的铟镓锌的原子比例设置为In：Ga：Zn＝2：2：1，也可以根据需要来将原子比设置为In：Ga：Zn＝1：1：4。
图8为根据本公开文本的一个实施例的栅极叠层的制造方法的流程示意图。如图8所示，根据本公开文本的一个实施例的栅极叠层的制造方法包括：
S301、在有源层上形成绝缘材料层；
S302、在绝缘材料层上形成导电层；
S303、在导电层上形成覆盖材料层；
S304、进行构图，以形成栅极叠层。
在一个实施例中，薄膜晶体管的制造方法还包括在进行构图以形成栅极叠层之后，对覆盖层的上表面和有源层的上表面进行等离子体处理。通过等离子体处理能够进一步解决栅极电极被氧化的问题，下文将对此予以详细描述。
本公开文本还提供了一种阵列基板的制造方法，包括如上所述的薄膜晶体管的制造方法。
图9为根据本公开文本的一个实施例的阵列基板的制造方法的流程示意图。如图9所示，根据本公开文本的一个实施例的阵列基板的制造方法还包括：
S2、在形成有源层之前，在所述衬底基板上形成遮光层和第二布线。其中，第二布线和遮光层被同时形成，遮光层能够阻挡来自所述有源层下方的光进入所述有源层；
S5、在形成有源层之后，在衬底基板上形成第一布线，其中，该第一布线与栅极叠层被同时形成，并且第一布线具有与栅极叠层相同的结构。
图10为根据本公开文本的一个实施例的阵列基板的制造方法的流程示意图。如图10所示，根据本公开文本的实施例的薄膜晶体管的制造方法还可以进一步包括：
S4、在形成遮光层和第二布线之后且在形成有源层之前，在遮光层上形成缓冲层，其中，缓冲层覆盖遮光层的上表面、第二布线的上表面和衬底基板的暴露上表面；
S6、在形成栅极叠层和第一布线之后，在覆盖层和第一布线上形成介 质层，其中，介质层的覆盖有源层的上表面以及缓冲层的未被有源层覆盖的上表面；
S7、在介质层中形成第一孔、第二孔和第三孔，其中，第一孔到达有源层的上表面，第二孔到达第一布线的上表面，第三孔到达第二布线的上表面，并且其中，第三孔被一次形成；
S8、在介质层上形成第一接触部、第二接触部和第三接触部，其中，第一接触部经由第一孔连接到源/漏极区域，第二接触部经由第二孔连接到第一布线，第三接触部经由第三孔连接到第二布线；
S9、在第一接触部、第二接触部和第三接触部上形成钝化层。
图11(A)-11(K)为根据本公开文本的一个实施例的阵列基板的制造方法的工艺流程图。下面将结合图11对根据本公开文本的一个实施例的薄膜晶体管的制造方法做进一步说明。
如图11(A)所示，根据本公开文本的实施例的阵列基板的制造方法包括：在衬底1上形成遮光层5和第二布线W2，其中第二布线和遮光层被同时形成。在一种实施方式中，可以采用溅射或者蒸镀方法沉积金属层，然后对金属层进行构图，以形成遮光层和第二布线。金属层的厚度范围可以为约50～400nm(例如，约100nm)。
进一步地，如图11(B)所示，根据本公开文本的实施例的阵列基板的制造方法还包括：在遮光层和第二布线上形成缓冲层6。该缓冲层6覆盖遮光层5的上表面、第二布线W2的上表面和衬底基板1的暴露上表面。在一种实施方式中，可以采用PECVD(Plasma Enhanced Chemical Vapor Deposition，等离子体增强化学气相沉积法)来沉积缓冲层。缓冲层的厚度范围可以为约100～500nm(例如，约300nm)。
进一步地，如图11(C)所示，根据本公开文本的实施例的阵列基板的制造方法还包括：在缓冲层6上形成有源层2。在一种实施方式中，可以采用溅射法在缓冲层上沉积半导体层，然后对半导体层进行构图，以形成有源层。有源层2的厚度范围可以为约10～100nm(例如，约40nm)。
进一步地，如图11(D)所示，根据本公开文本的实施例的阵列基板 的制造方法还包括：在有源层上形成绝缘材料层301’，该绝缘材料层301’覆盖有源层2的上表面和缓冲层6的暴露的上表面；在绝缘材料层301’上形成导电层302’；在导电层302’上形成覆盖材料层303’。
在一种实施方式中，可以采用PECVD来形成绝缘材料层301’。绝缘材料层301’可以包括硅氧化物(SiOx)。绝缘材料层301’的厚度范围可以为约100～500nm(例如，约150nm)。在一种实施方式中，可以采用溅射法来在绝缘材料层301’上形成导电层302’。导电层302’可以包括铜，其厚度范围可以为约50～1000nm(例如，约420nm)。覆盖材料层303’包括含镓氧化物。在一种实施方式中，含镓氧化物包括下列材料的至少一种：IGZO(indium gallium zinc oxide，铟镓锌氧化物)、GZO(Ga-doped ZnO，镓掺杂氧化锌)、IGO(Indium Gallium Oxide，氧化铟镓)、氧化镓或其组合。
进一步地，如图11(E)所示，根据本公开文本的实施例的阵列基板的制造方法还包括：对导电层302’和覆盖材料层303’进行构图，以形成栅极电极302和覆盖层303。例如，可以采用湿法刻蚀来对导电层302’和覆盖材料层303’进行构图。由于覆盖材料层303’包括含镓氧化物，其刻蚀速度比其下方的栅极电极的刻蚀速度要慢，因此能够解决包括诸如铜的栅极电极的侧边缘氧化的问题。当导电层302’包括诸如铜的材料时，用于导电层的刻蚀液也能够刻蚀包括含镓氧化物的刻蚀，因此，不会增加额外的工艺负担。
进一步地，如图11(F)所示，根据本公开文本的实施例的阵列基板的制造方法还包括：对绝缘材料层301’进行构图，以形成栅极绝缘层301。可以看出，根据本公开文本的实施例的薄膜晶体管的制造方法，能够同时形成栅极叠层3和第一布线W1。
进一步地，如图11(G)所示，根据本公开文本的实施例的阵列基板的制造方法还包括：对覆盖层的上表面和所述有源层的上表面进行等离子体处理。例如，可以施加包括下列材料的至少一种的等离子体：NH 3、He、Ar、H 2和N 2。通过施加等离子体处理，可以使得覆盖层和有源层的未被 栅极电极覆盖的区域失氧并且被导体化。由于施加了等离子体造成了氧缺乏，这样导致氧原子更不容易扩散，从而能够进一步解决栅极电极被氧化的问题。
进一步地，如图11(H)所示，根据本公开文本的实施例的阵列基板的制造方法还包括：在覆盖层303和第一布线W1上形成介质层4。介质层4覆盖与有源层2的上表面和缓冲层6的未被有源层2覆盖的上表面。例如，可以采用PECVD来形成介质层4。介质层4也可以包括硅氧化物(SiOx)，其厚度范围可以为约100～500nm(例如，约300nm)。采用的诸如含镓氧化物的材料作覆盖层能够承受较高的温度，从而可以在较高温度下进行介质层的沉积，能够保证器件的稳定性。
进一步地，如图11(I)所示，根据本公开文本的实施例的阵列基板的制造方法还包括：在介质层4中形成第一孔V1、第二孔V2和第三孔V3，其中，第一孔V1到达有源层2的上表面，第二孔V2到达第一布线W1的上表面，第三孔V3到达第二布线W2的上表面，并且其中，第三孔V3被一次形成。
在现有技术中，由于第三孔V3的深度比第一孔V1的深度更深，为了避免对第一孔V1过刻蚀而损伤第一孔之下的结构，需要进行两次刻蚀来形成第三孔。而在本公开文本的实施例中，覆盖层的材料更耐刻蚀，其刻蚀速度较慢。因此，可以仅进行一次刻蚀来形成第三孔，而无需担心刻蚀会损伤覆盖层之下的栅极电极。相比于传统的Mo基金属材料，本公开文本的实施例的覆盖层所采用的诸如含镓氧化物的材料与光刻胶的粘附力更好，从而能实现更好的刻蚀效果。
进一步地，如图11(J)所示，根据本公开文本的实施例的阵列基板的制造方法还包括：在介质层4上形成第一接触部C1、第二接触部C2和第三接触部C3，其中，第一接触部C1经由第一孔C1连接到源/漏极区域，第二接触部C2经由过第二孔V2连接到第一布线W1，第三接触部C3经由第三孔V3连接到第二布线W2。例如，可以通过溅射金属来填充第一孔C1、第二孔C2和第三孔C3并且覆盖介质层4，然后进行构图，以形成第 一接触部C1、第二接触部C2和第三接触部C3。第一接触部、第二接触部和第三接触部的厚度范围可以为50～400nm。
进一步地，如图11(K)所示，根据本公开文本的实施例的薄阵列基板的制造方法还包括：在第一接触部C1、第二接触部C2和第三接触部C3上形成钝化层。可以看出，钝化层7还覆盖了介质层4的暴露的表面。例如，可以采用PECVD来沉积钝化层7。钝化层7可以包括硅氧化物(SiOx)和硅氮化物(SiNx)中的至少一种，其厚度范围可以为约200～400nm(例如，约300nm)。
本公开文本的实施例还提供了显示装置的制造方法。本公开文本的实施例中的显示装置包括如上所述的阵列基板。本公开文本的实施例中的显示装置可以为：手机、平板电脑、电视机、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
已经描述了某特定实施例，这些实施例仅通过举例的方式展现，而且不旨在限制本公开文本的范围。事实上，本文所描述的新颖实施例可以以各种其它形式来实施；此外，可在不脱离本公开文本的精神下，做出以本文所描述的实施例的形式的各种省略、替代和改变。所附权利要求以及它们的等价物旨在覆盖落在本公开文本范围和精神内的此类形式或者修改。

Claims (17)

  1. 一种薄膜晶体管，包括：设置在衬底基板上的有源层和设置在所述有源层上的栅极叠层，其中，所述栅极叠层包括：
    设置在所述有源层上的栅极绝缘层；
    设置在所述栅极绝缘层上的栅极电极；
    设置在所述栅极电极上的覆盖层，所述覆盖层比所述栅极电极更容易捕获氧原子。
  2. 根据权利要求1所述的薄膜晶体管，其中，所述覆盖层包括含镓氧化物。
  3. 根据权利要求2所述的薄膜晶体管，其中，所述含镓氧化物包括下列材料的至少一种：IGZO、GZO、IGO、氧化镓、或其组合。
  4. 根据权利要求3所述的薄膜晶体管，其中，所述含镓氧化物是氧缺乏的。
  5. 根据权利要求1-4中任一项所述的薄膜晶体管，其中，所述覆盖层的材料和所述有源层的材料相同。
  6. 根据权利要求1-4中任一项所述的薄膜晶体管，其中，所述薄膜晶体管还包括：设置在所述覆盖层上的介质层，其中，所述介质层覆盖所述有源层的上表面。
  7. 根据权利要求6所述的薄膜晶体管，其中，所述薄膜晶体管还包括：
    设置在所述介质层上的第一接触部；
    以及位于所述介质层中的第一孔，
    其中，所述第一接触部经由所述第一孔连接到薄膜晶体管的源/漏极区域。
  8. 一种阵列基板，包括根据权利要求1-7中任一项所述的薄膜晶体管。
  9. 根据权利要求8所述的阵列基板，其中，所述阵列基板还包括：
    位于所述介质层中的第一布线，所述第一布线具有与所述栅极叠层相同的结构，所述第一布线的顶表面高于所述有源层的顶表面；
    设置在所述介质层上的第二接触部；
    设置在所述介质层中的第二孔，
    其中，所述第二接触部经由所述第二孔连接到所述第一布线。
  10. 根据权利要求9所述的阵列基板，其中，所述阵列基板还包括：
    设置在所述有源层和所述衬底基板之间的遮光层，以阻挡来自所述有源层下方的光进入所述有源层；
    第二布线，所述第二布线与所述遮光层位于同一层；
    设置在所述介质层上的第三接触部；
    穿过所述介质层且延伸到所述衬底基板中的第三孔，
    其中，所述第三接触部经由所述过第三孔连接到所述第二布线。
  11. 根据权利要求10所述的阵列基板，其中，所述阵列基板还包括：设置在所述有源层和所述衬底基板之间的缓冲层，
    其中，所述缓冲层覆盖所述遮光层的上表面、所述第二布线的上表面和所述衬底基板的上表面；
    设置在第一接触部、第二接触部和第三接触部上的钝化层。
  12. 一种显示装置，包括根据权利要求8-11中任一项所述的阵列基板。
  13. 一种薄膜晶体管的制造方法，包括：
    在衬底基板上形成有源层；
    在所述有源层上形成栅极叠层，
    其中，所述栅极叠层包括：
    设置在所述有源层上的栅极绝缘层；
    设置在所述栅极绝缘层上的栅极电极；
    设置在所述栅极电极上的覆盖层，所述覆盖层比所述栅极电极更容易捕获氧原子。
  14. 根据权利要求13所述的薄膜晶体管的制造方法，其中，所述覆盖层包括含镓氧化物。
  15. 根据权利要求14所述的薄膜晶体管的制造方法，其中，所述含镓氧化物包括下列材料的至少一种：IGZO，GZO，IGO，氧化镓或其组合形成所述栅极叠层包括：
    在所述有源层上形成绝缘材料层；
    在所述绝缘材料层上形成导电层；
    在所述导电层上形成覆盖材料层；
    进行构图，以形成所述栅极叠层。
  16. 一种阵列基板的制造方法，包括根据权利要求13-15中任一项所述的薄膜晶体管的制造方法。
  17. 根据权利要求16所述的阵列基板的制造方法，进一步包括：
    在形成所述有源层之前，在所述衬底基板上形成遮光层和第二布线，其中，第二布线和遮光层被同时形成，所述遮光层能够阻挡来自所述有源层下方的光进入所述有源层；
    在形成所述有源层之后，在所述衬底基板上形成第一布线，其中，所述第一布线与所述栅极叠层被同时形成，并且所述第一布线具有与所述栅极叠层相同的结构；
    在形成所述栅极叠层之后且形成所述介质层之前，对所述覆盖层的上表面和所述有源层的上表面进行等离子体处理。
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