WO2018205398A1 - 像素驱动电路、驱动方法及显示装置 - Google Patents

像素驱动电路、驱动方法及显示装置 Download PDF

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Publication number
WO2018205398A1
WO2018205398A1 PCT/CN2017/091678 CN2017091678W WO2018205398A1 WO 2018205398 A1 WO2018205398 A1 WO 2018205398A1 CN 2017091678 W CN2017091678 W CN 2017091678W WO 2018205398 A1 WO2018205398 A1 WO 2018205398A1
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Prior art keywords
pixel
sub
pixels
data line
column
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PCT/CN2017/091678
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English (en)
French (fr)
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陈猷仁
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惠科股份有限公司
重庆惠科金渝光电科技有限公司
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Priority to US16/612,098 priority Critical patent/US10971105B2/en
Publication of WO2018205398A1 publication Critical patent/WO2018205398A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3614—Control of polarity reversal in general
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3607—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals for displaying colours or for displaying grey scales with a specific pixel layout, e.g. using sub-pixels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0452—Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0254—Control of polarity reversal in general, other than for liquid crystal displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving

Definitions

  • the present application relates to the field of display technologies, and in particular, to a pixel driving circuit, a driving method, and a display device.
  • the source voltage signal needs to be converted in polarity within one frame, so that the power consumption of the source IC is significantly increased.
  • the IC temperature also rises when the image surface is displayed, resulting in deterioration of the reliability quality.
  • a pixel driving circuit includes a pixel array, a data line, and a scan line.
  • the pixel array includes a plurality of pixel units having four sub-pixels of different colors, and all of the sub-pixels exhibit a dot-reverse arrangement of positive and negative polarities with each other; the data lines and scan lines are orthogonally arranged in the pixel array.
  • the sub-pixels have opposite polarities.
  • a pixel driving method suitable for the above pixel driving circuit includes:
  • each column of data lines When two scan line driving voltage signals of one row of pixels are simultaneously input, each column of data lines writes a voltage signal to two sub-pixels, and the two sub-pixels are located on both sides of the data line, and are arranged in phase;
  • a display device comprising:
  • the source driving chip is configured to output a plurality of data lines, and the data lines are connected to the display panel and arranged in a column inversion between the positive and negative polarities.
  • the gate driving chip is configured to output a plurality of scan lines, the scan lines are connected to the display panel, and each of the two groups drives a row of pixel units.
  • the display panel is divided into a plurality of pixel groups by a data line and a scan line, each pixel group has two sub-pixels of different colors and opposite polarities; the sub-pixels are arranged side by side and in two adjacent pixel groups
  • the sub-pixels include white, red, green, and blue colors.
  • the pixel driving circuit and the display panel use the HSD pixel wiring design technology to reduce the number of source ICs used and save cost; and the dot polarity inversion pixel polarity arrangement method improves the screen display quality. More importantly, the HSD wiring design technology and the dot-reversed pixel polarity arrangement make the source voltage signal do not need to be switched in polarity within one frame, thereby reducing the power consumption of the entire panel and the temperature of the source IC. Improve the quality of trust.
  • FIG. 1 is a schematic structural diagram of a pixel driving circuit of an embodiment
  • FIG. 2 is a schematic structural diagram of a pixel unit according to an embodiment
  • FIG. 3 is a schematic diagram of sub-pixel wiring in a pixel unit according to an embodiment
  • FIG. 4 is a schematic diagram of sub-pixel wiring in a pixel unit of another embodiment
  • FIG. 5 is a schematic diagram of sub-pixel wiring in a pixel unit of another embodiment
  • FIG. 6 is a schematic diagram of sub-pixel wiring in a pixel unit of another embodiment
  • FIG. 7 is a schematic diagram of sub-pixel wiring in a pixel unit of another embodiment
  • FIG. 8 is a schematic diagram of sub-pixel wiring in a pixel unit of another embodiment
  • FIG. 9 is a flow chart of a pixel driving method according to an embodiment
  • FIG. 10 is a schematic structural view of a display panel according to an embodiment
  • FIG. 11 is a schematic structural view of a display panel of another embodiment.
  • FIG. 1 is a schematic structural diagram of a pixel driving circuit of an embodiment, which includes a pixel array 100, and a plurality of data lines S1, S2, S3, ..., S7, ... extending from the source driving chip 200.
  • the pixel array 100 includes a plurality of pixel units 110 having four sub-pixels of different colors, and all of the sub-pixels exhibit a dot-reverse arrangement of positive and negative polarities with each other, that is, each sub-pixel is adjacent to any of the adjacent pixels.
  • the sub-pixels have opposite polarities.
  • the data lines and the scan lines are orthogonally arranged in the pixel array, and two rows of pixel units 110 are arranged for each row.
  • Scan lines for example, the first row of pixel unit configuration scan lines G1, G2; each column of pixel units 110 is provided with two data lines, such as the first column of pixel unit configuration data S1, S2, each of which passes through a plurality of rows of pixel units .
  • Each data line connects two nearest sub-pixels having the same polarity (which may be two sub-pixels in the same pixel unit or two sub-pixels in different pixel units) when passing through a row of pixel units, and All sub-pixels connected to the same data line in the column direction have the same polarity, for example, the sub-pixels of the negative polarity are connected to the data line S1, and the sub-pixels of the positive polarity are connected to the data line S2. .
  • the sub-pixels connected to adjacent data lines have opposite polarities.
  • the data lines S1, S2, S3, and S4 are sequentially negative polarity, positive polarity, negative polarity, and positive polarity.
  • each column of pixel units only two data lines are arranged in each column of pixel units, which can reduce the number of source integrated circuits and save cost; all sub-pixels connected on the same data line have the same polarity, so that the source voltage signal is There is no need to do polarity switching in one frame, thereby reducing the power loss and temperature of the source integrated circuit; each sub-pixel exhibits a dot-reverse arrangement between positive and negative polarities, which improves the picture display quality.
  • the pixel unit 110 includes a first sub-pixel 111 , a second sub-pixel 112 , a third sub-pixel 113 , and a fourth sub-pixel 114 .
  • the first sub-pixel 111 is a white sub-pixel
  • the second sub-pixel 112 is a red sub-pixel
  • the third sub-pixel 113 is a green sub-pixel
  • the fourth sub-pixel 114 is a blue sub-pixel
  • each sub-pixel has a positive Negative two polarities.
  • the two data lines configured for it are the first data line 115 and the second data line 116, respectively.
  • the first data line 115 may be located on the left side of the entire pixel unit 110, and the second data line 116 is spaced apart from the first data line 115 by two sub-pixels. It can be understood that the two data lines can also be shifted to the right by 1 sub-pixel or 2 sub-pixels as a whole.
  • each data line passes through the pixel unit 110 of one row, two electrical connection lines are separated, and one sub-pixel located on both sides of the data line is respectively connected, and the two sub-pixels are separated by one sub-pixel. That is, the data line connects two inter-pixel sub-pixels, which are respectively located on both sides of the data line. Moreover, the data lines remain polar for one frame, so all sub-pixels connecting the same data line have the same polarity.
  • a plurality of rows of pixel units are defined as odd row pixel cells and even row pixel cells.
  • the first sub-pixels of odd-numbered rows and even-numbered rows of pixel cells are aligned, that is, the same color sub-pixels are all in the same column (FIG. 1) That is, this arrangement); the second is that on the basis of the first, the sub-pixels of the pixel units of the odd-numbered rows and the even-numbered rows are shifted from each other by two sub-pixels.
  • the sub-pixel arrangement in the pixel unit in the odd row is defined as the first order
  • the sub-pixel arrangement in the pixel unit in the even row is defined as the second order.
  • the first order is: the first sub-pixel 111, the second sub-pixel 112, the third sub-pixel 113, and the fourth sub-pixel 114 are sequentially arranged;
  • the second order is: the third sub-pixel 113, the first The four sub-pixels 114, the first sub-pixel 111, and the second sub-pixel 112 are sequentially arranged.
  • each sub-pixel exhibits a dot-reverse arrangement of positive and negative polarity phases, and each sub-pixel arrangement order is the first order or the second order, the sub-pixels of the same color have opposite colors in the odd-numbered rows and the even-numbered row pixel units. polarity. For example, in the odd row, the first sub-pixel 111 is white negative, and the first sub-pixel 111 in the even row is white positive.
  • the arrangement order of the four sub-pixels in the odd-numbered row and the even-line row pixel unit is the same, and is the first order, and the connection between the data line in the pixel array and the sub-pixel in the corresponding pixel unit
  • the method is: in the odd row, the first data line S1 is connected to the third sub-pixel (G) of the adjacent one column of the pixel unit and the first sub-pixel (W) of the current column; the second data line S2 is connected to the current column of the pixel unit.
  • first data line S1 is connected to a fourth sub-pixel (B) of its adjacent column of pixel units and a second sub-pixel of the current column a pixel (R); the second data line S2 connects the first sub-pixel (W) and the current column third sub-pixel (G) in the current column of pixel units.
  • the first data line S1 is negative polarity and the second data line S2 is positive polarity.
  • the first sub-pixel in the odd-line pixel unit, the first sub-pixel is white negative polarity, the second sub-pixel is red positive polarity, the third sub-pixel is green negative polarity, and the fourth sub-pixel is blue positive polarity.
  • the first sub-pixel in the even-numbered row of pixel units, the first sub-pixel is white positive and the second sub-pixel is red negative The polarity, the third sub-pixel is green positive polarity, and the third sub-pixel is blue negative polarity.
  • each sub-pixel of the odd-numbered row is sequentially aligned with each of the sub-pixels of the even-numbered row. Therefore, all of the sub-pixels satisfy the dot inversion arrangement between the positive and negative polar phases, and the first data line S1 and the second data line S2 do not need to be converted in polarity within one frame.
  • the arrangement order of the four sub-pixels in the odd-numbered row and the even-line row pixel unit is the same, and is the first order, and the connection between the data line in the pixel array and the sub-pixel in the corresponding pixel unit
  • the method is: in the odd row, the first data line S1 is connected to the fourth sub-pixel (B) of the adjacent column of pixel units and the second sub-pixel (R) of the current column; the second data line S2 is connected to the current column of pixel units.
  • the first data line S1 is connected to a third sub-pixel (G) of the adjacent one column of pixel units and a first sub-pixel of the current column a pixel (W);
  • the second data line S2 connects the second sub-pixel (R) in the current column of pixel units and the fourth sub-pixel (B) of the current column.
  • the first data line S1 is connected to the third sub-pixel (G) of the adjacent one column of the pixel unit and the first sub-pixel (W) of the current column;
  • the second data line S2 is connected a second sub-pixel (R) in the current column of pixel units and a fourth sub-pixel (B) of the current column;
  • the first data line S1 is connected to the second sub-pixel (R) of the adjacent one of the columns of pixel units
  • the fourth sub-pixel (B) of the current column is connected;
  • the second data line S2 is connected to the third sub-pixel (G) in the current column of pixel units and the first sub-pixel (W) of the current column.
  • the sub-pixels are sequentially aligned.
  • the first data line S1 is connected to the fourth sub-pixel (B) and the second sub-pixel (R) of the adjacent column of the adjacent column; the second data line S2 Connecting the first sub-pixel (W) and the current column third sub-pixel (G) in the current column of pixel units; in the even-numbered row, the first data line S1 is connected to the first sub-pixel (W) of the adjacent one of the column of pixel units And the current column third sub-pixel (G); the second data line S2 is connected to the fourth sub-pixel (B) and the current column second sub-pixel (R) in the current column of pixel units.
  • the first data line S1 is connected to the first sub-pixel (W) and the third sub-pixel (G) of the adjacent column of the adjacent column; the second data line S2 is connected.
  • the first data line S1 is connected to a fourth sub-pixel (B) of its adjacent column of pixel units and The second sub-pixel (R) of the current column is connected; the second data line S2 is connected to the first sub-pixel (W) and the third sub-pixel (G) of the current column of the current column.
  • the first data line S1 is connected to the second sub-pixel (R) of the adjacent one column of the pixel unit and the fourth sub-pixel (B) of the current column;
  • the second data line S2 is connected a third sub-pixel (G) in the current column of pixel units and a first sub-pixel (W) of the current column;
  • the first data line S1 is connected to a third sub-pixel (G) of its adjacent column of pixel units and The first column of the first sub-pixel (W) is currently connected;
  • the second data line S2 is connected to the second sub-pixel (R) and the fourth sub-pixel (B) of the current column.
  • the present application also provides a pixel driving method suitable for the above pixel driving circuit and display device. As shown in FIG. 9, the method includes the following steps:
  • Step S100 Acquire a data line driving voltage signal in which the positive and negative polarities are arranged in a reverse order.
  • Step S200 Control two scanning line driving voltage signals of each row of pixels to be simultaneously input, and sequentially input two scanning line driving voltage signals of each row.
  • Step S300 When two scan line driving voltage signals of one row of pixels are simultaneously input, each column of data lines writes a voltage signal to two sub-pixels, and the two sub-pixels are located on two sides of the data line. And arranged in phase.
  • Step S400 determining whether the voltage signal writing time is greater than one frame, and if yes, performing step S410a, otherwise performing step S410b.
  • Step S410a The voltage signal is polarity-switched during the period of each frame.
  • Step S410b Keep the polarity of the voltage signal in one frame unchanged.
  • the voltage signal is a data line driving voltage signal supplied from the source driving chip, and the voltage signal is set to be a column inversion arrangement of positive and negative polarity phases.
  • the driving voltage signal of the scan line is provided by a gate driving chip for controlling a thin film transistor switch (TFT switch), and writing a data voltage signal by controlling the TFT switch.
  • TFT switch thin film transistor switch
  • the application also provides a display device, as shown in FIG. 10, the display device includes:
  • the source driving chip 400 outputs a plurality of data lines S1, S2, S3, ..., S7, ..., the data lines are connected to the display panel 600 and have a positive and negative polarity Rotate
  • the gate driving chip 500 outputs a plurality of scanning lines G1, G2, ..., G8, ..., the scanning lines are connected to the display panel, and each of the two groups drives a row of pixels unit;
  • a display panel 600 is divided into a plurality of pixel groups 610 by data lines and scan lines, each pixel group having two sub-pixels of different colors and opposite polarities; the sub-pixels are juxtaposed and two adjacent The sub-pixels in the pixel group include white, red, green, and blue colors;
  • the pixel arrangement of the display panel 600 includes:
  • the sub-pixels in the adjacent two pixel groups 620 are different in color, and are arranged in a positive and negative polarity;
  • the adjacent sub-pixels 631 of the adjacent two pixel groups 630 have the same color and opposite polarities.
  • the pixel arrangement of the display panel 600' includes:
  • the sub-pixels in the adjacent two pixel groups 620' are different in color, and are arranged in a positive and negative polarity;
  • the adjacent sub-pixels 631' of the adjacent two pixel groups 630' have different colors and opposite polarities; wherein the white sub-pixels (W) are adjacent to the green sub-pixels (G), and the red sub-pixels (R) ) Adjacent to the blue sub-pixel (B).
  • the order of the color of the sub-pixels in the odd-numbered rows and the even-numbered rows is identical, that is, the sub-pixels on the same sub-pixel row have the same color. If the odd-numbered rows or the even-numbered rows of sub-pixels in the display panel 600 are totally translated by two sub-pixels (ie, one pixel group 610), the arrangement of the display panel 600' can be obtained.
  • HSD pixel wiring design technology is used, and only two data lines are arranged for each pixel unit, which reduces the number of source ICs used and saves cost;
  • the arrangement method improves the display quality of the screen. More importantly, the HSD wiring design technology and the dot-reversed pixel polarity arrangement make the source voltage signal do not need to be switched in polarity within one frame, thereby reducing the power consumption of the entire panel and the temperature of the source IC. Improve the quality of trust.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

一种像素驱动电路包括：像素阵列（100）、数据线（S1、S2、S3、...、S7、...）和扫描线（G1、G2、...、G8、...），其中，像素阵列（100）包括多个具有四条颜色不同的子像素的像素单元（110），所有的子像素相互之间呈现正负极性相间的点反转排列；数据线（S1、S2、S3、...、S7、...）和扫描线（G1、G2、...、G8、...）正交配置于像素阵列（100）中，且每行像素单元（110）设置两条扫描线、每列像素单元（110）设置两条数据线；每条数据线（S1、S2、S3、...、S7、...）在穿过一行像素单元（110）时，连接两个最近的具有相同极性的子像素，并且在列方向上连接在同一条数据线（S1、S2、S3、...、S7、...）上的所有子像素的极性都相同；相邻的数据线（S1、S2、S3、...、S7、...）连接的子像素极性相反。

Description

像素驱动电路、驱动方法及显示装置
本申请要求于2017年5月11日提交中国专利局、申请号为201710330458.7、申请名称为“像素驱动电路、驱动方法及显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，特别是涉及一种像素驱动电路、驱动方法及显示装置。
背景技术
随着显示器解析度与扫描率不断的提高，在考虑降低源集成电路(source IC)的使用数量上，许多产品在面板设计时采用基于半源驱动(half source driving，HSD)架构的像素接线设计。
然而，对于传统的HSD像素接线设计来说，其源极电压(source voltage)信号在一帧内需要做极性的转换，使得source IC的功耗明显增加。另外，在像面显示时IC温度也会上升，导致信赖性品质恶化。
发明内容
基于此，有必要提供一种能够降低功耗的像素驱动电路、驱动方法及显示装置。
一种像素驱动电路，包括像素阵列、数据线和扫描线。其中，像素阵列包括多个具有四条颜色不同的子像素的像素单元，所有的子像素相互之间呈现正负极性相间的点反转排列；所述数据线和扫描线正交配置于像素阵列中，且每行像素单元设置两条扫描线、每列像素单元设置两条数据线；每条数据 线在穿过一行像素单元时，连接两个最近的具有相同极性的子像素，并且在列方向上连接在同一条数据线上的所有子像素的极性都相同；相邻的数据线连接的子像素极性相反。
一种像素驱动方法，适用于上述像素驱动电路，包括：
获取正负极性呈列反转排列的数据线驱动电压信号；
控制每行像素的两条扫描线驱动电压信号同时输入，并依次输入各行的两条扫描线驱动电压信号；
当一行像素的两条扫描线驱动电压信号同时输入时，每列数据线写入电压信号至两个子像素，所述两个子像素位于所述数据线的两侧，且相间排列；
判断所述电压信号写入时间是否大于一帧，若是，则在每一帧的周期内做极性切换；否则保持一帧内极性不变。
一种显示装置，包括：
源极驱动芯片，设置为输出多条数据线，所述数据线连接显示面板且呈正负极性相间的列反转排列。
栅极驱动芯片，设置为输出多条扫描线，所述扫描线连接显示面板，且每两条为一组驱动一行像素单元。
显示面板，所述显示面板被数据线与扫描线划分为多个像素组，每个像素组具有两条颜色不同且极性相反的子像素；所述子像素并列排列且两相邻像素组中的子像素包括白、红、绿、蓝四种颜色。
上述像素驱动电路及显示面板，利用HSD像素接线设计技术，减少了source IC的使用数量，节省了成本；利用点反转的像素极性排列方式，提高了画面显示品质。更重要的是，利用HSD接线设计技术和点反转的像素极性排列方式，使得源极电压信号在一帧内不需要做极性切换，进而降低整体面板的功耗和source IC的温度，提升信赖性品质。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实 施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他实施例的附图。
图1为一实施例的像素驱动电路结构示意图；
图2为一实施例的像素单元结构示意图；
图3为一实施例的像素单元中子像素接线示意图；
图4为另一实施例的像素单元中子像素接线示意图；
图5为另一实施例的像素单元中子像素接线示意图；
图6为另一实施例的像素单元中子像素接线示意图；
图7为另一实施例的像素单元中子像素接线示意图；
图8为另一实施例的像素单元中子像素接线示意图；
图9为一实施例的像素驱动方法流程图；
图10为一实施例的显示面板结构示意图；
图11为另一实施例的显示面板结构示意图。
具体实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的较佳实施例。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本申请的公开内容的理解更加透彻全面。
图1为一实施例的像素驱动电路结构示意图，该结构包括像素阵列100、自源极驱动芯片200中延伸出来的多条数据线S1、S2、S3、...、S7、...和栅极驱动芯片300中延伸出来的多条扫描线G1、G2、...、G8、...。其中，像素阵列100包括多个具有四条颜色不同的子像素的像素单元110，所有的子像素相互之间呈现正负极性相间的点反转排列，即每个子像素都与相邻的任一子像素极性相反。
数据线和扫描线正交配置于像素阵列中，且每行像素单元110设置两条 扫描线，例如第一行像素单元配置扫描线G1、G2；每列像素单元110设置两条数据线，例如第一列像素单元配置数据S1、S2，每条数据线都会穿过多行像素单元。
每条数据线在穿过一行像素单元时，连接两个最近的具有相同极性的子像素(可以是同一像素单元中的两个子像素，也可以是不同像素单元中的两个子像素)，并且在列方向上连接在同一条数据线上的所有子像素的极性都相同，例如数据线S1上连接的都是负极性的子像素，而数据线S2上连接的都是正极性的子像素。相邻的数据线连接的子像素极性相反，如数据线S1、S2、S3、S4......依次为负极性、正极性、负极性、正极性......。
上述实施例中，每列像素单元只配置两条数据线，可以减少源集成电路的使用数量，节省成本；同一条数据线上连接的所有子像素的极性都相同，使得源极电压信号在一帧内不需要做极性切换，从而降低源集成电路的功率损耗和温度；各子像素之间呈现正负极性相间的点反转排列，提升了画面显示品质。
具体地，如图2所示，像素单元110包括第一子像素111、第二子像素112、第三子像素113及第四子像素114。其中，第一子像素111为白色子像素，第二子像素112为红色子像素，第三子像素113为绿色子像素，第四子像素114为蓝色子像素，并且各子像素皆具有正负两种极性。
对其中的一个像素单元110来说，为其配置的两条数据线分别为第一数据线115和第二数据线116。如图2所示，第一数据线115可以位于整个像素单元110左侧，第二数据线116与第一数据线115间隔两个子像素。可以理解，两条数据线也可以整体向右平移1个子像素或2个子像素。
每条数据线在穿过一行的像素单元110时，分出两条电性连接线，分别连接位于数据线两侧的一个子像素，这两个子像素之间相隔一个子像素。即，数据线连接两个相间的子像素，这两个子像素分别位于数据线两侧。而且，数据线在一帧内保持极性不变，因此连接同一条数据线的所有子像素具有相同的极性。
为方便描述，将多行像素单元定义为奇数行像素单元和偶数行像素单元。
在将像素单元排列成显示阵列时，可以有两种排列方式：第一种是奇数行和偶数行的像素单元的子像素都是对应对齐的，即相同颜色子像素都位于同一列(图1即是这种排列)；第二种是在第一种的基础上，将奇数行和偶数行的像素单元的子像素相互偏移两个子像素。为方便描述，对于第二种显示阵列的排列方式，将奇数行中的像素单元中的子像素排列定义为第一次序，将偶数行中的像素单元中的子像素排列定义为第二次序。在本实施例中，第一次序为：第一子像素111、第二子像素112、第三子像素113、第四子像素114顺序排列；第二次序为：第三子像素113、第四子像素114、第一子像素111、第二子像素112顺序排列。
由于各子像素呈现正负极性相间的点反转排列，且各子像素排列次序为第一次序或者第二次序，因此奇数行与偶数行像素单元中，相同颜色的子像素具有相反的极性。例如，奇数行中第一子像素111为白色负极性，则偶数行中第一子像素111为白色正极性。
以下分别对各种具体的像素排列及子像素连接的情况进行说明。
在其中一个实施例中，如图3所示，奇数行和偶素行像素单元中四个子像素的排列次序一致，且为第一次序，像素阵列中数据线与对应像素单元中子像素的连接方式为：在奇数行，第一数据线S1连接其相邻一列像素单元中的第三子像素(G)和当前列第一子像素(W)；第二数据线S2连接当前列像素单元中的第二子像素(R)和当前列第四子像素(B)；在偶数行，第一数据线S1连接其相邻一列像素单元中的第四子像素(B)和当前列第二子像素(R)；第二数据线S2连接当前列像素单元中的第一子像素(W)和当前列第三子像素(G)。
在本实施例中，第一数据线S1为负极性，第二数据线S2为正极性。通过上述连线方式，使得在奇数行像素单元中，第一子像素为白色负极性、第二子像素为红色正极性、第三子像素为绿色负极性、第四子像素为蓝色正极性；在偶数行像素单元中，第一子像素为白色正极性、第二子像素为红色负 极性、第三子像素为绿色正极性、第三子像素为蓝色负极性。并且，奇数行的各子像素与偶数行的各子像素依次对齐。因此所有子像素满足正负极性相间的点反转排列，并且在一帧内第一数据线S1和第二数据线S2不需要做极性的转换。
在另一个实施例中，如图4所示，奇数行和偶素行像素单元中四个子像素的排列次序一致，且为第一次序，像素阵列中数据线与对应像素单元中子像素的连接方式为：在奇数行，第一数据线S1连接其相邻一列像素单元中的第四子像素(B)和当前列第二子像素(R)；第二数据线S2连接当前列像素单元中的第一子像素(W)和当前列第三子像素(G)；在偶数行，第一数据线S1连接其相邻一列像素单元中的第三子像素(G)和当前列第一子像素(W)；第二数据线S2连接当前列像素单元中的第二子像素(R)和当前列第四子像素(B)。
在其中一个实施例中，如图5所示，奇数行像素单元中四个子像素为第一次序，偶数行像素单元中四个子像素为第二次序，则像素阵列中数据线与对应像素单元中子像素的连接方式为：在奇数行，第一数据线S1连接其相邻一列像素单元中的第三子像素(G)和当前列第一子像素(W)；第二数据线S2连接当前列像素单元中的第二子像素(R)和当前列第四子像素(B)；在偶数行，第一数据线S1连接其相邻一列像素单元中的第二子像素(R)和当前列第四子像素(B)；第二数据线S2连接当前列像素单元中的第三子像素(G)和当前列第一子像素(W)。
在本实施例中，奇数行的第一子像素、第二子像素、第三子像素、第四子像素分别与偶数行的第三子像素、第四子像素、第一子像素、第二子像素依次对齐。
在另一个实施例中，如图6所示，奇数行像素单元中四个子像素为第一次序，偶数行像素单元中四个子像素为第二次序，则像素阵列中数据线与对应像素单元中子像素的连接方式为：在奇数行，第一数据线S1连接其相邻一列像素单元中的第四子像素(B)和当前列第二子像素(R)；第二数据线S2 连接当前列像素单元中的第一子像素(W)和当前列第三子像素(G)；在偶数行，第一数据线S1连接其相邻一列像素单元中的第一子像素(W)和当前列第三子像素(G)；第二数据线S2连接当前列像素单元中的第四子像素(B)和当前列第二子像素(R)。
在其中一个实施例中，如图7所示，奇数行像素单元中四个子像素为第二次序，偶数行像素单元中四个子像素为第一次序，则像素阵列中数据线与对应像素单元中子像素的连接方式为：在奇数行，第一数据线S1连接其相邻一列像素单元中的第一子像素(W)和当前列第三子像素(G)；第二数据线S2连接当前列像素单元中的第四子像素(B)和当前列第二子像素(R)；在偶数行，第一数据线S1连接其相邻一列像素单元中的第四子像素(B)和当前列第二子像素(R)；第二数据线S2连接当前列像素单元中的第一子像素(W)和当前列第三子像素(G)。
在另一个实施例中，如图8所示，奇数行像素单元中四个子像素为第二次序，偶数行像素单元中四个子像素为第一次序，则像素阵列中数据线与对应像素单元中子像素的连接方式为：在奇数行，第一数据线S1连接其相邻一列像素单元中的第二子像素(R)和当前列第四子像素(B)；第二数据线S2连接当前列像素单元中的第三子像素(G)和当前列第一子像素(W)；在偶数行，第一数据线S1连接其相邻一列像素单元中的第三子像素(G)和当前列第一子像素(W)；第二数据线S2连接当前列像素单元中的第二子像素(R)和当前列第四子像素(B)。
本申请还提供一种像素驱动方法，适用于上述像素驱动电路及显示装置。如图9所示，该方法包括以下步骤：
步骤S100：获取正负极性呈列反转排列的数据线驱动电压信号。
步骤S200：控制每行像素的两条扫描线驱动电压信号同时输入，并依次输入各行的两条扫描线驱动电压信号。
步骤S300：当一行像素的两条扫描线驱动电压信号同时输入时，每列数据线写入电压信号至两个子像素，所述两个子像素位于所述数据线的两侧， 且相间排列。
步骤S400：判断所述电压信号写入时间是否大于一帧，若是，则执行步骤步骤S410a，否则执行步骤步骤S410b。
步骤S410a：在每一帧的周期内，所述电压信号做极性切换。
步骤S410b：保持一帧内所述电压信号极性不变。
上述像素驱动方法中，电压信号为源极驱动芯片提供的数据线驱动电压信号，该电压信号设置为正负极性相间的列反转排列。扫描线的驱动电压信号有栅极驱动芯片提供，该驱动电压信号用于控制薄膜晶体管开关(TFT开关)，通过控制TFT开关来实现数据电压信号的写入。
本申请还提供一种显示装置，如图10所示，该显示装置包括：
源极驱动芯片400，所述源极驱动芯片400输出多条数据线S1、S2、S3、...、S7、...，所述数据线连接显示面板600且呈正负极性相间的列反转排列；
栅极驱动芯片500，所述栅极驱动芯片500输出多条扫描线G1、G2、...、G8、...，所述扫描线连接显示面板，且每两条为一组驱动一行像素单元；
显示面板600，所述显示面板600被数据线与扫描线划分为多个像素组610，每个像素组具有两条颜色不同且极性相反的子像素；所述子像素并列排列且两相邻像素组中的子像素包括白、红、绿、蓝四种颜色；
所述显示面板600的像素排列方式包括：
在扫描线方向上，相邻两像素组620中的子像素颜色各不相同，且呈正负极性相间排列；
在数据线方向上，相邻两像素组630中相邻子像素631颜色相同，且极性相反。
在其中一个实施例中，如图11所示，显示面板600′的像素排列方式包括：
在扫描线方向上，相邻两像素组620′中的子像素颜色各不相同，且呈正负极性相间排列；
在数据线方向上，相邻两像素组630′中相邻子像素631′颜色不同，且极性相反；其中白色子像素(W)与绿色子像素(G)相邻，红色子像素(R) 与蓝色子像素(B)相邻。
上述显示面板600中，奇数行与偶数行中的子像素颜色的次序排列一致，也即同一子像素列上的子像素具有相同的颜色。若将显示面板600中的奇数行或者偶数行的子像素，整体平移两个子像素(即一个像素组610)距离，则可以得到显示面板600′的排列方式。
上述像素驱动电路、驱动方法及显示装置中，利用HSD像素接线设计技术，每个像素单元只设置两条数据线，减少了source IC的使用数量，节省了成本；利用点反转的像素极性排列方式，提高了画面显示品质。更重要的是，利用HSD接线设计技术和点反转的像素极性排列方式，使得源极电压信号在一帧内不需要做极性切换，进而降低整体面板的功耗和source IC的温度，提升信赖性品质。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (15)

  1. 一种像素驱动电路，包括：
    像素阵列，包括多个具有四条颜色不同的子像素的像素单元，所有的子像素相互之间呈现正负极性相间的点反转排列；及
    数据线和扫描线，所述数据线和扫描线正交配置于像素阵列中，且每行像素单元设置两条扫描线、每列像素单元设置两条数据线；
    其中每条数据线在穿过一行像素单元时连接两个最接近的具有相同极性的子像素，并且在列方向上连接在同一条数据线上的所有子像素的极性都相同；相邻的数据线连接的子像素极性相反。
  2. 根据权利要求1所述的像素驱动电路，其中：
    所述每行像素单元分为奇数行像素单元和偶数行像素单元；所述奇数行和偶数行像素单元中四个子像素的排列次序一致，且为第一次序：第一子像素、第二子像素、第三子像素及第四子像素依次排列。
  3. 根据权利要求2所述的像素驱动电路，其中：
    所述奇数行像素单元中四个子像素为第一次序，偶数行像素单元中四个子像素为第二次序：第三子像素、第四子像素、第一子像素及第二子像素依次排列。
  4. 根据权利要求2所述的像素驱动电路，其中：
    所述奇数行像素单元中四个子像素为第二次序：第三子像素、第四子像素、第一子像素及第二子像素依次排列；偶数行像素单元中四个子像素为第一次序。
  5. 根据权利要求2所述的像素驱动电路，其中：
    所述每列像素单元中，两条数据线依次为第一数据线和第二数据线；
    所述第一数据线位于所述第一次序的四个子像素中第一子像素相邻；
    所述第二数据线位于所述第一次序的四个子像素中第二子像素和第三子像素之间。
  6. 根据权利要求5所述的像素驱动电路，其中，所述奇数行和偶数行像 素单元中四个子像素的排列次序一致，且为第一次序，则所述数据线与所述子像素的连接方式为：
    在奇数行，所述第一数据线连接其相邻一列像素单元中的第三子像素和当前列第一子像素；所述第二数据线连接当前列像素单元中的第二子像素和当前列第四子像素；
    在偶数行，所述第一数据线连接其相邻一列像素单元中的第四子像素和当前列第二子像素；所述第二数据线连接当前列像素单元中的第一子像素和当前列第三子像素。
  7. 根据权利要求5所述的像素驱动电路，其中，所述奇数行和偶数行像素单元中四个子像素的排列次序一致，且为第一次序，则所述数据线与所述子像素的连接方式为：
    在奇数行，所述第一数据线连接其相邻一列像素单元中的第四子像素和当前列第二子像素；所述第二数据线连接当前列像素单元中的第一子像素和当前列第三子像素；
    在偶数行，所述第一数据线连接其相邻一列像素单元中的第三子像素和当前列第一子像素；所述第二数据线连接当前列像素单元中的第二子像素和当前列第四子像素。
  8. 根据权利要求5所述的像素驱动电路，其中，所述奇数行像素单元中四个子像素为第一次序，偶数行像素单元中四个子像素为第二次序，则所述数据线与所述子像素的连接方式为：
    在奇数行，所述第一数据线连接其相邻一列像素单元中的第三子像素和当前列第一子像素；所述第二数据线连接当前列像素单元中的第二子像素和当前列第四子像素；
    在偶数行，所述第一数据线连接其相邻一列像素单元中的第二子像素和当前列第四子像素；所述第二数据线连接当前列像素单元中的第三子像素和当前列第一子像素。
  9. 根据权利要求5所述的像素驱动电路，其中，所述奇数行像素单元中 四个子像素为第一次序，偶数行像素单元中四个子像素为第二次序，则所述数据线与所述子像素的连接方式为：
    在奇数行，所述第一数据线连接其相邻一列像素单元中的第四子像素和当前列第二子像素；所述第二数据线连接当前列像素单元中的第一子像素和当前列第三子像素；
    在偶数行，所述第一数据线连接其相邻一列像素单元中的第一子像素和当前列第三子像素；所述第二数据线连接当前列像素单元中的第四子像素和当前列第二子像素。
  10. 根据权利要求5所述的像素驱动电路，其中，所述奇数行像素单元中四个子像素为第二次序，偶数行像素单元中四个子像素为第一次序，则所述数据线与所述子像素的连接方式为：
    在奇数行，所述第一数据线连接其相邻一列像素单元中的第一子像素和当前列第三子像素；所述第二数据线连接当前列像素单元中的第四子像素和当前列第二子像素；
    在偶数行，所述第一数据线连接其相邻一列像素单元中的第四子像素和当前列第二子像素；所述第二数据线连接当前列像素单元中的第一子像素和当前列第三子像素。
  11. 根据权利要求5所述的像素驱动电路，其中，所述奇数行像素单元中四个子像素为第二次序，偶数行像素单元中四个子像素为第一次序，则所述数据线与所述子像素的连接方式为：
    在奇数行，所述第一数据线连接其相邻一列像素单元中的第二子像素和当前列第四子像素；所述第二数据线连接当前列像素单元中的第三子像素和当前列第一子像素；
    在偶数行，所述第一数据线连接其相邻一列像素单元中的第三子像素和当前列第一子像素；所述第二数据线连接当前列像素单元中的第二子像素和当前列第四子像素。
  12. 一种像素驱动方法，适用于权利要求1的像素驱动电路，包括：
    获取正负极性呈列反转排列的数据线驱动电压信号；
    控制每行像素的两条扫描线驱动电压信号同时输入，并依次输入各行的两条扫描线驱动电压信号；
    当一行像素的两条扫描线驱动电压信号同时输入时，每列数据线写入电压信号至两个子像素，所述两个子像素位于所述数据线的两侧，且相间排列；及
    判断所述电压信号写入时间是否大于一帧，若是，则在每一帧的周期内做极性切换；否则保持一帧内极性不变。
  13. 一种显示装置，包括：
    源极驱动芯片，设置为输出多条数据线，所述数据线连接显示面板且呈正负极性相间的列反转排列；
    栅极驱动芯片，设置为输出多条扫描线，所述扫描线连接显示面板，且每两条为一组驱动一行像素单元；及
    显示面板，所述显示面板被数据线与扫描线划分为多个像素组，每个像素组具有两条颜色不同且极性相反的子像素；所述子像素并列排列且两相邻像素组中的子像素包括白、红、绿、蓝四种颜色。
  14. 根据权利要求13所述的显示装置，其中，所述显示面板的像素排列方式包括：
    在扫描线方向上，相邻两像素组中的子像素颜色各不相同，且呈正负极性相间排列；
    在数据线方向上，相邻两像素组中相邻子像素颜色相同，且极性相反。
  15. 根据权利要求13所述的显示装置，其中，所述显示面板的像素排列方式还包括：
    在扫描线方向上，相邻两像素组中的子像素颜色各不相同，且呈正负极性相间排列；
    在数据线方向上，相邻两像素组中相邻子像素颜色不同，且极性相反；其中白色子像素与绿色子像素相邻，红色子像素与蓝色子像素相邻。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110738959A (zh) * 2019-10-30 2020-01-31 京东方科技集团股份有限公司 一种显示基板及其制作方法和显示装置

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107393460B (zh) * 2017-08-08 2020-03-27 惠科股份有限公司 一种显示装置的驱动方法和驱动装置
CN109949760B (zh) * 2017-12-21 2022-03-11 咸阳彩虹光电科技有限公司 一种像素矩阵驱动方法及显示装置
CN108257563B (zh) * 2018-01-03 2019-12-27 惠科股份有限公司 显示装置
CN108269542B (zh) * 2018-01-03 2020-03-03 惠科股份有限公司 显示装置
CN108182919B (zh) * 2018-01-03 2020-02-04 惠科股份有限公司 显示装置
CN109471288B (zh) * 2018-07-02 2021-10-29 惠科股份有限公司 显示面板及液晶显示面板的制造方法
CN208569265U (zh) * 2018-07-17 2019-03-01 惠科股份有限公司 阵列基板及液晶显示面板
CN109283760A (zh) * 2018-10-22 2019-01-29 惠科股份有限公司 显示面板
CN109256081B (zh) * 2018-11-16 2022-04-08 京东方科技集团股份有限公司 一种源极驱动电路、显示面板
CN209343752U (zh) 2018-12-05 2019-09-03 惠科股份有限公司 一种显示面板和显示装置
TWI686790B (zh) * 2018-12-11 2020-03-01 友達光電股份有限公司 顯示裝置及其驅動方法
CN109599073B (zh) * 2019-01-09 2020-12-25 惠科股份有限公司 一种显示装置、驱动方法和显示器
US11024215B2 (en) * 2019-02-22 2021-06-01 Novatek Microelectronics Corp. Display panel having dual-gate structure, control circuit, and display device
CN110111755A (zh) * 2019-06-18 2019-08-09 厦门天马微电子有限公司 一种显示面板、其驱动方法及显示装置
TWI767167B (zh) * 2019-12-12 2022-06-11 友達光電股份有限公司 畫素單元及顯示面板
US11307680B2 (en) * 2020-02-12 2022-04-19 Smash Engineering Inc. Computer mouse adapter and associated methods
JP2022154077A (ja) * 2021-03-30 2022-10-13 凸版印刷株式会社 表示装置
CN113552752B (zh) 2021-07-13 2022-09-09 深圳市华星光电半导体显示技术有限公司 液晶显示面板及显示装置
CN113777839B (zh) * 2021-08-19 2022-08-05 深圳市华星光电半导体显示技术有限公司 显示面板及移动终端
CN113781972A (zh) * 2021-09-13 2021-12-10 Tcl华星光电技术有限公司 显示面板
CN113936619B (zh) 2021-10-28 2022-08-23 深圳市华星光电半导体显示技术有限公司 液晶显示面板及其驱动方法、终端
CN114170986B (zh) * 2021-12-09 2023-01-24 Tcl华星光电技术有限公司 液晶显示面板及显示装置
US11947230B2 (en) 2022-03-30 2024-04-02 Suzhou China Star Optoelectronics Technology Co., Ltd. Array substrate, liquid crystal display panel, and display device
CN114488639B (zh) * 2022-03-30 2024-01-12 苏州华星光电技术有限公司 阵列基板、液晶显示面板及显示装置
CN114944110A (zh) * 2022-05-25 2022-08-26 Tcl华星光电技术有限公司 显示面板及显示终端
CN116597771B (zh) * 2023-05-24 2024-02-02 北京显芯科技有限公司 一种发光基板及其驱动方法、显示装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101566744A (zh) * 2009-06-08 2009-10-28 友达光电股份有限公司 液晶显示器及其液晶显示面板
CN101996603A (zh) * 2010-10-18 2011-03-30 深圳市华星光电技术有限公司 液晶显示装置及其驱动方法
US20110285950A1 (en) * 2010-05-20 2011-11-24 Au Optronics Corporation Active device array substrate
CN103065596A (zh) * 2009-12-03 2013-04-24 乐金显示有限公司 液晶显示器
JP2014026069A (ja) * 2012-07-26 2014-02-06 Kyocera Display Corp 液晶表示装置

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100825105B1 (ko) * 2002-05-04 2008-04-25 삼성전자주식회사 액정 표시 장치
KR101179233B1 (ko) * 2005-09-12 2012-09-04 삼성전자주식회사 액정표시장치 및 그 제조방법
JP4877363B2 (ja) * 2009-06-29 2012-02-15 カシオ計算機株式会社 液晶表示装置及びその駆動方法
CN102750919A (zh) * 2012-06-26 2012-10-24 北京京东方光电科技有限公司 一种显示面板及其驱动方法、显示装置
CN202948235U (zh) * 2012-11-09 2013-05-22 北京京东方光电科技有限公司 一种阵列基板、显示面板和显示装置
CN104658489B (zh) * 2013-11-20 2018-05-11 顾晶 一种用于lcd面板的驱动方法及其驱动ic

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101566744A (zh) * 2009-06-08 2009-10-28 友达光电股份有限公司 液晶显示器及其液晶显示面板
CN103065596A (zh) * 2009-12-03 2013-04-24 乐金显示有限公司 液晶显示器
US20110285950A1 (en) * 2010-05-20 2011-11-24 Au Optronics Corporation Active device array substrate
CN101996603A (zh) * 2010-10-18 2011-03-30 深圳市华星光电技术有限公司 液晶显示装置及其驱动方法
JP2014026069A (ja) * 2012-07-26 2014-02-06 Kyocera Display Corp 液晶表示装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110738959A (zh) * 2019-10-30 2020-01-31 京东方科技集团股份有限公司 一种显示基板及其制作方法和显示装置
CN110738959B (zh) * 2019-10-30 2023-05-05 京东方科技集团股份有限公司 一种显示基板及其制作方法和显示装置

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