WO2018040769A1 - 阵列基板及显示面板、显示装置 - Google Patents

阵列基板及显示面板、显示装置 Download PDF

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Publication number
WO2018040769A1
WO2018040769A1 PCT/CN2017/093366 CN2017093366W WO2018040769A1 WO 2018040769 A1 WO2018040769 A1 WO 2018040769A1 CN 2017093366 W CN2017093366 W CN 2017093366W WO 2018040769 A1 WO2018040769 A1 WO 2018040769A1
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pixel
display
array substrate
pixels
display domain
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PCT/CN2017/093366
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English (en)
French (fr)
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龙春平
马永达
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京东方科技集团股份有限公司
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Priority to US15/751,461 priority Critical patent/US10914997B2/en
Publication of WO2018040769A1 publication Critical patent/WO2018040769A1/zh

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    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
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    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
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    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
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Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to an array substrate, a display panel, and a display device.
  • multi-domain display modes are often used in some wide viewing angle liquid crystal displays to increase the viewing angle of the display.
  • the multi-domain display mode refers to dividing a plurality of regions in one sub-pixel, and the deflection angles of the liquid crystals in different regions are different.
  • the multi-domain display mode can reduce all liquid crystals in the pixels. The difference in contrast between different viewing angles caused by the same deflection angle increases the viewing angle.
  • a liquid crystal display employing a multi-domain display mode
  • different pixel voltages are required to be provided in a single pixel of the array substrate to form different deflection angles of the liquid crystal molecules; pixels of the array substrate are adjacent to two grids on the array substrate The line is formed by a region surrounded by two adjacent data lines, and one pixel is generally controlled by one or two thin film transistors located at the intersection of one gate line and one data line.
  • one or two thin film transistors in one pixel are generally used to provide pixel voltage signals of different polarities from the same data line in a time division manner, and the array substrate using the pixel structure is reduced.
  • the charging time of the pixel is not conducive to achieving high frequency driving.
  • the present disclosure provides an array substrate and a display panel, and a display device, which can improve charging time of pixels in a multi-domain liquid crystal display mode, and is advantageous for realizing high frequency driving.
  • An array substrate comprising a plurality of pixels distributed in an array, wherein:
  • Two data lines are disposed between each adjacent two columns of pixels, and data lines are disposed on both sides of each column of pixels;
  • a gate line is disposed between each adjacent two rows of pixels, and data lines are disposed on both sides of each row of pixels;
  • Each pixel includes at least two display domain regions, and each display domain region is correspondingly connected with a switching device;
  • each display domain is connected to a gate line on either side of the corresponding pixel through a corresponding switching device;
  • each display domain is connected to a data line adjacent to the pixel on either side of the corresponding pixel by a corresponding switching device.
  • each pixel includes at least two display domain regions, and each display domain region is connected with a switching device; in each pixel, each display domain region passes through a corresponding switching device and One gate line on one side of the corresponding pixel is connected, and the gate line of at least one side of each pixel is connected with the display domain area in the corresponding pixel; in each pixel, each display domain area passes through a corresponding switching device and a corresponding pixel A data line of the side adjacent to the pixel is connected, and a data line of at least one side of each pixel is connected to a display domain in the corresponding pixel.
  • each pixel In the above array substrate, two data lines are disposed between two adjacent columns of pixels, and two data lines are disposed on both sides of each pixel. Therefore, at least two display domain regions in each pixel can be respectively Different data lines acquire pixel voltage signals, or each adjacent two pixels can respectively acquire pixel voltage signals by different data lines, and adjust poles of pixel voltage signals provided by data lines corresponding to each display domain or each pixel.
  • the polarity of the pixel voltage signals of adjacent display domains or adjacent pixels can be made different. The problem that the pixel charging time is reduced due to the pixel voltage signals of different polarities provided by the same data line in time division is improved, which is advantageous for realizing high frequency driving and reducing power consumption of the display panel.
  • the at least two display domain regions in each pixel are sequentially distributed along the row direction of the corresponding pixel;
  • the at least two display domain regions in each pixel are sequentially arranged along a column direction of the corresponding pixel; or
  • the at least two display domain regions in each pixel are distributed in an array.
  • the array substrate further includes a gate driver connected to each of the gate lines, and a source driver connected to each of the data lines, the source driver including a positive polarity source driver and a negative polarity source driver.
  • the polarity of the source driver connected to the data line corresponding to the at least two display domain regions in one pixel and the at least two in the other pixel have opposite polarities.
  • the polarity of the source driver connected to the data line corresponding to the at least two display domain regions in one pixel and the at least two in the other pixel have opposite polarities.
  • one source driver connected to the data line to which the data line corresponding to the domain region is connected and the data line corresponding to the other display domain region is connected The opposite polarity.
  • one source driver connected to the data line to which the data line corresponding to the domain region is connected and the data line corresponding to the other display domain region is connected The opposite polarity.
  • the switching device is a thin film transistor.
  • width and length ratios of the channels of the corresponding thin film transistors of the two display domain regions in each pixel are the same; or
  • the width to length ratio of the channel of the corresponding thin film transistor of each of the two display domain regions in each pixel is different.
  • the present disclosure also provides a display panel comprising the array substrate as described above, and a color filter substrate connected to the array substrate, the color filter substrate comprising a plurality of array-distributed sub-pixel regions, each sub-pixel The projection of the region on the array substrate covers two adjacent display domain regions.
  • the two display domain regions covered by the projection of each sub-pixel region on the array substrate are located in the same pixel on the array substrate.
  • the two display domain regions covered by the projection of each sub-pixel region on the array substrate are located in adjacent two pixels on the array substrate.
  • the present disclosure also provides a display device including the display panel as described above.
  • 1a is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure
  • Figure 1b is a schematic diagram showing the arrangement of display domain regions in a single pixel
  • Figure 1c is a schematic diagram showing the arrangement of display domain regions in a single pixel
  • Figure 1d is a schematic diagram showing the arrangement of display domain regions in a single pixel
  • FIG. 2a is another schematic structural diagram of an array substrate according to an embodiment of the present disclosure.
  • FIG. 2b is another schematic structural diagram of an array substrate according to an embodiment of the present disclosure.
  • 2c is another schematic structural diagram of an array substrate according to an embodiment of the present disclosure.
  • Figure 3a is a polar distribution diagram of a voltage signal applied to each pixel on the array substrate shown in Figure 1a;
  • Figure 3b is a polar distribution diagram of voltage signals applied to each pixel on the array substrate shown in Figure 2a;
  • Figure 3c is a polar distribution diagram of voltage signals applied to each pixel on the array substrate shown in Figure 2b;
  • Figure 3d is a polar distribution diagram of voltage signals applied to each pixel on the array substrate shown in Figure 2c;
  • FIG. 4 is a schematic structural diagram of a display panel according to another embodiment of the present disclosure.
  • FIG. 5 is another schematic structural diagram of a display panel according to another embodiment of the present disclosure.
  • FIG. 1a is a schematic structural diagram of an array substrate according to the embodiment.
  • the array substrate 01 includes a plurality of pixels distributed in an array, such as the pixels 11-14 in the first row shown in FIG. 1a. And pixels 11-31 located in the first column, each pixel being formed by two data lines and two gate lines being crossed, for example, the pixel 11 shown in FIG. 1 is gate line gate1, gate2 and data line data1 Data2 is formed around;
  • Two data lines are disposed between each adjacent two columns of pixels, and data lines are disposed on both sides of each column of pixels;
  • the first column of pixels 11-31 and the second column of pixels 12-32 shown in FIG. 1a are
  • two data lines data2 and data3 are disposed between the first column of pixels 11-31 and the second column of pixels 12-32
  • data lines data1 and data lines data2 are disposed on both sides of the first column of pixels 11-31.
  • the data line data3 and the data line data4 are disposed on both sides of the second column of pixels 12-32;
  • a gate line is disposed between each adjacent two rows of pixels, and data lines are disposed on both sides of each row of pixels; taking the first row of pixels 11-14 and the second row of pixels 21-24 shown in FIG. 1a as an example a gate line gate2 is disposed between the first row of pixels 11-14 and the second row of pixels 21-24, and the gate line gate1 and the gate line gate2 are disposed on both sides of the first row of pixels 11-14, and the second row of pixels 21-24 sides are provided with gate line gate2 and gate line gate3;
  • Each pixel includes two display domain regions, and each display domain region is connected with a switching device; a display domain region is a region where a switching device is controlled inside one pixel, and in specific implementation, the display domain region is provided for Controlling pixel electrodes of liquid crystal molecules located in the display domain; taking the pixel 11 shown in FIG. 1a as an example, 11 display domain regions 111 and 112 are provided, wherein the display domain 111 and the switching device 113 correspond Connecting, displaying the domain region 112 and the switching device 114 correspondingly connected;
  • FIG. 1d is a schematic diagram showing the arrangement of display domain regions in a single pixel, wherein two display domain regions in each pixel are sequentially arranged along the column direction of the corresponding pixel; or, as shown in FIG. 1b, FIG. 1b is a single pixel.
  • FIG. 1c is a schematic diagram showing the arrangement of display domain regions in a single pixel, each pixel has four display domain regions, and four display domain region arrays are distributed;
  • Each display domain in each pixel is connected to a gate line on either side of the pixel through a corresponding switching device, and the display domain in each pixel can be connected to the gate line on one side or both sides of the corresponding pixel;
  • the display domain region 111 in the pixel 11 is connected to the gate line gate1 through the correspondingly connected switching device 113, and the display domain region 112 is connected to the gate line gate2 through the correspondingly connected switching device 114;
  • FIG. 1b two display domain regions in the pixel 11 in FIG. 1b are connected to the gate line gate1;
  • Each display domain in each pixel is connected to a data line adjacent to a corresponding pixel on either side of the pixel through a corresponding switching device, and the display domain in each pixel can be on one side or two sides of the corresponding pixel.
  • the display domain 111 is connected to the data line data2 through the correspondingly connected switching device 113, and the domain region 112 is also connected through the correspondingly connected switching device 114 and the data line data2.
  • two display domain regions in the pixel 11 are respectively connected to the data lines data1 and data2; when a plurality of display domain regions distributed in the array are provided in the pixel, the display region regions and The connection manner of the gate line and the data line is similar to the case where two display domain regions are provided in each of the above pixels, that is, the display domain regions of the plurality of arrays are all connected to the same gate line or the same data line, or Two of the display domain regions of the plurality of arrays are respectively connected to different gate lines or data lines.
  • the row direction is the extending direction of the gate lines
  • the column direction is the extending direction of the data lines.
  • each pixel includes at least two display domain regions, and each display domain region is connected with a switching device; in each pixel, each display domain region passes through a corresponding switching device Connected to a gate line on one side of the corresponding pixel, and the gate line of at least one side of each pixel is connected to the display domain area in the corresponding pixel; in each pixel, each display domain area passes through a corresponding switching device and a corresponding pixel One side Connected to a data line immediately adjacent to the pixel, and the data line of at least one side of each pixel is connected to the display domain in the corresponding pixel.
  • each pixel In the above array substrate, two data lines are disposed between two adjacent columns of pixels, and two data lines are disposed on both sides of each pixel. Therefore, at least two display domain regions in each pixel can be respectively Different data lines acquire pixel voltage signals, or each adjacent two pixels can respectively acquire pixel voltage signals by different data lines, and adjust poles of pixel voltage signals provided by data lines corresponding to each display domain or each pixel.
  • the polarity of the pixel voltage signals of adjacent display domains or adjacent pixels can be made different. The problem that the pixel charging time is reduced due to the pixel voltage signals of different polarities provided by the same data line in time division is improved, which is advantageous for realizing high frequency driving and reducing power consumption of the display panel.
  • the array substrate provided in this embodiment can realize dot inversion driving of low-power multi-domain liquid crystal display.
  • the driving method of the liquid crystal display panel may include: a frame inversion method, a line inversion method, and a dot inversion method, wherein the dot inversion method refers to a frame image.
  • the dot inversion method refers to a frame image.
  • Each of the sub-pixels and the four sub-pixels adjacent to the periphery have opposite voltage polarities.
  • the liquid crystal display panel In the dot inversion mode, the liquid crystal display panel has the least problem of flicker and crosstalk, and the display effect is optimal.
  • the array substrate provided in this embodiment further includes a gate driver connected to each gate line, and a source driver connected to each of the data lines, the source driver including a positive polarity source driver and a negative polarity source driver.
  • the polarity of the source driver connected to the data line corresponding to the at least two display domain regions in another pixel is opposite; at the same time, at least one of the two pixels adjacent in the column direction, the at least one pixel
  • the polarity of the source driver connected to the data line corresponding to the two display domain regions is opposite to the polarity of the source driver connected to the data line corresponding to the at least two display domain regions in the other pixel.
  • the polarity of the pixel signal voltage applied to any two adjacent pixels in the row and column direction is opposite to achieve dot inversion driving in units of pixels.
  • the display domain regions in each pixel are connected to the same data line, and of the two pixels adjacent in the column direction, two of the pixels display the domain connection.
  • the data line is different from the data line connecting the two display domain regions in another pixel; taking the first column of pixels 11-31 as an example, among the pixels 11 and 21 adjacent in the column direction, the display domain region in the pixel 11 111 and 112 are connected to the data line data2 on the side of the first column of pixels 11-31, and the two display domain regions in the pixel 12 are connected to the data line data1 located on the other side of the first column of pixels 11-31;
  • two display domain regions in the pixels of the odd column are connected to the data lines of the first side of the corresponding column, and two display domain regions in the pixels of the even column and the corresponding columns of the columns
  • the data lines on the two sides are connected.
  • the first side and the second side may be different sides of a column, for example, the left side and the right side of the column, respectively.
  • the two display domains and the first side of the corresponding first column 11-31 The data lines data2 are connected, and the two display domains in the pixel 13 are connected to the data line data6 on the first side of the corresponding third column 13-33; in the pixels 12, 14 of the even column, two of the pixels 12
  • the display domain region is connected to the data line data3 of the second side of the corresponding second column 12-32, and the two display domain regions of the pixel 14 are connected to the data line data7 of the second side of the corresponding fourth column 14-34.
  • FIG. 3a is a polarity distribution diagram of a voltage signal applied to each pixel on the array substrate shown in FIG. 1a, and two data lines between adjacent two columns of pixels are respectively positive polarity.
  • the source driver and the negative source driver are connected, and two data lines on each side of each column of pixels are respectively connected to the positive source driver and the negative source driver; specifically, the first column of pixels 11-31 and the first Taking the two columns of pixels 12-32 as an example, the data line data1 on the side of the first column of pixels 11-31 is connected to the positive polarity source driver, and the data line data2 on the other side is connected to the negative polarity source driver; the second column of pixels
  • the data line data3 on the 12-32 side is connected to the positive polarity source driver, and the data line data4 on the other side is connected to the negative polarity source driver, so that the first column pixel 11-31 and the second column pixel 12-32
  • the data line data2 is connected to the negative polarity source driver, and the data line data
  • Two of the two pixels adjacent in the column direction are different from the data lines connected to the two display domains in the other pixel, and are located in the pixels of the odd columns.
  • the two display domain regions are connected to the data lines of the first side of the respective columns, and the two display domain regions located in the pixels of the even columns are connected to the data lines of the second side of the respective columns, so that the rows are
  • the polarity of the voltage signals of the two pixels adjacent in the direction is opposite, and the polarities of the voltage signals of the two pixels adjacent in the column direction are opposite; the first side and the second side may respectively be different sides of one column, for example respectively Is the left and right side of the column. Specifically, taking the pixel 22 shown in FIG.
  • the two display domain regions in the pixel 22 are connected to the data line data4 that supplies the negative polarity voltage signal, so that a negative voltage signal is applied to the pixel 22, and since the pixel 22 is present at the pixel 22
  • the data lines connected to the pixels 12 and 32 adjacent to the pixel 22 in the column direction are the data lines data3 that provide the positive polarity voltage signal, so that the positive voltage signals are applied to the pixels 12 and 32;
  • the data line connected to the pixel 21 adjacent to the pixel 22 is the data line data1 that supplies the positive polarity voltage signal, and the other data line connected to the pixel 23 adjacent to the pixel 22 is the data line data5 that provides the positive polarity voltage signal.
  • the array substrate can also adopt the structure shown in FIG. 2a, and FIG. 2a is a schematic structural diagram of the array substrate of another structure provided in the embodiment, in the same row of pixels.
  • the two display domains in each pixel may also be connected to the data lines on the same side of the respective columns, and of the two pixels adjacent in the column direction, two of the pixels display the data of the domain connection.
  • the line is different from the data line connecting the two display domain regions in another pixel; taking the first row 11-14 shown in FIG. 2a as an example, the pixels 11, 12, 13, 14 are each corresponding to the corresponding column The data lines on one side are connected.
  • the array substrate of the structure shown in FIG. 2a realizes the dot-inversion driving in units of pixels, and the source drivers of the two data lines connected between adjacent two columns of pixels have the same polarity and are adjacent to each other.
  • the two data lines between the column pixels are a group, and the polarity of the source driver connected to each adjacent two sets of data lines is opposite; as shown in FIG. 3b, FIG. 3b is the array substrate applied in FIG. 2a.
  • the polarity distribution map of the voltage signal of each pixel is taken as an example.
  • the pixel 22 shown in FIG. 3b is taken as an example.
  • the polarity of the pixel adjacent to the pixel 22 in the row direction and the column direction is opposite to that of the pixel 22. Point in pixels Turn the drive.
  • dot inversion driving in units of pixels
  • the polarity of the source driver connected to the data line corresponding to one display domain is opposite to the polarity of the source driver connected to the data line corresponding to the other display domain; and adjacent in the column direction
  • the polarity of the source driver connected to the data line corresponding to one display domain region is opposite to the polarity of the source driver connected to the data line corresponding to the other display domain region
  • a dot inversion drive that displays the domain area as a unit.
  • FIG. 2b is a schematic diagram of another structure of the array substrate provided in the embodiment.
  • the data lines connected in the area are different, and the display domain areas in the same row are connected to the data lines on the same side of the corresponding pixel; see FIG. 3c, which is shown in FIG. 3c, which is applied to each pixel on the array substrate shown in FIG. 2b.
  • the source driver of the two data lines connected between each adjacent two columns of pixels when implementing the dot inversion driving in units of pixels, the source driver of the two data lines connected between each adjacent two columns of pixels
  • the polarity is the same, and the two data lines between two adjacent columns of pixels are grouped, and the polarity of the source drivers connected to each adjacent two sets of data lines is opposite, so that the array substrate in FIG. 2b is along
  • the polarity of the pixel voltage signals applied to the two display domain regions adjacent to each other in the row and column directions are opposite, and dot inversion driving in units of display domain regions is realized.
  • FIG. 2c is a schematic diagram of an array substrate of another structure provided by the embodiment.
  • any adjacent two display domain regions connected in the same column are connected. Different, and in the display domain region of the same row, the display domain regions of the odd rows are connected to the data lines on the first side of the corresponding pixel, and the display domain regions of the even rows are connected to the data lines on the second side of the corresponding pixel, the first side is The second side may be a different side of a column, for example, the left and right sides of the column, respectively.
  • FIG. 3d is a polarity distribution diagram of a voltage signal applied to each pixel on the array substrate shown in FIG.
  • the array substrate of the structure shown in FIG. 2c realizes a point in pixels.
  • the polarity of the source driver connected to two data lines between two adjacent columns of pixels is opposite, and each column of pixels
  • the polarity of the source driver connected to the two adjacent data lines on both sides is opposite, so that the polarities of the pixel voltage signals applied on the two display domain regions adjacent in the row and column direction in the array substrate in FIG. 2c are In contrast, dot inversion driving in units of display domain regions is realized.
  • the same data line does not need to be time-divided to provide voltage signals of different polarities, thereby reducing power consumption.
  • the switching device in the array substrate provided by the embodiment is a thin film transistor, and a source or a drain of each thin film transistor is connected to a data line of one side of the corresponding pixel.
  • the area of the two display domain regions may be the same or different; for example, in the array substrate shown in FIG. 1, two display domain regions in each pixel have different sizes.
  • the width-to-length ratio of the channel of the thin film transistor is set according to the size of the area of the display domain corresponding to the thin film transistor.
  • the two display domain regions respectively correspond to each other.
  • the width-to-length ratio of the channel of the thin film transistor is the same; and when the area of the two display domain regions in one pixel is different, the width and length ratio of the channel of the corresponding thin film transistor of the two display domains are different.
  • the ratio of the area of two pixels adjacent in the column direction is equal to the ratio of the channel width of the thin film transistors corresponding to the two pixels, thereby ensuring the synchronization of charging and discharging of the two pixels, and the display domain regions of different areas can be in the same time.
  • FIG. 4 and FIG. 5 are schematic structural diagrams of a display panel according to the embodiment.
  • the array substrate 02 provided in the first embodiment, and the color filter substrate 02 connected to the array substrate, the color filter substrate includes a plurality of sub-pixel regions distributed in an array, and the sub-pixel region is a light transmissive layer on the color filter substrate.
  • the sub-pixel defines an area.
  • the sub-pixel may be any one of three color sub-pixels of red, green and blue (RGB), and the projection of each sub-pixel area on the array substrate covers two adjacent displays. Domain area.
  • the projection of each sub-pixel region in the color filter substrate on the array substrate covers two adjacent display domain regions, and two display domain regions in each sub-pixel region can respectively acquire pixels by different data lines.
  • a voltage signal that adjusts the pixels provided by each display domain or the corresponding data line of each pixel The polarity of the voltage signal is such that the polarity of the pixel voltage signals of adjacent display domains or adjacent pixels is different.
  • the problem that the pixel charging time is reduced due to the pixel voltage signals of different polarities provided by the same data line in time division is improved, which is advantageous for realizing high frequency driving and reducing power consumption of the display panel.
  • the same data line does not need to be time-divided to provide voltage signals of different polarities, thereby reducing power consumption.
  • each sub-pixel region in the color filter substrate on the array substrate covers two adjacent display domain regions in two ways:
  • Implementation 1 As shown in FIG. 4, the two display domain regions covered by the projection of each sub-pixel region on the array substrate are located in the same pixel on the array substrate, that is, each sub-pixel region and the array substrate on the color filter substrate.
  • the adjacent two gate lines are aligned with the adjacent two data lines.
  • the two display regions in one sub-pixel region are provided by the same data line.
  • the polarity voltage signal has the same polarity of the voltage signals applied in different display domain regions in the same sub-pixel region to control the deflection of the liquid crystal molecules in the display domain region, which is advantageous for realizing wide viewing angle display of the display panel.
  • Implementation 2 As shown in FIG. 5, the two display domain regions covered by the projection of each sub-pixel region on the array substrate are located in two adjacent pixels on the array substrate.
  • each sub-pixel on the color filter substrate The pixel area is aligned with each pixel on the array substrate in the row direction, and is misaligned in the column direction, that is, one display domain is misaligned, or each sub-pixel area on the color filter substrate and each pixel on the array substrate are in the column direction.
  • the upper alignment is misaligned in the row direction, that is, one display domain is misaligned.
  • two display domain regions in one sub-pixel region are provided with voltage signals of opposite polarities by two different data lines, and are applied in different display domain regions in the same sub-pixel region.
  • the polarity of the voltage signals is reversed to control the deflection of the liquid crystal molecules in the display domain, which is advantageous for achieving a wide viewing angle display of the display panel.
  • the arrangement manner of the sub-pixel regions of the color filter substrate may be arranged in RGB order as shown in FIG. 4 and FIG. 5 .
  • the rows of the sub-pixel regions are arranged.
  • the column is not limited to the above.
  • the present embodiment provides a display device, including the display panel provided by the above embodiments.

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Abstract

一种阵列基板（01）及显示面板、显示装置。阵列基板（01）包括阵列分布的多个像素（11-34），每相邻两列像素（11-31，12-32）之间设置有两条数据线（data2，data3），且每列像素（11-31）两侧均设置有数据线（data1，data2）；每相邻两行像素（11-14，21-24）之间设置有一条栅线（gate2），且每行像素（11-14）两侧均设置有栅线（gate1，gate2）；每个像素（11）包括两个沿列方向排列的显示畴区（111，112），每个显示畴区（111，112）对应连接有一个开关器件（113，114）。

Description

阵列基板及显示面板、显示装置
相关申请的交叉引用
本申请要求于2016年8月31日提交的、名称为“阵列基板及显示面板、显示装置”的中国专利申请NO.201621024899.1的优先权，该专利申请的公开内容通过引用方式整体并入本文。
技术领域
本公开涉及显示技术领域，特别涉及一种阵列基板及显示面板、显示装置。
背景技术
目前，在一些宽视角液晶显示器中常使用多畴显示模式来增大显示器的观看视角。多畴显示模式指在一个亚像素内划分出多个区域，位于不同区域内的液晶的偏转角度不同，与传统的单畴显示模式相比，多畴显示模式可降低由于像素内的全部液晶的偏转角度相同而造成的不同观看视角上的对比度差异，进而增大了观看视角。
在采用多畴显示模式的液晶显示器中，需在其阵列基板的单个像素内提供不同的像素电压，以使液晶分子形成不同的偏转角度；阵列基板的像素由阵列基板上相邻的两条栅线和相邻的两条数据线包围的区域形成，一个像素一般由一个或两个位于一条栅线和一条数据线交叉处的薄膜晶体管控制。为实现在单个像素内提供不同的像素电压，目前一般采用一个像素内的一个或两个薄膜晶体管从同一条数据线分时提供不同极性的像素电压信号，采用此像素结构的阵列基板降低了像素的充电时间，不利于实现高频驱动。
公开内容
本公开提供一种阵列基板及显示面板、显示装置，该阵列基板可在多畴液晶显示模式下提高像素的充电时间，有利于实现高频驱动。
为实现上述目的，本公开提供如下的技术方案：
一种阵列基板，包括阵列分布的多个像素，其中：
每相邻两列像素之间设置有两条数据线，且每列像素两侧均设置有数据线；
每相邻两行像素之间设有一条栅线，且每行像素两侧均设置有数据线；
每个像素包括至少两个显示畴区，每个显示畴区对应连接有一个开关器件；
每个像素中，每个显示畴区通过对应的开关器件与对应的像素任意一侧的一条栅线连接；
每个像素中，每个显示畴区通过对应的开关器件与对应像素任意一侧的与所述像素紧邻的一条数据线连接。
本公开提供的阵列基板中，每相邻两列像素之间设置有两条数据线，且每列像素两侧均设置有数据线；每相邻两行像素之间设有一条栅线，且每行像素两侧均设置有数据线；每个像素包括至少两个显示畴区，每个显示畴区对应连接有一个开关器件；每个像素中，每个显示畴区通过对应的开关器件与对应的像素一侧的一条栅线连接，且每个像素至少一侧的栅线与对应像素中的显示畴区连接；每个像素中，每个显示畴区通过对应的开关器件与对应像素一侧的与所述像素紧邻的一条数据线连接，且每个像素至少一侧的数据线与对应像素中的显示畴区连接。
上述阵列基板中，相邻两列像素之间设有两条数据线，且每个像素的两侧均设有两条数据线，因此，每个像素中的至少两个显示畴区可分别由不同的数据线获取像素电压信号，或，每相邻两个像素可分别由不同的数据线获取像素电压信号，调整每个显示畴区或每个像素对应的数据线提供的像素电压信号的极性，即可使相邻的显示畴区或相邻的像素的像素电压信号极性不同。改善了由于同一数据线分时提供不同极性的像素电压信号带来的像素充电时间降低的问题，有利于实现高频驱动，且可降低显示面板功耗。
在一个实施例中，每个像素中的所述至少两个显示畴区沿对应像素的行方向依次分布；或，
每个像素中的所述至少两个显示畴区沿对应像素的列方向依次分布；或，
每个像素中的所述至少两个显示畴区呈阵列分布。
进一步地，阵列基板还包括与每个栅线连接的栅极驱动器，以及与每个数据线连接的源极驱动器，所述源极驱动器包括正极性源极驱动器和负极性源极驱动器。
进一步地，沿行方向相邻的任意两个像素中，一个像素内的所述至少两个显示畴区对应的数据线所连接的源极驱动器的极性与另一个像素内的所述至少两个显示畴区对应的数据线所连接的源极驱动器的极性相反。
进一步地，沿列方向相邻的任意两个像素中，一个像素内的所述至少两个显示畴区对应的数据线所连接的源极驱动器的极性与另一个像素内的所述至少两个显示畴区对应的数据线所连接的源极驱动器的极性相反。
进一步地，沿行方向相邻的任意两个显示畴区中，一个显示畴区对应的数据线所连接的源极驱动器的极性与另一个显示畴区对应的数据线所连接的源极驱动器的极性相反。
进一步地，沿列方向相邻的任意两个显示畴区中，一个显示畴区对应的数据线所连接的源极驱动器的极性与另一个显示畴区对应的数据线所连接的源极驱动器的极性相反。
在一个实施例中，所述开关器件为薄膜晶体管。
进一步地，每个像素中的所述两个显示畴区各自对应的薄膜晶体管的沟道的宽长比相同；或，
每个像素中的所述两个显示畴区各自对应的薄膜晶体管的沟道的宽长比不同。
本公开还提供了一种显示面板，包括如上所述的阵列基板，以及与所述阵列基板对盒连接的彩膜基板，所述彩膜基板包括多个阵列分布的子像素区域，每个子像素区域在所述阵列基板上的投影覆盖两个相邻的显示畴区。
在一个实施例中，每个子像素区域在所述阵列基板上的投影覆盖的两个显示畴区位于所述阵列基板上的同一个像素中。
在一个实施例中，每个子像素区域在所述阵列基板上的投影覆盖的两个显示畴区位于所述阵列基板上的相邻的两个像素中。
本公开还提供了一种显示装置，包括如上所述的显示面板。
附图说明
图1a是本公开一个实施例提供的一种阵列基板的结构示意图；
图1b是单个像素中的显示畴区排列方式示意图；
图1c是单个像素中的显示畴区排列方式示意图；
图1d是单个像素中的显示畴区排列方式示意图；
图2a是本公开一个实施例提供的阵列基板的另一种结构示意图；
图2b是本公开一个实施例提供的阵列基板的另一种结构示意图；
图2c是本公开一个实施例提供的阵列基板的另一种结构示意图；
图3a是施加在图1a中所示的阵列基板上的每个像素的电压信号的极性分布图；
图3b是施加在图2a中所示的阵列基板上的每个像素的电压信号的极性分布图；
图3c是施加在图2b中所示的阵列基板上的每个像素的电压信号的极性分布图；
图3d是施加在图2c中所示的阵列基板上的每个像素的电压信号的极性分布图；
图4是本公开另一实施例提供的一种显示面板的结构示意图；
图5是本公开另一实施例提供的显示面板的另一种结构示意图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
需要说明的是，附图中各部件的形状和大小不反映阵列基板的真实比例，目的只是示意说明本公开内容。
参见图1a所示，图1a是本实施例提供的一种阵列基板的结构示意图，该阵列基板01包括阵列分布的多个像素，例如图1a中所示的位于第一行的像素11-14，以及位于第一列的像素11-31，每个像素由交叉的两条数据线和两条栅线围绕形成，例如图1中所示的像素11即由栅线gate1、gate2和数据线data1、data2围绕形成；
每相邻两列像素之间设置有两条数据线，且每列像素两侧均设置有数据线；以图1a中所示的第一列像素11-31和第二列像素12-32为例，第一列像素11-31和第二列像素12-32之间设有两条数据线data2和data3，且第一列像素11-31的两侧设有数据线data1和数据线data2，第二列像素12-32的两侧设有数据线data3和数据线data4；
每相邻两行像素之间设有一条栅线，且每行像素两侧均设置有数据线；以图1a中所示的第一行像素11-14和第二行像素21-24为例，第一行像素11-14和第二行像素21-24之间设有一条栅线gate2，且第一行像素11-14的两侧设有栅线gate1和栅线gate2，第二行像素21-24两侧设有栅线gate2和栅线gate3；
每个像素包括两个显示畴区，每个显示畴区对应连接有一个开关器件；一个显示畴区为一个开关器件在一个像素内部所控制的区域，具体实施中，显示畴区内设有用于控制位于该显示畴区内的液晶分子的像素电极；以图1a中所示的像素11为例，11中设有两个显示畴区111和112，其中，显示畴区111和开关器件113对应连接，显示畴区112和开关器件114对应连接；
具体实施中，每个像素内的显示畴区至少为两个，每个像素内也可设置多个显示畴区，显示畴区在对应的像素内具有多种排列方式，具体参见图1a和图1d所示，图1d是单个像素中的显示畴区排列方式示意图，每个像素中的两个显示畴区沿对应像素的列方向依次分布；或，参见图1b所示，图1b是单个像素中的显示畴区排列方式示意图，每个像素中的两个显示畴区沿对应像素的 行方向依次分布；或，参见图1c所示，图1c是单个像素中的显示畴区排列方式示意图，每个像素中具有四个显示畴区，且四个显示畴区阵列分布；
每个像素中的每个显示畴区通过对应的开关器件与像素任意一侧的一条栅线连接，则每个像素中的显示畴区可与对应像素一侧或两侧的栅线连接；具体参见图1a中所示的像素11，像素11中的显示畴区111通过对应连接的开关器件113与栅线gate1连接，显示畴区112通过对应连接的开关器件114与栅线gate2连接；此外，参见图1b所示，图1b中的像素11中的两个显示畴区均与栅线gate1连接；
每个像素中的每个显示畴区通过对应的开关器件与像素任意一侧的与对应的像素相邻的一条数据线连接，则每个像素中的显示畴区可与对应像素一侧或两侧的数据线连接；具体参见图1a中所示的像素11，显示畴区111通过对应连接的开关器件113与数据线data2连接、显示畴区112也通过对应连接的开关器件114与数据线data2连接；此外，参见图1b或图1d所示，像素11中的两个显示畴区分别与数据线data1和data2连接；在像素中设有多个阵列分布的显示畴区时，显示畴区与栅线和数据线的连接方式与上述每个像素中设有两个显示畴区的情形类似，即多个阵列分布的显示畴区可均与同一条栅线或同一条数据线连接，或，多个阵列分布的显示畴区中的两部分分别与不同的栅线或数据线连接。
需要说明的是，在本实施例提供的阵列基板01中，行方向为栅线的延伸方向，列方向为数据线的延伸方向。
本公开提供的阵列基板01中，每相邻两列像素之间设置有两条数据线，且每列像素两侧均设置有数据线；每相邻两行像素之间设有一条栅线，且每行像素两侧均设置有数据线；每个像素包括至少两个显示畴区，每个显示畴区对应连接有一个开关器件；每个像素中，每个显示畴区通过对应的开关器件与对应的像素一侧的一条栅线连接，且每个像素至少一侧的栅线与对应像素中的显示畴区连接；每个像素中，每个显示畴区通过对应的开关器件与对应像素一侧 的与所述像素紧邻的一条数据线连接，且每个像素至少一侧的数据线与对应像素中的显示畴区连接。
上述阵列基板中，相邻两列像素之间设有两条数据线，且每个像素的两侧均设有两条数据线，因此，每个像素中的至少两个显示畴区可分别由不同的数据线获取像素电压信号，或，每相邻两个像素可分别由不同的数据线获取像素电压信号，调整每个显示畴区或每个像素对应的数据线提供的像素电压信号的极性，即可使相邻的显示畴区或相邻的像素的像素电压信号极性不同。改善了由于同一数据线分时提供不同极性的像素电压信号带来的像素充电时间降低的问题，有利于实现高频驱动，且可降低显示面板功耗。
本实施例提供的阵列基板可实现低功耗的多畴液晶显示的点反转驱动。液晶显示面板的驱动方式可以包括：帧反转(Frame Inversion)方式、线反转(Line Inversion)方式和点反转(Dot Inversion)方式，其中，点反转方式是指在一帧画面中，每一子像素与周边相邻的四个子像素的电压极性均相反。在点反转方式下，液晶显示面板的闪烁及串扰问题最少，显示效果最优。
下面具体说明实施例提供的阵列基板实现点反转驱动的实现方式：
具体实施中，本实施例提供的阵列基板还包括与每个栅线连接的栅极驱动器，以及与每个数据线连接的源极驱动器，源极驱动器包括正极性源极驱动器和负极性源极驱动器。
调整各个像素与源极驱动器的连接方式，使沿行方向相邻的任意两个像素中，一个像素内的所述至少两个显示畴区对应的数据线所连接的源极驱动器的极性与另一个像素内的所述至少两个显示畴区对应的数据线所连接的源极驱动器的极性相反；同时，使沿列方向相邻的任意两个像素中，一个像素内的所述至少两个显示畴区对应的数据线所连接的源极驱动器的极性与另一个像素内的所述至少两个显示畴区对应的数据线所连接的源极驱动器的极性相反，则可使行列方向上任意相邻的两个像素上施加的像素信号电压的极性相反，以实现以像素为单位的点反转驱动。
上述驱动方式的具体实施可参见图1a所示，每个像素中的显示畴区均连接到同一数据线，且沿列方向相邻的两个像素中，一个像素中的两个显示畴区连接的数据线与另一个像素中的两个显示畴区连接的数据线不同；以第一列像素11-31为例，沿列方向相邻的像素11、21中，像素11中的显示畴区111和112与位于第一列像素11-31一侧的数据线data2连接，像素12中的两个显示畴区与位于第一列像素11-31另一侧的数据线data1连接；
同一行像素中，位于奇数列的像素中的两个显示畴区与各自对应的列的第一侧的数据线连接，位于偶数列的像素中的两个显示畴区与各自对应的列的第二侧的数据线连接，第一侧与第二侧可以分别是一列的不同侧，例如分别是列的左侧和右侧。具体以图1中所示的第一行像素11-14为例，位于奇数列的像素11、13中，像素11中的两个显示畴区与对应的第一列11-31的第一侧的数据线data2连接，像素13中的两个显示畴区与对应的第三列13-33的第一侧的数据线data6连接；位于偶数列的像素12、14中，像素12中的两个显示畴区与对应的第二列12-32的第二侧的数据线data3连接，像素14中的两个显示畴区与对应的第四列14-34的第二侧的数据线data7连接。
参见图3a所示，图3a是施加在图1a中所示的阵列基板上的每个像素的电压信号的极性分布图，每相邻两列像素之间的两条数据线分别与正极性源极驱动器和负极性源极驱动器连接，且每列像素两侧的两条数据线分别与正极性源极驱动器和负极性源极驱动器连接；具体地，以第一列像素11-31和第二列像素12-32为例，第一列像素11-31一侧的数据线data1与正极性源极驱动器连接，而另一侧的数据线data2与负极性源极驱动器连接；第二列像素12-32一侧的数据线data3与正极性源极驱动器连接，而另一侧的数据线data4与负极性源极驱动器连接，从而使第一列像素11-31和第二列像素12-32之间的数据线data2与负极性源极驱动器连接，而数据线data3与正极性源极驱动器连接；
由于沿列方向相邻的两个像素中，一个像素中的两个显示畴区连接的数据线与另一个像素中的两个显示畴区连接的数据线不同，且位于奇数列的像素中 的两个显示畴区与各自对应的列的第一侧的数据线连接，位于偶数列的像素中的两个显示畴区与各自对应的列的第二侧的数据线连接，则使得沿行方向相邻的两个像素的电压信号的极性相反，且沿列方向相邻的两个像素的电压信号的极性相反；第一侧与第二侧可以分别是一列的不同侧，例如分别是列的左侧和右侧。具体以图3a中所示的像素22为例，像素22中的两个显示畴区与提供负极性电压信号的数据线data4连接，使像素22上施加负极性的电压信号，而由于在像素22所在列方向上与像素22相邻的像素12和32所连接的数据线为提供正极性电压信号的数据线data3，使得像素12和32上施加的是正极性的电压信号；在像素22所在行方向上与像素22相邻的像素21所连接的数据线是提供正极性电压信号的数据线data1，另一个与像素22相邻的像素23所连接的数据线是提供正极性电压信号的数据线data5，使得像素21和23上施加的是正极性的电压信号，则在行方向和列方向上与像素22相邻的像素的电压极性与像素22均相反，实现了以像素为单位的点反转驱动。
此外，为实现以像素为单位的点反转驱动，阵列基板还可采用图2a中所示结构，图2a是本实施例提供的另一种结构的阵列基板的结构示意图，在同一行像素中，每个像素中的两个显示畴区还可与各自对应的列的同一侧的数据线连接，而沿列方向相邻的两个像素中，一个像素中的两个显示畴区连接的数据线与另一个像素中的两个显示畴区连接的数据线不同；以图2a中所示的第一行11-14为例，像素11、12、13、14均与各自对应的列的第一侧的数据线连接。
图2a中所示结构的阵列基板在实现以像素为单位的点反转驱动时，每相邻两列像素之间的两条数据线连接的源极驱动器的极性相同，且以相邻两列像素之间的两条数据线为一组，每相邻两组数据线连接的源极驱动器的极性相反；具体参见图3b所示，图3b是施加在图2a中所示的阵列基板上的每个像素的电压信号的极性分布图，以图3b所示的像素22为例，在行方向和列方向上与像素22相邻的像素的电压极性与像素22均相反，实现了以像素为单位的点反 转驱动。
除上述以像素为单位实现点反转驱动之外，还可以显示畴区为单位实现点反转驱动，通过调整各个像素与源极驱动器的连接方式，使沿行方向相邻的任意两个显示畴区中，一个显示畴区对应的数据线所连接的源极驱动器的极性与另一个显示畴区对应的数据线所连接的源极驱动器的极性相反；且使沿列方向相邻的任意两个显示畴区中，一个显示畴区对应的数据线所连接的源极驱动器的极性与另一个显示畴区对应的数据线所连接的源极驱动器的极性相反，即可实现以显示畴区为单位的点反转驱动。
上述驱动方式的具体实施可参见图2b所示，图2b是本实施例提供的另一种结构的阵列基板示意图，图2b所示的阵列基板中，位于同一列的任意相邻两个显示畴区连接的数据线不同，且位于同一行的显示畴区均连接对应的像素同一侧的数据线；参见图3c所示，图3c是施加在图2b中所示的阵列基板上的每个像素的电压信号的极性分布图，图2b中所示结构的阵列基板在实现以像素为单位的点反转驱动时，每相邻两列像素之间的两条数据线连接的源极驱动器的极性相同，且以相邻两列像素之间的两条数据线为一组，每相邻两组数据线连接的源极驱动器的极性相反，则使图2b中的阵列基板中，沿行列方向相邻的两个显示畴区上施加的像素电压信号的极性均相反，实现了以显示畴区为单位的点反转驱动。
此外，参见图2c所示，图2c是本实施例提供的另一种结构的阵列基板示意图，图2c所示的阵列基板中，位于同一列的任意相邻两个显示畴区连接的数据线不同，且位于同一行的显示畴区中，奇数行的显示畴区连接对应的像素第一侧的数据线，偶数行的显示畴区连接对应的像素第二侧的数据线，第一侧与第二侧可以分别是一列的不同侧，例如分别是列的左侧和右侧。参见图3d所示，图3d是施加在图2c中所示的阵列基板上的每个像素的电压信号的极性分布图，图2c中所示结构的阵列基板在实现以像素为单位的点反转驱动时，每相邻两列像素之间的两条数据线连接的源极驱动器的极性相反，且每列像素 两侧相邻的两条数据线连接的源极驱动器的极性相反，则使图2c中的阵列基板中，沿行列方向相邻的两个显示畴区上施加的像素电压信号的极性均相反，实现了以显示畴区为单位的点反转驱动。
上述阵列基板与现有结构的阵列基板相比，在实现点反转显示模式时，同一数据线不需分时提供不同极性的电压信号，从而降低了功耗。
具体实施中，本实施例提供的上述阵列基板中的开关器件为薄膜晶体管，每个薄膜晶体管的源极或漏极与对应的像素的一侧的数据线连接。
每个像素中，两个显示畴区的面积可相同也可不同；例如图1中所示的阵列基板中，每个像素中的两个显示畴区的大小均不同。
进一步地，薄膜晶体管的沟道的宽长比根据薄膜晶体管对应的显示畴区的面积大小不同进行设置，在一个像素中的两个显示畴区的面积大小相同时，两个显示畴区各自对应的薄膜晶体管的沟道的宽长比相同；而在一个像素中的两个显示畴区的面积大小不相同时，两个显示畴区各自对应的薄膜晶体管的沟道的宽长比不同，沿列方向相邻的两个像素的面积比例等于两个像素对应的薄膜晶体管的沟道宽度的比例，从而确保该两个像素充放电的同步性，可使不同面积的显示畴区在相同时间内完成像素充电。
基于同一发明构思，本发明的另一实施例提供了一种显示面板，参见图4和图5所示，图4和图5是本实施例提供的一种显示面板的结构示意图，该显示面板包括上述实施例一提供的阵列基板02，以及与阵列基板对盒连接的彩膜基板02，彩膜基板包括多个阵列分布的子像素区域，子像素区域为彩膜基板上的一个透光的子像素定义的区域，具体实施中，该子像素可为红绿蓝(RGB)三种颜色的子像素中的任意一种，每个子像素区域在阵列基板上的投影覆盖两个相邻的显示畴区。
上述显示面板中，彩膜基板中的每个子像素区域在阵列基板上的投影覆盖两个相邻的显示畴区，每个子像素区域中的两个显示畴区可分别由不同的数据线获取像素电压信号，调整每个显示畴区或每个像素对应的数据线提供的像素 电压信号的极性，即可使相邻的显示畴区或相邻的像素的像素电压信号极性不同。改善了由于同一数据线分时提供不同极性的像素电压信号带来的像素充电时间降低的问题，有利于实现高频驱动，且可降低显示面板功耗。
同时，参见上述实施例中点反转驱动的实现方式，该显示基板在实现点反转显示模式时，同一数据线不需分时提供不同极性的电压信号，从而降低了功耗。
具体实施中，彩膜基板中的每个子像素区域在阵列基板上的投影覆盖两个在相邻的显示畴区可采用如下两种方式实现：
实现方式一：参见图4所示，每个子像素区域在阵列基板上的投影覆盖的两个显示畴区位于阵列基板上的同一个像素中，即彩膜基板上的每个子像素区域与阵列基板上的相邻两条栅线和相邻两条数据线交叉形成的区域对齐，则参见上述点反转模式的实现方式可知，一个子像素区域内的两个显示畴区由同一数据线提供相同极性的电压信号，在同一子像素区域内的不同显示畴区施加的电压信号的极性相同，以控制显示畴区的液晶分子偏转，有利于实现显示面板的宽视角显示。
实现方式二：参见图5所示，每个子像素区域在阵列基板上的投影覆盖的两个显示畴区位于阵列基板上相邻的两个像素中，具体实施中，彩膜基板上的每个子像素区域与阵列基板上每个像素在行方向上对齐，而在列方向上错位对齐，即错位一个显示畴区，或，彩膜基板上的每个子像素区域与阵列基板上每个像素在列方向上对齐，而在行方向上错位对齐，即错位一个显示畴区。则参见上述点反转模式的实现方式可知，一个子像素区域内的两个显示畴区由两条不同数据线提供相反极性的电压信号，在同一子像素区域内的不同显示畴区施加的电压信号的极性相反，以控制显示畴区的液晶分子偏转，有利于实现显示面板的宽视角显示。
需要说明的是，上述两种实现方式中，彩膜基板的子像素区域的排列方式可按照图4和图5中所示采用RGB顺序排列，具体实施中，子像素区域的排 列不限于上述方式。
基于同一发明构思，本实施例提供了一种显示装置，包括上述实施例提供的显示面板。
显然，本领域的技术人员可以对本公开实施例进行各种改动和变型而不脱离本公开的精神和范围。这样，倘若本公开的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (13)

  1. 一种阵列基板，包括阵列分布的多个像素，其中：
    每相邻两列像素之间设置有两条数据线，且每列像素两侧均设置有数据线；
    每相邻两行像素之间设有一条栅线；
    每个像素包括至少两个显示畴区，每个显示畴区对应连接有一个开关器件；
    每个像素中的每个显示畴区通过对应的开关器件与该像素的任意一侧的一条栅线连接；
    每个像素中的每个显示畴区通过对应的开关器件与该像素的任意一侧的与所述像素紧邻的一条数据线连接。
  2. 根据权利要求1所述的阵列基板，其中，每个像素中的所述至少两个显示畴区沿对应像素的行方向依次分布；或，
    每个像素中的所述至少两个显示畴区沿对应像素的列方向依次分布；或，
    每个像素中的所述至少两个显示畴区以阵列的形式分布。
  3. 根据权利要求1或2所述的阵列基板，其中，还包括与每个栅线连接的栅极驱动器，以及与每个数据线连接的源极驱动器，所述源极驱动器包括正极性源极驱动器和负极性源极驱动器。
  4. 根据权利要求3所述的阵列基板，其中，沿行方向相邻的任意两个像素中，一个像素内的所述至少两个显示畴区对应的数据线所连接的源极驱动器的极性与另一个像素内的所述至少两个显示畴区对应的数据线所连接的源极驱动器的极性相反。
  5. 根据权利要求4所述的阵列基板，其中，沿列方向相邻的任意两个像素中，一个像素内的所述至少两个显示畴区对应的数据线所连接的源极驱动器的极性与另一个像素内的所述至少两个显示畴区对应的数据线所连接的源极驱动器的极性相反。
  6. 根据权利要求3所述的阵列基板，其中，沿行方向相邻的任意两个显示畴区中，一个显示畴区对应的数据线所连接的源极驱动器的极性与另一个显示畴区对应的数据线所连接的源极驱动器的极性相反。
  7. 根据权利要求6所述的阵列基板，其中，沿列方向相邻的任意两个显示畴区中，一个显示畴区对应的数据线所连接的源极驱动器的极性与另一个显示畴区对应的数据线所连接的源极驱动器的极性相反。
  8. 根据权利要求1-7任一项所述的阵列基板，其中，所述开关器件为薄膜晶体管。
  9. 根据权利要求8所述的阵列基板，其中，每个像素中的所述任意两个显示畴区各自对应的薄膜晶体管的沟道的宽长比相同；或，
    每个像素中的所述任意两个显示畴区各自对应的薄膜晶体管的沟道的宽长比不同。
  10. 一种显示面板，其中，包括如权利要求1-9任一项所述的阵列基板，以及与所述阵列基板对盒连接的彩膜基板，所述彩膜基板包括多个呈阵列分布的子像素区域，每个子像素区域在所述阵列基板上的投影覆盖两个相邻的显示畴区。
  11. 根据权利要求10所述的显示面板，其中，每个子像素区域在所述阵列基板上的投影覆盖的两个显示畴区位于所述阵列基板上的同一个像素中。
  12. 根据权利要求10所述的显示面板，其中，每个子像素区域在所述阵列基板上的投影覆盖的两个显示畴区位于所述阵列基板上的相邻的两个像素中。
  13. 一种显示装置，其中，包括如权利要求10-12任一项所述的显示面板。
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