WO2018205318A1 - 一种tft阵列基板及其制作方法 - Google Patents

一种tft阵列基板及其制作方法 Download PDF

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Publication number
WO2018205318A1
WO2018205318A1 PCT/CN2017/086233 CN2017086233W WO2018205318A1 WO 2018205318 A1 WO2018205318 A1 WO 2018205318A1 CN 2017086233 W CN2017086233 W CN 2017086233W WO 2018205318 A1 WO2018205318 A1 WO 2018205318A1
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Prior art keywords
layer
gate electrode
buffer layer
patterning
bottom gate
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PCT/CN2017/086233
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English (en)
French (fr)
Inventor
曾勉
刘晓娣
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Priority to US15/541,343 priority Critical patent/US10290666B2/en
Publication of WO2018205318A1 publication Critical patent/WO2018205318A1/zh
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0241—Manufacture or treatment of multiple TFTs using liquid deposition, e.g. printing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/471—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having different architectures, e.g. having both top-gate and bottom-gate TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a TFT array substrate and a method of fabricating the same.
  • Dual gate TFT double gate transistor
  • Single-gate TFT single-gate thin film transistor
  • Vth threshold voltage
  • the threshold voltage is more important, stable, uniform threshold voltage can make AMOLED display brightness more uniform, display quality is higher.
  • the thickness of the buffer layer corresponding to the bottom gate electrode is too thick, which affects the ability of the bottom gate electrode to control the performance of the entire array substrate, thereby affecting the overall performance of the display panel.
  • the present invention provides a TFT array substrate and a method for fabricating the same, which can reduce the thickness of the buffer layer region corresponding to the bottom gate electrode to serve as a bottom gate insulating layer, and improve the ability of the bottom gate electrode to control the performance of the array substrate.
  • a first embodiment of the present invention provides a method for fabricating a TFT array substrate, comprising: providing a substrate; depositing a light shielding metal layer on the substrate; and patterning the light shielding metal layer to form a bottom gate electrode Depositing a buffer layer on the bottom gate electrode and the substrate, patterning the buffer layer such that the buffer layer above the bottom gate electrode is thinned, and the thickness of the thinned region of the buffer layer is set such that the buffer layer is thinned a region is used as a bottom gate insulating layer between the bottom gate electrode and the semiconductor pattern; a semiconductor layer is deposited on the buffer layer, and the semiconductor layer is patterned to form a semiconductor disposed opposite to the bottom gate electrode in the thinned region of the buffer layer a pattern; wherein the mask used for patterning the buffer layer is the same mask as the mask used for patterning the semiconductor layer or the mask used for patterning the light-shielding metal layer.
  • a second embodiment of the present invention provides a method for fabricating a TFT array substrate, comprising: providing a substrate; depositing a light shielding metal layer on the substrate; and patterning the light shielding metal layer to form a bottom gate electrode Depositing a buffer layer on the bottom gate electrode and the substrate, patterning the buffer layer such that the buffer layer above the bottom gate electrode is thinned; depositing a semiconductor layer on the buffer layer, and patterning the semiconductor layer to A semiconductor pattern disposed opposite to the bottom gate electrode is formed in the thinned region of the buffer layer.
  • a third embodiment of the present invention provides a TFT array substrate, including: a substrate; a bottom gate electrode formed on the substrate; and a buffer layer for covering the bottom gate electrode and the substrate, wherein the buffer layer is disposed a thinned region of the bottom gate electrode; a semiconductor pattern formed in the thinned region and disposed opposite to the bottom gate electrode.
  • the TFT array substrate of the present invention is formed by depositing a light-shielding metal layer on the substrate, and patterning the light-shielding metal layer to form a bottom gate electrode, thereby Depositing a buffer layer on the substrate having the bottom gate electrode and patterning the buffer layer to thin the buffer layer corresponding to the bottom gate electrode, further depositing a semiconductor layer on the buffer layer, and patterning the semiconductor layer Thereafter, a semiconductor pattern disposed opposite to the bottom gate electrode is formed in the thinned region of the buffer layer. Therefore, the buffer layer of the thinned region of the TFT array substrate of the present invention can be used as the bottom gate insulating layer corresponding to the bottom gate electrode, thereby improving the control of the performance of the entire gate substrate by the bottom gate electrode.
  • FIG. 1 is a schematic flow chart of a method for fabricating an array substrate according to an embodiment of the invention
  • FIG. 2 is a schematic flow chart of a method for fabricating an array substrate according to still another embodiment of the present invention.
  • FIG. 3 to FIG. 13 are schematic views showing a manufacturing process of fabricating an array substrate by the manufacturing method of FIG. 2.
  • FIG. 1 is a schematic flow chart of a first embodiment of a method for fabricating a TFT array substrate according to the present invention. As shown in FIG. 1 , a method for fabricating a TFT array substrate of the present embodiment includes:
  • the substrate 100 is a transparent substrate, and may be a glass substrate, a plastic substrate or a flexible substrate of another suitable material, which is not limited herein.
  • S102 depositing a light-shielding metal layer 110 on the substrate 100, and patterning the light-shielding metal layer 110 to form the bottom gate electrode 101.
  • a light-shielding metal layer 110 is sputtered on the substrate 100.
  • the material of the light-shielding metal layer 110 includes, but is not limited to, a stack combination of one or more of metal materials such as molybdenum, aluminum, copper, titanium, and the like.
  • the light shielding metal layer 110 is patterned to form the bottom gate electrode 101.
  • S103 depositing a buffer layer 120 on the bottom gate electrode 101 and the substrate 100, and patterning the buffer layer 120 such that the buffer layer 120 above the bottom gate electrode 101 is thinned.
  • a buffer layer 120 is further deposited on the substrate 100 on which the bottom gate electrode 101 is formed.
  • the material of the buffer layer 120 may be silicon oxide and/or silicon nitride, and the buffer layer 120 is patterned to correspond to the bottom gate.
  • the buffer layer 120 above the electrode 101 is thinned.
  • S104 depositing a semiconductor layer on the buffer layer 120 and patterning the semiconductor layer.
  • a semiconductor layer (not shown) is deposited on the buffer layer 120.
  • the material of the semiconductor layer may be a metal oxide semiconductor, which is simplified by using high electron mobility and compatibility with an amorphous silicon process. Process, the purpose of reducing production costs.
  • the semiconductor layer is patterned to form a semiconductor pattern 102 disposed opposite to the bottom gate electrode 101 in the thinned region of the buffer layer 120.
  • the bottom gate electrode 101 can be improved to the array substrate. 200 performance control.
  • the manufacturing method of the array substrate 200 of this embodiment includes:
  • S202 depositing a light-shielding metal layer 110 on the substrate 100, and patterning the light-shielding metal layer 110 to form the bottom gate electrode 101.
  • the steps S201-S202 are similar to the steps S101-S102 of the foregoing embodiment, and details are not described herein again. It should be noted that the materials of the substrate 100 and the light shielding metal layer 110 of the present embodiment and the substrate 100 and the light shielding metal layer 110 of the above embodiments may be the same or different.
  • S203 depositing a buffer layer 120 on the bottom gate electrode 101 and the substrate 100, and patterning the buffer layer 120 such that the buffer layer 120 above the bottom gate electrode 101 is thinned.
  • a buffer layer 120 is deposited on the substrate 100 having the bottom gate electrode 101.
  • the material of the buffer layer 120 may be one or a combination of silicon oxide or silicon nitride.
  • the deposition buffer layer 120 can provide a good interface for the subsequent deposition of the semiconductor layer (not shown).
  • the thickness of the deposited buffer layer 120 is designed to prevent impurities such as alkali metal ions on the substrate 100 from contaminating the semiconductor layer. should.
  • the buffer layer 120 is exposed, developed, and etched by a mask process such that the buffer layer 120 over the bottom gate electrode 101 is thinned, wherein the thickness of the thinned region of the buffer layer 120 is set such that the buffer layer 120
  • the thinned region serves as the bottom gate insulating layer 121 between the bottom gate electrode 101 and the subsequently formed semiconductor pattern 102, thereby improving the control of the performance of the array substrate 200 by the bottom gate electrode 101.
  • S204 depositing a semiconductor layer on the buffer layer 120 and patterning the semiconductor layer.
  • a semiconductor layer is deposited on the buffer layer 120, and the material of the semiconductor layer may be a metal oxide semiconductor.
  • the semiconductor layer is patterned by a mask process to form a semiconductor pattern 102 disposed opposite to the bottom gate electrode 101 in the thinned region of the buffer layer 120 such that the thinned region of the buffer layer 120 serves as the bottom gate electrode 101.
  • step S201 to step S204 the mask used for patterning the buffer layer 120 is masked by a mask process, and the mask used for patterning the semiconductor layer or the masking layer 110 is patterned.
  • the mask used is the same mask, which simplifies the process and saves mask cost.
  • the mask used for patterning the buffer layer 120 is the same mask as the mask used for patterning the semiconductor layer and the mask used for patterning the light-shielding metal layer 110.
  • the region where the light-shielding metal layer 110 and the semiconductor are etched is different from the region where the buffer layer 120 is etched. Therefore, in this embodiment, the photoresist layer used for patterning the semiconductor layer can be set.
  • the photoresist layer used for patterning the light-shielding metal layer 110 is one of a positive photoresist layer and a negative photoresist layer, and the photoresist layer used for patterning the buffer layer 120 is positive.
  • the other of the photoresist layer and the negative photoresist layer enables development etching of the buffer layer 120 and the different regions of the light-shielding metal layer 110 and the semiconductor layer without adding a new mask.
  • a light shielding metal layer 110 is deposited on the substrate 100, and a photoresist layer (not shown) is deposited on the light shielding metal layer 110.
  • the thickness of the light-shielding metal layer 110 is about 100 nm, the material is molybdenum, and the photoresist layer is a positive photoresist layer.
  • the positive photoresist layer is exposed and developed by using a mask (not shown), wherein the mask includes a light transmitting portion and a light blocking portion, and the light shielding portion of the mask corresponds to the region 101' to be etched into the bottom gate electrode.
  • the light portion corresponds to a region other than the region 101 ′ corresponding to the bottom gate electrode to be etched, and the positive photoresist layer is exposed and developed by using a mask to obtain a cover corresponding to the bottom gate electrode region 101 ′ to be etched.
  • the positive photoresist pattern 201 is as shown in FIG.
  • the light-shielding metal layer 110 is etched by etching the light-shielding metal layer 110 to the positive-resistance pattern 201, so that the region 101' to be etched into the bottom gate electrode is left to form the bottom gate electrode 101, and The light-shielding metal layer 110 covered by the positive photoresist pattern 201 is etched away, and then the positive photoresist pattern 201 is removed to form a bottom gate electrode 101 over the substrate 100, as shown in FIG.
  • Step S203 referring to FIG. 5-6, a buffer layer 120 is deposited on the substrate 100 on which the bottom gate electrode 101 is formed by chemical vapor deposition.
  • the buffer layer 120 is made of silicon oxide and has a thickness of about 300 nm.
  • the buffer layer 120 functions in this embodiment to provide a good interface for the subsequently deposited semiconductor layer, and its thickness is designed to prevent alkali metal plasma on the substrate 100 from contaminating the subsequently deposited semiconductor layer.
  • a photoresist layer (not shown) is deposited over the buffer layer 120, and the photoresist layer is a negative photoresist layer.
  • the negative photoresist layer is subjected to exposure and development using a mask so that the light shielding portion of the mask corresponds to the region to be thinned.
  • the bottom gate electrode 101 is formed by using a light-shielding metal in the embodiment, and the buffer layer 120 is transparent due to the material properties of the buffer layer 120. Therefore, in the present embodiment, a self-alignment technique can be employed such that the light shielding portion of the mask corresponds to the region of the bottom gate electrode 101, and the light transmitting portion corresponds to other regions than the region of the bottom gate electrode 101.
  • a negative photoresist pattern 301 covering a region other than the region other than the bottom gate electrode 101 is obtained, as shown in FIG.
  • the buffer layer 120 is etched by the negative photoresist pattern 301 such that the region of the buffer layer 120 that is not covered by the negative photoresist pattern 301 is thinned and covered by the negative photoresist pattern 301
  • the thickness of the region is preserved, that is, the buffer layer 120 corresponding to the upper gate electrode 101 is thinned, and the thinned region is used as the bottom gate insulating layer 121 of the bottom gate electrode 101, and the negative photoresist pattern 301 is removed to form a bottom gate.
  • the buffer layer 120 of the electrode 101, and the region of the buffer layer 120 corresponding to the bottom gate electrode 101 is thinned as the bottom gate insulating layer 121, as shown in FIG.
  • the thickness of the bottom gate insulating layer 121 is controllable.
  • the buffer layer 120 can be patterned by using a dry etching method, and by controlling the power of the plasma during the dry etching and the etching speed, the controllable adjustment needs to be retained as the thinned region of the buffer layer 120. thickness of.
  • the thickness of the thinned region of the buffer layer 120 is preferably the bottom gate insulating layer 121 of the array substrate 200 suitable as a double gate structure, so as to improve the ability of the bottom gate electrode 101 to control the performance of the entire array substrate 200.
  • the bottom gate electrode 101 can be patterned by using the same mask, and the buffer layer 120 corresponding to the upper gate electrode 101 can be thinned, and only needs to be over the bottom gate electrode 101.
  • the photoresist layer and the photoresist layer overlying the buffer layer 120 can be disposed with different photoresists without redesigning the mask and reducing the generation cost.
  • by forming the bottom gate electrode 101 by using the light-shielding metal layer 110 it is also convenient to implement a self-alignment process in the mask process, improve the alignment precision, and improve the production efficiency.
  • the thickness of the thinned region of the buffer layer 120 can be controlled, and the thinned region of the buffer layer 120 can be reduced to be excessively etched or the thickness of the thinned region is too thick. The risk of improving the ability of the bottom gate electrode 101 to control the performance of the entire array substrate 200 cannot be achieved.
  • Step S204 depositing a semiconductor layer on the buffer layer 120 and depositing a photoresist layer over the semiconductor layer.
  • the material of the semiconductor layer can be selected as IGZO (Indium Gallium Zinc Oxide; indium gallium zinc oxide) having a thickness of about 60 nm and a photoresist layer being a positive photoresist layer.
  • the semiconductor layer is patterned by a mask, and the process is similar to the process of fabricating the bottom gate electrode 101.
  • the light shielding portion of the mask corresponds to the thinned region, and the light transmitting portion corresponds to other regions than the thinned region.
  • the semiconductor pattern 102 disposed opposite to the bottom gate electrode 101 is formed in the thinned region of the buffer layer 120.
  • the difference from the above embodiment is that a negative photoresist layer is covered over the light shielding metal layer 110, a positive photoresist layer is covered over the buffer layer 120, and a negative photoresist is covered over the semiconductor layer. Floor. Then, the negative photoresist layer on the light-shielding metal layer 110, the positive photoresist layer on the buffer layer 120, and the negative photoresist layer on the semiconductor layer are respectively exposed, developed, and etched by using the same mask to obtain and The array substrate 200 of the same structure as the above embodiment.
  • the light-transmitting portion of the mask corresponds to a region to be etched into the bottom gate electrode 101, and the light-shielding portion corresponds to In addition to the region to be etched into the region of the bottom gate electrode, and for the positive photoresist layer covered over the buffer layer 120, the light-transmitting region of the mask corresponds to the region to be thinned of the buffer layer 120.
  • the development etching process is similar to the above embodiment, and will not be described herein.
  • S205 depositing a top gate insulating layer (not shown) and a top gate metal layer (not shown) on the semiconductor pattern 102 and the buffer layer 120, and patterning at least the top gate metal layer.
  • a top gate insulating layer is deposited on the semiconductor pattern 102 and the buffer layer 120 using a chemical vapor deposition method, and a top gate metal layer is sputtered over the top gate insulating layer.
  • the material of the top gate insulating layer may be silicon oxide and/or silicon chloride, the thickness of the top gate insulating layer is about 150 nm, and the material of the top gate metal layer may be one of metals such as copper, molybdenum, titanium, aluminum, and the like. Or a plurality of stacks, and the material of the top gate metal layer may be the same as or different from the material of the bottom gate electrode 101.
  • At least the top gate metal layer is patterned using a mask process to form a top gate electrode 104 disposed opposite the semiconductor pattern 102.
  • the top gate insulating layer and the top gate metal layer are simultaneously patterned by using a mask.
  • the top gate insulating layer pattern 103 and the top gate electrode 104 are formed, and the top gate insulating layer pattern 103 and the top gate electrode 104 do not completely cover the semiconductor pattern 102.
  • the top gate insulating layer pattern 103 and the top gate are formed.
  • the electrode 104 covers the intermediate portion of the semiconductor pattern 102.
  • S206 Conducting a region of the metal oxide semiconductor pattern 102 on both sides of the top gate electrode 104 with the top gate electrode 104 as a mask.
  • the present embodiment may employ the patterned gate electrode 104 as a mask and the top gate of the metal oxide semiconductor pattern 102.
  • the areas on both sides of the electrode 104 are conductorized.
  • the top gate electrode 104 as a mask, the two sides of the metal oxide semiconductor pattern 102 are subjected to laser conductor treatment by an automatic alignment adjustment technique, so that the two sides of the metal oxide semiconductor pattern 102 are electrically conductive, such as Figure 9 shows. Therefore, the embodiment does not need to design an additional mask to conduct the conductor pattern 102, thereby reducing the process cost.
  • S207 depositing an interlayer dielectric layer 130 on the top gate electrode 104, the metal oxide semiconductor pattern 102, and the buffer layer 120, and patterning the interlayer dielectric layer 130.
  • An interlayer dielectric layer 130 is deposited on the top gate electrode 104, the metal oxide semiconductor pattern 102 and the buffer layer 120 by vapor deposition.
  • the material of the interlayer dielectric layer 130 may be silicon oxide, silicon nitride or both. Combined, the thickness is about 400 nm.
  • the interlayer dielectric layer 130 is patterned by a mask process to form first vias 131 and second vias 132 respectively located on both sides of the metal oxide semiconductor pattern 102, as shown in FIG.
  • S208 depositing a source/drain metal layer (not shown) on the interlayer dielectric layer 130, and patterning the source/drain metal layers to form source electrodes 142 respectively located on both sides of the top gate electrode 104 and Drain 141.
  • a source/drain metal layer is deposited on the interlayer dielectric layer 130, and the source/drain metal layer is patterned by a mask process to form source 142 and drain respectively on both sides of the top gate electrode 104.
  • the electrode 141 and the source 142 are electrically connected to the two side regions of the MOS pattern 102 through the first via 131 and the second via 132, that is, the source 142 and the drain 141 are respectively oxidized with the metal.
  • the conductors on both sides of the semiconductor pattern 102 are electrically connected as shown in FIG.
  • S209 depositing a passivation layer 150 on the source 142, the drain 141, and the interlayer dielectric layer 130, and patterning the passivation layer 150.
  • a passivation layer 150 is deposited over the source 142, the drain 141, and the interlayer dielectric layer 130.
  • the material of the passivation layer 150 may be silicon oxide and/or silicon nitride, and has a thickness of about 200 nm.
  • the passivation layer 150 is patterned by a mask process to form a third via 151 corresponding to the source 142 or the drain 141, as shown in FIG.
  • S210 depositing a transparent conductive layer (not shown) on the passivation layer 150, and patterning the transparent conductive layer to form the pixel electrode 105.
  • a transparent conductive layer is sputtered on the passivation layer 150, and the material of the transparent conductive layer may be ITO (Indium tin) Oxide; indium tin oxide), the transparent conductive layer is patterned by a mask process to form the pixel electrode 105, and the pixel electrode 105 is electrically connected to the source 142 or the drain 141 through the third via 151. As shown in FIG. 13, the pixel electrode 105 is electrically connected to the source 142 through the third via 151.
  • the thickness data values of the portions of the array substrate 200 described in this embodiment such as the thickness of the light-shielding metal layer 110 is about 100 nm.
  • the thickness of the buffer layer 120 is about 300 nm, etc., and those skilled in the art can understand that the data values are merely illustrative. The invention should not be limited thereto. In other embodiments, the thickness of each layer of the array substrate 200 can be used. Other data values.
  • the array substrate 200 is a TFT backplane of an AMOLED, it is further required to further cover a passivation layer 150 with a flat layer (not shown) and pass the mask layer through a mask process.
  • the patterning process is performed to form a fourth via hole (not shown) that communicates with the third via hole 151.
  • the pixel electrode 105 is formed on the flat layer, and is electrically connected to the source 142 or the drain 141 through the fourth via and the third via 151.
  • the patterning process of the bottom gate electrode 101, the buffer layer 120, and the semiconductor layer can be realized by the same mask, and the top gate electrode 104 is used as a mask.
  • the film can realize the conductor treatment on both sides of the semiconductor pattern 102, and the above processes do not need to design a new mask, reduce the number of masks, improve production efficiency, and reduce production cost.
  • the buffer layer 120 of the present embodiment can be used both as the bottom gate insulating layer 121 and as the buffer layer 120, and can be thinned by the buffer layer 120 corresponding to the bottom gate electrode 101, and can be controlled and adjusted.
  • the thickness of the buffer layer 120 of the thinned region is such that the thinned region is suitable as the bottom gate insulating layer 121, and the ability of the bottom gate electrode 101 to control the performance of the entire array substrate 200 is improved, and other regions of the buffer layer 120 that are not thinned are further
  • the alkali metal plasma on the substrate 100 can be prevented from contaminating the subsequently deposited semiconductor layer, improving the overall performance of the active matrix substrate 200.
  • the present invention also provides a TFT array substrate 200.
  • the array substrate 200 is fabricated in the above manner. As shown in FIG. 13, the substrate 200 includes a substrate 100, a bottom gate electrode 101 formed on the substrate 100, and a bottom gate electrode 101. And the buffer layer 120 of the substrate 100 and the semiconductor pattern 102.
  • the buffer layer 120 is provided with a thinned region corresponding to the upper surface of the bottom gate electrode 101.
  • the semiconductor pattern 102 is disposed in the thinned region and disposed opposite to the bottom gate electrode 101.
  • the thickness of the thinned region of the buffer layer 120 is set such that the thinned region of the buffer layer 120 serves as the bottom gate insulating layer 121 between the bottom gate electrode 101 and the semiconductor pattern 102. Therefore, the embodiment
  • the buffer layer 120 of the array substrate 200100 can be realized as the bottom gate insulating layer 121, and can also serve as a buffering function, and the thinned region thereof serves as the bottom gate insulating layer 121, which can improve the performance of the bottom gate electrode 101 to the entire array substrate 200.
  • the controllability of the buffer layer 120 prevents impurities such as alkali metal ions on the substrate 100 from contaminating the semiconductor pattern 102.
  • the array substrate of the present invention is formed by patterning a light-shielding metal layer to form a bottom gate electrode, thereby depositing a buffer layer on the bottom gate electrode and the substrate, and buffer layer. Performing a patterning process such that the buffer layer above the bottom gate electrode is thinned, further depositing a semiconductor layer on the buffer layer and patterning the semiconductor layer to form a bottom gate electrode in the thinned region of the buffer layer The semiconductor pattern is disposed.
  • the buffer layer of the embodiment can be thinned, and the thinned region can be used as the bottom gate insulating layer of the bottom gate electrode, thereby improving the control ability of the bottom gate electrode to the performance of the entire array substrate, and The other regions of the buffer layer are maintained to a certain thickness to prevent alkali metal plasma impurities on the substrate from contaminating the semiconductor layer.

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  • Thin Film Transistor (AREA)

Abstract

一种TFT阵列基板（200）及其制作方法，其中TFT阵列基板（200）的制作方法包括使用遮光金属（110）在基板（100）上形成底栅电极（101），进而在形成有底栅电极（101）的基板（100）上沉积缓冲层（120），并对该缓冲层（120）进行图案化处理，使得对应于底栅电极（101）上方的缓冲层（120）被薄化，进一步在缓冲层（120）上的薄化区域内形成与底栅电极（101）相对设置的半导体图案（102）。因此，通过减薄缓冲层（120）对应于底栅电极（101）区域的厚度，提高底栅电极（101）对整个阵列基板（200）性能的控制能力。

Description

一种TFT阵列基板及其制作方法
【技术领域】
本发明涉及显示技术领域，特别是涉及一种TFT阵列基板及其制作方法。
【背景技术】
在有源阵列显示装置中，由于采用Dual gate TFT（双栅极晶体管）比Single-gate TFT(单栅极薄膜晶体管)具有较高的迁移率，较大的开态电流，更小的亚阈值摆幅，阈值电压（Vth）稳定性和均匀性好等优点，可以较好的控制阈值电压偏移，从而更好的保证显示面板的显示品质。特别是对于AMOLED（Active Matrix Organic Light Emitting Diode；有源矩阵有机发光二极体）显示装置，阈值电压的重要性更为突出，稳定、均匀的阈值电压可以使AMOLED的显示亮度更均匀，显示品质较高。然而，传统的Dual-Gate TFT阵列基板的制造方法的底栅电极对应的缓冲层的厚度过厚，影响底栅电极对整个阵列基板性能的控制能力，进而影响显示面板的整体性能。
【发明内容】
有鉴于此，本发明提供一种TFT阵列基板及其制作方法，实现减薄底栅电极对应的缓冲层区域的厚度以作为底栅绝缘层，提高底栅电极对阵列基板的性能的控制能力。
为解决上述问题，本发明的第一实施例提供一种TFT阵列基板的制作方法，包括：提供一基板；在基板上沉积遮光金属层，对遮光金属层进行图案化处理，以形成底栅电极；在底栅电极及基板上沉积缓冲层，对缓冲层进行图案化处理，以使得底栅电极上方的缓冲层被薄化，且缓冲层的薄化区域的厚度设置成使得缓冲层的薄化区域作为底栅电极与半导体图案之间的底栅绝缘层；在缓冲层上沉积半导体层，对半导体层进行图案化处理，以在缓冲层的薄化区域内形成与底栅电极相对设置的半导体图案；其中，对缓冲层进行图案化处理所使用的掩膜与对半导体层进行图案化处理所使用的掩膜或对遮光金属层进行图案化处理所使用的掩膜为同一掩膜。
为解决上述问题，本发明的第二实施例提供一种TFT阵列基板的制作方法，包括：提供一基板；在基板上沉积遮光金属层，对遮光金属层进行图案化处理，以形成底栅电极；在底栅电极及基板上沉积缓冲层，对缓冲层进行图案化处理，以使得底栅电极上方的缓冲层被薄化；在缓冲层上沉积半导体层，对半导体层进行图案化处理，以在缓冲层的薄化区域内形成与底栅电极相对设置的半导体图案。
为解决上述问题，本发明的第三实施例提供一种TFT阵列基板，包括：基板；底栅电极，形成在基板上；缓冲层，用于覆盖底栅电极和基板，其中缓冲层设置有位于底栅电极的薄化区域；半导体图案，形成于薄化区域内且与底栅电极相对设置。
通过上述方案，本发明的有益效果是：区别于现有技术，本发明的TFT阵列基板的通过在基板上沉积遮光金属层，对该遮光金属层进行图案化处理以形成底栅电极，进而在具有底栅电极的基板上沉积缓冲层并对该缓冲层进行图案化处理，以使得对应于底栅电极上方的缓冲层薄化，在缓冲层上进一步沉积半导体层并对该半导体层图案化处理后，使得在缓冲层的薄化区域内形成与底栅电极相对设置的半导体图案。因此，本发明的TFT阵列基板的薄化区域的缓冲层可用作底栅电极对应的底栅绝缘层，提高底栅电极对整个阵列基板的性能的控制。
【附图说明】
图1是本发明一实施例的阵列基板的制作方法的流程示意图；
图2是本发明又一实施例的阵列基板的制作方法的流程示意图；
图3-图13是采用图2的制作方法制作阵列基板的制作工艺示意图。
【具体实施方式】
为了使本发明所要解决的技术问题、技术方案及有益效果更加清楚、明白，以下结合附图和实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
请参看图1，图1是本发明TFT阵列基板的制作方法的第一实施方式的流程示意图，如图1所示，本实施方式的TFT阵列基板的制作方法包括：
S101：提供一基板100。
基板100为透明基板，可选为玻璃基板、塑料基板或其他合适材质的可挠性基板，在此不作限制。
S102：在基板100上沉积遮光金属层110，并对遮光金属层110进行图案化处理，以形成底栅电极101。
在基板100上溅射一层遮光金属层110，遮光金属层110的材料包括但不限于为钼、铝、铜、钛等金属材料中的一种或多种的堆栈组合。
对该遮光金属层110进行图案化处理，以形成底栅电极101。
S103：在底栅电极101及基板100上沉积缓冲层120，并对缓冲层120进行图案化处理，以使得底栅电极101上方的缓冲层120被薄化。
在形成有底栅电极101的基板100上进一步沉积缓冲层120，缓冲层120的材料可选为氧化硅和/或氮化硅，并对该缓冲层120进行图案化处理，使得对应于底栅电极101上方的缓冲层120被薄化。
S104：在缓冲层120上沉积半导体层，并对半导体层进行图案化处理。
在缓冲层120上沉积半导体层（图未示），半导体层的材料可选为金属氧化物半导体，利用其较高的电子迁移率及与非晶硅制程的相容性较高，以达到简化制程，降低生产成本的目的。
对半导体层进行图案化处理，以在缓冲层120的薄化区域内形成与底栅电极101相对设置的半导体图案102。
因此，本实施例中，通过对底栅电极101对应上方的缓冲层120进行薄化处理，以使得缓冲层120对应于底栅电极101的位置被薄化，可提高底栅电极101对阵列基板200性能的控制。
请进一步参看图2，图2的实施例是在图1的实施例的基础上作进一步描述。如图2所示，本实施例的阵列基板200的制作方法包括：
S201：提供一基板100。
S202：在基板100上沉积遮光金属层110，并对遮光金属层110进行图案化处理，以形成底栅电极101。
其中，步骤S201-S202与上述实施例的步骤S101-S102类似，在此不再赘述。需要说明的是，本实施例与上述实施例的基板100及遮光金属层110的材料与上述实施例的基板100及遮光金属层110的材料可相同或不同。
S203：在底栅电极101及基板100上沉积缓冲层120，并对缓冲层120进行图案化处理，以使得底栅电极101上方的缓冲层120被薄化。
在具有底栅电极101的基板100上沉积缓冲层120，缓冲层120的材料可选为氧化硅或氮化硅中的一种或组合。本实施例中，沉积缓冲层120可为后续沉积半导体层（图未示）提供一个良好的界面，沉积的缓冲层120的厚度设计为可防止基板100上的碱金属离子等杂质污染半导体层为宜。
采用一道掩膜工艺对缓冲层120进行曝光、显影及刻蚀，以使得底栅电极101上方的缓冲层120被薄化，其中，缓冲层120的薄化区域的厚度设置成使得缓冲层120的薄化区域作为底栅电极101与后续形成的半导体图案102之间的底栅绝缘层121，从而提高底栅电极101对阵列基板200性能的控制。
S204：在缓冲层120上沉积半导体层，并对半导体层进行图案化处理。
在缓冲层120上沉积半导体层，半导体层的材料可选为金属氧化物半导体。
采用一道掩膜工艺对该半导体层进行图案化处理，以在缓冲层120的薄化区域内形成与底栅电极101相对设置的半导体图案102，使得缓冲层120的薄化区域作为底栅电极101与半导体图案102之间的底栅绝缘层121。
其中，步骤S201-步骤S204，分别采用一道掩膜工艺对缓冲层120进行图案化处理所使用的掩膜与对半导体层进行图案化处理所使用的掩膜或对遮光金属层110进行图案化处理所使用的掩膜为同一掩膜，进而简化制程，节省掩膜成本。
本实施例中对缓冲层120进行图案化处理所使用的掩膜与对半导体层进行图案化处理所使用的掩膜及对遮光金属层110进行图案化处理所使用的掩膜为同一掩膜。而由于对遮光金属层110及对半导体进行刻蚀的区域与对缓冲层120进行刻蚀的区域不同，因此，本实施例中可通过设定对半导体层进行图案化处理所使用的光阻层及对遮光金属层110进行图案化处理所使用的光阻层为正性光阻层和负性光阻层中的一个，而对缓冲层120进行图案化处理所使用的光阻层为正性光阻层和负性光阻层中的另一个，从而实现在不增加新的掩膜的前提下对缓冲层120与对遮光金属层110及对半导体层的不同区域进行显影刻蚀。
在一个具体实施例中，步骤S202，请参阅图3-图4，在基板100上沉积一层遮光金属层110，并在遮光金属层110上沉积一层光阻层（图未示）。可选地，遮光金属层110的厚度约为100nm，材料为钼，光阻层为正性光阻层。
采用掩膜（图未示）对该正性光阻层进行曝光显影，其中，掩膜包括透光部及遮光部，掩膜的遮光部对应待刻蚀成底栅电极的区域101'，透光部对应除了对应待刻蚀成底栅电极的区域101'以外的其他区域，利用掩膜对该正性光阻层进行曝光显影后，获得覆盖对应于待刻蚀成底栅电极区域101'的正性光阻图案201，如图3所示。
利用对该正性光阻图案201对遮光金属层110进行刻蚀，使得遮光金属层110图案化，即使得待刻蚀成底栅电极的区域101'被保留下来形成底栅电极101，而未被正性光阻图案201覆盖的遮光金属层110被刻蚀掉，然后去除该正性光阻图案201，形成位于基板100上方的底栅电极101，如图4所示。
步骤S203，请参阅图5-图6，采用化学气相沉积法在形成有底栅电极101的基板100上沉积缓冲层120，缓冲层120材料选为氧化硅，其厚度约为300nm。缓冲层120在本实施例的作用是可使得后续沉积半导体层有一个良好的界面，并且其厚度的设计可以防止基板100上的碱金属等离子污染后续沉积的半导体层。
在缓冲层120上方沉积一层光阻层（图未示），光阻层为负性光阻层。
采用掩膜对该负性光阻层进行曝光显影，使掩膜的遮光部对应于待薄化区域。在本实施例中，为了简化制程，同时也为了便于进行自对准操作，本实施例中通过采用遮光金属形成底栅电极101，而由于缓冲层120的材料特性，缓冲层120是透明的，因此，本实施例中可采用自对准技术，使得掩膜的遮光部对应于底栅电极101的区域，透光部对应于除了底栅电极101区域以外的其他区域。利用掩膜对该负性光阻层进行曝光显影后，获得覆盖对应于除底栅电极101区域以外的其他区域的负性光阻图案301，如图5所示。
利用该负性光阻图案301对缓冲层120进行刻蚀，使得未被负性光阻图案301所覆盖缓冲层120的区域被薄化而被负性光阻图案301所覆盖的缓冲层120的区域的厚度得以保留，即使得对应于底栅电极101上方的缓冲层120被薄化，薄化区域作为底栅电极101的底栅绝缘层121，去除负性光阻图案301，形成覆盖底栅电极101的缓冲层120，且缓冲层120对应于底栅电极101的区域被薄化以作为底栅绝缘层121，如图6所示。
在本实施例中，底栅绝缘层121的厚度是可调控的。具体地，可通过采用干法刻蚀法对缓冲层120进行图案化处理，通过控制干刻时等离子体的功率及刻蚀速度，从而实现可控调整需要保留下来作为缓冲层120的薄化区域的厚度。其中，缓冲层120的薄化区域的厚度以适合作为双栅结构的阵列基板200的底栅绝缘层121为宜，以实现提高底栅电极101对整个阵列基板200性能的控制能力。
因此，本实施例中采用同一道掩膜便可图案化形成底栅电极101，同时可将对应于底栅电极101上方的缓冲层120进行薄化处理，只需要将覆盖于底栅电极101上方的光阻层与覆盖于缓冲层120上方的光阻层设置为不同的光阻即可，而无需重新设计掩膜，降低生成成本。并且，通过采用遮光金属层110制作底栅电极101，也方便在进行掩膜制程中实行自对准工艺，提高对准精度，提高生产效率。此外，通过控制干刻时等离子体的功率及刻蚀的速度可实现调控缓冲层120的薄化区域的厚度，可以降低缓冲层120的薄化区域被刻蚀过度或者薄化区域的厚度过厚而无法实现提高底栅电极101对整个阵列基板200性能的控制能力的风险。
步骤S204，请参阅图7，在缓冲层120上沉积半导体层，并在半导体层上方沉积一层光阻层。其中，半导体层的材料可选为IGZO（Indium Gallium Zinc Oxide；铟镓锌氧化物），厚度为约60nm，光阻层为正性光阻层。
采用掩膜对半导体层进行图案化处理，其制程与制作底栅电极101的制程类似，掩膜的遮光部对应于薄化区域，透光部对应于除了薄化区域以外的其他区域。利用掩膜对半导体层进行曝光、显影及刻蚀后，在缓冲层120的薄化区域内形成与底栅电极101相对设置的半导体图案102。
在又一个具体实施例中，与上述实施例的区别在于，在遮光金属层110上方覆盖负性光阻层，在缓冲层120上方覆盖正性光阻层，在半导体层上方覆盖负性光阻层。然后采用同一道掩膜分别对遮光金属层110上的负性光阻层、缓冲层120上的正性光阻层及半导体层上的负性光阻层进行曝光、显影及刻蚀，获得与上述实施例相同结构的阵列基板200。其中，对于遮光金属层110上方覆盖的负性光阻层及对于半导体层上方覆盖的负性光阻层，掩膜的透光部对应于待蚀刻成底栅电极101的区域，遮光部对应于除待蚀刻成底栅电极的区域'以外的其他区域，而对于缓冲层120上方覆盖的正性光阻层，掩膜的透光区域对应于缓冲层120的待薄化区域。其显影刻蚀过程与上述实施例类似，在此不再赘述。
S205：在半导体图案102及缓冲层120上沉积顶栅绝缘层（图未示）和顶栅金属层（图未示），并至少对顶栅金属层进行图案化处理。
具体地，使用化学气相沉积法在半导体图案102及缓冲层120上沉积顶栅绝缘层，并在顶栅绝缘层上方溅射一层顶栅金属层。其中，顶栅绝缘层的材料可以为氧化硅和/或氯化硅，顶栅绝缘层的厚度为约150nm，顶栅金属层的材料可以为铜、钼、钛、铝等金属中的一种或多种的堆栈，且顶栅金属层的材料可与底栅电极101的材料相同或不同。
采用一道掩膜工艺至少对顶栅金属层进行图案化处理，以形成与半导体图案102相对设置的顶栅电极104。本实施例中，为优化设计，同时为了防止顶栅绝缘层影响底栅电极101及半导体图案102对整个阵列基板200的性能，采用掩膜同时对顶栅绝缘层及顶栅金属层同时进行图案化处理，以形成顶栅绝缘层图案103及顶栅电极104，顶栅绝缘层图案103及顶栅电极104未完全覆盖半导体图案102，如图8所示，顶栅绝缘层图案103及顶栅电极104覆盖于半导体图案102的中间区域。
S206：以顶栅电极104作为掩膜，对金属氧化物半导体图案102的位于顶栅电极104两侧的区域进行导体化。
具体地，由于半导体图案102为金属氧化物半导体图案102，并且为了降低生产成本，本实施例可采用图案化处理后的顶栅电极104作为掩膜，对金属氧化物半导体图案102的位于顶栅电极104两侧的区域进行导体化。例如，采用顶栅电极104作为掩膜板，采用自动对准调整技术对金属氧化物半导体图案102的两侧区域进行激光导体化处理，使得金属氧化物半导体图案102的两侧区域导体化，如图9所示。因此，本实施例无需设计额外的掩膜以对半导体图案102进行导体化，降低制程成本。
S207：在顶栅电极104、金属氧化物半导体图案102及缓冲层120上沉积层间介质层130，并对层间介质层130进行图案化处理。
采用气相沉积法在顶栅电极104、金属氧化物半导体图案102及缓冲层120上沉积一层层间介质层130，层间介质层130的材料可选为氧化硅、氮化硅或两者的组合，厚度为约400nm。
采用一道掩膜工艺对层间介质层130进行图案化处理，以形成分别位于金属氧化物半导体图案102两侧区域的第一过孔131及第二过孔132，如图10所示。
S208：在层间介质层130上沉积源/漏极金属层（图未示），并对源/漏极金属层进行图案化处理，以形成分别位于顶栅电极104两侧的源极142及漏极141。
在层间介质层130上沉积源/漏极金属层，通过一道掩膜工艺对该源/漏极金属层进行图案化处理，以形成分别位于顶栅电极104的两侧的源极142及漏极141，并且漏极141及源极142分别通过第一过孔131及第二过孔132与金属氧化物半导体图案102的两侧区域电连接，即源极142及漏极141分别与金属氧化物半导体图案102两侧的导体电连接，如图11所示。
S209：在源极142、漏极141及层间介质层130上沉积钝化层150，并对钝化层150进行图案化处理。
在源极142、漏极141及层间介质层130上沉积钝化层150，钝化层150的材料可选为氧化硅和/或氮化硅，厚度为约200nm。
并采用一道掩膜工艺对钝化层150进行图案化处理，以形成与源极142或漏极141对应的第三过孔151，如图12所示。
S210：在钝化层150上沉积透明导电层（图未示），并对透明导电层进行图案化处理，以形成像素电极105。
在钝化层150上溅射一层透明导电层，透明导电层的材料可选为ITO（Indium tin oxide；氧化铟锡），采用一道掩膜工艺对透明导电层进行图案化处理，以形成像素电极105，并且该像素电极105通过第三过孔151与源极142或漏极141电连接。如图13所示，像素电极105通过第三过孔151与源极142电连接。
至此，完成了本实施例中阵列基板200各层的制作，需要注意的是，在本实施例中所描述的阵列基板200各部分层的厚度数据值，如遮光金属层110的厚度约为100nm及缓冲层120的厚度约为300nm等，本领域技术人员可理解这些数据值仅为举例说明，本发明不应以此为限制，在其他实施例中，阵列基板200的各层的厚度可采用其他数据值。
并且，在其他实施例中，若阵列基板200为AMOLED的TFT背板，则还需要在钝化层150上进一步覆盖一层平坦层（图未示），并通过一道掩膜工艺对钝化层150进行图案化处理，以形成与第三过孔151连通的第四过孔（图未示）。像素电极105形成于平坦层上，并且通过该第四过孔及第三过孔151与源极142或漏极141电连接。
因此，本实施例的双栅极氧化物半导体阵列基板200100的制作，可通过同一道掩膜实现对底栅电极101、缓冲层120及半导体层的图案化处理，并且通过顶栅电极104作为掩膜，可以实现对半导体图案102两侧区域的导体化处理，上述制程均无需设计新的掩膜，减少掩膜数量，提高生产效率，降低生产成本。并且，本实施例的缓冲层120既可用作底栅绝缘层121，又可作为缓冲层120实现双重作用，通过对底栅电极101对应区域的缓冲层120进行薄化处理，且可控调整薄化区域的缓冲层120的厚度，使得薄化区域适合作为底栅绝缘层121，提高底栅电极101对整个阵列基板200性能的控制能力，而缓冲层120的其他未被薄化的区域还可以防止基板100上的碱金属等离子污染后续沉积的半导体层，提高有源阵列基板200的整体性能。
本发明还提供一种TFT阵列基板200，该阵列基板200采用上述方式制作而成，如图13所示，其包括有基板100、形成于基板100上的底栅电极101、覆盖底栅电极101及基板100的缓冲层120及与半导体图案102。其中，缓冲层120上设置有对应于底栅电极101上方的薄化区域，半导体图案102设置于薄化区域内且与底栅电极101相对设置。
其中，在本实施例中，缓冲层120的薄化区域的厚度设置成使得缓冲层120的薄化区域作为底栅电极101与半导体图案102之间的底栅绝缘层121，因此，本实施例的阵列基板200100的缓冲层120即可实现作为底栅绝缘层121的作用，还可用作缓冲作用，其薄化区域作为底栅绝缘层121，可提高底栅电极101对整个阵列基板200性能的控制能力，而缓冲层120的其他区域可防止基板100上的碱金属离子等杂质污染半导体图案102。
综上所述，区域别于现有技术，本发明的阵列基板的制作，通过采用遮光金属层图案化处理后形成底栅电极，进而在底栅电极及基板上沉积缓冲层，并对缓冲层进行图案化处理，使得底栅电极上方的缓冲层被薄化，进一步在缓冲层上沉积半导体层并对该半导体层进行图案化处理，从而在缓冲层的薄化区域内形成与底栅电极相对设置的半导体图案，因此，本实施例的缓冲层通过薄化设计，既可使得薄化区域作为底栅电极的底栅绝缘层，提高底栅电极对整个阵列基板的性能的控制能力，又使得缓冲层的其他区域保持一定的厚度，防止基板上的碱金属等离子杂质污染半导体层。
以上参照附图说明了本发明的优选实施例，并非因此局限本发明的权利范围。本领域技术人员不脱离本发明的范围和实质内所作的任何修改、等同替换和改进，均应在本发明的权利范围之内。

Claims (19)

  1. 一种TFT阵列基板的制作方法，其中，所述制作方法包括：
    提供一基板；
    在所述基板上沉积遮光金属层，对所述遮光金属层进行图案化处理，以形成底栅电极；
    在所述底栅电极及所述基板上沉积缓冲层，对所述缓冲层进行图案化处理，以使得所述底栅电极上方的所述缓冲层被薄化，且所述缓冲层的薄化区域的厚度设置成使得所述缓冲层的薄化区域作为所述底栅电极与半导体图案之间的底栅绝缘层；
    在所述缓冲层上沉积半导体层，对所述半导体层进行图案化处理，以在所述缓冲层的薄化区域内形成与所述底栅电极相对设置的所述半导体图案；
    其中，对所述缓冲层进行图案化处理所使用的掩膜与对所述半导体层进行图案化处理所使用的掩膜或对所述遮光金属层进行图案化处理所使用的掩膜为同一掩膜。
  2. 根据权利要求1所述的制作方法，其中，对所述半导体层进行图案化处理所使用的光阻层及对所述遮光金属层进行图案化处理所使用的光阻层为正性光阻层和负性光阻层中的一个，对所述缓冲层进行图案化处理所使用的光阻层为正性光阻层和负性光阻层中的另一个。
  3. 根据权利要求1所述的制作方法，其中，所述制作方法还包括：
    在所述半导体图案及所述缓冲层上沉积顶栅绝缘层和顶栅金属层，至少对所述顶栅金属层进行图案化处理，以形成与所述半导体图案相对设置的顶栅电极。
  4. 根据权利要求3所述的制作方法，其中，所述半导体图案为金属氧化物半导体图案，所述制作方法还包括：
    以所述顶栅电极作为掩膜，对所述金属氧化物半导体图案的位于所述顶栅电极两侧的区域进行导体化。
  5. 根据权利要求4所述的制作方法，其中，所述制作方法还包括：
    在所述顶栅电极、所述金属氧化物半导体图案及所述缓冲层上沉积层间介质层，并对所述层间介质层进行图案化处理，以形成分别对应于所述金属氧化物半导体图案的两侧区域的第一过孔及第二过孔；
    在所述层间介质层上沉积源/漏金属层，并对所述源/漏金属层进行图案化处理，以形成分别位于所述顶栅电极的两侧的源极及漏极，所述源极及所述漏极分别通过所述第一过孔及所述第二过孔与所述金属氧化物半导体图案的两侧区域电连接。
  6. 根据权利要求5所述的制作方法，其中，所述制作方法还包括：
    在所述源极、所述漏极及所述层间介质层上沉积钝化层，并对所述钝化层进行图案化处理，以形成与所述源极或所述漏极对应的第三过孔；
    在所述钝化层上沉积透明导电层，并对所述透明导电层进行图案化处理，以形成像素电极，所述像素电极通过所述第三过孔与所述源极或所述漏极电连接。
  7. 一种TFT阵列基板的制作方法，其中，所述制作方法包括：
    提供一基板；
    在所述基板上沉积遮光金属层，对所述遮光金属层进行图案化处理，以形成底栅电极；
    在所述底栅电极及所述基板上沉积缓冲层，对所述缓冲层进行图案化处理，以使得所述底栅电极上方的所述缓冲层被薄化；
    在所述缓冲层上沉积半导体层，对所述半导体层进行图案化处理，以在所述缓冲层的薄化区域内形成与所述底栅电极相对设置的半导体图案。
  8. 根据权利要求7所述的制作方法，其中，所述缓冲层的薄化区域的厚度设置成使得所述缓冲层的薄化区域作为所述底栅电极与所述半导体图案之间的底栅绝缘层。
  9. 根据权利要求7所述的制作方法，其中，对所述缓冲层进行图案化处理所使用的掩膜与对所述半导体层进行图案化处理所使用的掩膜或对所述遮光金属层进行图案化处理所使用的掩膜为同一掩膜。
  10. 根据权利要求9所述的制作方法，其中，对所述半导体层进行图案化处理所使用的光阻层及对所述遮光金属层进行图案化处理所使用的光阻层为正性光阻层和负性光阻层中的一个，对所述缓冲层进行图案化处理所使用的光阻层为正性光阻层和负性光阻层中的另一个。
  11. 根据权利要求7所述的制作方法，其中，所述制作方法还包括：
    在所述半导体图案及所述缓冲层上沉积顶栅绝缘层和顶栅金属层，至少对所述顶栅金属层进行图案化处理，以形成与所述半导体图案相对设置的顶栅电极。
  12. 根据权利要求11所述的制作方法，其中，所述半导体图案为金属氧化物半导体图案，所述制作方法还包括：
    以所述顶栅电极作为掩膜，对所述金属氧化物半导体图案的位于所述顶栅电极两侧的区域进行导体化。
  13. 根据权利要求12所述的制作方法，其中，所述制作方法还包括：
    在所述顶栅电极、所述金属氧化物半导体图案及所述缓冲层上沉积层间介质层，并对所述层间介质层进行图案化处理，以形成分别对应于所述金属氧化物半导体图案的两侧区域的第一过孔及第二过孔；
    在所述层间介质层上沉积源/漏金属层，并对所述源/漏金属层进行图案化处理，以形成分别位于所述顶栅电极的两侧的源极及漏极，所述源极及所述漏极分别通过所述第一过孔及所述第二过孔与所述金属氧化物半导体图案的两侧区域电连接。
  14. 根据权利要求13所述的制作方法，其中，所述制作方法还包括：
    在所述源极、所述漏极及所述层间介质层上沉积钝化层，并对所述钝化层进行图案化处理，以形成与所述源极或所述漏极对应的第三过孔；
    在所述钝化层上沉积透明导电层，并对所述透明导电层进行图案化处理，以形成像素电极，所述像素电极通过所述第三过孔与所述源极或所述漏极电连接。
  15. 一种TFT阵列基板，其中，所述阵列基板包括：
    基板；
    底栅电极，形成在所述基板上；
    缓冲层，用于覆盖所述底栅电极和所述基板，其中所述缓冲层设置有位于所述底栅电极的薄化区域；
    半导体图案，形成于所述薄化区域内且与所述底栅电极相对设置。
  16. 根据权利要求15所述的阵列基板，其中，所述缓冲层的薄化区域的厚度设置成使得所述缓冲层的薄化区域作为所述底栅电极与所述半导体图案之间的底栅绝缘层。
  17. 根据权利要求15所述的阵列基板，其中，所述阵列基板还包括：
    顶栅绝缘层，设置于所述半导体图案上，
    顶栅电极，设置于所述顶栅绝缘层上，并与所述半导体图案相对设置。
  18. 根据权利要求17所述的阵列基板，其中，所述阵列基板还包括：
    层间介质层，覆盖于所述顶栅电极上方，并且所述层间介质层对应于所述半导体图案的两侧区域形成有第一过孔及第二过孔；
    源极及漏极，设置于所述层间介质层上，且分别通过所述第一过孔及所述第二过孔与所述半导体图案的两侧区域电连接。
  19. 根据权利要求18所述的阵列基板，其中，所述阵列基板还包括：
    钝化层，设置于所述层间介质层上且覆盖所述源极及所述漏极，且所述钝化层对应于所述源极或所述漏极上方形成有第三过孔；
    像素电极，通过所述第三过孔与所述源极或所述漏极电连接。
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