WO2018201560A1 - 金属氧化物tft器件及其制作方法 - Google Patents

金属氧化物tft器件及其制作方法 Download PDF

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WO2018201560A1
WO2018201560A1 PCT/CN2017/088193 CN2017088193W WO2018201560A1 WO 2018201560 A1 WO2018201560 A1 WO 2018201560A1 CN 2017088193 W CN2017088193 W CN 2017088193W WO 2018201560 A1 WO2018201560 A1 WO 2018201560A1
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layer
zinc oxide
indium gallium
metal oxide
gallium zinc
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French (fr)
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翟玉浩
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US15/545,325 priority Critical patent/US10304966B2/en
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/67Thin-film transistors [TFT]
    • H10D30/6704Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/67Thin-film transistors [TFT]
    • H10D30/674Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00Subject matter not provided for in other groups of this subclass

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  • the present invention relates to the field of display technologies, and in particular, to a metal oxide TFT device and a method of fabricating the same.
  • Flat panel displays have many advantages such as thin body, power saving, no radiation, etc., and have been widely used.
  • Existing flat panel displays mainly include a liquid crystal display (LCD) and an organic light emitting display (OLED).
  • LCD liquid crystal display
  • OLED organic light emitting display
  • liquid crystal displays which include a casing, a liquid crystal panel disposed in the casing, and a backlight module disposed in the casing.
  • the structure of the liquid crystal panel is composed of a color filter substrate (CF), a thin film transistor array substrate (TFT Array Substrate), and a liquid crystal layer (Liquid Crystal Layer) disposed between the two substrates.
  • the working principle is that the rotation of the liquid crystal molecules of the liquid crystal layer is controlled by applying a driving voltage on the two substrates, and the light of the backlight module is refracted to generate a picture.
  • the organic electroluminescent display also requires a TFT substrate, a TFT device as a switching member and a driving member, and a pixel structure arranged in an array on the TFT substrate.
  • TFT devices are also abundantly present in large-area integrated circuits.
  • a technique in which a metal oxide such as Indium Gallium Zinc Oxide (IGZO) is used as an active layer of a TFT device is a current hot technology.
  • Metal oxides have high electron mobility, excellent film thickness uniformity and surface flatness, and are highly compatible with amorphous silicon processes, so metal oxides are gradually becoming active layers of TFT devices in LCDs and OLEDs. Preferred material.
  • the electron mobility of the active layer of the metal oxide TFT device represented by IGZO still needs to be further improved, and in general, the contact interface between the IGZO and the gate insulating layer may capture electrons due to the presence of defects, affecting the TFT. The switching state of the device.
  • An object of the present invention is to provide a metal oxide TFT device which can further improve electron mobility, reduce interface defects of an active layer and a gate insulating layer, and improve electrical properties of a TFT device.
  • Another object of the present invention is to provide a method for fabricating a metal oxide TFT device, and the metal oxide TFT device obtained by the method can further improve electron mobility and reduce The interface defects between the source layer and the gate insulating layer improve the electrical properties of the TFT device.
  • the present invention first provides a metal oxide TFT device including a substrate, a gate electrode disposed on the substrate, a gate insulating layer covering the gate and the substrate, and being disposed above the gate An active layer on the gate insulating layer, and a source and a drain respectively contacting the two sides of the active layer on the gate insulating layer;
  • the active layer includes a lower indium gallium zinc oxide film, an upper indium gallium zinc oxide film disposed opposite to the lower indium gallium zinc oxide film, and an upper layer of the indium gallium zinc oxide film and the upper layer
  • An intermediate conductive layer between the indium gallium zinc oxide films; the intermediate conductive layer is made of a high indium containing metal oxide or a high zinc containing metal oxide.
  • the material of the intermediate conductive layer is one of indium tin oxide, indium zinc oxide, and aluminum-doped zinc oxide.
  • the intermediate conductive layer has a thickness of 2 nm to 10 nm, and the active layer has a thickness of 30 nm to 100 nm.
  • the sheet resistance of the intermediate conductive layer is ⁇ 1x10 4 ⁇ / ⁇ .
  • the substrate is a glass substrate
  • the material of the gate, the source, and the drain is one of molybdenum, aluminum, or a stack of molybdenum and aluminum;
  • the material of the gate insulating layer is silicon oxide or aluminum oxide.
  • the invention also provides a method for fabricating a metal oxide TFT device, comprising:
  • the intermediate conductive layer is formed by depositing one of indium tin oxide, indium zinc oxide, and aluminum-doped zinc oxide.
  • the intermediate conductive layer has a thickness of 2 nm to 10 nm, and the active layer has a thickness of 30 nm to 100 nm.
  • the sheet resistance of the intermediate conductive layer is ⁇ 1x10 4 ⁇ / ⁇ .
  • the substrate is a glass substrate
  • the materials of the first metal layer and the second metal layer are each one of molybdenum and aluminum, or molybdenum and Aluminum stack combination;
  • the material of the gate insulating layer is silicon oxide or aluminum oxide.
  • the present invention also provides a metal oxide TFT device including a substrate, a gate electrode disposed on the substrate, a gate insulating layer covering the gate and the substrate, and the gate electrode disposed above the gate electrode An active layer on the insulating layer, and a source and a drain respectively contacting the two sides of the active layer on the gate insulating layer;
  • the active layer includes a lower indium gallium zinc oxide film, an upper indium gallium zinc oxide film disposed opposite to the lower indium gallium zinc oxide film, and an upper layer of the indium gallium zinc oxide film and the upper layer
  • the material of the intermediate conductive layer is one of indium tin oxide, indium zinc oxide, and aluminum-doped zinc oxide;
  • the intermediate conductive layer has a thickness of 2 nm to 10 nm, and the active layer has a thickness of 30 nm to 100 nm.
  • the present invention provides a metal oxide TFT device having an active layer using a sandwich-like structure, including a lower indium gallium zinc oxide film, an upper indium gallium zinc oxide film, and a sandwich layer.
  • An intermediate conductive layer between the underlying indium gallium zinc oxide film and the upper indium gallium zinc oxide film, and the material of the intermediate conductive layer is a high indium containing metal oxide or a high zinc containing metal oxide;
  • the vacant s-orbital of zinc ions can form an electron transport path, and the intermediate conductive layer made of high-indium-containing metal oxide or high-zinc-containing metal oxide can increase the concentration of carriers, thereby further improving the electrons of the TFT device.
  • the intermediate conductive layer is equivalent to the main channel, and the lower indium gallium zinc oxide film serves to improve the contact interface between the active layer and the gate insulating layer.
  • the interface defects are reduced, thereby avoiding the occurrence of interface defects affecting the electrical properties of the TFT device and improving the electrical properties of the TFT device.
  • the active layer adopts a sandwich-like structure, including a lower indium gallium zinc oxide film and an upper indium gallium zinc oxide film.
  • an intermediate conductive layer interposed between the lower indium gallium zinc oxide film and the upper indium gallium zinc oxide film, and the material of the intermediate conductive layer is a high indium containing metal oxide or a high zinc containing metal
  • the oxide can further increase the electron mobility, reduce the interface defects of the active layer and the gate insulating layer, and improve the electrical properties of the TFT device.
  • FIG. 1 is a schematic cross-sectional structural view of a metal oxide TFT device of the present invention
  • FIG. 2 is a flow chart showing a method of fabricating a metal oxide TFT device of the present invention
  • FIG. 3 is a schematic view showing the first step of the method for fabricating the metal oxide TFT device of the present invention
  • FIG. 4 is a schematic view showing a step 2 of a method of fabricating a metal oxide TFT device of the present invention
  • Figure 5 is a schematic view showing the third step of the method for fabricating the metal oxide TFT device of the present invention.
  • FIG. 6 is a schematic view showing a step 4 of a method of fabricating a metal oxide TFT device of the present invention
  • Figure 7 is a schematic view showing the fifth step of the method of fabricating the metal oxide TFT device of the present invention.
  • the present invention firstly provides a metal oxide TFT device, comprising a substrate 1 , a gate 3 disposed on the substrate 1 , a gate insulating layer 5 covering the gate 3 and the substrate 1 , and An active layer 7 disposed on the gate insulating layer 5 above the gate 3, and a source 91 and a drain respectively disposed on the gate insulating layer 5 on both sides of the active layer 7 92.
  • the active layer 7 adopts a sandwich-like structure, and includes a lower indium gallium zinc oxide film 71, an upper indium gallium zinc oxide film 73 disposed opposite to the lower indium gallium zinc oxide film 71, and a sandwich An intermediate conductive layer 75 between the lower indium gallium zinc oxide film 71 and the upper indium gallium zinc oxide film 73 is described.
  • the material of the intermediate conductive layer 75 is a high indium containing metal oxide, that is, a metal oxide having a high indium content, or a high zinc-containing metal oxide, that is, a metal oxide having a high zinc content.
  • the material of the intermediate conductive layer 75 is preferably one of Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), and Al-doped ZnO (AZO).
  • ITO Indium Tin Oxide
  • IZO Indium Zinc Oxide
  • AZO Al-doped ZnO
  • the vacant s orbit of positive trivalent indium ions (In 3+ ) or normal divalent zinc ions (Zn 2+ ) can form an electron transport path, and the middle is composed of a high indium containing metal oxide or a high zinc-containing metal oxide.
  • the conductive layer 75 contains a large amount of In 3+ or Zn 2+ , which can greatly increase the electron mobility of the TFT device and increase the carrier concentration; and at the same time, the resistance of the intermediate conductive layer 75 is relative to the underlying indium gallium zinc oxide film 71 and The upper indium gallium zinc oxide film 73 has a low electric resistance, the carriers are mainly concentrated on the intermediate conductive layer 75, the intermediate conductive layer 75 is equivalent to the main channel, and the lower indium gallium zinc oxide film 71 is used to improve the active.
  • the function of the contact interface between the layer 7 and the gate insulating layer 5 reduces interface defects, thereby avoiding the occurrence of interface defects affecting the electrical properties of the TFT device and improving the electrical properties of the TFT device.
  • the thickness of the active layer 7 is 30 nm to 100 nm; the thickness of the intermediate conductive layer 75 is moderate, and the effect of increasing the electron mobility and increasing the carrier concentration is not obvious, and the thickness is too thick.
  • the source 91 and the drain 92 may be turned on to form a normal TFT device. Therefore, it is preferable that the intermediate conductive layer 75 has a thickness of 2 nm to 10 nm, and the argon gas (Ar) is adjusted when the intermediate conductive layer 75 is formed.
  • the sheet resistance of the intermediate conductive layer 73 is controlled to be ⁇ 1x10 4 ⁇ / ⁇ with process conditions such as flow ratio of oxygen (O 2 ) and film formation pressure.
  • the substrate 1 is preferably a glass substrate; the material of the gate 3, the source 91, and the drain 92 is one of molybdenum (Mo), aluminum (Al), or a stack of molybdenum and aluminum.
  • the material of the gate insulating layer 5 is silicon oxide (SiO 2 ) or aluminum oxide (Al 2 O 3 ).
  • the present invention also provides a method for fabricating a metal oxide TFT device, comprising the following steps:
  • Step S1 as shown in FIG. 3, a substrate 1 is provided, a first metal layer is deposited on the substrate 1 by a physical vapor deposition process (PVD), and the first metal is deposited by a yellow light process and an etching process.
  • the layer is patterned to obtain the gate 3.
  • PVD physical vapor deposition process
  • the substrate 1 is preferably a glass substrate; the material of the first metal layer is one of molybdenum, aluminum, or a stack of molybdenum and aluminum.
  • Step S2 as shown in FIG. 4, a gate insulating layer 5 is deposited on the gate 3 and the substrate 1 by Plasma Enhanced Chemical Vapor Deposition (PECVD).
  • PECVD Plasma Enhanced Chemical Vapor Deposition
  • the material of the gate insulating layer 5 is silicon oxide or aluminum oxide.
  • Step S3 depositing an indium gallium zinc oxide film on the gate insulating layer 5 to form a lower indium gallium zinc oxide film 71, and depositing a high indium containing metal oxide or a high zinc containing metal oxide.
  • An intermediate conductive layer 75 is formed, followed by deposition of indium gallium zinc oxide to form an upper indium gallium zinc oxide film 73.
  • the step S3 deposits one of indium tin oxide, indium zinc oxide, and aluminum-doped zinc oxide to form the intermediate conductive layer 75.
  • the thickness of the active layer 7 is 30 nm to 100 nm; and the thickness of the intermediate conductive layer 75 is preferably 2 nm to 10 nm.
  • the sheet resistance of the intermediate conductive layer 73 is controlled to be ⁇ 1 ⁇ 10 4 ⁇ / ⁇ by adjusting process conditions such as a flow ratio of argon gas to oxygen gas and a film forming pressure.
  • Step S4 as shown in FIG. 6, the stacked lower indium gallium zinc oxide film 71, the intermediate conductive layer 75, and the upper indium gallium zinc oxide film 73 are patterned by a yellow light process and an etching process to form a pattern.
  • An active layer 7 similar to the sandwich structure is located above the gate 3.
  • Step S5 as shown in FIG. 7, a second metal layer is deposited on the gate insulating layer 5 and the active layer 7 by a physical vapor deposition process, and the second metal layer is formed by a yellow light process and an etching process.
  • the row patterning process results in source 91 and drain 92 contacting the two sides of the active layer 7, respectively.
  • the material of the second metal layer is one of molybdenum, aluminum, or a stack of molybdenum and aluminum.
  • the metal oxide TFT device obtained by the above method has the active layer 7 interposed between the lower indium gallium zinc oxide film 71 and the upper indium gallium zinc oxide film 73 with a high indium containing metal oxide or a high content.
  • the zinc metal oxide is an intermediate conductive layer 75 of the material, and the s-over s orbit of In 3+ or Zn 2+ can form an electron transport path, and the intermediate conductive layer 75 contains a large amount of In 3+ or Zn 2+ , which can greatly improve
  • the electron mobility of the TFT device increases the carrier concentration; and since the resistance of the intermediate conductive layer 75 is lower than that of the lower indium gallium zinc oxide film 71 and the upper indium gallium zinc oxide film 73, the carriers are mainly Focusing on the intermediate conductive layer 75, the intermediate conductive layer 75 is equivalent to the main channel, and the lower indium gallium zinc oxide film 71 functions to improve the contact interface between the active layer 7 and the gate insulating layer 5, thereby reducing interface defects. Therefore, it is possible to
  • the metal oxide TFT device of the present invention has a sandwich-like active layer, including a lower indium gallium zinc oxide film, an upper indium gallium zinc oxide film, and an underlying indium gallium.
  • An intermediate conductive layer between the zinc oxide film and the upper indium gallium zinc oxide film, and the material of the intermediate conductive layer is a high indium containing metal oxide or a high zinc containing metal oxide; due to indium ions or zinc ions
  • the vacant s orbit can form an electron transport path, and the intermediate conductive layer made of a high indium-containing metal oxide or a high-zinc-containing metal oxide can increase the carrier concentration, thereby further increasing the electron mobility of the TFT device, and simultaneously Since the carriers are mainly concentrated in the intermediate conductive layer, the intermediate conductive layer is equivalent to the main channel, and the lower indium gallium zinc oxide film functions to improve the contact interface between the active layer and the gate insulating layer, thereby reducing interface defects.
  • the active layer adopts a sandwich-like structure including a lower indium gallium zinc oxide film, an upper indium gallium zinc oxide film, and a clip.
  • An intermediate conductive layer disposed between the lower indium gallium zinc oxide film and the upper indium gallium zinc oxide film, and the material of the intermediate conductive layer is a high indium containing metal oxide or a high zinc containing metal oxide.

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Abstract

一种金属氧化物TFT器件及其制作方法,有源层(7)采用类似三明治的结构,包括下层铟镓锌氧化物薄膜(71)、与下层铟镓锌氧化物薄膜相对设置的上层铟镓锌氧化物薄膜(73)、及夹设在下层铟镓锌氧化物薄膜与上层铟镓锌氧化物薄膜之间的中间导电层(75),且中间导电层的材料为高含铟金属氧化物、或高含锌金属氧化物,能够进一步提高电子迁移率,减少有源层与栅极绝缘层(5)的界面缺陷,改善TFT器件的电性。

Description

金属氧化物TFT器件及其制作方法 技术领域
本发明涉及显示技术领域,尤其涉及一种金属氧化物TFT器件及其制作方法。
背景技术
平板显示器具有机身薄、省电、无辐射等众多优点,得到了广泛的应用。现有的平板显示器主要包括液晶显示器(Liquid Crystal Display,LCD)及有机电致发光显示器(Organic Light Emitting Display,OLED)。
现有市场上的液晶显示器大部分为背光型液晶显示器,其包括壳体、设于壳体内的液晶面板及设于壳体内的背光模组(Backlight Module)。液晶面板的结构是由一彩色滤光片基板(Color Filter,CF)、一薄膜晶体管阵列基板(Thin Film Transistor Array Substrate,TFT Array Substrate)以及一配置于两基板间的液晶层(Liquid Crystal Layer)所构成,其工作原理是通过在两基板上施加驱动电压来控制液晶层的液晶分子的旋转,将背光模组的光线折射出来产生画面。
有机电致发光显示器同样需要TFT基板,以TFT器件作为开关部件和驱动部件,并在TFT基板上制作出呈阵列式排布的像素结构。
另外,在大面积集成电路中也大量存在TFT器件。
以金属氧化物(如铟镓锌氧化物(Indium Gallium Zinc Oxide,IGZO))作为TFT器件的有源层的技术是当前的热门技术。金属氧化物具有较高的电子迁移率、优良的膜厚均匀性和表面平坦性,与非晶硅制程相容性较高,所以金属氧化物逐渐成为LCD及OLED中TFT器件的有源层的首选材料。
目前,以IGZO为代表的金属氧化物TFT器件的有源层的电子迁移率仍需进一步提高,并且通常情况下,IGZO与栅极绝缘层的接触界面会由于缺陷的存在而捕获电子,影响TFT器件的开关态。
发明内容
本发明的目的在于提供一种金属氧化物TFT器件,能够进一步提高电子迁移率,减少有源层与栅极绝缘层的界面缺陷,改善TFT器件的电性。
本发明的另一目的在于提供一种金属氧化物TFT器件的制作方法,通过该方法制得的金属氧化物TFT器件能够进一步提高电子迁移率,减少有 源层与栅极绝缘层的界面缺陷,改善TFT器件的电性。
为实现上述目的,本发明首先提供一种金属氧化物TFT器件,包括基板、设在所述基板上的栅极、覆盖所述栅极与基板的栅极绝缘层、于所述栅极上方设在所述栅极绝缘层上的有源层、及设在所述栅极绝缘层上分别接触所述有源层两侧的源极与漏极;
所述有源层包括下层铟镓锌氧化物薄膜、与所述下层铟镓锌氧化物薄膜相对设置的上层铟镓锌氧化物薄膜、及夹设在所述下层铟镓锌氧化物薄膜与上层铟镓锌氧化物薄膜之间的中间导电层;所述中间导电层的材料为高含铟金属氧化物、或高含锌金属氧化物。
所述中间导电层的材料为氧化铟锡、氧化铟锌、掺铝氧化锌中的一种。
所述中间导电层的厚度为2nm~10nm,所述有源层的厚度为30nm~100nm。
所述中间导电层的方块电阻≥1x104Ω/□。
所述基板为玻璃基板;
所述栅极、源极、与漏极的材料均为钼、铝中的一种、或钼与铝的堆栈组合;
所述栅极绝缘层的材料为氧化硅、或氧化铝。
本发明还提供一种金属氧化物TFT器件的制作方法,包括:
提供基板,在所述基板上沉积第一金属层并对第一金属层进行图案化处理,得到栅极;
在所述栅极与基板上沉积栅极绝缘层;
在所述栅极绝缘层上先沉积铟镓锌氧化物形成下层铟镓锌氧化物薄膜,再沉积高含铟金属氧化物或高含锌金属氧化物形成中间导电层,接着沉积铟镓锌氧化物形成上层铟镓锌氧化物薄膜;
对层叠的下层铟镓锌氧化物薄膜、中间导电层、与上层铟镓锌氧化物薄膜进行图案化处理,形成位于所述栅极上方的有源层;
在所述栅极绝缘层及有源层上沉积第二金属层并对第二金属层进行图案化处理,得到分别接触所述有源层两侧的源极与漏极。
通过沉积氧化铟锡、氧化铟锌、掺铝氧化锌中的一种形成中间导电层。
所述中间导电层的厚度为2nm~10nm,所述有源层的厚度为30nm~100nm。
所述中间导电层的方块电阻≥1x104Ω/□。
所述基板为玻璃基板;
所述第一金属层、与第二金属层的材料均为钼、铝中的一种、或钼与 铝的堆栈组合;
所述栅极绝缘层的材料为氧化硅、或氧化铝。
本发明还提供一种金属氧化物TFT器件,包括基板、设在所述基板上的栅极、覆盖所述栅极与基板的栅极绝缘层、于所述栅极上方设在所述栅极绝缘层上的有源层、及设在所述栅极绝缘层上分别接触所述有源层两侧的源极与漏极;
所述有源层包括下层铟镓锌氧化物薄膜、与所述下层铟镓锌氧化物薄膜相对设置的上层铟镓锌氧化物薄膜、及夹设在所述下层铟镓锌氧化物薄膜与上层铟镓锌氧化物薄膜之间的中间导电层;所述中间导电层的材料为高含铟金属氧化物、或高含锌金属氧化物;
其中,所述中间导电层的材料为氧化铟锡、氧化铟锌、掺铝氧化锌中的一种;
其中,所述中间导电层的厚度为2nm~10nm,所述有源层的厚度为30nm~100nm。
本发明的有益效果:本发明提供的一种金属氧化物TFT器件,其有源层采用类似三明治的结构,包括下层铟镓锌氧化物薄膜、上层铟镓锌氧化物薄膜、及夹设在所述下层铟镓锌氧化物薄膜与上层铟镓锌氧化物薄膜之间的中间导电层,且所述中间导电层的材料为高含铟金属氧化物、或高含锌金属氧化物;由于铟离子或锌离子的空置s轨道能够形成电子传输路径,以高含铟金属氧化物、或高含锌金属氧化物为材料的中间导电层能够增加载流子的浓度,从而能够进一步提高TFT器件的电子迁移率,同时由于载流子主要集中在所述中间导电层,中间导电层相当于主沟道,下层铟镓锌氧化物薄膜便起到改善有源层与栅极绝缘层的接触界面的作用,减少界面缺陷,从而能够避免界面缺陷影响TFT器件电性的现象发生,改善TFT器件的电性。本发明提供的一种金属氧化物TFT器件的制作方法所制得的金属氧化物TFT器件中,有源层采用类似三明治的结构,包括下层铟镓锌氧化物薄膜、上层铟镓锌氧化物薄膜、及夹设在所述下层铟镓锌氧化物薄膜与上层铟镓锌氧化物薄膜之间的中间导电层,且所述中间导电层的材料为高含铟金属氧化物、或高含锌金属氧化物,能够进一步提高电子迁移率,减少有源层与栅极绝缘层的界面缺陷,改善TFT器件的电性。
附图说明
为了能更进一步了解本发明的特征以及技术内容,请参阅以下有关本发明的详细说明与附图,然而附图仅提供参考与说明用,并非用来对本发 明加以限制。
附图中,
图1为本发明的金属氧化物TFT器件的剖面结构示意图;
图2为本发明的金属氧化物TFT器件的制作方法的流程图;
图3为本发明的金属氧化物TFT器件的制作方法的步骤1的示意图;
图4为本发明的金属氧化物TFT器件的制作方法的步骤2的示意图;
图5为本发明的金属氧化物TFT器件的制作方法的步骤3的示意图;
图6为本发明的金属氧化物TFT器件的制作方法的步骤4的示意图;
图7为本发明的金属氧化物TFT器件的制作方法的步骤5的示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果,以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图1,本发明首先提供一种金属氧化物TFT器件,包括基板1、设在所述基板1上的栅极3、覆盖所述栅极3与基板1的栅极绝缘层5、于所述栅极3上方设在所述栅极绝缘层5上的有源层7、及设在所述栅极绝缘层5上分别接触所述有源层7两侧的源极91与漏极92。
所述有源层7采用类似三明治的结构,包括下层铟镓锌氧化物薄膜71、与所述下层铟镓锌氧化物薄膜71相对设置的上层铟镓锌氧化物薄膜73、及夹设在所述下层铟镓锌氧化物薄膜71与上层铟镓锌氧化物薄膜73之间的中间导电层75。所述中间导电层75的材料为高含铟金属氧化物即铟含量较高的金属氧化物、或高含锌金属氧化物即锌含量较高的金属氧化物。
具体地,所述中间导电层75的材料优选氧化铟锡(Indium Tin Oxide,ITO)、氧化铟锌(Indium Zinc Oxide,IZO)、掺铝氧化锌(Al-doped ZnO,AZO)中的一种。由于正三价的铟离子(In3+)或正二价锌离子(Zn2+)的空置s轨道能够形成电子传输路径,以高含铟金属氧化物、或高含锌金属氧化物为材料的中间导电层75含有大量的In3+或Zn2+,能够大幅提高TFT器件的电子迁移率,增加载流子的浓度;同时由于中间导电层75的电阻相对于下层铟镓锌氧化物薄膜71及上层铟镓锌氧化物薄膜73的电阻要低,载流子主要集中在所述中间导电层75,中间导电层75相当于主沟道,下层铟镓锌氧化物薄膜71便起到改善有源层7与栅极绝缘层5的接触界面的作用,减少界面缺陷,从而能够避免界面缺陷影响TFT器件电性的现象发生,改善TFT器件的电性。
进一步地,所述有源层7的厚度为30nm~100nm;所述中间导电层75 的厚度要适中,太薄会使得提高电子迁移率、增加载流子浓度的效果不明显,太厚则有可能导致源极91与漏极92导通,无法形成正常的TFT器件,因此优选中间导电层75的厚度为2nm~10nm,并在所述中间导电层75成膜时通过调节氩气(Ar)与氧气(O2)的流量比例、成膜压力等工艺条件来控制所述中间导电层73的方块电阻≥1x104Ω/□。
具体地,所述基板1优选玻璃基板;所述栅极3、源极91、与漏极92的材料均为钼(Mo)、铝(Al)中的一种、或钼与铝的堆栈组合;所述栅极绝缘层5的材料为氧化硅(SiO2)、或氧化铝(Al2O3)。
请参阅图2,本发明还提供一种金属氧化物TFT器件的制作方法,包括以下步骤:
步骤S1、如图3所示,提供基板1,通过物理气相沉积工艺(Physical Vapor Deposition,PVD)在所述基板1上沉积第一金属层并通过黄光工艺和刻蚀工艺来对第一金属层进行图案化处理,得到栅极3。
具体地,所述基板1优选玻璃基板;所述第一金属层的材料为钼、铝中的一种、或钼与铝的堆栈组合。
步骤S2、如图4所示,通过等离子体化学气相沉积(Plasma Enhanced Chemical Vapor Deposition,PECVD)在所述栅极3与基板1上沉积栅极绝缘层5。
具体地,所述栅极绝缘层5的材料为氧化硅、或氧化铝。
步骤S3、如图5所示,在所述栅极绝缘层5上先沉积铟镓锌氧化物形成下层铟镓锌氧化物薄膜71,再沉积高含铟金属氧化物或高含锌金属氧化物形成中间导电层75,接着沉积铟镓锌氧化物形成上层铟镓锌氧化物薄膜73。
具体地,该步骤S3沉积氧化铟锡、氧化铟锌、掺铝氧化锌中的一种形成中间导电层75。
所述有源层7的厚度为30nm~100nm;所述中间导电层75的厚度优选2nm~10nm。
该步骤S3在所述中间导电层75成膜时通过调节氩气与氧气的流量比例、成膜压力等工艺条件来控制所述中间导电层73的方块电阻≥1x104Ω/□。
步骤S4、如图6所示,通过黄光工艺与刻蚀工艺来对层叠的下层铟镓锌氧化物薄膜71、中间导电层75、与上层铟镓锌氧化物薄膜73进行图案化处理,形成位于所述栅极3上方的类似于三明治结构的有源层7。
步骤S5、如图7所示,通过物理气相沉积工艺在所述栅极绝缘层5及有源层7上沉积第二金属层并通过黄光工艺和刻蚀工艺来对第二金属层进 行图案化处理,得到分别接触所述有源层7两侧的源极91与漏极92。
具体地,所述第二金属层的材料为钼、铝中的一种、或钼与铝的堆栈组合。
经上述方法制得的金属氧化物TFT器件,其有源层7在下层铟镓锌氧化物薄膜71与上层铟镓锌氧化物薄膜73之间夹设以高含铟金属氧化物、或高含锌金属氧化物为材料的中间导电层75,由于In3+或Zn2+的空置s轨道能够形成电子传输路径,所述中间导电层75含有大量的In3+或Zn2+,能够大幅提高TFT器件的电子迁移率,增加载流子的浓度;同时由于中间导电层75的电阻相对于下层铟镓锌氧化物薄膜71及上层铟镓锌氧化物薄膜73的电阻要低,载流子主要集中在所述中间导电层75,中间导电层75相当于主沟道,下层铟镓锌氧化物薄膜71便起到改善有源层7与栅极绝缘层5的接触界面的作用,减少界面缺陷,从而能够避免界面缺陷影响TFT器件电性的现象发生,改善TFT器件的电性。
综上所述,本发明的金属氧化物TFT器件,其有源层采用类似三明治的结构,包括下层铟镓锌氧化物薄膜、上层铟镓锌氧化物薄膜、及夹设在所述下层铟镓锌氧化物薄膜与上层铟镓锌氧化物薄膜之间的中间导电层,且所述中间导电层的材料为高含铟金属氧化物、或高含锌金属氧化物;由于铟离子或锌离子的空置s轨道能够形成电子传输路径,以高含铟金属氧化物、或高含锌金属氧化物为材料的中间导电层能够增加载流子的浓度,从而能够进一步提高TFT器件的电子迁移率,同时由于载流子主要集中在所述中间导电层,中间导电层相当于主沟道,下层铟镓锌氧化物薄膜便起到改善有源层与栅极绝缘层的接触界面的作用,减少界面缺陷,从而能够避免界面缺陷影响TFT器件电性的现象发生,改善TFT器件的电性。本发明的金属氧化物TFT器件的制作方法所制得的金属氧化物TFT器件中,有源层采用类似三明治的结构,包括下层铟镓锌氧化物薄膜、上层铟镓锌氧化物薄膜、及夹设在所述下层铟镓锌氧化物薄膜与上层铟镓锌氧化物薄膜之间的中间导电层,且所述中间导电层的材料为高含铟金属氧化物、或高含锌金属氧化物,能够进一步提高电子迁移率,减少有源层与栅极绝缘层的界面缺陷,改善TFT器件的电性。
以上所述,对于本领域的普通技术人员来说,可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形,而所有这些改变和变形都应属于本发明后附的权利要求的保护范围。

Claims (13)

  1. 一种金属氧化物TFT器件,包括基板、设在所述基板上的栅极、覆盖所述栅极与基板的栅极绝缘层、于所述栅极上方设在所述栅极绝缘层上的有源层、及设在所述栅极绝缘层上分别接触所述有源层两侧的源极与漏极;
    所述有源层包括下层铟镓锌氧化物薄膜、与所述下层铟镓锌氧化物薄膜相对设置的上层铟镓锌氧化物薄膜、及夹设在所述下层铟镓锌氧化物薄膜与上层铟镓锌氧化物薄膜之间的中间导电层;所述中间导电层的材料为高含铟金属氧化物、或高含锌金属氧化物。
  2. 如权利要求1所述的金属氧化物TFT器件,其中,所述中间导电层的材料为氧化铟锡、氧化铟锌、掺铝氧化锌中的一种。
  3. 如权利要求1所述的金属氧化物TFT器件,其中,所述中间导电层的厚度为2nm~10nm,所述有源层的厚度为30nm~100nm。
  4. 如权利要求3所述的金属氧化物TFT器件,其中,所述中间导电层的方块电阻≥1x104Ω/□。
  5. 如权利要求1所述的金属氧化物TFT器件,其中,
    所述基板为玻璃基板;
    所述栅极、源极、与漏极的材料均为钼、铝中的一种、或钼与铝的堆栈组合;
    所述栅极绝缘层的材料为氧化硅、或氧化铝。
  6. 一种金属氧化物TFT器件的制作方法,包括:
    提供基板,在所述基板上沉积第一金属层并对第一金属层进行图案化处理,得到栅极;
    在所述栅极与基板上沉积栅极绝缘层;
    在所述栅极绝缘层上先沉积铟镓锌氧化物形成下层铟镓锌氧化物薄膜,再沉积高含铟金属氧化物或高含锌金属氧化物形成中间导电层,接着沉积铟镓锌氧化物形成上层铟镓锌氧化物薄膜;
    对层叠的下层铟镓锌氧化物薄膜、中间导电层、与上层铟镓锌氧化物薄膜进行图案化处理,形成位于所述栅极上方的有源层;
    在所述栅极绝缘层及有源层上沉积第二金属层并对第二金属层进行图案化处理,得到分别接触所述有源层两侧的源极与漏极。
  7. 如权利要求6所述的金属氧化物TFT器件的制作方法,其中,通 过沉积氧化铟锡、氧化铟锌、掺铝氧化锌中的一种形成中间导电层。
  8. 如权利要求6所述的金属氧化物TFT器件的制作方法,其中,所述中间导电层的厚度为2nm~10nm,所述有源层的厚度为30nm~100nm。
  9. 如权利要求8所述的金属氧化物TFT器件的制作方法,其中,所述中间导电层的方块电阻≥1x104Ω/□。
  10. 如权利要求6所述的金属氧化物TFT器件的制作方法,其中,
    所述基板为玻璃基板;
    所述第一金属层、与第二金属层的材料均为钼、铝中的一种、或钼与铝的堆栈组合;
    所述栅极绝缘层的材料为氧化硅、或氧化铝。
  11. 一种金属氧化物TFT器件,包括基板、设在所述基板上的栅极、覆盖所述栅极与基板的栅极绝缘层、于所述栅极上方设在所述栅极绝缘层上的有源层、及设在所述栅极绝缘层上分别接触所述有源层两侧的源极与漏极;
    所述有源层包括下层铟镓锌氧化物薄膜、与所述下层铟镓锌氧化物薄膜相对设置的上层铟镓锌氧化物薄膜、及夹设在所述下层铟镓锌氧化物薄膜与上层铟镓锌氧化物薄膜之间的中间导电层;所述中间导电层的材料为高含铟金属氧化物、或高含锌金属氧化物;
    其中,所述中间导电层的材料为氧化铟锡、氧化铟锌、掺铝氧化锌中的一种;
    其中,所述中间导电层的厚度为2nm~10nm,所述有源层的厚度为30nm~100nm。
  12. 如权利要求11所述的金属氧化物TFT器件,其中,所述中间导电层的方块电阻≥1x104Ω/□。
  13. 如权利要求11所述的金属氧化物TFT器件,其中,
    所述基板为玻璃基板;
    所述栅极、源极、与漏极的材料均为钼、铝中的一种、或钼与铝的堆栈组合;
    所述栅极绝缘层的材料为氧化硅、或氧化铝。
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