WO2018196069A1 - 无机薄膜晶体管的制作方法、柔性显示装置 - Google Patents

无机薄膜晶体管的制作方法、柔性显示装置 Download PDF

Info

Publication number
WO2018196069A1
WO2018196069A1 PCT/CN2017/085562 CN2017085562W WO2018196069A1 WO 2018196069 A1 WO2018196069 A1 WO 2018196069A1 CN 2017085562 W CN2017085562 W CN 2017085562W WO 2018196069 A1 WO2018196069 A1 WO 2018196069A1
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor layer
type semiconductor
thin film
film transistor
forming
Prior art date
Application number
PCT/CN2017/085562
Other languages
English (en)
French (fr)
Inventor
梁博
Original Assignee
武汉华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 武汉华星光电技术有限公司 filed Critical 武汉华星光电技术有限公司
Priority to US15/540,543 priority Critical patent/US11004957B2/en
Publication of WO2018196069A1 publication Critical patent/WO2018196069A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates

Definitions

  • the present invention belongs to the field of display technologies, and in particular, to a method for fabricating an inorganic thin film transistor for a flexible display device and a flexible display device.
  • Inorganic thin film transistors are superior to organic thin film transistors in many aspects of electrical properties, but flexible electronic processes based on inorganic thin film transistors are cumbersome, costly, and have poor device stability.
  • Inorganic thin film transistors combined with nanoimprinting and transfer technology can ensure high electron mobility and saturation speed, and bring flexibility and bending stability close to organic thin film transistors.
  • the present invention provides a method of fabricating an inorganic thin film transistor for a flexible display device using a nanoimprinting and transfer technique, and a flexible display device.
  • the present invention provides a method of fabricating an inorganic thin film transistor, comprising: sequentially forming a P-type semiconductor layer and an N-type semiconductor layer on a hard substrate; forming a recess penetrating the N-type semiconductor layer in the P-type semiconductor layer Forming a source and a drain respectively on both sides of the recess on the N-type semiconductor layer; and the P-type semiconductor layer, the N-type semiconductor layer, and the source by flipping transfer And transferring the drain to the flexible substrate; sequentially forming a gate insulating layer and a gate on the P-type semiconductor layer; and forming a planar layer covering the gate on the gate insulating layer.
  • a method of sequentially forming a P-type semiconductor layer and an N-type semiconductor layer on a hard substrate includes: depositing a semiconductor layer on the hard substrate; sequentially performing ion implantation, crystallization, and thermal annealing on the semiconductor layer Processing to form the P-type semiconductor layer and the N-type semiconductor layer.
  • a method of forming a recess penetrating through the N-type semiconductor layer in the P-type semiconductor layer includes: coating an imprint photoresist on the N-type semiconductor layer; and applying the stamp to the press The photoresist is subjected to hot stamping to form a through hole exposing the N-type semiconductor layer in the imprint photoresist; etching the exposed N-type semiconductor layer, and in the P-type The groove is etched in the semiconductor layer; the remaining embossed photoresist is removed.
  • the exposed N-type semiconductor layer and the P-type semiconductor layer are etched by dry etching.
  • an adhesive layer is formed on the flexible substrate before the flip transfer; after the flip transfer is completed, the adhesive layer is filled between the source and the flexible substrate, the drain and Between the flexible substrates, between the N-type semiconductor layer and the flexible substrate, and in the recess.
  • the hard substrate is a glass substrate.
  • the flexible substrate is made of at least one of polyethylene terephthalate, polyethylene naphthalate, and polyimide.
  • a flexible display device having an inorganic thin film transistor fabricated by the above-described fabrication method.
  • the flexible display device is a flexible organic electroluminescent display device.
  • the invention has the beneficial effects of preparing an inorganic thin film transistor suitable for a flexible display process and having good electrical properties by nanoimprinting, obtaining a narrow-channel inorganic thin film transistor device by designing the structure of the inorganic thin film transistor, and reducing the process Requirements, cost savings.
  • the inorganic thin film transistor device can be scaled to a flexible substrate suitable for large scale production of inorganic thin film transistors for flexible display devices.
  • FIGS. 1A through 1F are flow charts of a method of fabricating an inorganic thin film transistor in accordance with an embodiment of the present invention
  • FIGS. 2A through 2D are flow diagrams of forming a groove in accordance with an embodiment of the present invention.
  • FIGS. 1A through 1F are flow charts of a method of fabricating an inorganic thin film transistor in accordance with an embodiment of the present invention. It should be noted that the inorganic thin film transistor prepared according to an embodiment of the present invention can be suitably applied to a flexible display device such as a flexible organic electroluminescence display device.
  • Step 1 Referring to FIG. 1A, a P-type semiconductor layer 210 and an N-type semiconductor layer 220 are sequentially formed on the rigid substrate 100.
  • the hard substrate 100 may be made of glass, ceramic or metal.
  • the rigid substrate 100 is preferably made of glass.
  • step one Specific methods for implementing step one include:
  • a semiconductor layer is deposited on the hard substrate 100.
  • a Si layer that is, a semiconductor layer, may be formed on the rigid substrate 100 by chemical vapor deposition (CVD).
  • the semiconductor layer is subjected to IMP ion implantation, ELA crystallization, or high temperature thermal annealing treatment to form a P-type semiconductor layer 210 and an N-type semiconductor layer 220.
  • Step 2 Referring to FIG. 1B, a recess 230 penetrating the N-type semiconductor layer 220 is formed in the P-type semiconductor layer 210.
  • FIGS. 2A through 2D are flow diagrams of forming a groove in accordance with an embodiment of the present invention.
  • a specific method of forming the groove 230 according to an embodiment of the present invention includes:
  • an imprint photoresist 1000 is applied over the N-type semiconductor layer 220.
  • the imprint photoresist 1000 is subjected to hot stamping using the imprinting mold 2000 to form a via hole 1010 exposing the N-type semiconductor layer 220 in the imprint photoresist 1000.
  • the exposed N-type semiconductor layer 220 is etched away, and the recess 230 is etched in the P-type semiconductor layer 210.
  • the exposed N-type semiconductor layer 220 and P-type semiconductor layer 210 are etched by dry etching.
  • Step 3 Referring to FIG. 1C, a source 310 and a drain 320 respectively located on both sides of the recess 230 are formed on the N-type semiconductor layer 220.
  • Step 4 Referring to FIG. 1D, the P-type semiconductor layer 210, the N-type semiconductor layer 220, the source 310, and the drain 320 are transferred onto the flexible substrate 400 by flip transfer.
  • an adhesive layer 500 is formed on the flexible substrate 400 before the flip transfer; after the flip transfer is completed, the adhesive layer 500 is filled between the source 310 and the flexible substrate 400, the drain 320, and the flexible substrate 400. Between, between the N-type semiconductor layer 220 and the flexible substrate 400 and in the recess 230.
  • the adhesive layer 500 may not be disposed, which may save a process and simplify the manufacturing process.
  • the flexible substrate 400 may be made of at least one of polyethylene terephthalate, polyethylene naphthalate, polyimide, or the like.
  • Step 5 Referring to FIG. 1E, a gate insulating layer 600 and a gate electrode 700 are sequentially formed on the P-type semiconductor layer 210. It should be noted that before the gate insulating layer 600 and the gate 700 are formed, the P-type semiconductor layer 210 may be patterned according to actual needs to obtain a desired active layer structure.
  • Step 6 Referring to FIG. 1F, a planar layer 800 covering the gate 700 is formed on the gate insulating layer 600.
  • an inorganic thin film transistor suitable for a flexible display process and having good electrical properties is prepared by a nanoimprint method, and a narrow channel inorganic film is obtained by designing the structure of the inorganic thin film transistor. Transistor devices and reduce process requirements, saving costs.
  • the inorganic thin film transistor device can be scaled to a flexible substrate suitable for large scale production of inorganic thin film transistors for flexible display.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Nanotechnology (AREA)
  • Thin Film Transistor (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

一种无机薄膜晶体管的制作方法，包括：在硬质基板（100）上依次形成P型半导体层（210）和N型半导体层（220）；在P型半导体层中形成贯穿N型半导体层的凹槽（230）；在N型半导体层上形成分别位于凹槽两侧的源极（310）和漏极（320）；通过翻转转移的方式将P型半导体层、N型半导体层、源极和漏极转移到柔性基板（400）上；在P型半导体层上依次形成栅极绝缘层（600）和栅极（700）；在栅极绝缘层上形成覆盖栅极的平坦层（800）。还提供了一种由该制作方法制作的无机薄膜晶体管的柔性显示装置。通过纳米压印的方法制备适于柔性显示制程且有良好电学性能的无机薄膜晶体管，通过设计无机薄膜晶体管的结构，获得窄沟道无机薄膜晶体管器件，并降低制程要求，节约成本。

Description

无机薄膜晶体管的制作方法、柔性显示装置 技术领域
本发明属于显示技术领域，具体地讲，涉及一种用于柔性显示装置的无机薄膜晶体管的制作方法、柔性显示装置。
背景技术
无机薄膜晶体管(Thin-filmtransistor，简称TFT)在电性性能的多个方面都优于有机薄膜晶体管，但基于无机薄膜晶体管的柔性电子学制程较为繁琐，成本高昂，且器件稳定性较差。结合纳米压印和转印技术的无机薄膜晶体管，既能保证较高的电子迁移率和饱和速度，又能带来接近有机薄膜晶体管的柔性和耐弯折稳定性。
因此，有必要提供一种利用纳米压印和转印技术制作无机薄膜晶体管的方法。
发明内容
本发明提供了一种利用纳米压印和转印技术的用于柔性显示装置的无机薄膜晶体管的制作方法、柔性显示装置。
本发明提供了一种无机薄膜晶体管的制作方法，包括：在硬质基板上依次形成P型半导体层和N型半导体层；在所述P型半导体层中形成贯穿所述N型半导体层的凹槽；在所述N型半导体层上形成分别位于所述凹槽两侧的源极和漏极；通过翻转转移的方式将所述P型半导体层、所述N型半导体层、所述源极和所述漏极转移到柔性基板上；在所述P型半导体层上依次形成栅极绝缘层和栅极；在所述栅极绝缘层上形成覆盖所述栅极的平坦层。
可选地，在硬质基板上依次形成P型半导体层和N型半导体层的方法包括：在所述硬质基板上沉积形成半导体层；对所述半导体层依次进行离子注入、结晶和热退火处理，以形成所述P型半导体层和所述N型半导体层。
可选地，在所述P型半导体层中形成贯穿所述N型半导体层的凹槽的方法包括：在所述N型半导体层上涂布压印光阻；利用压印模具对所述压印光阻进行热压印成型，以在所述压印光阻中形成暴露所述N型半导体层的通孔；将暴露出的所述N型半导体层刻蚀去除，并在所述P型半导体层中刻蚀形成所述凹槽；将剩余的所述压印光阻去除。
可选地，利用干刻的方式对暴露出的所述N型半导体层和所述P型半导体层进行刻蚀。
可选地，在翻转转移之前，在所述柔性基板上形成粘合层；在翻转转移完成之后，所述粘合层填充于所述源极和所述柔性基板之间、所述漏极和所述柔性基板之间、所述N型半导体层和所述柔性基板之间以及所述凹槽中。
可选地，所述硬质基板为玻璃基板。
可选地，所述柔性基板采用聚对苯二甲酸乙二醇酯、聚萘二甲酸乙二醇酯、聚酰亚胺中的至少一种制成。
根据本发明的另一方面，还提供了一种具有由上述的制作方法制作的无机薄膜晶体管的柔性显示装置。
可选地，所述柔性显示装置为柔性有机电致发光显示装置。
本发明的有益效果：通过纳米压印的方法制备适于柔性显示制程且有良好电学性能的无机薄膜晶体管，通过对无机薄膜晶体管的结构的设计，获得窄沟道无机薄膜晶体管器件，并降低制程要求，节约成本。此外，可以将无机薄膜晶体管器件规模化转移到柔性基底，适于规模化制备用于柔性显示装置的无机薄膜晶体管。
附图说明
通过结合附图进行的以下描述，本发明的实施例的上述和其它方面、特点和优点将变得更加清楚，附图中：
图1A至图1F是根据本发明的实施例的制作无机薄膜晶体管的方法流程图；
图2A至图2D是根据本发明的实施例的形成凹槽的流程图。
具体实施方式
以下，将参照附图来详细描述本发明的实施例。然而，可以以许多不同的形式来实施本发明，并且本发明不应该被解释为限制于这里阐述的具体实施例。相反，提供这些实施例是为了解释本发明的原理及其实际应用，从而使本领域的其他技术人员能够理解本发明的各种实施例和适合于特定预期应用的各种修改。
在附图中，为了清楚展示器件结构，夸大了层和区域的厚度。相同的标号在整个说明书和附图中表示相同的元器件。
将理解的是，当诸如层、膜、区域或基底的元件被称作“在”另一元件“上”时，该元件可以直接在所述另一元件上，或者也可以存在中间元件。可选择地，当元件被称作“直接在”另一元件“上”时，不存在中间元件。
图1A至图1F是根据本发明的实施例制作无机薄膜晶体管的方法流程图。应当说明的是，根据本发明实施例制备的无机薄膜晶体管可很好地应用于柔性显示装置中，诸如柔性有机电致发光显示装置。
根据本发明的实施例的无机薄膜晶体管的制作方法包括：
步骤一：参照图1A，在硬质基板100上依次形成P型半导体层210和N型半导体层220。
硬质基板100可以采用玻璃、陶瓷或金属制成。在本实施例中，硬质基板100优选地采用玻璃制成。
实现步骤一的具体方法包括：
首先，在硬质基板100上沉积形成半导体层。这里可以采用化学气相沉积法(CVD)在硬质基板100上形成Si层，即所述半导体层。
其次，对所述半导体层进行IMP离子注入、ELA结晶或高温热退火处理，以形成P型半导体层210和N型半导体层220。
步骤二：参照图1B，在P型半导体层210中形成贯穿N型半导体层220的凹槽230。
图2A至图2D是根据本发明的实施例的形成凹槽的流程图。
根据本发明的实施例的形成凹槽230的具体方法包括：
首先，参照图2A，在N型半导体层220上涂布压印光阻1000。
接着，参照图2B，利用压印模具2000对压印光阻1000进行热压印成型，以在压印光阻1000中形成暴露所述N型半导体层220的通孔1010。
接着，参照图2C，将暴露出的N型半导体层220刻蚀去除，并在P型半导体层210中刻蚀形成凹槽230。
这里，进一步地，利用干刻的方式对暴露出的N型半导体层220和P型半导体层210进行刻蚀。
最后，参照图2D，将剩余的压印光阻1000去除。
步骤三：参照图1C，在N型半导体层220上形成分别位于凹槽230两侧的源极310和漏极320。
步骤四：参照图1D，通过翻转转移的方式将P型半导体层210、N型半导体层220、源极310和漏极320转移到柔性基板400上。
这里，进一步地，在翻转转移之前，在柔性基板400上形成粘合层500；在翻转转移完成之后，粘合层500填充于源极310和柔性基板400之间、漏极320和柔性基板400之间、N型半导体层220和柔性基板400之间以及凹槽230中。
需要说明的是，作为本发明的另一实施方式，粘合层500不设置也可以，这样可以节省一道制程，从而简化制作流程。
此外，柔性基板400可以采用聚对苯二甲酸乙二醇酯、聚萘二甲酸乙二醇酯、聚酰亚胺等中的至少一种制成。
步骤五：参照图1E，在P型半导体层210上依次形成栅极绝缘层600和栅极700。需要说明的是，在形成栅极绝缘层600和栅极700之前，可根据实际需求对P型半导体层210进行图案化处理，获取需要的有源层结构。
步骤六：参照图1F，在栅极绝缘层600上形成覆盖栅极700的平坦层800。
综上所述，根据本发明的实施例，通过纳米压印的方法制备适于柔性显示制程且有良好电学性能的无机薄膜晶体管，通过对无机薄膜晶体管的结构的设计，获得窄沟道无机薄膜晶体管器件，并降低制程要求，节约成本。此外，可以将无机薄膜晶体管器件规模化转移到柔性基底，适于规模化制备用于柔性显示的无机薄膜晶体管。
虽然已经参照特定实施例示出并描述了本发明，但是本领域的技术人员将理解：在不脱离由权利要求及其等同物限定的本发明的精神和范围的情况下，可在此进行形式和细节上的各种变化。

Claims (9)

  1. 一种无机薄膜晶体管的制作方法，其中，包括：
    在硬质基板上依次形成P型半导体层和N型半导体层；
    在所述P型半导体层中形成贯穿所述N型半导体层的凹槽；
    在所述N型半导体层上形成分别位于所述凹槽两侧的源极和漏极；
    通过翻转转移的方式将所述P型半导体层、所述N型半导体层、所述源极和所述漏极转移到柔性基板上；
    在所述P型半导体层上依次形成栅极绝缘层和栅极；
    在所述栅极绝缘层上形成覆盖所述栅极的平坦层。
  2. 根据权利要求1所述的制作方法，其中，在硬质基板上依次形成P型半导体层和N型半导体层的方法包括：
    在所述硬质基板上沉积形成半导体层；
    对所述半导体层依次进行离子注入、结晶和热退火处理，以形成所述P型半导体层和所述N型半导体层。
  3. 根据权利要求1所述的制作方法，其中，在所述P型半导体层中形成贯穿所述N型半导体层的凹槽的方法包括：
    在所述N型半导体层上涂布压印光阻；
    利用压印模具对所述压印光阻进行热压印成型，以在所述压印光阻中形成暴露所述N型半导体层的通孔；
    将暴露出的所述N型半导体层刻蚀去除，并在所述P型半导体层中刻蚀形成所述凹槽；
    将剩余的所述压印光阻去除。
  4. 根据权利要求3所述的制作方法，其中，利用干刻的方式对暴露出的所述N型半导体层和所述P型半导体层进行刻蚀。
  5. 根据权利要求1所述的制作方法，其中，在翻转转移之前，在所述柔性基板上形成粘合层；
    在翻转转移完成之后，所述粘合层填充于所述源极和所述柔性基板之间、所述漏极和所述柔性基板之间、所述N型半导体层和所述柔性基板之间以及所述凹槽中。
  6. 根据权利要求1所述的制作方法，其中，所述硬质基板为玻璃基板。
  7. 根据权利要求1所述的制作方法，其中，所述柔性基板采用聚对苯二甲酸乙二醇酯、聚萘二甲酸乙二醇酯、聚酰亚胺中的至少一种制成。
  8. 一种具有由权利要求1所述的制作方法制作的无机薄膜晶体管的柔性显示装置。
  9. 根据权利要求8所述的柔性显示装置，其中，所述柔性显示装置为柔性有机电致发光显示装置。
PCT/CN2017/085562 2017-04-28 2017-05-23 无机薄膜晶体管的制作方法、柔性显示装置 WO2018196069A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US15/540,543 US11004957B2 (en) 2017-04-28 2017-05-23 Manufacturing methods of inorganic thin film transistors (TFTs) and flexible display devices

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201710296914.0A CN107093558A (zh) 2017-04-28 2017-04-28 无机薄膜晶体管的制作方法、柔性显示装置
CN201710296914.0 2017-04-28

Publications (1)

Publication Number Publication Date
WO2018196069A1 true WO2018196069A1 (zh) 2018-11-01

Family

ID=59638350

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/085562 WO2018196069A1 (zh) 2017-04-28 2017-05-23 无机薄膜晶体管的制作方法、柔性显示装置

Country Status (2)

Country Link
CN (1) CN107093558A (zh)
WO (1) WO2018196069A1 (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109103206B (zh) * 2018-08-22 2021-03-19 京东方科技集团股份有限公司 薄膜晶体管结构、阵列基板和薄膜晶体管结构的制造方法
TWI702579B (zh) 2019-05-07 2020-08-21 友達光電股份有限公司 軟性顯示器
CN111725149B (zh) * 2019-10-21 2022-06-07 中国科学院上海微系统与信息技术研究所 一种柔性电子器件及其制备方法
CN111653205B (zh) * 2020-07-15 2021-12-28 上海天马微电子有限公司 可拉伸显示面板和显示装置
CN113471297B (zh) * 2021-06-01 2023-06-20 华南理工大学 一种基于金属氧化物纳米纤维网络有源层的可拉伸薄膜晶体管及其制备方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101281948A (zh) * 2008-04-29 2008-10-08 北京大学 薄膜型光子晶格结构GaN基发光二极管的制备方法
CN101587830A (zh) * 2008-05-21 2009-11-25 上海市纳米科技与产业发展促进中心 大面积纳米线p-n结阵列及其制备方法
CN103066178A (zh) * 2012-12-29 2013-04-24 映瑞光电科技(上海)有限公司 一种倒装光子晶体led芯片及其制造方法
CN106206611A (zh) * 2016-08-19 2016-12-07 京东方科技集团股份有限公司 阵列基板及其制备方法、显示装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06252400A (ja) * 1992-12-28 1994-09-09 Sony Corp 横型絶縁ゲート型電界効果トランジスタの製法
KR20160028587A (ko) * 2014-09-03 2016-03-14 삼성디스플레이 주식회사 박막 트랜지스터 어레이 기판과 이의 제조 방법 및 이를 포함하는 액정 표시 장치
US9704999B2 (en) * 2015-03-20 2017-07-11 Wisconsin Alumni Research Foundation Thin film transistors with trench-defined nanoscale channel lengths
CN110299405B (zh) * 2016-07-04 2021-05-04 华为技术有限公司 一种基于二维半导体的电子器件及其制造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101281948A (zh) * 2008-04-29 2008-10-08 北京大学 薄膜型光子晶格结构GaN基发光二极管的制备方法
CN101587830A (zh) * 2008-05-21 2009-11-25 上海市纳米科技与产业发展促进中心 大面积纳米线p-n结阵列及其制备方法
CN103066178A (zh) * 2012-12-29 2013-04-24 映瑞光电科技(上海)有限公司 一种倒装光子晶体led芯片及其制造方法
CN106206611A (zh) * 2016-08-19 2016-12-07 京东方科技集团股份有限公司 阵列基板及其制备方法、显示装置

Also Published As

Publication number Publication date
CN107093558A (zh) 2017-08-25

Similar Documents

Publication Publication Date Title
WO2018196069A1 (zh) 无机薄膜晶体管的制作方法、柔性显示装置
JP4831406B2 (ja) 半導体装置の製造方法
US10236388B2 (en) Dual gate oxide thin-film transistor and manufacturing method for the same
Zhao et al. High‐performance full‐photolithographic top‐contact conformable organic transistors for soft electronics
WO2016074204A1 (zh) 基于双栅极结构的低温多晶硅薄膜晶体管及其制备方法
TW200605356A (en) Method for fabricating a thin film transistor and related circuits
EP1958243A4 (en) METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE
TW200735366A (en) Double gate thin-film transistor and method for forming the same
CN103151305A (zh) 一种薄膜晶体管阵列基板、制备方法以及显示装置
WO2016008277A1 (zh) 一种有机单晶场效应电路及其制备方法
WO2015188594A1 (zh) 多晶硅层及显示基板的制备方法、显示基板
TW200727487A (en) Structure of thin film transistor array and method for making the same
WO2016201725A1 (zh) 低温多晶硅tft基板的制作方法及低温多晶硅tft基板
WO2018120309A1 (zh) Oled显示装置的阵列基板及其制作方法
WO2017024612A1 (zh) 氧化物半导体tft基板的制作方法及其结构
US20120280235A1 (en) Thin film fet device and method for forming the same
WO2016026176A1 (zh) Tft基板的制作方法及其结构
WO2019029007A1 (zh) 一种tft基板的制备方法、tft基板以及oled显示面板
JP2020520119A (ja) Ｔｆｔ基板の製造方法
WO2019184026A1 (zh) Cmos晶体管的制备方法、阵列基板的制备方法
TWI257177B (en) Manufacturing processes for a thin film transistor and a pixel structure
WO2020228421A1 (zh) 阵列基板、其制备方法及显示面板
US11004957B2 (en) Manufacturing methods of inorganic thin film transistors (TFTs) and flexible display devices
JPWO2022249872A5 (zh)
JP2007194337A5 (zh)

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 15540543

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17907477

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 17907477

Country of ref document: EP

Kind code of ref document: A1