WO2018188319A1 - 低温多晶硅薄膜晶体管及其制造方法、显示基板 - Google Patents

低温多晶硅薄膜晶体管及其制造方法、显示基板 Download PDF

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WO2018188319A1
WO2018188319A1 PCT/CN2017/108031 CN2017108031W WO2018188319A1 WO 2018188319 A1 WO2018188319 A1 WO 2018188319A1 CN 2017108031 W CN2017108031 W CN 2017108031W WO 2018188319 A1 WO2018188319 A1 WO 2018188319A1
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substrate
layer
pattern
orthographic projection
amorphous silicon
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PCT/CN2017/108031
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English (en)
French (fr)
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何晓龙
李治福
袁广才
钱海蛟
李东升
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京东方科技集团股份有限公司
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Priority to US15/781,327 priority Critical patent/US10700107B2/en
Priority to EP17898329.2A priority patent/EP3518290A4/en
Publication of WO2018188319A1 publication Critical patent/WO2018188319A1/zh

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Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a low temperature polysilicon thin film transistor and a method of fabricating the same, and a display substrate including the low temperature polysilicon thin film transistor.
  • polycrystalline silicon (p-Si) thin film transistors have advantages of high mobility and low power consumption relative to amorphous silicon (a-Si) thin film transistors (TFTs), in recent years, applications of polysilicon thin film transistors have become more and more popular. widely.
  • top-gate LTPS thin film transistors are generally top-gate thin film transistors, and top-gate LTPS thin film transistors generally require a process of preparing a light shielding layer, performing source/drain doping, and setting a lightly doped drain (Ldd) structure. The process is complicated and the cost is high.
  • Ldd lightly doped drain
  • the conventional bottom gate type LTPS thin film transistor in order to solve the problem of excessive channel leakage current, it is generally required to fabricate an a-Si/p-Si/a-Si type channel, but the conventional manufacturing process cannot be guaranteed.
  • the positional accuracy of the intermediate p-Si affects the channel width and uniformity of the thin film transistor.
  • the manufacturing process of the conventional bottom gate type LTPS thin film transistor there is also a problem that the back channel etching damages the active layer.
  • embodiments of the present disclosure propose an improved low A tempered polysilicon thin film transistor and a method of fabricating the same, and a display substrate including the low temperature polysilicon thin film transistor.
  • a low temperature polysilicon thin film transistor is provided.
  • a low temperature polysilicon thin film transistor may include: a substrate; a gate disposed on the substrate; and an active layer disposed on the gate, the active layer including a channel region having a polysilicon A region and an amorphous silicon region respectively located on both sides of the polysilicon region.
  • An orthographic projection of the polysilicon region on the substrate is located within an orthographic projection of the gate on the substrate and an area of orthographic projection of the polysilicon region on the substrate is less than the gate on the substrate The area of the orthographic projection on.
  • the low temperature polysilicon thin film transistor may further include: an etch barrier layer disposed on the active layer, and an orthographic projection of the polysilicon region on the substrate is located at the etch barrier A layer is within an orthographic projection on the substrate and an area of the orthographic projection of the polysilicon region on the substrate is less than an area of an orthographic projection of the etch stop layer on the substrate.
  • an orthographic projection of the etch stop layer on the substrate is located within an orthographic projection of the gate on the substrate and an area of the orthographic projection of the etch stop layer on the substrate Less than the area of the orthographic projection of the gate on the substrate.
  • the low temperature polysilicon thin film transistor may further include: an ohmic contact layer disposed on the etch barrier layer and the active layer, and ohmic contact on the etch barrier layer in a region corresponding to the polysilicon region The layer is etched away, and both ends of the etch barrier layer in a direction parallel to the substrate are covered by the ohmic contact layer.
  • the low temperature polysilicon thin film transistor may further include: a source and a drain disposed on the ohmic contact layer, the patterns of the source and the drain being the same as the pattern of the ohmic contact layer.
  • a display substrate there is also provided a display substrate.
  • the display substrate may include the low temperature polysilicon thin film transistor described in any of the above embodiments.
  • a method of fabricating a low temperature polysilicon thin film transistor is also provided.
  • a method of fabricating a low temperature polysilicon thin film transistor may include the steps of: providing a substrate; forming a gate on the substrate; forming an amorphous silicon layer on the gate; Forming an ohmic contact layer on the silicon layer; forming a source/drain layer on the ohmic contact layer; forming a pattern of the ohmic contact layer and a pattern of the source and drain layers by a patterning process so that in a region corresponding to the polysilicon region to be formed The ohmic contact layer and the source and drain layers are etched away; and a laser annealing process is performed on the amorphous silicon layer using a reticle to convert amorphous silicon in a partial region of the amorphous silicon layer into polysilicon.
  • An orthographic projection of the open area of the reticle on the substrate is located within an orthographic projection of the gate on the substrate and an area of the orthographic projection of the open area of the reticle on the substrate is less than the area of the gate on the substrate The area of the orthographic projection.
  • the manufacturing method may further include the steps of: forming an etch barrier layer on the amorphous silicon layer; and forming a pattern of the etch barrier layer by a patterning process.
  • the step of forming an ohmic contact layer on the amorphous silicon layer includes: forming an ohmic contact layer on the pattern of the etch stop layer and the amorphous silicon layer, and the orthographic projection of the formed polysilicon region on the substrate falls The pattern of the etch stop layer is within the orthographic projection on the substrate and the area of the orthographic projection of the formed polysilicon region on the substrate is less than the area of the orthographic projection of the pattern of the etch stop layer on the substrate.
  • an orthographic projection of the pattern of the etch barrier layer on the substrate falls within an orthographic projection of the gate on the substrate and a pattern of the etch barrier layer is on the substrate
  • the area of the orthographic projection is smaller than the area of the orthographic projection of the gate on the substrate.
  • the pattern of the ohmic contact layer and the source and drain layers is formed by a patterning process such that the ohmic contact layer and the source and drain layers are etched away in a region corresponding to the polysilicon region to be formed, including: etching An ohmic contact layer and a source/drain layer in a region corresponding to the polysilicon region to be formed to expose a portion of the pattern of the etch barrier layer, and such that the pattern of the etch barrier layer is along both ends parallel to the substrate Both are covered by an ohmic contact layer.
  • the manufacturing method may further include: Etching the substrate without using the pattern of the ohmic contact layer and/or the source/drain layer as a mask A pattern of ohmic contact layers and/or source and drain layers and an amorphous silicon layer covered by a pattern of etch stop layers.
  • the step of performing a laser annealing process on the amorphous silicon layer by using the reticle may include: keeping the laser light source fixed, extending the time that the laser light emitted by the laser light source illuminates the amorphous silicon layer, so that the amorphous silicon layer is Amorphous silicon in a portion of the predetermined region is converted into polysilicon.
  • the step of forming the pattern of the ohmic contact layer and the pattern of the source and drain layers by the patterning process may include forming a pattern of the ohmic contact layer and a pattern of the source and drain layers by one patterning process such that the pattern of the source and drain electrodes The same pattern as the ohmic contact layer.
  • the step of forming a pattern of the ohmic contact layer and a pattern of the source and drain layers by a patterning process may include: forming a pattern of source and drain electrodes by wet etching; and forming a pattern of the ohmic contact layer by dry etching .
  • a method of fabricating a low temperature polysilicon thin film transistor is provided.
  • a method of fabricating a low temperature polysilicon thin film transistor may include the steps of: providing a substrate; forming a gate on the substrate; forming an amorphous silicon layer on the gate; Forming an ohmic contact layer on the silicon layer; forming a pattern of the ohmic contact layer by a patterning process such that the ohmic contact layer in the region corresponding to the polysilicon region to be formed is etched away; and performing laser processing on the amorphous silicon layer using the reticle The annealing process converts amorphous silicon in a partial region of the amorphous silicon layer into polysilicon.
  • An orthographic projection of the open area of the reticle on the substrate is located within an orthographic projection of the gate on the substrate and an area of the orthographic projection of the open area of the reticle on the substrate is less than the area of the gate on the substrate The area of the orthographic projection.
  • the method may further include the steps of: forming an etch barrier layer on the amorphous silicon layer; and forming a pattern of the etch barrier layer by a patterning process.
  • the step of forming an ohmic contact layer on the amorphous silicon layer may include: forming an ohmic contact layer on the pattern of the etch stop layer and the amorphous silicon layer, and forming an orthographic projection of the polysilicon region on the substrate.
  • the pattern of the etch stop layer is within the orthographic projection on the substrate and the area of the orthographic projection of the formed polysilicon region on the substrate is less than the area of the orthographic projection of the pattern of the etch stop layer on the substrate.
  • an orthographic projection of the pattern of the etch stop layer on the substrate falls into the An area of the gate within the orthographic projection on the substrate and an orthographic projection of the pattern of the etch stop layer on the substrate is less than an area of the orthographic projection of the gate on the substrate.
  • the step of performing a laser annealing process on the amorphous silicon layer by using the reticle comprises: keeping the laser light source fixed, and prolonging the time that the laser light emitted by the laser light source illuminates the amorphous silicon layer, so that the amorphous silicon layer is Amorphous silicon in a portion of the predetermined region is converted into polysilicon.
  • the manufacturing method may further include: on the ohmic contact layer Forming a source drain layer; and patterning the source drain layer by a patterning process such that the source and drain layers in the region corresponding to the formed polysilicon region are etched away.
  • FIG. 1 is a flow chart of a method of fabricating a low temperature polysilicon thin film transistor in accordance with an embodiment of the present disclosure
  • FIG. 10 is a flowchart of a method of fabricating a low temperature polysilicon thin film transistor according to another embodiment of the present disclosure.
  • FIG. 11 is a flowchart of a method of fabricating a low temperature polysilicon thin film transistor according to still another embodiment of the present disclosure.
  • FIG. 12 is a schematic structural diagram of a low temperature polysilicon thin film transistor according to an embodiment of the present disclosure.
  • on may mean that one layer is directly formed or disposed on another layer, and may also represent one.
  • the layers are formed indirectly or on another layer, ie there are other layers between the two layers.
  • a method of fabricating a low temperature polysilicon thin film transistor is provided.
  • FIG. 1 shows a flow chart of a method of fabricating a low temperature polysilicon thin film transistor in accordance with an embodiment of the present disclosure.
  • 2, 2A and 3-9 schematically illustrate various main steps of a method of fabricating a low temperature polysilicon thin film transistor in accordance with an embodiment of the present disclosure.
  • a method of manufacturing a low temperature polysilicon thin film transistor according to an embodiment of the present disclosure will be described in detail with reference to FIGS. 1-9.
  • a substrate 20 is provided as shown in FIG.
  • the substrate may be a transparent substrate such as a glass substrate.
  • a gate electrode 22 is formed on the substrate 20 as shown in FIG.
  • a full layer of gate material layer 22' may be deposited on substrate 20, as shown in Figure 2A, and then patterned by a patterning process to form a pattern of gate material layers, i.e., gate 22 as shown in FIG.
  • the patterning process referred to herein generally includes process steps such as photoresist coating, masking, exposure, development, etching, photoresist stripping, etc., and various types commonly used in the field can be used according to actual process requirements.
  • a patterning process is used to form the structures in the embodiments of the present disclosure.
  • a gate insulating layer 24 and an amorphous silicon layer 26' are sequentially formed on the substrate 20 on which the gate electrode 22 is formed, as shown in Fig. 3. Specifically, a full layer of the gate insulating layer 24 may be deposited on the substrate 20 on which the gate electrode 22 is formed, and then an entire layer of the amorphous silicon layer 26' may be deposited on the gate insulating layer 24. In some embodiments, after the formation of the amorphous silicon layer 26', a dehydrogenation process is also performed to avoid hydrogen explosion during crystallization of amorphous silicon. It will be understood by those skilled in the art that the amorphous silicon layer is an active layer or a semiconductor layer of a thin film transistor.
  • an etch stop layer 28' is formed on the amorphous silicon layer 26' as shown in FIG. Specifically, an etch stop layer 28' is formed on the amorphous silicon layer 26' by deposition.
  • the etch stop layer 28' can be formed of silicon oxide or silicon nitride.
  • the pattern 28 of the etch stop layer is formed by a patterning process as shown in FIG.
  • the orthographic projection of the pattern 28 of etch stop layer on the substrate 20 falls within the orthographic projection of the gate 22 on the substrate 20, and the orthographic projection of the pattern 28 of the etch stop layer on the substrate 20 The area is smaller than the area of the orthographic projection of the gate 22 on the substrate 20.
  • the width WESL of the pattern 28 of etch stop layers in a direction parallel to the substrate 20 is smaller than the width WG of the gate 22 in a direction parallel to the substrate 20.
  • an ohmic contact layer 30' and a source/drain layer 32' are sequentially formed on the substrate 20 as shown in Fig. 6.
  • the ohmic contact layer 30' and the source and drain layer 32' are sequentially formed on the substrate 20 by deposition to cover the pattern 28 of the etch barrier layer and the amorphous silicon layer 26'.
  • the ohmic contact layer 30' is formed of doped amorphous silicon, for example, from N-type doped amorphous silicon or P-type doped amorphous silicon.
  • the source and drain layer 32' is formed of a metal material.
  • the step of forming the ohmic contact layer 30' on the substrate 20 may include depositing a layer of pre-doped N-doped amorphous silicon or P-doped amorphous silicon on the substrate 20. . In still other embodiments, the step of forming the ohmic contact layer 30' on the substrate 20 may include: depositing a second amorphous silicon layer on the substrate 20; and doping the second amorphous silicon layer.
  • the pattern 30 of the ohmic contact layer and the pattern 32 of the source and drain layers are formed by a patterning process, as shown in FIG.
  • the pattern 30 of the ohmic contact layer and the source and drain layers are patterned
  • the case 32 can be the same, so that the pattern 30 of the ohmic contact layer and the pattern 32 of the source and drain layers can be formed by one patterning process, thereby simplifying the manufacturing process and improving the processing efficiency.
  • the ohmic contact layer 30' and the source and drain layer 32' are respectively formed of an amorphous silicon material and a metal material
  • the pattern 30 of the ohmic contact layer and the pattern 32 of the source and drain layers are formed by a patterning process.
  • the process steps of photoresist coating, masking, exposure, development, photoresist stripping, etc. are all the same, but the etching process steps may be different.
  • the pattern 30 of the ohmic contact layer may be formed by a dry etching process, and the pattern 32 of the source and drain layers is formed by a wet etching process.
  • the pattern 30 of the ohmic contact layer and the pattern 32 of the source and drain layers are formed by a patterning process such that a portion of the pattern of the etch stop layer is exposed and the barrier layer is etched Both ends 281, 282 of the pattern 28 in a direction parallel to the substrate are covered by the pattern 30 of the ohmic contact layer.
  • the width of the channel 321 in the pattern 32 of the source drain layer and the channel 301 in the pattern 30 of the ohmic contact layer in a direction parallel to the substrate and the pattern 28 each being smaller than the etch barrier layer are parallel to The width WESL in the direction of the substrate.
  • step S108 a laser annealing process is performed on the amorphous silicon layer 26' using the reticle 100, so that amorphous silicon in a partial region of the amorphous silicon layer 26' is converted into polycrystalline silicon.
  • the laser light source 200, the reticle 100, and the substrate 20 are sequentially disposed from top to bottom, and the laser beam 202 emitted from the laser light source 200 is formed toward the substrate 20 through the opening region 102 of the reticle 100.
  • One side of the amorphous silicon layer 26' is irradiated.
  • the laser annealing process used may be an excimer laser annealing process, and accordingly, the laser beam 202 emitted by the laser source 200 is an excimer laser beam 202.
  • the excimer laser beam 202 is continuously irradiated to a portion of the amorphous silicon layer 26' for a while, the irradiated portion of the amorphous silicon layer 26' can be melted and then recrystallized to be converted into polycrystalline silicon.
  • the orthographic projection of the open region 102 of the reticle 100 on the substrate 20 is within the orthographic projection of the gate 22 on the substrate 20 and the area of the orthographic projection of the open region 102 of the reticle on the substrate 20 is less than
  • the area of the orthographic projection of the gate 22 on the substrate 20 is as shown in Fig. 8A.
  • the laser beam is irradiated over the entire range of the substrate 20, and the step difference of the gate, such as the step angle caused by the slope angle ⁇ of the gate shown in FIG. 8A, causes crystallization to occur.
  • the unevenness causes a large leakage current of the formed thin film transistor and a decrease in performance of the thin film transistor.
  • the laser beam is irradiated only above the gate, thereby avoiding the phenomenon of crystallization non-uniformity caused by the step difference in the conventional laser annealing process.
  • the orthographic projection of the open area 102 of the reticle on the substrate may be slightly larger than the orthographic projection of the channel 321 in the pattern 32 of the source and drain layers on the substrate, ie, in the pattern 32 of the source and drain layers.
  • the orthographic projection of the channel 321 on the substrate is located within the orthographic projection of the open region 102 of the reticle on the substrate, and the area of the orthographic projection of the channel 321 in the pattern 32 of the source and drain layers on the substrate is slightly less than The area of the orthographic projection of the open area 102 of the reticle on the substrate.
  • the emitted laser light can also be confined in the channel region by the pattern of the source and drain, so that the amorphous silicon under the etch barrier layer in the channel region is crystallized, so that the crystallized region can be precisely controlled, and at the same time
  • the aligning requirements of the stencil are reduced, which is conducive to mass production.
  • the source and drain layers are generally formed of a metal material and have good thermal conductivity, the pattern of the ohmic contact layer under the source and drain layers is performed when laser irradiation is performed. 30 and the amorphous silicon layer 26' are unable to absorb the thermal energy of the excimer laser beam 202. That is, the pattern 32 of the source and drain layers also functions as a masking layer so that the portion of the amorphous silicon layer 26' that is blocked by it does not transform into polysilicon. Moreover, since the source and drain layers are generally formed of a metal material and have good thermal conductivity, the source and drain layers can ensure that portions of the amorphous silicon layer that are blocked by them are not converted into polysilicon.
  • the self-aligned laser annealing is performed on the channel region by using the pattern of the source and drain layers as a occlusion layer, thereby ensuring the positional accuracy of the formed polysilicon region, and A thin film transistor having a narrow channel is formed.
  • laser source 200 emits a laser beam 202 that first passes through reticle 100, and only laser beam 202 at open region 102 of the reticle can pass through reticle 100. Since the orthographic projection of the open area 102 of the reticle 100 on the substrate 20 is located within the orthographic projection of the gate 22 on the substrate 20 and the area of the orthographic projection of the open area 102 of the reticle on the substrate 20 is smaller than the area of the gate 22 on the substrate The area of the orthographic projection on 20, so the illumination range of the laser beam 202 is on the substrate 20 The upper orthographic projection falls within the range of the orthographic projection of the gate 22 on the substrate 20, as shown in Fig. 8B.
  • the pattern 32 of the source and drain layers also functions as a mask layer so that the portion of the amorphous silicon layer 26' that is blocked by it does not be converted into polysilicon.
  • the pattern 28 of the etch stop layer does not absorb the thermal energy of the laser beam 202, a portion of the amorphous silicon layer 26' under the pattern 28 of the etch stop layer will absorb the thermal energy of the laser beam 202 to form a polysilicon region.
  • the channel region of the amorphous silicon layer 26' is formed to include the polysilicon region 262 located in the middle and the amorphous silicon region 264 located on both sides of the polysilicon region 262 (as shown in FIG. 9 below), That is, the channel region of the amorphous silicon layer 26' is formed into a structure of a-Si/p-Si/a-Si, so that the leakage current at the time of the off state can be ensured to be small.
  • the orthographic projection of polysilicon region 262 on substrate 20 is within the orthographic projection of pattern 28 of etch stop layer on substrate 20 and the area of orthographic projection of said polysilicon region on said substrate
  • the area of the orthographic projection of the pattern 28 of the etch stop layer on the substrate 20 is smaller than the area of the orthographic projection of the gate electrode 22 on the substrate 20, so that the laser beam passes only through the open region of the reticle and the channel of the pattern of the source and drain layers. In this way, the positional accuracy of the intermediate p-Si can be ensured.
  • the orthographic projection of the pattern 28 of the etch stop layer on the substrate 20 is within the orthographic projection of the gate 22 on the substrate 20 and the pattern 28 of the etch stop layer is positive on the substrate 20.
  • the projected area is smaller than the area of the orthographic projection of the gate 22 on the substrate 20, that is, the width WESL of the pattern 28 of the etch barrier layer in the direction parallel to the substrate 20 is smaller than the width WG of the gate 22 in the direction parallel to the substrate 20.
  • the laser source 200 can be kept stationary, extending the time that the laser beam 202 emitted by the laser source illuminates the amorphous silicon layer 26', that is, the laser beam 202 can continuously illuminate the amorphous silicon.
  • a portion of the predetermined area of the layer 26' is for a predetermined time to completely convert the amorphous silicon in a predetermined portion of the amorphous silicon layer into polysilicon.
  • the uniformity of the formed polysilicon can be further ensured by the continuous irradiation of such a laser light source.
  • the reticle 100 may be a reticle that is self-contained by the laser source 200, or may be a separate reticle, ie, not a reticle that is self-contained by the laser source 200.
  • step S109 the pattern 30 of the ohmic contact layer and/or the pattern of the source and drain layers on the substrate 20 are etched using the pattern 30 of the ohmic contact layer and/or the pattern 32 of the source and drain layers as a mask. And an amorphous silicon layer 26' covered by the pattern 28 of the etch barrier layer, as shown in FIG. In this step, the pattern 28 of the etch barrier layer is over the channel region of the amorphous silicon layer 26', and the a-Si/p-Si/a-Si protecting the channel region is not etched, thereby solving The problem of back channel damage.
  • the amorphous pattern of the ohmic contact layer pattern 30 and/or the source/drain layer pattern 32 and the etch stop layer pattern 28 on the substrate 20 may be etched by dry etching. Silicon layer 26'.
  • a method of manufacturing a low temperature polysilicon thin film transistor according to an embodiment of the present disclosure may include the following steps:
  • the orthographic projection of the open area of the reticle on the substrate is located within the orthographic projection of the gate on the substrate and the area of the orthographic projection of the open area of the reticle on the substrate is smaller than the gate The area of the orthographic projection on the substrate.
  • the self-aligned laser annealing is performed on the channel region by using the pattern of the source and drain layers as a occlusion layer, thereby ensuring the positional accuracy of the formed polysilicon region, and A thin film transistor having a narrow channel is formed.
  • a method of fabricating a low temperature polysilicon thin film transistor may include the following steps:
  • S1106 performing a laser annealing process on the amorphous silicon layer by using a mask plate, so that amorphous silicon in a partial region of the amorphous silicon layer is converted into polysilicon.
  • the orthographic projection of the open area of the reticle on the substrate is located within the orthographic projection of the gate on the substrate and the area of the orthographic projection of the open area of the reticle on the substrate is smaller than the gate The area of the orthographic projection on the substrate.
  • the pattern 30 of the ohmic contact layer over the amorphous silicon layer 26' can absorb the thermal energy of the laser beam 202 to form an ohmic contact layer of silicon atoms partially or completely in a crystalline state, thus The energy of the laser beam 202 will gradually decay in the pattern 30 of the ohmic contact layer and cannot be transferred to the amorphous silicon layer 26' below it.
  • the pattern 28 of the etch stop layer does not absorb the thermal energy of the laser beam 202, a portion of the underlying pattern 28 of the etch barrier layer is amorphous.
  • the silicon layer 26' will absorb the thermal energy of the laser beam 202 to form a polysilicon region.
  • the ohmic contact layer is used as the occlusion layer to achieve self-aligned laser annealing of the channel region, thereby also forming a-Si/p.
  • the channel region of the -Si/a-Si structure is not only the range of the laser irradiation is positioned by means of the reticle, but also the pattern of the ohmic contact layer is used as the occlusion layer to achieve self-aligned laser annealing of the channel region, thereby also forming a-Si/p.
  • the following steps may be performed:
  • step S109 in the previously described embodiment may also be performed as needed after step S1108. Further, step S1108 and step S109 may be simultaneously performed by a patterning process. That is, the pattern of the source and drain and the pattern of the amorphous silicon layer can be formed by the same patterning process.
  • a low temperature polysilicon thin film transistor 1200 may include: a substrate 120, a gate electrode 122 disposed on the substrate; and an active layer 126 disposed on the gate, the active layer including a channel region
  • the channel region has a polysilicon region 1262 and an amorphous silicon region 1264 located on either side of the polysilicon region.
  • An orthographic projection of the polysilicon region 1262 on the substrate is located within an orthographic projection of the gate 122 on the substrate and an area of orthographic projection of the polysilicon region on the substrate is less than the gate on the substrate The area of the orthographic projection on.
  • a channel region of a-Si/p-Si/a-Si can be easily realized when a polysilicon region is formed using a laser annealing process, and high positioning of an intermediate polysilicon region can be realized. Precision.
  • the low temperature polysilicon thin film transistor 1200 may further include an etch stop layer 128 disposed on the active layer.
  • an orthographic projection of polysilicon region 1262 on the substrate is within an orthographic projection of etch stop layer 128 on the substrate and the polysilicon region is on the substrate
  • the area of the orthographic projection on the substrate is smaller than the area of the orthographic projection of the etch stop layer on the substrate.
  • the orthographic projection of the etch stop layer 128 on the substrate is again within the orthographic projection of the gate 122 on the substrate and the area of the orthographic projection of the etch stop layer on the substrate Less than the area of the orthographic projection of the gate on the substrate.
  • the material of the etch stop layer 128 may comprise silicon oxide or silicon nitride.
  • the low temperature polysilicon thin film transistor 1200 further includes an ohmic contact layer 130 disposed over the etch stop layer 128 and the active layer 126.
  • the ohmic contact layer 130 on the etch barrier layer 128 is etched away, and the etch barrier layer 128 is etched at both ends 1281, 1282 in a direction parallel to the substrate. They are covered by the ohmic contact layer 130, respectively.
  • the material of the ohmic contact layer 130 may include N-type doped amorphous silicon or P-type doped amorphous silicon.
  • the low temperature polysilicon thin film transistor 1200 further includes a source 132 and a drain 134 disposed on the ohmic contact layer 130.
  • the pattern of the source and drain electrodes may be the same as the pattern of the ohmic contact layer 130.
  • a display substrate may be further provided, which may include the low temperature polysilicon thin film transistor described above.
  • a display device may be further provided, which may include the low temperature polysilicon thin film transistor or display substrate described above.
  • the display device may include, but is not limited to, an electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like, or any product or component having a display function.

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Abstract

提供一种低温多晶硅薄膜晶体管，包括：基板（20）、设置在基板上的栅极（22）、和设置在栅极上的有源层，有源层包括沟道区，沟道区具有多晶硅区域（262）和分别位于多晶硅区域两侧的非晶硅区域（264）。多晶硅区域在基板上的正投影位于栅极在基板上的正投影内并且多晶硅区域在基板上的正投影的面积小于栅极在基板上的正投影的面积。还提供一种低温多晶硅薄膜晶体管的制造方法、包括该低温多晶硅薄膜晶体管的显示基板以及包括这种显示基板的显示装置。

Description

低温多晶硅薄膜晶体管及其制造方法、显示基板 技术领域
本公开涉及显示技术领域，尤其涉及一种低温多晶硅薄膜晶体管及其制造方法、和包括该低温多晶硅薄膜晶体管的显示基板。
背景技术
由于相对于非晶硅(a-Si)薄膜晶体管(TFT)，多晶硅(p-Si)薄膜晶体管具有高迁移率、低功耗等优点，所以，近年来，多晶硅薄膜晶体管的应用也越来越广泛。
早期的多晶硅薄膜晶体管制造工艺的温度高达1000℃，因此基板材料的选择受到很大的限制。近年来，随着激光加工等技术的发展，多晶硅薄膜晶体管制造工艺的温度可以降至600℃以下，利用这种制造工艺所形成的多晶硅薄膜晶体管一般被称为低温多晶硅(Low Temperature Poly-silicon，简称为LTPS)薄膜晶体管。
传统的LTPS薄膜晶体管一般为顶栅型薄膜晶体管，顶栅型LTPS薄膜晶体管通常需要制备遮光层、进行源/漏极掺杂和设置轻掺杂漏极(lightly doped drain，简称Ldd)结构等工艺，工艺复杂，成本较高。
另外，在现有的底栅型LTPS薄膜晶体管中，为解决沟道漏电流过大的问题，一般需要制作a-Si/p-Si/a-Si型沟道，但是传统的制造工艺无法保证中间p-Si的位置精度，从而影响了薄膜晶体管的沟道宽度和均匀性。而且，在传统的底栅型LTPS薄膜晶体管的制造工艺中，还存在背沟道刻蚀对有源层的损伤的问题。
发明内容
为了解决上述问题的至少一个方面，本公开的实施例提出了一种改进的低 温多晶硅薄膜晶体管及其制造方法、和包括该低温多晶硅薄膜晶体管的显示基板。
根据本公开实施例的一个方面，提供一种低温多晶硅薄膜晶体管。
根据一个示例性实施例，低温多晶硅薄膜晶体管可包括：基板；设置在基板上的栅极；和设置在栅极上的有源层，该有源层包括沟道区，该沟道区具有多晶硅区域和分别位于多晶硅区域两侧的非晶硅区域。所述多晶硅区域在所述基板上的正投影位于所述栅极在所述基板上的正投影内并且所述多晶硅区域在所述基板上的正投影的面积小于所述栅极在所述基板上的正投影的面积。
根据一些实施例，所述的低温多晶硅薄膜晶体管还可包括：设置在所述有源层上的刻蚀阻挡层，并且，所述多晶硅区域在所述基板上的正投影位于所述刻蚀阻挡层在所述基板上的正投影内并且所述多晶硅区域在所述基板上的正投影的面积小于所述刻蚀阻挡层在所述基板上的正投影的面积。
根据一些实施例，所述刻蚀阻挡层在所述基板上的正投影位于所述栅极在所述基板上的正投影内并且所述刻蚀阻挡层在所述基板上的正投影的面积小于所述栅极在所述基板上的正投影的面积。
根据一些实施例，所述低温多晶硅薄膜晶体管还可包括：设置在刻蚀阻挡层和有源层上的欧姆接触层，并且，在与多晶硅区域对应的区域中，刻蚀阻挡层上的欧姆接触层被刻蚀掉，并且刻蚀阻挡层沿平行于基板的方向的两端均被欧姆接触层覆盖。
根据一些实施例，所述低温多晶硅薄膜晶体管还可包括：设置在所述欧姆接触层上的源极和漏极，源极和漏极的图案与所述欧姆接触层的图案相同。
根据本公开实施例的另一方面，还提供一种显示基板。
根据一个示例性实施例，显示基板可包括上述实施例中任一个所述的低温多晶硅薄膜晶体管。
根据本公开实施例的又一方面，还提供一种低温多晶硅薄膜晶体管的制造方法。
根据一个示例性的实施例，低温多晶硅薄膜晶体管的制造方法可包括以下步骤：提供一基板；在所述基板上形成栅极；在所述栅极上形成非晶硅层；在所述非晶硅层上形成欧姆接触层；在所述欧姆接触层上形成源漏极层；通过构图工艺形成欧姆接触层的图案和源漏极层的图案，使得在与待形成的多晶硅区域对应的区域中的欧姆接触层和源漏极层被刻蚀掉；和利用掩模版对非晶硅层执行激光退火工艺，使得非晶硅层的部分区域中的非晶硅转变为多晶硅。所述掩模版的开口区域在基板上的正投影位于所述栅极在基板上的正投影内并且所述掩模版的开口区域在基板上的正投影的面积小于所述栅极在基板上的正投影的面积。
根据一些实施例，所述制造方法还可包括以下步骤：在所述非晶硅层上形成刻蚀阻挡层；和通过构图工艺形成刻蚀阻挡层的图案。在非晶硅层上形成欧姆接触层的步骤包括：在所述刻蚀阻挡层的图案和所述非晶硅层上形成欧姆接触层，并且，形成的多晶硅区域在基板上的正投影落入所述刻蚀阻挡层的图案在基板上的正投影内并且形成的多晶硅区域在基板上的正投影的面积小于所述刻蚀阻挡层的图案在基板上的正投影的面积。
根据一些实施例，所述刻蚀阻挡层的图案在所述基板上的正投影落入所述栅极在所述基板上的正投影内并且所述刻蚀阻挡层的图案在所述基板上的正投影的面积小于所述栅极在所述基板上的正投影的面积。
根据一些实施例，通过构图工艺形成欧姆接触层和源漏极层的图案使得在与待形成的多晶硅区域对应的区域中的欧姆接触层和源漏极层被刻蚀掉的步骤包括：刻蚀在与待形成的多晶硅区域对应的区域中的欧姆接触层和源漏极层，以暴露出刻蚀阻挡层的图案的一部分，并且使得刻蚀阻挡层的图案沿平行于基板的方向的两端均被欧姆接触层覆盖。
根据一些实施例，在利用具有掩模版的激光光源对非晶硅层执行激光退火工艺使得非晶硅层的部分区域中的非晶硅转变为多晶硅的步骤之后，所述制造方法还可包括：以欧姆接触层和/或源漏极层的图案为掩模，刻蚀基板上的未被 欧姆接触层和/或源漏极层的图案和刻蚀阻挡层的图案覆盖的非晶硅层。
根据一些实施例，利用掩模版对非晶硅层执行激光退火工艺的步骤可包括：保持激光光源固定不动，延长激光光源发出的激光照射非晶硅层的时间，以使得非晶硅层的部分预定区域中的非晶硅转变为多晶硅。
根据一些实施例，通过构图工艺形成欧姆接触层的图案和源漏极层的图案的步骤可包括：通过一次构图工艺形成欧姆接触层的图案和源漏极层的图案，使得源漏极的图案与欧姆接触层的图案相同。
根据一些实施例，通过构图工艺形成欧姆接触层的图案和源漏极层的图案的步骤可包括：通过湿法刻蚀形成源漏极的图案；和通过干法刻蚀形成欧姆接触层的图案。
根据本公开的又一个方面，提供了一种低温多晶硅薄膜晶体管的制造方法。
根据一个示例性的实施例，低温多晶硅薄膜晶体管的制造方法可包括以下步骤：提供一基板；在所述基板上形成栅极；在所述栅极上形成非晶硅层；在所述非晶硅层上形成欧姆接触层；通过构图工艺形成欧姆接触层的图案，使得在与待形成的多晶硅区域对应的区域中的欧姆接触层被刻蚀掉；和利用掩模版对非晶硅层执行激光退火工艺，使得非晶硅层的部分区域中的非晶硅转变为多晶硅。所述掩模版的开口区域在基板上的正投影位于所述栅极在基板上的正投影内并且所述掩模版的开口区域在基板上的正投影的面积小于所述栅极在基板上的正投影的面积。
在一些实施例中，所述方法还可包括以下步骤：在所述非晶硅层上形成刻蚀阻挡层；和通过构图工艺形成刻蚀阻挡层的图案。在非晶硅层上形成欧姆接触层的步骤可包括：在所述刻蚀阻挡层的图案和所述非晶硅层上形成欧姆接触层，并且形成的多晶硅区域在基板上的正投影落入所述刻蚀阻挡层的图案在基板上的正投影内并且形成的多晶硅区域在基板上的正投影的面积小于所述刻蚀阻挡层的图案在基板上的正投影的面积。
在一些实施例中，所述刻蚀阻挡层的图案在所述基板上的正投影落入所述 栅极在所述基板上的正投影内并且所述刻蚀阻挡层的图案在所述基板上的正投影的面积小于所述栅极在所述基板上的正投影的面积。
在一些实施例中，通过构图工艺形成欧姆接触层的图案使得在与待形成的多晶硅区域对应的区域中的欧姆接触层被刻蚀掉的步骤可包括：刻蚀在与待形成的多晶硅区域对应的区域中的欧姆接触层，以暴露出部分刻蚀阻挡层的图案，并且使得刻蚀阻挡层的图案沿平行于基板的方向的两个侧端分别被欧姆接触层覆盖。
在一些实施例中，利用掩模版对非晶硅层执行激光退火工艺的步骤包括：保持激光光源固定不动，延长激光光源发出的激光照射非晶硅层的时间，以使得非晶硅层的部分预定区域中的非晶硅转变为多晶硅。
根据一些实施例，在利用掩膜版对非晶硅层执行激光退火工艺使得非晶硅层的部分区域中的非晶硅转变为多晶硅之后，所述制造方法还可包括：在欧姆接触层上形成源漏极层；和通过构图工艺形成源漏极层的图案，使得在与形成的多晶硅区域对应的区域中的源漏极层被刻蚀掉。
附图说明
通过下文中参照附图对本公开所作的描述，本公开的其它目的和优点将显而易见，并可帮助对本公开有全面的理解。
图1是根据本公开的一个实施例的低温多晶硅薄膜晶体管的制造方法的流程图；
图2、2A和3-9示意性地示出了根据本公开的一个实施例的低温多晶硅薄膜晶体管的制造方法的各个主要步骤；
图10是根据本公开的另一个实施例的低温多晶硅薄膜晶体管的制造方法的流程图；
图11是根据本公开的又一个实施例的低温多晶硅薄膜晶体管的制造方法的流程图；和
图12是根据本公开的一个实施例的低温多晶硅薄膜晶体管的结构示意图。
具体实施方式
下面通过实施例，并结合附图，对本公开的技术方案作进一步具体的说明。在说明书中，相同或相似的附图标号指示相同或相似的部件。下述参照附图对本公开的实施方式的说明旨在对本公开的总体发明构思进行解释，而不应当理解为对本公开的一种限制。
另外，在下面的详细描述中，为便于解释，阐述了许多具体的细节以提供对本披露实施例的全面理解。然而明显地，一个或多个实施例在没有这些具体细节的情况下也可以被实施。公知的结构和装置以图示的方式体现以简化附图。
需要说明的是，本文中所述的“在……上”、“在……上形成”和“设置在……上”可以表示一层直接形成或设置在另一层上，也可以表示一层间接形成或设置在另一层上，即两层之间还存在其它的层。
根据本公开的一个方面，提供了一种低温多晶硅薄膜晶体管的制造方法。
图1示出了根据本公开的一个实施例的低温多晶硅薄膜晶体管的制造方法的流程图。图2、2A和3-9示意性地示出了根据本公开的一个实施例的低温多晶硅薄膜晶体管的制造方法的各个主要步骤。接下来将结合图1-9对根据本公开的一个实施例的低温多晶硅薄膜晶体管的制造方法进行详细的说明。
在步骤S101中，提供一基板20，如图2所示。具体地，该基板可以是透明基板，例如玻璃基板。
在步骤S102中，在基板20上形成栅极22，如图2所示。具体地，可以先在基板20上沉积一整层栅极材料层22’，如图2A所示，然后通过构图工艺形成栅极材料层的图案，即图2中所示的栅极22。需要说明的是，本文中所称的构图工艺一般包括光刻胶涂覆、掩模、曝光、显影、刻蚀、光刻胶剥离等工艺步骤，可以根据实际工艺需求采用本领域常用的各种构图工艺来形成本公开实施例中的结构。
在步骤S103中，依次在形成有栅极22的基板20上形成栅绝缘层24和非晶硅层26’，如图3所示。具体地，可以先在形成有栅极22的基板20上沉积一整层的栅绝缘层24，然后在栅绝缘层24上沉积一整层的非晶硅层26’。在一些实施例中，在形成非晶硅层26’之后，还执行脱氢工艺，以避免在非晶硅晶化过程中发生氢爆。本领域技术人员应理解，该非晶硅层即薄膜晶体管的有源层或半导体层。
在步骤S104中，在非晶硅层26’上形成刻蚀阻挡层28’，如图4所示。具体地，通过沉积的方式在非晶硅层26’上形成刻蚀阻挡层28’。在一些实施例中，刻蚀阻挡层28’可以由氧化硅或氮化硅形成。
在步骤S105中，通过构图工艺形成刻蚀阻挡层的图案28，如图5所示。在一些实施例中，刻蚀阻挡层的图案28在基板20上的正投影落入栅极22在基板20上的正投影内，并且刻蚀阻挡层的图案28在基板20上的正投影的面积小于栅极22在基板20上的正投影的面积。在图5示出的实施例中，刻蚀阻挡层的图案28在平行于基板20的方向上的宽度WESL小于栅极22在平行于基板20的方向上的宽度WG。
在步骤S106中，在基板20上依次形成欧姆接触层30’和源漏极层32’，如图6所示。在一些实施例中，欧姆接触层30’和源漏极层32’依次通过沉积的方式形成在基板20上，以覆盖刻蚀阻挡层的图案28和非晶硅层26’。在一些实施例中，欧姆接触层30’由掺杂的非晶硅形成，例如，由N型掺杂的非晶硅或P型掺杂的非晶硅形成。源漏极层32’由金属材料形成。
在一些实施例中，在基板20上形成欧姆接触层30’的步骤可以包括：在基板20上沉积一层预先掺杂好的N型掺杂的非晶硅或P型掺杂的非晶硅。在另一些实施例中，在基板20上形成欧姆接触层30’的步骤可以包括：在基板20上沉积第二非晶硅层；和对第二非晶硅层进行掺杂。
在步骤S107中，通过构图工艺形成欧姆接触层的图案30和源漏极层的图案32，如图7所示。在一些实施例中，欧姆接触层的图案30和源漏极层的图 案32可以相同，这样，可以通过一次构图工艺形成欧姆接触层的图案30和源漏极层的图案32，从而简化制造工艺，提高加工效率。在一个示例中，考虑到欧姆接触层30’和源漏极层32’分别由非晶硅材料和金属材料形成，在通过构图工艺形成欧姆接触层的图案30和源漏极层的图案32的制造工艺中，光刻胶涂覆、掩模、曝光、显影、光刻胶剥离等工艺步骤都相同，但是，刻蚀工艺步骤可以不同。具体地，可以通过干法刻蚀工艺形成欧姆接触层的图案30，通过湿法刻蚀工艺形成源漏极层的图案32。在一些实施例中，如图7所示，通过构图工艺形成欧姆接触层的图案30和源漏极层的图案32，使得暴露出刻蚀阻挡层的图案的一部分，并且使得刻蚀阻挡层的图案28沿平行于基板的方向的两端281、282均被欧姆接触层的图案30覆盖。也就是说，源漏极层的图案32中的沟道321和欧姆接触层的图案30中的沟道301在平行于基板的方向上的宽度和均小于刻蚀阻挡层的图案28在平行于基板的方向上的宽度WESL。
在步骤S108中，利用掩模版100对非晶硅层26’执行激光退火工艺，使得非晶硅层26’的部分区域中的非晶硅转变为多晶硅。
具体地，如图8A所示，从上至下依次设置激光光源200、掩模版100和基板20，激光光源200发出的激光光束202通过掩模版100的开口区域102朝向基板20的形成有所述非晶硅层26’的一侧照射。在一个示例中，所使用的激光退火工艺可以是准分子激光退火工艺，相应地，激光光源200发出的激光光束202为准分子激光光束202。当准分子激光光束202持续照射非晶硅层26’的一部分一段时间后，可以使非晶硅层26’的被照射的部分熔融后再结晶，从而转变成多晶硅。
在一些实施例中，掩模版100的开口区域102在基板20上的正投影位于栅极22在基板20上的正投影内并且掩膜版的开口区域102在基板20上的正投影的面积小于栅极22在基板20上的正投影的面积，如图8A所示。通过这样的设置方式，使得激光光源200发出的激光仅照射在与栅极22对应的区域中，而不会影响栅极22之外的区域中的非晶硅。而且，在传统的激光退火工 艺中，由于没有设置掩模版，所以激光光束会照射在基板20的整个范围内，而栅极的段差，例如图8A所示的栅极的坡度角θ导致的段差，会导致晶化时出现不均匀，从而导致形成的薄膜晶体管的漏电流大、薄膜晶体管的性能下降。而在本公开的实施例中，通过设置掩模版，使得激光光束仅照射聚焦于栅极上方，从而避免出现传统的激光退火工艺中的段差导致的结晶化不均匀的现象。可选地，所述掩模版的开口区域102在基板上的正投影可以略大于源漏极层的图案32中的沟道321在基板上的正投影，即源漏极层的图案32中的沟道321在基板上的正投影位于所述掩模版的开口区域102在基板上的正投影内，并且源漏极层的图案32中的沟道321在基板上的正投影的面积略小于所述掩模版的开口区域102在基板上的正投影的面积。这样，射出的激光也可以被源漏极的图案限定在沟道区内，使得沟道区中位于刻蚀阻挡层下面的非晶硅被晶化，从而可以精确控制晶化区域，同时对掩模版的对位要求降低，有利于量产。
进一步地，在图8A示出的实施例中，由于源漏极层一般由金属材料形成，具有较好的导热性，所以在进行激光照射时，位于源漏极层下方的欧姆接触层的图案30以及非晶硅层26’无法吸收到准分子激光光束202的热能。也就是说，源漏极层的图案32同时也起遮挡层的作用，使得被其遮挡的非晶硅层26’的部分不会转变成多晶硅。而且，由于源漏极层一般由金属材料形成，具有较好的导热性，所以源漏极层能够确保被其遮挡的非晶硅层的部分不会转变成多晶硅。在该实施例中，不仅借助掩模版定位激光照射的范围，还以源漏极层的图案作为遮挡层对沟道区域实现自对准激光退火，从而能够保证形成的多晶硅区域的位置精度，并且形成具有窄沟道的薄膜晶体管。
参见图8A和8B，激光光源200发出激光光束202，激光光束202首先通过掩模版100，仅掩模版的开口区域102处的激光光束202能够透过掩模版100。由于掩模版100的开口区域102在基板20上的正投影位于栅极22在基板20上的正投影内并且掩膜版的开口区域102在基板20上的正投影的面积小于栅极22在基板20上的正投影的面积，所以激光光束202的照射范围在基板20 上的正投影落入栅极22在基板20上的正投影的范围内，如图8B所示。然后，仅透过源漏极层的图案32中的沟道321的激光光束202能够照射在非晶硅层26’的一部分上，从而使得非晶硅层26’的该部分转变为多晶硅，如图8A所示。也就是说，在该实施例中，源漏极层的图案32同时也起遮挡层的作用，使得被其遮挡的非晶硅层26’的部分不会转变成多晶硅。同时，由于刻蚀阻挡层的图案28不会吸收激光光束202的热能，因此，刻蚀阻挡层的图案28下方的部分非晶硅层26’将可以吸收激光光束202的热能而形成多晶硅区域。
通过这样的方式，非晶硅层26’的沟道区被形成为包括位于中间的多晶硅区域262和和分别位于多晶硅区域262两侧的非晶硅区域264(如下面的图9所示)，即，非晶硅层26’的沟道区被形成为a-Si/p-Si/a-Si的结构，从而能够保证关态时的漏电流较小。此外，在该实施例中，由于多晶硅区域262在基板20上的正投影位于刻蚀阻挡层的图案28在基板20上的正投影内并且所述多晶硅区域在所述基板上的正投影的面积小于所述刻蚀阻挡层的图案在所述基板上的正投影的面积，并且刻蚀阻挡层的图案28在基板20上的正投影又位于栅极22在基板20上的正投影内并且刻蚀阻挡层的图案28在基板20上的正投影的面积小于栅极22在基板20上的正投影的面积，因此激光光束仅透过掩模版的开口区域和源漏极层的图案的沟道，通过这样的方式可以保证中间的p-Si的位置精度。
在该实施例中，如上所述，刻蚀阻挡层的图案28在基板20上的正投影位于栅极22在基板20上的正投影内并且刻蚀阻挡层的图案28在基板20上的正投影的面积小于栅极22在基板20上的正投影的面积，即刻蚀阻挡层的图案28在平行于基板20的方向上的宽度WESL小于栅极22在平行于基板20的方向上的宽度WG，这样，a-Si/p-Si/a-Si结构中两个a-Si在平行于基板20的方向上的宽度也不会过大，从而不会过多影响薄膜晶体管开态时的电流。
在一些实施例中，可以保持激光光源200固定不动，延长激光光源发出的激光光束202照射非晶硅层26’的时间，即激光光束202可以连续照射非晶硅 层26’的部分预定区域达预定的时间，以使得非晶硅层的部分预定区域中的非晶硅完全转变为多晶硅。与传统的激光退火形成多晶硅的工艺相比，不需要移动激光光源，即不需要形成多个晶道，从而避免了多个晶道之间的多晶硅不均匀的现象。在本公开的实施例中，通过这样的激光光源固定不动的连续照射，可以进一步保证形成的多晶硅均匀性较好。
在一些实施例中，所述掩模版100可以为激光光源200自带的掩模版，或者，可以为单独的掩模版，即不是激光光源200自带的掩模版。
在步骤S109中，以欧姆接触层的图案30和/或源漏极层的图案32为掩模，刻蚀基板20上的未被欧姆接触层的图案30和/或源漏极层的图案32以及刻蚀阻挡层的图案28覆盖的非晶硅层26’，如图9所示。在该步骤中，刻蚀阻挡层的图案28覆盖在非晶硅层26’的沟道区上方，保护沟道区的a-Si/p-Si/a-Si不会被刻蚀，从而解决了背沟道损伤的问题。在一些实施例中，可以通过干法刻蚀的方式刻蚀基板20上的未被欧姆接触层的图案30和/或源漏极层的图案32以及刻蚀阻挡层的图案28覆盖的非晶硅层26’。
在上述实施例中，结合图1-9详细描述了根据本公开实施例的制造方法的各个步骤，但是，本领域技术人员应该理解，在本公开的其它实施例中，一些步骤和细节可以省略。例如，如图10所示，根据本公开实施例的低温多晶硅薄膜晶体管的制造方法可以包括以下步骤：
S1001、提供一基板；
S1002、在所述基板上形成栅极；
S1003、在所述栅极上形成非晶硅层；
S1004、在所述非晶硅层上形成欧姆接触层；
S1005、在所述欧姆接触层上形成源漏极层；
S1006、通过构图工艺形成欧姆接触层的图案和源漏极层的图案，使得在与待形成的多晶硅区域对应的区域中的欧姆接触层和源漏极层被刻蚀掉；和
S1007、利用掩模版对非晶硅层执行激光退火工艺，使得非晶硅层的部分 区域中的非晶硅转变为多晶硅，
其中，所述掩模版的开口区域在基板上的正投影位于所述栅极在基板上的正投影内并且所述掩膜版的开口区域在基板上的正投影的面积小于所述栅极在基板上的正投影的面积。
在该实施例中，不仅借助掩模版定位激光照射的范围，还以源漏极层的图案作为遮挡层对沟道区域实现自对准激光退火，从而能够保证形成的多晶硅区域的位置精度，并且形成具有窄沟道的薄膜晶体管。
在可替换的实施例中，也可以不按照上述实施例中描述的顺序执行制造方法的各个步骤。例如，如图11所示，根据可替换的实施例的低温多晶硅薄膜晶体管的制造方法可以包括以下步骤：
S1101、提供一基板；
S1102、在所述基板上形成栅极；
S1103、在所述栅极上形成非晶硅层；
S1104、在所述非晶硅层上形成欧姆接触层；
S1105、通过构图工艺形成欧姆接触层的图案，使得在与待形成的多晶硅区域对应的区域中的欧姆接触层被刻蚀掉；和
S1106、利用掩模版对非晶硅层执行激光退火工艺，使得非晶硅层的部分区域中的非晶硅转变为多晶硅，
其中，所述掩模版的开口区域在基板上的正投影位于所述栅极在基板上的正投影内并且所述掩膜版的开口区域在基板上的正投影的面积小于所述栅极在基板上的正投影的面积。
在该实施例中，返回参见图8A，位于非晶硅层26’上方的欧姆接触层的图案30可以吸收激光光束202的热能而形成部分或完全具有结晶状态的硅原子的欧姆接触层，因此，激光光束202的能量将于欧姆接触层的图案30中逐渐衰减而无法传递至其下方的非晶硅层26’中。同时，由于刻蚀阻挡层的图案28不会吸收激光光束202的热能，因此，刻蚀阻挡层的图案28下方的部分非晶 硅层26’将可以吸收激光光束202的热能而形成多晶硅区域。也就是说，在该实施例中，不仅借助掩模版定位激光照射的范围，还以欧姆接触层的图案作为遮挡层对沟道区域实现自对准激光退火，从而也形成具有a-Si/p-Si/a-Si结构的沟道区。
在该实施例中，在利用掩模版对非晶硅层执行激光退火工艺使得非晶硅层的部分区域中的非晶硅转变为多晶硅之后，可以再执行以下步骤：
S1107、在欧姆接触层上形成源漏极层；和
S1108、通过构图工艺形成源漏极层的图案，使得在与形成的多晶硅区域对应的区域中的源漏极层被刻蚀掉。
在进一步的实施例中，还可以在步骤S1108之后再根据需要执行前文所述实施例中的步骤S109。此外，也可以通过构图工艺使得步骤S1108和步骤S109同时执行。即，可以通过同一构图工艺，形成源漏极的图案和非晶硅层的图案。
根据本公开的另一个方面，还提供了一种通过上述实施例描述的制造方法制造的低温多晶硅薄膜晶体管。
参见图12，根据本公开实施例的低温多晶硅薄膜晶体管1200可以包括：基板120、设置在基板上的栅极122；和设置在栅极上的有源层126，该有源层包括沟道区，该沟道区具有多晶硅区域1262和分别位于多晶硅区域两侧的非晶硅区域1264。多晶硅区域1262在所述基板上的正投影位于所述栅极122在所述基板上的正投影内并且所述多晶硅区域在所述基板上的正投影的面积小于所述栅极在所述基板上的正投影的面积。
通过设计具有这样结构的低温多晶硅薄膜晶体管，可以在使用激光退火工艺形成多晶硅区域时，容易实现a-Si/p-Si/a-Si的沟道区，并且能够实现中间的多晶硅区域的高定位精度。
仍参见图12，低温多晶硅薄膜晶体管1200还可以包括设置在所述有源层上的刻蚀阻挡层128。如图12所示，多晶硅区域1262在所述基板上的正投影位于刻蚀阻挡层128在所述基板上的正投影内并且所述多晶硅区域在所述基板 上的正投影的面积小于所述刻蚀阻挡层在所述基板上的正投影的面积。通过设置刻蚀阻挡层来保护其下方的有源层，特别是有源层的沟道区，从而能够解决背沟道损伤的问题。
在一些实施例中，刻蚀阻挡层128在所述基板上的正投影又位于栅极122在所述基板上的正投影内并且所述刻蚀阻挡层在所述基板上的正投影的面积小于所述栅极在所述基板上的正投影的面积。
在一些实施例中，刻蚀阻挡层128的材料可以包括氧化硅或氮化硅。
在图12所示的实施例中，低温多晶硅薄膜晶体管1200还包括设置在刻蚀阻挡层128和有源层126上的欧姆接触层130。如图12所示，在与多晶硅区域1262对应的区域中，刻蚀阻挡层128上的欧姆接触层130被刻蚀掉，并且刻蚀阻挡层128沿平行于基板的方向的两端1281、1282分别被欧姆接触层130覆盖。在一些实施例中，欧姆接触层130的材料可以包括N型掺杂的非晶硅或P型掺杂的非晶硅。
在图示的实施例中，低温多晶硅薄膜晶体管1200还包括设置在欧姆接触层130上的源极132和漏极134。源极和漏极的图案可以与欧姆接触层130的图案相同。
根据本公开的又一个方面，还可以提供一种显示基板，该显示基板可以包括上文所述的低温多晶硅薄膜晶体管。
根据本公开的再一个方面，还可以提供一种显示装置，该显示装置可以包括上文所述的低温多晶硅薄膜晶体管或显示基板。该显示装置可以包括但不限于：电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
虽然本公开的一些实施例已被图示和说明，本领域普通技术人员将理解，在不背离本公开的原则和实质的情况下，可对这些实施例做出改变，本公开的范围以权利要求和它们的等同物限定。

Claims (20)

  1. 一种低温多晶硅薄膜晶体管，包括：
    基板；
    设置在基板上的栅极；和
    设置在栅极上的有源层，该有源层包括沟道区，该沟道区具有多晶硅区域和分别位于多晶硅区域两侧的非晶硅区域，
    其中，所述多晶硅区域在所述基板上的正投影位于所述栅极在所述基板上的正投影内并且所述多晶硅区域在所述基板上的正投影的面积小于所述栅极在所述基板上的正投影的面积。
  2. 根据权利要求1所述的低温多晶硅薄膜晶体管，还包括：设置在所述有源层上的刻蚀阻挡层，并且，所述多晶硅区域在所述基板上的正投影位于所述刻蚀阻挡层在所述基板上的正投影内并且所述多晶硅区域在所述基板上的正投影的面积小于所述刻蚀阻挡层在所述基板上的正投影的面积。
  3. 根据权利要求2所述的低温多晶硅薄膜晶体管，其中，所述刻蚀阻挡层在所述基板上的正投影位于所述栅极在所述基板上的正投影内并且所述刻蚀阻挡层在所述基板上的正投影的面积小于所述栅极在所述基板上的正投影的面积。
  4. 根据权利要求2或3所述的低温多晶硅薄膜晶体管，还包括：设置在刻蚀阻挡层和有源层上的欧姆接触层，
    其中，在与多晶硅区域对应的区域中，刻蚀阻挡层上的欧姆接触层被刻蚀掉，并且刻蚀阻挡层沿平行于基板的方向的两端均被欧姆接触层覆盖。
  5. 根据权利要求4所述的低温多晶硅薄膜晶体管，还包括：设置在所述欧姆接触层上的源极和漏极，
    其中，源极和漏极的图案与所述欧姆接触层的图案相同。
  6. 一种显示基板，包括上述权利要求中任一项所述的低温多晶硅薄膜晶 体管。
  7. 一种低温多晶硅薄膜晶体管的制造方法，包括以下步骤：
    提供一基板；
    在所述基板上形成栅极；
    在所述栅极上形成非晶硅层；
    在所述非晶硅层上形成欧姆接触层；
    在所述欧姆接触层上形成源漏极层；
    通过构图工艺形成欧姆接触层的图案和源漏极层的图案，使得在与待形成的多晶硅区域对应的区域中的欧姆接触层和源漏极层被刻蚀掉；和
    利用掩模版对非晶硅层执行激光退火工艺，使得非晶硅层的部分区域中的非晶硅转变为多晶硅，
    其中，所述掩模版的开口区域在基板上的正投影位于所述栅极在基板上的正投影内并且所述掩模版的开口区域在基板上的正投影的面积小于所述栅极在基板上的正投影的面积。
  8. 根据权利要求7所述的制造方法，还包括以下步骤：
    在所述非晶硅层上形成刻蚀阻挡层；和
    通过构图工艺形成刻蚀阻挡层的图案；
    其中，在非晶硅层上形成欧姆接触层的步骤包括：在所述刻蚀阻挡层的图案和所述非晶硅层上形成欧姆接触层，
    并且其中，形成的多晶硅区域在基板上的正投影落入所述刻蚀阻挡层的图案在基板上的正投影内并且形成的多晶硅区域在基板上的正投影的面积小于所述刻蚀阻挡层的图案在基板上的正投影的面积。
  9. 根据权利要求8所述的制造方法，其中，所述刻蚀阻挡层的图案在所述基板上的正投影落入所述栅极在所述基板上的正投影内并且所述刻蚀阻挡层的图案在所述基板上的正投影的面积小于所述栅极在所述基板上的正投影的面积。
  10. 根据权利要求7所述的制造方法，其中，通过构图工艺形成欧姆接触层和源漏极层的图案使得在与待形成的多晶硅区域对应的区域中的欧姆接触层和源漏极层被刻蚀掉的步骤包括：刻蚀在与待形成的多晶硅区域对应的区域中的欧姆接触层和源漏极层，以暴露出刻蚀阻挡层的图案的一部分，并且使得刻蚀阻挡层的图案沿平行于基板的方向的两端均被欧姆接触层覆盖。
  11. 根据权利要求8或9所述的制造方法，其中，在利用具有掩模版的激光光源对非晶硅层执行激光退火工艺使得非晶硅层的部分区域中的非晶硅转变为多晶硅的步骤之后，还包括：
    以欧姆接触层和/或源漏极层的图案为掩模，刻蚀基板上的未被欧姆接触层和/或源漏极层的图案和刻蚀阻挡层的图案覆盖的非晶硅层。
  12. 根据权利要求7所述的制造方法，其中，利用掩模版对非晶硅层执行激光退火工艺的步骤包括：保持激光光源固定不动，延长激光光源发出的激光照射非晶硅层的时间，以使得非晶硅层的部分预定区域中的非晶硅转变为多晶硅。
  13. 根据权利要求7所述的制造方法，其中，通过构图工艺形成欧姆接触层的图案和源漏极层的图案的步骤包括：通过一次构图工艺形成欧姆接触层的图案和源漏极层的图案，使得源漏极的图案与欧姆接触层的图案相同。
  14. 根据权利要求7所述的制造方法，其中，通过构图工艺形成欧姆接触层的图案和源漏极层的图案的步骤包括：
    通过湿法刻蚀形成源漏极的图案；和
    通过干法刻蚀形成欧姆接触层的图案。
  15. 一种低温多晶硅薄膜晶体管的制造方法，包括以下步骤：
    提供一基板；
    在所述基板上形成栅极；
    在所述栅极上形成非晶硅层；
    在所述非晶硅层上形成欧姆接触层；
    通过构图工艺形成欧姆接触层的图案，使得在与待形成的多晶硅区域对应的区域中的欧姆接触层被刻蚀掉；和
    利用掩模版对非晶硅层执行激光退火工艺，使得非晶硅层的部分区域中的非晶硅转变为多晶硅，
    其中，所述掩模版的开口区域在基板上的正投影位于所述栅极在基板上的正投影内并且所述掩模版的开口区域在基板上的正投影的面积小于所述栅极在基板上的正投影的面积。
  16. 根据权利要求15所述的制造方法，还包括以下步骤：
    在所述非晶硅层上形成刻蚀阻挡层；和
    通过构图工艺形成刻蚀阻挡层的图案；
    其中，在非晶硅层上形成欧姆接触层的步骤包括：在所述刻蚀阻挡层的图案和所述非晶硅层上形成欧姆接触层，
    并且其中，形成的多晶硅区域在基板上的正投影落入所述刻蚀阻挡层的图案在基板上的正投影内并且形成的多晶硅区域在基板上的正投影的面积小于所述刻蚀阻挡层的图案在基板上的正投影的面积。
  17. 根据权利要求16所述的制造方法，其中，所述刻蚀阻挡层的图案在所述基板上的正投影落入所述栅极在所述基板上的正投影内并且所述刻蚀阻挡层的图案在所述基板上的正投影的面积小于所述栅极在所述基板上的正投影的面积。
  18. 根据权利要求15所述的制造方法，其中，通过构图工艺形成欧姆接触层的图案使得在与待形成的多晶硅区域对应的区域中的欧姆接触层被刻蚀掉的步骤包括：刻蚀在与待形成的多晶硅区域对应的区域中的欧姆接触层，以暴露出部分刻蚀阻挡层的图案，并且使得刻蚀阻挡层的图案沿平行于基板的方向的两个侧端分别被欧姆接触层覆盖。
  19. 根据权利要求15所述的制造方法，其中，利用掩模版对非晶硅层执行激光退火工艺的步骤包括：保持激光光源固定不动，延长激光光源发出的激 光照射非晶硅层的时间，以使得非晶硅层的部分预定区域中的非晶硅转变为多晶硅。
  20. 根据权利要求15所述的制造方法，其中，在利用掩模版对非晶硅层执行激光退火工艺使得非晶硅层的部分区域中的非晶硅转变为多晶硅之后，还包括：
    在欧姆接触层上形成源漏极层；和
    通过构图工艺形成源漏极层的图案，使得在与形成的多晶硅区域对应的区域中的源漏极层被刻蚀掉。
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