WO2018188127A1 - 存储接口、时序控制方法及存储系统 - Google Patents

存储接口、时序控制方法及存储系统 Download PDF

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Publication number
WO2018188127A1
WO2018188127A1 PCT/CN2017/082353 CN2017082353W WO2018188127A1 WO 2018188127 A1 WO2018188127 A1 WO 2018188127A1 CN 2017082353 W CN2017082353 W CN 2017082353W WO 2018188127 A1 WO2018188127 A1 WO 2018188127A1
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Prior art keywords
storage device
main controller
data rate
clock signal
input
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PCT/CN2017/082353
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English (en)
French (fr)
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涂君
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华为技术有限公司
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Priority to CN201780089446.8A priority Critical patent/CN110495100B/zh
Priority to US16/605,135 priority patent/US11023176B2/en
Publication of WO2018188127A1 publication Critical patent/WO2018188127A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/08—Clock generators with changeable or programmable clock frequency
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G06F3/0611—Improving I/O performance in relation to response time
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0658—Controller construction arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled

Definitions

  • the present application relates to the field of storage technologies, and in particular, to a storage interface, a timing control method, and a storage system.
  • the Embedded Multi Media Card is an embedded memory standard specification set by the MMC Association for products such as mobile phones or tablets.
  • the maximum rate mode supported by the eMMC4.51 protocol is HS200
  • the maximum rate mode supported by the eMMC5.0 protocol is HS400.
  • the HS200 has an interface frequency of 200MHz and uses a single data rate mode with a bandwidth of 200MB/s.
  • the HS400's interface frequency is also 200MHz, with dual data rate mode and a bandwidth of 400MB/s.
  • the eMMC 5.0 protocol stipulates that the eMMC chip cannot work directly in the HS400 mode.
  • the host controller (Host) needs to negotiate with the eMMC chip in the HS200 interface mode, and then switch to the HS400 interface mode by configuring the corresponding registers of the eMMC chip. That is to say, the eMMC storage interface of the eMMC5.0 version on the main controller side needs to support the dynamic switching of the two working modes of HS200 and HS400.
  • Figure 1 shows a timing comparison of the HS200 interface and the HS400 interface.
  • the phase of the clock signal HS200_CLK outputted by the HS200 interface is different from the phase of the clock signal HS400_CLK output by the HS400 interface.
  • the clock signal HS200_CLK and the clock signal HS400_CLK respectively correspond to the intermediate position between the data signal HS200_DATA and the data signal HS400_DATA, satisfying the stability of the data sampling.
  • the clock signal (CLK) inside the main controller as a reference, HS200_CLK shifts backward by 180°, and HS400_CLK shifts backward by 90°.
  • the eMMC storage interface shown in FIG. 2 is provided. As shown in FIG. 2, the existing eMMC storage interface generates three clock signals through an internal phase lock loop (PLL): tx_clk, tx_clk_90, and tx_clk_180, and tx_clk is a main controller output for sampling data signals.
  • PLL phase lock loop
  • the clock, tx_clk_90 is the clock signal that the main controller outputs to the eMMC device when the eMMC storage interface is in the HS400 operating mode
  • the tx_clk_180 is the clock signal that the main controller outputs to the eMMC device when the eMMC storage interface is in the HS200 operating mode.
  • tx_clk_90 is shifted backward by 90° than tx_clk
  • tx_clk_180 is shifted backward by 180° than tx_clk.
  • the clock selection module CLK_MUX is used to select a clock signal output by the eMMC storage interface.
  • the clock selection module CLK_MUX selects tx_clk_180 as the clock signal output by the eMMC storage interface.
  • the clock selection module CLK_MUX selects tx_clk_90 as the clock signal output by the eMMC storage interface.
  • the existing eMMC storage interface shown in FIG. 2 can dynamically switch between the two operating modes of HS200 and HS400 by switching the output clock signal.
  • the existing eMMC storage interface shown in Figure 2 has the following disadvantages:
  • the existing eMMC storage interface has strict requirements on the delay of the data output clock path. Since the interface frequency of the HS200 and the HS400 is up to 200 MHz, the delay of the clock signal tx_clk to the input-output unit IOE1 and the delay of the clock signal tx_clk_90 (or tx_clk_180) to the input-output unit IOE2 need to be controlled to about 1 nanosecond.
  • the internal signal delay of the eMMC storage interface is formed by the cumulative delay of the segmentation delay of a large number of programmable logic units and path units, and it is desirable to perform nanosecond-level precision on such accumulated delays. Control is very difficult.
  • the integration scale of the FPGA chip will be large, that is, integrate multiple sets of circuit structures as shown in FIG. It can be understood that the distance and delay between the respective phase-locked loop PLLs inside the FPGA chip to the corresponding input and output units are different, and the distance between each clock selection module CLK_MUX inside the FPGA chip to the corresponding input and output unit is The delay is also different. In this way, it is more difficult to control the signal delays in multiple eMMC storage interfaces to the nanosecond level.
  • the wiring between the programmable logic units may be different. It is also very important to control the signal delay in the FPGA of various wiring designs to the nanosecond level. difficult.
  • the present application provides a storage interface, a timing control method, and a storage system.
  • the delay processing of the data signal outputted by the main controller to the storage device and the inversion processing of the clock signal output by the main controller to the storage device are simple. Effectively implement the storage interface in different data rate modes to meet the requirements of input data setup time and input data retention time when outputting data.
  • the present application provides a storage interface, which is connected between a main controller and a storage device, and may include: a first programmable input output unit and a second programmable input/output unit, wherein:
  • the first programmable input/output unit is configured to perform phase inversion on a clock signal output by the main controller, and output the inverted clock signal to the storage device for sampling the main controller a data signal output to the storage device;
  • the second programmable input/output unit delays the data signal output by the main controller, and outputs the delayed data signal to the storage device, and the delayed data signal is in time series
  • the clock signal outputted by the main controller is delayed by time ⁇ T, and T CLK /2- ⁇ T ⁇ T ISU and ⁇ T ⁇ T IH ;
  • T CLK represents the period of the clock signal
  • T ISU represents the minimum input setup time required by the storage device in different data rate modes
  • T IH represents the minimum input hold time required by the storage device in different data rate modes.
  • the storage device can include: a storage medium and a device controller, wherein the device controller is operative to output the write clock signal and the delayed portion according to the storage interface Describe the data signal to perform a write operation on the storage medium.
  • the storage interface is integrated on the primary controller, or the storage interface is independent of the primary controller.
  • the plurality of data rate modes corresponding to the storage device may be expressed as: a single data rate mode and a dual data rate mode.
  • the clock signal and data signal output by the memory interface satisfy: T CLK /2- ⁇ T ⁇ T ISU-SDR and ⁇ T ⁇ T IH-SDR , T CLK /2- ⁇ T ⁇ T ISU-DDR and ⁇ T ⁇ T IH-DDR , where T ISU-SDR and T ISU-DDR respectively represent the minimum input setup time required by the storage device in single data rate mode and double data rate mode, T IH- HS200 , T IH-HS400 respectively represent the minimum input hold time required by the storage device in single data rate mode, double data rate mode.
  • the storage interface can support the storage device to dynamically switch between a single data rate mode and a dual data rate mode.
  • the storage device can perform the sampling of the delayed data signal according to the phase-shifted clock signal in different data rate modes, and can meet the requirements of the shortest input setup time and the shortest input hold time. . That is, the storage interface can support the storage device to dynamically switch between multiple data rate modes.
  • the first programmable input output unit and the second programmable input output unit may be two separate programmable logic devices, or may be integrated in the same programmable In the logic device.
  • the storage interface can include a plurality of sets of the first programmable input and output units and the second programmable ones respectively corresponding to the plurality of storage devices An input output unit, wherein a storage device corresponds to a group of the first programmable input output unit and the second programmable input output unit.
  • the various storage devices support different data rate modes.
  • the storage device may be an embedded multimedia card eMCC
  • the plurality of data rate modes corresponding to the data signal include: HS200 and HS400, where: T CLK / 2- ⁇ T ⁇ T ISU-HS200 and ⁇ T ⁇ T IH-HS200 , T CLK /2- ⁇ T ⁇ T ISU- HS400 and ⁇ T ⁇ T IH- HS400 , where T ISU-HS200 and T ISU-HS400 respectively indicate eMMC at HS200
  • T IH-HS200 and T IH-HS400 respectively represent the minimum input hold time required by the eMMC in the HS200 and HS400 data rate modes.
  • the input setup time t ISU T CLK /2- ⁇ T before the rising edge of the inverted clock signal tx_clk
  • the input settling time t ISU T CLK /2- ⁇ T before the rising edge of the inverted clock signal tx_clk
  • the input hold time t IH ⁇ T after the rising edge of the inverted clock signal tx_clk .
  • the input rise time t ISU T CLK /2- ⁇ T of the rising edge of the inverted clock signal tx_clk
  • the input hold time t IH ⁇ after the rising edge of the inverted clock signal tx_clk T.
  • T CLK /2- ⁇ T ⁇ 1.4ns, ⁇ T ⁇ 0.4ns can meet the minimum input setup time and the shortest input hold time required by HS200 and HS400. That is to say, for the eMMC, the clock signal of the output of the main controller is phase-reversed through the storage interface, and the data signal output by the main controller is delayed by ⁇ T ( ⁇ T ⁇ [0.4 Ns, 1.1ns]), the storage interface can support eMMC to dynamically switch between HS200 and HS400.
  • the main controller writes data to the eMMC
  • the data signal output by the main controller is delayed by the storage interface, and the clock signal output by the main controller is inverted.
  • Can support The eMMC switches between different data rate modes. It is not necessary to separately generate two kinds of clock signals with different phases for the two data rate modes of HS200 and HS400, and it is not necessary to strictly control the delay difference between the clock signals of different phases, which is simple to implement. In addition, the difference in delay between different batches of programmable logic devices and programmable logic devices at different temperatures and voltages has little effect on the transmission timing of the memory interface.
  • the application provides a storage system, which may include: a main controller, a storage device, and a storage interface connected between the main controller and the storage device, where the storage interface includes a first Programming the input/output unit and the second programmable input/output unit, wherein: the first programmable input/output unit is configured to perform phase inversion on a clock signal output by the main controller, and output the inverted clock Signaling to the storage device, for sampling a data signal output by the main controller to the storage device;
  • the second programmable input/output unit delays the data signal output by the main controller, and outputs the delayed data signal to the storage device, and the delayed data signal is in time series
  • the clock signal outputted by the main controller is delayed by time ⁇ T, and T CLK /2- ⁇ T ⁇ T ISU and ⁇ T ⁇ T IH ;
  • T CLK represents the period of the clock signal
  • T ISU represents the minimum input setup time required by the storage device in different data rate modes
  • T IH represents the minimum input hold time required by the storage device in different data rate modes.
  • the storage interface may be the storage interface described in the first aspect and any one of the possible embodiments of the first aspect.
  • the storage interface may be the storage interface described in the first aspect and any one of the possible embodiments of the first aspect.
  • the storage interface may be the storage interface described in the first aspect and any one of the possible embodiments of the first aspect.
  • the present application provides a timing control method, which may include: a terminal inverting a clock signal output from a main controller to a storage device by a first programmable input/output unit, and passing the second programmable input and output The unit outputs the data signal to the storage device by the main controller for a delay time ⁇ T.
  • the clock signal can be used to sample the data signal; T CLK / 2 - ⁇ T ⁇ T ISU and ⁇ T ⁇ T IH ; T CLK represents the period of the clock signal, and T ISU represents a different data rate mode
  • T IH represents the minimum input hold time required by the storage device in different data rate modes.
  • the terminal may include the first programmable input output unit and the second programmable input output unit.
  • the terminal may provide a storage interface to the storage device, and the storage interface may include the first programmable input and output unit and the second programmable input and output unit.
  • the storage device may be integrated in the terminal as internal storage of the terminal.
  • the storage device may also be externally stored outside the terminal as external storage of the terminal. For a specific implementation of the storage interface, reference may be made to the first aspect, and details are not described herein.
  • the terminal when the terminal writes data to the storage device, the data signal outputted by the terminal is subjected to delay processing, and the clock signal output by the terminal is phase-shifted, thereby implementing the
  • the storage device samples the delayed data signal according to the phase-shifted clock signal in different data rate modes, and can meet the requirements of the shortest input setup time and the shortest input hold time. That is, the terminal can support the storage device to dynamically switch between multiple data rate modes.
  • the plurality of data rate modes corresponding to the storage device can be represented as: a single data rate mode and a dual data rate mode.
  • the clock signal and data signal output by the memory interface 10 satisfy: T CLK /2- ⁇ T ⁇ T ISU-SDR and ⁇ T ⁇ T IH-SDR , T CLK /2- ⁇ T ⁇ T ISU-DDR and ⁇ T ⁇ T IH-DDR , where T ISU-SDR and T ISU-DDR respectively represent the minimum input setup time required by the storage device in single data rate mode and double data rate mode, T IH - HS200 , T IH- HS400 respectively represent the minimum input hold time required by the storage device in single data rate mode, double data rate mode.
  • storage interface 10 can support dynamic switching of the storage device between a single data rate mode and a dual data rate mode.
  • the storage device can be an embedded multimedia card eMCC.
  • the eMCC can operate in single data rate mode HS200 or dual data rate mode HS400. In single data rate mode, the eMCC performs a read/write operation of the data signal only on the rising edge of the clock signal. In the dual data rate mode, the eMCC performs a write operation and a read operation on the rising and falling edges of the clock signal, respectively.
  • the inverted clock signal output to the eMMC and the delayed data signal can satisfy: T CLK /2- ⁇ T ⁇ T ISU-HS200 and ⁇ T ⁇ T IH-HS200 , T CLK /2- ⁇ T ⁇ T ISU- HS400 and ⁇ T ⁇ T IH- HS400, where T ISU-HS200 and T ISU-HS400 respectively represent the minimum input setup time required by eMMC in HS200 and HS400 data rate modes, T IH- HS200 and T IH-HS400 respectively represent the minimum input hold time required by eMMC in HS200 and HS400 data rate modes.
  • the storage interface 10 can support the eMMC to dynamically switch between the two data rate modes HS200 and HS400.
  • the application provides a terminal comprising a functional unit for performing the method described in the third aspect.
  • the application provides a terminal, including: a processor, an internal memory, where the internal memory includes: a main controller, a storage device, and is connected between the main controller and the storage device Storage interface.
  • the memory interface can include a first programmable input output unit and a second programmable input output unit.
  • the first programmable input and output unit is configured to perform phase inversion on a clock signal output by the main controller, and output the inverted clock signal to the storage device for sampling the main
  • the controller outputs a data signal to the storage device.
  • the second programmable input/output unit is configured to delay processing the data signal output by the main controller, and output the delayed data signal to the storage device, and the delayed data signal
  • the timing is delayed by a time ⁇ T from the clock signal output by the main controller, and T CLK /2 - ⁇ T ⁇ T ISU and ⁇ T ⁇ T IH .
  • T CLK represents the period of the clock signal
  • T ISU represents the minimum input setup time required by the storage device in different data rate modes
  • T IH represents the minimum input hold time required by the storage device in different data rate modes.
  • the storage interface may be the storage interface described in the first aspect and any one of the possible embodiments of the first aspect.
  • the storage interface may be the storage interface described in the first aspect and any one of the possible embodiments of the first aspect.
  • the storage interface may be the storage interface described in the first aspect and any one of the possible embodiments of the first aspect.
  • a sixth aspect a computer readable storage medium storing program code for implementing the timing control method described in any one of the third aspect and the third aspect, the program The code includes execution instructions for running the timing control method described in any one of the possible aspects of the third aspect and the third aspect.
  • FIG. 1 is a timing comparison diagram of a HS200 interface and an HS400 interface in the prior art
  • FIG. 2 is a schematic structural diagram of an eMMC storage interface in the prior art
  • FIG. 3 is a schematic structural diagram of an eMMC storage system according to the present application.
  • 4A is a timing diagram of the eMMC operating in the data rate mode HS200;
  • 4B is a timing diagram of the eMMC operating in the data rate mode HS400;
  • FIG. 5 is a schematic structural diagram of a storage interface provided by an embodiment of the present application.
  • FIG. 6 is a timing diagram of a memory interface provided by the present application for inverting a clock signal and delaying a data signal in two rate modes of HS200 and HS400;
  • FIG. 7 is a schematic structural diagram of a storage interface provided by another embodiment of the present application.
  • FIG. 8 is a schematic flowchart diagram of a timing control method according to an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of a terminal according to an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of a terminal according to another embodiment of the present application.
  • FIG. 3 illustrates an eMMC storage system to which the present application relates.
  • the eMMC storage system may include a main controller 100 and an eMMC 200, and the main controller 100 controls the eMMC 200 through the storage interface 300. among them:
  • the eMMC 200 integrates an internal controller 400 and a storage medium 500.
  • the internal controller 400 can be used for Error Checking and Correction (ECC), Bad Block Management (BBM), and Wear Leveling.
  • Storage medium 500 can be an erasable and reprogrammable storage medium such as Nand Flash.
  • the eMMC200 also implements the eMMC interface.
  • the main controller 100 only needs to issue commands to the eMMC200 through the interface bus, and does not need to configure any memory management functions, such as ECC, BMM, Wear Leveling, and the like.
  • the interface bus between the main controller 100 and the eMMC 200 may include: a clock line CLK, a command and response transmission line CMD, and a bidirectional data line Data.
  • each clock cycle on the clock line CLK can transmit a 1-bit command or response signal on the command and response transmission line CMD, or transmit 1-bit data (in single data rate mode) or 2 bits on the bidirectional data line Data.
  • Data dual data rate mode
  • the eMMC protocol supports multiple data rate modes.
  • Figures 4A and 4B show the input timing of the eMMC for the two data rate modes, HS200 and HS400, respectively.
  • FIG. 4A shows the timing of the eMMC operating under data rate mode HS200.
  • the HS200 is a single data rate mode.
  • the eMMC chip performs a read/write operation only on the rising edge of the clock signal, that is, the HS200 samples once in one clock cycle.
  • the HS200 has a bandwidth of up to 200MB/s.
  • the eMMC protocol specifies the steady-state time before and after the sampling point in HS200 mode as follows:
  • t ISU represents the input setup time and t IH represents the input hold time.
  • the input setup time is the time that the input data must remain stable before the rising edge of the clock.
  • the input hold time is the time that the input data must remain stable after the rising edge of the clock. It can be seen that the shortest input setup time in HS200 mode is 1.4ns and the shortest input hold time is 0.8ns.
  • FIG. 4B shows the timing of the eMMC operating under data rate mode HS400.
  • the HS400 is a dual data rate mode.
  • the eMMC chip performs a read operation and a write operation on the rising and falling edges of the clock signal, that is, the HS400 samples twice in one clock cycle.
  • the HS400 has a bandwidth of up to 400MB/s. In order to protect The data near the sampling point is stable.
  • the eMMC protocol specifies the steady-state time before and after the sampling point in HS400 mode as follows:
  • t ISU represents the input setup time
  • t IH represents the input hold time
  • the main controller 100 needs to negotiate with the eMMC 200 to work in the HS200 data rate mode, and then switch to the HS400 data rate mode by configuring the corresponding registers of the eMMC 200.
  • the main controller 100 can meet the shortest input setup time and the shortest input hold time in the HS200 mode in timing, the shortest input setup in the HS400 mode can also be satisfied.
  • the time and the shortest input hold time then the main controller 100 can control the eMMC chip 200 to switch between the two data rate modes HS200 and HS400.
  • the storage interface 300 may be integrated in the main controller 100, or may be independent of the main controller 100, without limitation.
  • the present application provides a storage interface, which is connected between the main controller and the storage device, and can simply and effectively realize that the data signals outputted to the storage device by the storage interface in different data rate modes satisfy the input specified by the protocol. Data setup time and input data retention time requirements.
  • the main inventive principles of the application may include:
  • the storage interface For a storage device operating in different data rate modes, the storage interface performs delay processing on the data signal output from the main controller to the storage device, and performs phase shift processing on the clock signal output from the main controller to the storage device, so that the phase shift is performed.
  • the rising/falling edge of the subsequent clock signal corresponds in time to the intermediate position of the delayed data signal, thereby satisfying the requirements of the shortest input settling time and the shortest input hold time in the different data rate modes.
  • the rising edge/falling edge of the clock signal can be used to sample the output data, and if the rising edge/falling edge of the clock signal corresponds to the middle position of the output data signal, the output data before and after the sampling time can be ensured to be stable. That is, the shortest input setup time and the shortest input hold time that meet the requirements of the storage device.
  • the intermediate position may refer to a position indicated by a rectangular shaded area in the figure, that is, a sampling moment corresponding to the data signal may fluctuate within a certain range, and the following conditions are satisfied.
  • Can: t ISU ⁇ t ISU-min , t IH ⁇ t IH-min , where t ISU-min indicates the shortest input setup time (in HS200 mode, t IH-min 0.8 ns), t IH-nim indicates the shortest input Keep time.
  • FIG. 3 only shows one storage system to which the present application is applicable. The same applies to other storage systems that need to switch between multiple data transmission rates.
  • FIG. 5 is a schematic structural diagram of a storage interface according to an embodiment of the present application.
  • the storage interface 10 is connected between the main controller and the storage device, and the storage interface 10 may be integrated in the main controller or may be independent of the main controller.
  • the storage device can operate in a variety of data rate modes.
  • the memory interface 10 can include a first programmable input output unit 103 and a second programmable input output unit 105. among them:
  • the first programmable input and output unit 103 can be configured to perform phase inversion on the clock signal (tx_clk) output by the main controller, and output the inverted clock signal to the storage device for sampling the main
  • the controller outputs a data signal to the storage device.
  • the period of the inverted clock signal can be expressed as T CLK .
  • the first programmable input/output unit 103 is connected to the clock circuit 101 in the main controller.
  • the clock circuit 101 can be used to generate a clock signal.
  • the clock circuit 101 may be a phase-locked loop PLL circuit, or may be other types of clock circuits, which are not limited herein.
  • the second programmable input and output unit 105 can be configured to perform delay processing on the data signal output by the main controller, and output the delayed data signal to the storage device.
  • the delayed data signal is delayed in timing by a time ⁇ T from the clock signal output by the main controller, and T CLK /2 - ⁇ T ⁇ T ISU and ⁇ T ⁇ T IH .
  • T CLK represents the period of the clock signal
  • T ISU represents the minimum input setup time required by the storage device in different data rate modes
  • T IH represents the minimum input hold time required by the storage device in different data rate modes.
  • the storage device may include: a storage medium and a device controller, wherein the device controller is configured to: according to the write clock signal output by the storage interface 10 and the delayed data signal, The storage medium performs a write operation.
  • the plurality of data rate modes corresponding to the storage device may be expressed as: a single data rate mode and a dual data rate mode.
  • the clock signal and data signal output by the memory interface 10 satisfy: T CLK /2- ⁇ T ⁇ T ISU-SDR and ⁇ T ⁇ T IH-SDR , T CLK /2- ⁇ T ⁇ T ISU-DDR and ⁇ T ⁇ T IH-DDR , where T ISU-SDR and T ISU-DDR respectively represent the minimum input setup time required by the storage device in single data rate mode and double data rate mode, T IH - HS200 , T IH- HS400 respectively represent the minimum input hold time required by the storage device in single data rate mode, double data rate mode.
  • the storage interface 10 can support the storage device to dynamically switch between a single data rate mode and a dual data rate mode.
  • the master controller outputs a clock period T of the data signal to the memory device.
  • Data is consistent with T CLK .
  • the clock period T Data of the main controller outputting the data signal to the storage device is T CLK 1/2.
  • the storage device can perform the sampling of the delayed data signal according to the phase-shifted clock signal in different data rate modes, and can meet the requirements of the shortest input setup time and the shortest input hold time. . That is, the storage interface 10 can support the storage device to dynamically switch between multiple data rate modes.
  • the eMCC can operate in single data rate mode HS200, or dual data rate mode HS400.
  • single data rate mode the eMCC performs a read/write operation of the data signal only on the rising edge of the clock signal.
  • dual data rate mode the eMCC performs a write operation and a read operation on the rising and falling edges of the clock signal, respectively.
  • the clock and data signals to the memory interface 10 outputs eMMC may satisfy: T CLK / 2- ⁇ T ⁇ T ISU -HS200 and ⁇ T ⁇ T IH-HS200, T CLK / 2- ⁇ T ⁇ T ISU- HS400 and ⁇ T ⁇ T IH-HS400, wherein, T ISU-HS200, T ISU -HS400 respectively represent the minimum input eMMC at HS200, HS400 both the required data rate mode setup time, T IH-HS200, T IH- The HS400 represents the minimum input hold time required by the eMMC in the HS200 and HS400 data rate modes, respectively. In this way, the storage interface 10 can support the eMMC to dynamically switch between the two data rate modes HS200 and HS400.
  • tx_clk represents a clock signal that the storage interface 10 outputs to the eMMC.
  • the period of the output interface signal HS200_DATA of the storage interface 10 in the HS200 rate mode coincides with the period of tx_clk, and the period of the output interface signal HS400_DATA of the storage interface 10 in the HS400 rate mode is 1/2 of the period of tx_clk.
  • the memory interface 10 performs phase inversion on the clock signal tx_clk, and delays the data signal by delaying ⁇ T.
  • the rising edge of the clock signal tx_clk before the phase shift processing does not correspond to the intermediate position of the data signal HS200_DATA, and does not satisfy the minimum input setup time and the shortest input hold time required by the eMMC under the HS200.
  • Data sampling cannot be performed.
  • the rising and falling edges of the clock signal tx_clk before the phase shifting process do not correspond to the intermediate position of the data signal HS400_DATA, and do not satisfy the minimum input setup time and the shortest input hold time required by the eMMC under HS400, and cannot be executed. Data sampling.
  • the rising edge of the phase-reversed tx_clk corresponds to the middle position of the data signal HS200_DATA, and satisfies the minimum input setup time and the shortest input hold time required by the eMMC under HS200, and can be used to execute data. sampling.
  • the rising and falling edges of tx_clk after phase inversion correspond to the middle position of data signal HS400_DATA, which meet the minimum input setup time and the shortest input hold time required by eMMC under HS400, and can be used to perform data sampling. .
  • the eMMC protocol defines the steady-state time before and after the sampling point in the HS200 mode as follows: t ISU ⁇ 1.4 ns, t IH ⁇ 0.8 ns, and the steady-state time of the eMMC protocol before and after the sampling point in the HS400 mode.
  • the provisions are as follows: t ISU ⁇ 0.4 ns, t IH ⁇ 0.4 ns.
  • the input rise time t ISU T CLK /2- ⁇ T of the rising edge of the inverted clock signal tx_clk
  • the input hold time t IH ⁇ after the rising edge of the inverted clock signal tx_clk T.
  • t ISU T CLK /2- ⁇ T ⁇ 0.4ns
  • t IH ⁇ T ⁇ 0.4ns.
  • T CLK /2- ⁇ T ⁇ 1.4ns, ⁇ T ⁇ 0.4ns can meet the minimum input setup time and the shortest input hold time required by HS200 and HS400. That is to say, for the eMMC, the clock signal of the output of the main controller is phase-reversed through the storage interface 10, and the data signal output by the main controller is delayed by ⁇ T ( ⁇ T ⁇ [ 0.4ns, 1.1ns]), storage interface 10 can support eMMC to dynamically switch between HS200 and HS400.
  • a programmable logic device having a delay parameter satisfying the delay requirement of ⁇ T ⁇ [0.4 ns, 1.1 ns] may be selected as the second programmable input/output unit 105.
  • processing can support eMMC to switch between different data rate modes. There is no need to separate the two data rate modes for HS200 and HS400. Two kinds of clock signals with different phases are generated, and there is no need to strictly control the delay difference between the two clock signals with different phases, which is simple to implement. In addition, the difference in delay between different batches of programmable logic devices and programmable logic devices at different temperatures and voltages has little effect on the transmission timing of the memory interface.
  • the data signal output by the storage interface 10 to the main controller can be performed. Different degrees of delay processing, therefore, the storage interface 10 provided by the present application can be applied to different storage devices.
  • the data rate modes in which the different storage devices each support dynamic switching may be different.
  • the first programmable input and output unit 103 and the second programmable input and output unit 105 may be two independent programmable logic devices, or may be integrated in the same programmable In the logic device.
  • the storage interface 10 may include a plurality of sets of the first programmable input and output units 103 corresponding to the plurality of storage devices, respectively.
  • a second programmable input and output unit 105 wherein each group corresponds to a type of storage device.
  • the various storage devices support different data rate modes.
  • the storage device 1-3 supports the same data rate mode, and the minimum input setup time and the shortest input hold time required in different rate modes are also the same.
  • the storage device 4-6 supports the same data rate mode, and the minimum input setup time and the shortest input hold time required in the different rate modes are also the same.
  • storage device 1-3 and storage device 4-6 support different data rate modes.
  • the storage device 1-3 is a storage device
  • the storage device 4-6 is another storage device, which respectively supports different data rate modes, and needs to use different data signals output by the main controller through the storage interface 10. Delay processing. It should be noted that FIG. 7 is only used to explain the embodiments of the present invention, and should not be construed as limiting.
  • a plurality of storage interfaces 10 shown in FIG. 5 may be connected to the main controller, where one storage interface 10 corresponds to one storage device.
  • the present application further provides a timing control method for a storage interface, wherein a phase inversion of a clock signal output by the main controller is performed by a programmable input/output unit, and the main control is performed.
  • the data signal output by the device is subjected to delay processing, and then the inverted clock signal and the delayed data signal are output to the storage device, which can support the storage device to dynamically switch between different data rate modes.
  • the terminal performs phase inversion by using a clock signal that the main controller outputs to the storage device through the first programmable input/output unit.
  • the terminal outputs a data signal delay time ⁇ T of the main controller to the storage device by using a second programmable input/output unit.
  • the clock signal can be used to sample the data signal; T CLK / 2 - ⁇ T ⁇ T ISU and ⁇ T ⁇ T IH ; T CLK represents the period of the clock signal, and T ISU represents a different data rate mode
  • T CLK represents the period of the clock signal
  • T ISU represents a different data rate mode
  • the minimum input setup time required by the storage device, T IH represents the minimum input hold time required by the storage device in different data rate modes.
  • the terminal may include the first programmable input output unit and the second programmable input output unit.
  • the terminal may provide a storage interface to the storage device, and the storage interface may include the first programmable input and output unit and the second programmable input and output unit.
  • the storage device may be integrated in the terminal as internal storage of the terminal.
  • the storage device may also be independent of the terminal as the terminal External storage. For specific implementations of the storage interface, reference may be made to the foregoing embodiments, and details are not described herein again.
  • the plurality of data rate modes corresponding to the storage device may be expressed as: a single data rate mode and a dual data rate mode.
  • the clock signal and data signal output by the memory interface 10 satisfy: T CLK /2- ⁇ T ⁇ T ISU-SDR and ⁇ T ⁇ T IH-SDR , T CLK /2- ⁇ T ⁇ T ISU-DDR and ⁇ T ⁇ T IH-DDR , where T ISU-SDR and T ISU-DDR respectively represent the minimum input setup time required by the storage device in single data rate mode and double data rate mode, T IH - HS200 , T IH- HS400 respectively represent the minimum input hold time required by the storage device in single data rate mode, double data rate mode.
  • the storage interface 10 can support the storage device to dynamically switch between a single data rate mode and a dual data rate mode.
  • the storage device can be an embedded multimedia card eMCC.
  • the eMCC can operate in single data rate mode HS200 or dual data rate mode HS400. In single data rate mode, the eMCC performs a read/write operation of the data signal only on the rising edge of the clock signal. In the dual data rate mode, the eMCC performs a write operation and a read operation on the rising and falling edges of the clock signal, respectively.
  • the inverted clock signal output to the eMMC and the delayed data signal can satisfy: T CLK /2- ⁇ T ⁇ T ISU-HS200 and ⁇ T ⁇ T IH-HS200 , T CLK /2- ⁇ T ⁇ T ISU- HS400 and ⁇ T ⁇ T IH- HS400, where T ISU-HS200 and T ISU-HS400 respectively represent the minimum input setup time required by eMMC in HS200 and HS400 data rate modes, T IH- HS200 and T IH-HS400 respectively represent the minimum input hold time required by eMMC in HS200 and HS400 data rate modes.
  • the storage interface 10 can support the eMMC to dynamically switch between the two data rate modes HS200 and HS400.
  • the terminal when the terminal writes data to the storage device, the data signal outputted by the terminal is subjected to delay processing, and the clock signal output by the terminal is phase-shifted, thereby implementing the
  • the storage device samples the delayed data signal according to the phase-shifted clock signal in different data rate modes, and can meet the requirements of the shortest input setup time and the shortest input hold time. That is, the terminal can support the storage device to dynamically switch between multiple data rate modes.
  • the present application also provides a terminal.
  • the terminal can be used to implement the timing control method described in the embodiment of FIG.
  • the terminal 90 may include: a first timing control unit and a second timing control unit, wherein:
  • the first timing control unit is configured to perform phase inversion by a clock signal that the main controller outputs to the storage device through the first programmable input and output unit.
  • the second timing control unit is operable to delay the data signal output time ⁇ T of the main controller to the storage device by the second programmable input/output unit.
  • the clock signal can be used to sample the data signal.
  • T CLK /2 - ⁇ T ⁇ T ISU and ⁇ T ⁇ T IH
  • T CLK represents the period of the clock signal
  • T ISU represents the minimum input setup time required by the storage device in different data rate modes
  • T IH indicates different The minimum input hold time required by the storage device in data rate mode.
  • the terminal may include the first programmable input output unit and the second programmable input output unit.
  • the terminal may provide a storage interface to the storage device, and the storage interface may include the first programmable input and output unit and the second programmable input and output unit.
  • the storage device may be integrated in the terminal as internal storage of the terminal.
  • the storage device may also be externally stored outside the terminal as external storage of the terminal. For specific implementations of the storage interface, reference may be made to the foregoing embodiments, and details are not described herein again.
  • each functional unit included in the terminal 90 can be referred to the method embodiment of FIG. 8, and details are not described herein again.
  • the present application also provides a terminal.
  • the terminal may include the storage interface 10 described in the embodiment of FIG. 5, which may be used to implement the timing control method described in the embodiment of FIG.
  • the terminal 30 can include a processor 301, a memory 302 coupled to the processor 301, a radio frequency module 303, an input and output system 304, and an eMMC 305. These components can communicate over one or more communication buses 14.
  • the radio frequency module 303 is for receiving and transmitting signals, and mainly integrates the receiver and transmitter of the terminal 30.
  • the radio frequency module 303 can include, but is not limited to, a Wi-Fi module 3031 and a telecommunications radio module 3033.
  • the Wi-Fi module 3031 can be used to access the Internet.
  • the telecom radio module 3033 may be a GSM (2G) module, a WCDMA (3G) module, or an LTE (4G) module, and may be used to establish a call connection through a telecommunication carrier network and other devices, or may be used to access the Internet through a telecommunication carrier network.
  • the radio frequency module 303 may further include a Bluetooth module or the like.
  • the radio frequency module 303 can be implemented on a separate chip.
  • the input and output system 304 is mainly used to implement the interaction function between the terminal 30 and the user/external environment, and mainly includes the input and output devices of the terminal 30.
  • the input and output system 304 can include a touch screen controller 3041, an audio controller 3045, and a sensor controller 3047. Each controller may be coupled to a corresponding peripheral device (touch screen 3051, audio circuit 3055, and motion sensor 3057.
  • the input/output system 304 may also include other I/O peripherals.
  • the eMMC 305 can be used to expand the internal storage space of the terminal 30 and store user data such as pictures, documents, and mails of the user.
  • the eMMC 305 can be implemented as an eMMC storage system as shown in FIG. 3, and can be independently configured with a main controller 306.
  • the main controller 306 can also be integrated in the processor 301.
  • the eMMC 305 can support dynamic switching between a plurality of different data rate modes. For details, refer to the content of the embodiment of FIG. 5, and details are not described herein again.
  • terminal 30 may also include other types of memory, such as SDCard, which is not limited herein.
  • the processor 301 can be integrated to include: one or more CPUs, a clock module, and a power management module.
  • the clock module is primarily used to generate a clock for data transfer and timing control for the processor 301.
  • the power management module is mainly used to provide a stable, high-accuracy voltage for the processor 301, the radio frequency module 303, and the input/output system 304 and the like.
  • the memory 302 is coupled to the processor 301 for storing various software programs and/or sets of instructions, running software, inputting and outputting data, intermediate results, and exchanging information with external memory.
  • the memory 302 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more volatile random access memories (RAM).
  • RAM volatile random access memories
  • Memory 302 can also be used to store operating systems such as ANDROID, IOS, WINDOWS, or LINUX embedded operating systems.
  • FIG. 10 is only an implementation manner of the embodiment of the present invention.
  • the terminal 30 may further include more or fewer components, which are not limited herein.
  • the present application further provides a storage system, which may include: a main controller, a storage device, and a storage interface connected between the main controller and the storage device, the storage interface including the first programmable Input and output unit and second programmable input and output unit.
  • the first programmable input/output unit is configured to perform phase inversion on a clock signal output by the main controller, and output the inverted clock signal to the storage device for sampling the main
  • the controller outputs a data signal to the storage device.
  • the second programmable input/output unit delays the data signal output by the main controller, and outputs the delayed data signal to the storage device, and the delayed data signal is in time series
  • the clock signal outputted by the main controller is delayed by time ⁇ T, and T CLK /2 - ⁇ T ⁇ T ISU and ⁇ T ⁇ T IH .
  • T CLK denotes a clock signal period
  • T ISU represents the minimum required input of the storage device different data rate mode setup time
  • T IH represents the shortest input different data rate mode of the storage device required retention time.
  • the main controller when the main controller writes data to the storage device, the data signal output by the main controller is delayed by the storage interface, and the clock signal output by the main controller is implemented.
  • Performing an inversion process can support the storage device to switch between different data rate modes. It is not necessary to separately generate clock signals for different data rate modes, and it is not necessary to strictly control the delay difference between different clock signals corresponding to different data rate modes, which is simple to implement.
  • the difference in delay between different batches of programmable logic devices and programmable logic devices at different temperatures and voltages has little effect on the transmission timing of the memory interface.
  • the program can be stored in a computer readable storage medium, when the program is executed
  • the flow of the method embodiments as described above may be included.
  • the foregoing storage medium includes various media that can store program codes, such as a ROM or a random access memory RAM, a magnetic disk, or an optical disk.

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Abstract

本申请公开了一种存储接口，所述存储接口连接在主控制器和存储设备之间，可包括：第一可编程输入输出单元，用于对主控制器输出的时钟信号进行相位反转，并输出反相后的时钟信号给存储设备；第二可编程输入输出单元，用于对主控制器输出的数据信号进行延时处理，并输出延时后的数据信号给存储设备，延时后的数据信号比主控制器输出的时钟信号延后了时间△T，且TCLK/2-△T≥TISU且△T≥TIH；其中，TCLK表示时钟信号的周期，TISU表示不同数据速率模式下存储设备要求的最短输入建立时间，TIH表示不同数据速率模式下存储设备要求的最短输入保持时间。上述方案可简单的实现存储设备在不同速率模式之间切换。

Description

存储接口、时序控制方法及存储系统 技术领域
本申请涉及存储技术领域，特别涉及存储接口、时序控制方法及存储系统。
背景技术
嵌入式多媒体卡(Embedded Multi Media Card，eMMC)为MMC协会所订立的、主要是针对手机或平板电脑等产品的内嵌式存储器标准规格。目前，eMMC4.51协议支持的最大速率模式为HS200，eMMC5.0协议支持的最大速率模式为HS400。HS200的接口频率为200MHz，采用单数据速率模式，带宽为200MB/s。HS400的接口频率也是200MHz，采用双数据速率模式，带宽为400MB/s。
eMMC5.0协议规定eMMC芯片不能直接工作在HS400模式。主控制器(Host)需要和eMMC芯片先协商工作在HS200接口模式，然后通过配置eMMC芯片的相应寄存器才能切换到HS400接口模式。也即是说，主控制器侧的eMMC5.0版本的eMMC存储接口需要支持HS200和HS400这两种工作模式的动态切换。
图1示出了HS200接口和HS400接口的时序对比图。如图1所示，HS200接口输出的时钟信号HS200_CLK的相位和HS400接口输出的时钟信号HS400_CLK的相位是不同的。时钟信号HS200_CLK和时钟信号HS400_CLK分别对应在数据信号HS200_DATA和数据信号HS400_DATA的中间位置，满足数据采样的稳定性。具体的，以主控制器内部的时钟信号(CLK)为参考，HS200_CLK向后移相180°，HS400_CLK向后移相90°。
现有技术中，为了支持HS200和HS400这两种工作模式的动态切换，提供了图2所示的eMMC存储接口。如图2所示，现有的eMMC存储接口通过内部的锁相环(Phase Lock Loop，PLL)产生3个时钟信号：tx_clk、tx_clk_90和tx_clk_180，tx_clk是主控制器输出的用于采样数据信号的时钟，tx_clk_90是eMMC存储接口处于HS400工作模式时主控制器输出给eMMC器件的时钟信号，tx_clk_180是eMMC存储接口处于HS200工作模式时主控制器输出给eMMC器件的时钟信号。其中，tx_clk_90比tx_clk向后移相90°，tx_clk_180比tx_clk向后移相180°。时钟选择模块CLK_MUX用于对eMMC存储接口输出的时钟信号进行选择。当eMMC存储接口处于HS200工作模式时，时钟选择模块CLK_MUX选择tx_clk_180作为eMMC存储接口输出的时钟信号。当eMMC存储接口处于HS400工作模式时，时钟选择模块CLK_MUX选择tx_clk_90作为eMMC存储接口输出的时钟信号。
图2所示的这种现有的eMMC存储接口通过切换输出的时钟信号，可实现在HS200和HS400这两种工作模式之间进行动态切换。但是，图2所示的这种现有的eMMC存储接口存在下述缺点：
(1)为了满足eMCC协议规定的输入数据建立时间(Input Setup Time)和输入数据保持时间(Input Hold Time)的要求，现有的eMMC存储接口对数据输出时钟路径的时延要求非常严格。由于HS200和HS400的接口频率最高可达200MHz，时钟信号tx_clk到输入输出单元IOE1的时延和时钟信号tx_clk_90(或tx_clk_180)到输入输出单元IOE2的时延之差需要控制在1纳秒左右。对于利用可编程逻辑阵列(Field Programmable GateArray，FPGA) 实现的eMMC存储接口来说，eMMC存储接口的内部信号时延是由大量的可编程逻辑单元和路径单元的分段时延累加形成的，想要对这种累加时延进行纳秒级别的精确控制是非常困难的。
(2)对于需要利用单个FPGA芯片实现多个eMMC存储接口的设计来说，FPGA芯片的集成规模会很大，即集成多组图2所示的电路结构。可以理解的，FPGA芯片内部的各个锁相环PLL到相应的输入输出单元之间的距离和时延是不同的，FPGA芯片内部的各个时钟选择模块CLK_MUX到相应的输入输出单元之间的距离和时延也是不同的。这样，要将多个eMMC存储接口内的信号时延均控制在纳秒级就更加困难。
(3)在对实现eMMC存储接口的FPGA进行设计修改时，可编程逻辑单元之间的布线可能会不同，要将各种不同布线设计的FPGA内的信号时延都控制在纳秒级也是非常困难的。
(4)同一个加载文件应用在不同批次的FPGA器件上，或者同一个FPGA器件运行在不同的温度、电压环境下，eMMC存储接口的时延参数都会有所不同，要将这些不同情况下的FPGA内的信号时延都控制在纳秒级是非常困难的。
从上可以看出，对现有技术提供的eMMC存储接口进行时延控制是十分困难的。
发明内容
本申请提供了存储接口、时序控制方法及存储系统，通过对主控制器输出给存储设备的数据信号进行延时处理，以及对主控制器输出给存储设备的时钟信号进行反相处理，可简单有效的实现不同数据速率模式下的存储接口在输出数据时满足输入数据建立时间和输入数据保持时间的要求。
第一方面，本申请提供了一种存储接口，所述存储接口连接在主控制器和存储设备之间，可包括：第一可编程输入输出单元和第二可编程输入输出单元，其中：
所述第一可编程输入输出单元用于对所述主控制器输出的时钟信号进行相位反转，并输出所述反相后的时钟信号给所述存储设备，用于采样所述主控制器输出给所述存储设备的数据信号；
所述第二可编程输入输出单元对所述主控制器输出的数据信号进行延时处理，并输出延时后的所述数据信号给所述存储设备，延时后的所述数据信号在时序上比所述主控制器输出的时钟信号延后了时间△T，且TCLK/2-△T≥TISU且△T≥TIH；
其中，TCLK表示所述时钟信号的周期，TISU表示不同数据速率模式下所述存储设备要求的最短输入建立时间，TIH表示不同数据速率模式下所述存储设备要求的最短输入保持时间。
结合第一方面，在一些实施例中，所述存储设备可包括：存储介质和设备控制器，其中，所述设备控制器可用于根据存储接口输出的所述写时钟信号和延时后的所述数据信号，对所述存储介质执行写操作。
结合第一方面，在一些实施例中，所述存储接口集成在所述主控制器上，或者，所述存储接口独立在所述主控制器外。
结合第一方面，在一些实施例中，所述存储设备对应的多种数据速率模式可以表现为：单数据速率模式和双数据速率模式。在这两种数据速率模式下，存储接口输出的时钟信号 和数据信号满足：TCLK/2-△T≥TISU-SDR且△T≥TIH-SDR，TCLK/2-△T≥TISU-DDR且△T≥TIH-DDR，其中，TISU-SDR、TISU-DDR分别表示所述存储设备在单数据速率模式、双数据速率模式下要求的最短输入建立时间，TIH-HS200、TIH-HS400分别表示所述存储设备在单数据速率模式、双数据速率模式下要求的最短输入保持时间。这样，存储接口可支持所述存储设备在单数据速率模式和双数据速率模式之间动态切换。
可以理解的，在所述主控器向所述存储设备写入数据时，通过对所述主控制器输出的数据信号进行延时处理，并且对所述主控制器输出的时钟信号进行移相处理，可实现所述存储设备在不同数据速率模式下，根据移相后的所述时钟信号对延时后的所述数据信号进行采样，都能满足最短输入建立时间和最短输入保持时间的要求。也即是说，存储接口可支持所述存储设备在多种数据速率模式之间动态切换。
结合第一方面，在一些实施例中，所述第一可编程输入输出单元和所述第二可编程输入输出单元可以是两个分别独立的可编程逻辑器件，也可以集成在同一个可编程逻辑器件中。
结合第一方面，在一些实施例中，为了同时支持多种存储设备，所述存储接口可包括分别对应多种存储设备的多组所述第一可编程输入输出单元和所述第二可编程输入输出单元，其中，一种存储设备对应一组所述第一可编程输入输出单元和所述第二可编程输入输出单元。所述多种存储设备支持的数据速率模式不同。
结合第一方面，在一些实施例中，所述存储设备可以是嵌入式多媒体卡eMCC，所述数据信号对应的多种数据速率模式包括：HS200和HS400，其中：TCLK/2-△T≥TISU-HS200且△T≥TIH-HS200，TCLK/2-△T≥TISU-HS400且△T≥TIH-HS400，其中，TISU-HS200、TISU-HS400分别表示eMMC在HS200、HS400这两种数据速率模式下要求的最短输入建立时间，TIH-HS200、TIH-HS400分别表示eMMC在HS200、HS400这两种数据速率模式下要求的最短输入保持时间。
HS200模式下，反相后的时钟信号tx_clk的上升沿之前的输入建立时间tISU＝TCLK/2-△T，反相后的时钟信号tx_clk的上升沿之后的输入保持时间tIH＝TCLK/2+△T。这里，eMMC的存储接口的频率为200MHz，TCLK＝5ns。因此，HS200模式下eMMC要求的最短输入保持时间一定可以满足，只需要满足tISU＝TCLK/2-△T≥1.4ns即可。
HS400模式下，反相后的时钟信号tx_clk的上升沿之前的输入建立时间tISU＝TCLK/2-△T，反相后的时钟信号tx_clk的上升沿之后的输入保持时间tIH＝△T。同样的，反相后的时钟信号tx_clk的下升沿之前的输入建立时间tISU＝TCLK/2-△T，反相后的时钟信号tx_clk的下升沿之后的输入保持时间tIH＝△T。HS400模式下，需要满足tISU＝TCLK/2-△T≥0.4ns，tIH＝△T≥0.4ns。
可以计算的，TCLK/2-△T≥1.4ns，△T≥0.4ns，即可满足HS200和HS400这两种速率模式各自要求的最短输入建立时间和最短输入保持时间。也即是说，对于eMMC来说，通过存储接口将所述主控制器的输出的时钟信号进行相位反转，并将所述主控制器输出的数据信号延时△T(△T∈[0.4ns,1.1ns])，存储接口可支持eMMC在HS200和HS400这两种速率模式之间动态切换。
可以理解的，在所述主控器向eMMC写入数据时，通过存储接口对所述主控制器输出的数据信号进行延时处理，并且对所述主控制器输出的时钟信号进行反相处理，可支持 eMMC在不同数据速率模式之间切换。不需要为HS200和HS400这两种数据速率模式分别产生两种相位不同的时钟信号，也不需要对这两种相位不同的时钟信号之间的时延差进行严格的控制，实现起来很简单。另外，不同批次的可编程逻辑器件和可编程逻辑器件在不同温度、电压下的时延差异对存储接口的发送时序影响很小。
第二方面，本申请提供了一种存储系统，可包括：主控制器、存储设备，以及连接在所述主控制器和所述存储设备之间的存储接口，所述存储接口包括第一可编程输入输出单元和第二可编程输入输出单元，其中：所述第一可编程输入输出单元用于对所述主控制器输出的时钟信号进行相位反转，并输出所述反相后的时钟信号给所述存储设备，用于采样所述主控制器输出给所述存储设备的数据信号；
所述第二可编程输入输出单元对所述主控制器输出的数据信号进行延时处理，并输出延时后的所述数据信号给所述存储设备，延时后的所述数据信号在时序上比所述主控制器输出的时钟信号延后了时间△T，且TCLK/2-△T≥TISU且△T≥TIH；
其中，TCLK表示所述时钟信号的周期，TISU表示不同数据速率模式下所述存储设备要求的最短输入建立时间，TIH表示不同数据速率模式下所述存储设备要求的最短输入保持时间。
具体的，所述存储接口可以是第一方面及第一方面的任意一种可能的实施例所描述的存储接口，具体可参考第一方面，这里不赘述。
第三方面，本申请提供了一种时序控制方法，可包括：终端通过第一可编程输入输出单元将主控制器输出给存储设备的时钟信号进行相位反转，并通过第二可编程输入输出单元将所述主控制器输出给所述存储设备的数据信号延迟时间△T。这里，所述时钟信号可用于采样所述数据信号；TCLK/2-△T≥TISU且△T≥TIH；TCLK表示所述时钟信号的周期，TISU表示不同数据速率模式下所述存储设备要求的最短输入建立时间，TIH表示不同数据速率模式下所述存储设备要求的最短输入保持时间。
本申请中，所述终端可包括所述第一可编程输入输出单元和所述第二可编程输入输出单元。具体的，所述终端可以向所述存储设备提供存储接口，所述存储接口可包括所述第一可编程输入输出单元和所述第二可编程输入输出单元。所述存储设备可以集成在所述终端中，作为所述终端的内部存储。所述存储设备也可以独立在所述终端外，作为所述终端的外部存储。关于所述存储接口的具体实现可参考第一方面，这里不赘述。
可以理解的，在所述终端向所述存储设备写入数据时，通过对所述终端输出的数据信号进行延时处理，并且对所述终端输出的时钟信号进行移相处理，可实现所述存储设备在不同数据速率模式下，根据移相后的所述时钟信号对延时后的所述数据信号进行采样，都能满足最短输入建立时间和最短输入保持时间的要求。也即是说，所述终端可支持所述存储设备在多种数据速率模式之间动态切换。
结合第三方面，在一些实施例中，所述存储设备对应的多种数据速率模式可以表现为：单数据速率模式和双数据速率模式。在这两种数据速率模式下，存储接口10输出的时钟信号和数据信号满足：TCLK/2-△T≥TISU-SDR且△T≥TIH-SDR，TCLK/2-△T≥TISU-DDR且△T≥TIH-DDR，其中，TISU-SDR、TISU-DDR分别表示所述存储设备在单数据速率模式、双数据速率模式下要求的最短输入建立时间，TIH-HS200、TIH-HS400分别表示所述存储设备在单数据速率模式、双数据速率模式下要求的最短输入保持时间。这样，存储接口10可支持所述存储设 备在单数据速率模式和双数据速率模式之间动态切换。
结合第三方面，在一些实施例中，所述存储设备可以是嵌入式多媒体卡eMCC。eMCC可以工作在单数据速率模式HS200，或者双数据速率模式HS400下。在单数据速率模式下，eMCC仅在时钟信号的上升沿执行数据信号的读/写操作。在双数据速率模式下，eMCC分别在时钟信号的上升沿、下降沿各执行一次写操作、读操作。
具体的，输出给eMMC的反相后的时钟信号和延时后的数据信号可满足：TCLK/2-△T≥TISU-HS200且△T≥TIH-HS200，TCLK/2-△T≥TISU-HS400且△T≥TIH-HS400，其中，TISU-HS200、TISU-HS400分别表示eMMC在HS200、HS400这两种数据速率模式下要求的最短输入建立时间，TIH-HS200、TIH-HS400分别表示eMMC在HS200、HS400这两种数据速率模式下要求的最短输入保持时间。这样，存储接口10可支持eMMC在HS200、HS400这两种数据速率模式之间动态切换。
可以计算的，对于eMMC来说，通过将所述主控制器的输出的时钟信号进行相位反转，并将所述主控制器输出的数据信号延时△T(△T∈[0.4ns,1.1ns])，即可支持eMMC在HS200和HS400这两种速率模式之间动态切换。关于具体计算过程，可参考图5实施例的内容，这里不再赘述。
第四方面，本申请提供了一种终端，包括用于执行第三方面描述的方法的功能单元。
第五方面，本申请提供了一种终端，包括：处理器、内部存储器，其中，所述内部存储器包括：主控制器、存储设备，以及连接在所述主控制器和所述存储设备之间的存储接口。所述存储接口可包括第一可编程输入输出单元和第二可编程输入输出单元。其中：所述第一可编程输入输出单元可用于对所述主控制器输出的时钟信号进行相位反转，并输出所述反相后的时钟信号给所述存储设备，用于采样所述主控制器输出给所述存储设备的数据信号。所述第二可编程输入输出单元可用于对所述主控制器输出的数据信号进行延时处理，并输出延时后的所述数据信号给所述存储设备，延时后的所述数据信号在时序上比所述主控制器输出的时钟信号延后了时间△T，且TCLK/2-△T≥TISU且△T≥TIH。这里，TCLK表示所述时钟信号的周期，TISU表示不同数据速率模式下所述存储设备要求的最短输入建立时间，TIH表示不同数据速率模式下所述存储设备要求的最短输入保持时间。
具体的，所述存储接口可以是第一方面及第一方面的任意一种可能的实施例所描述的存储接口，具体可参考第一方面，这里不赘述。
第六方面，提供了一种计算机可读存储介质，所述可读存储介质上存储有实现第三方面及第三方面的任意一种可能的实施例描述的时序控制方法的程序代码，该程序代码包含运行第三方面及第三方面的任意一种可能的实施例描述的时序控制方法的执行指令。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍。
图1是现有技术中的HS200接口和HS400接口的时序对比图；
图2是现有技术中的eMMC存储接口的结构示意图；
图3是本申请涉及的eMMC存储系统的结构示意图；
图4A是eMMC工作在数据速率模式HS200下的时序示意图；
图4B是eMMC工作在数据速率模式HS400下的时序示意图；
图5是本申请的一个实施例提供的存储接口的结构示意图；
图6是本申请提供的存储接口在HS200和HS400两种速率模式下对时钟信号进行反相处理和对数据信号进行延迟处理的时序示意图；
图7是本申请的另一个实施例提供的存储接口的结构示意图；
图8是本申请的一个实施例提供的时序控制方法的流程示意图；
图9是本申请的一个实施例提供的终端的结构示意图；
图10是本申请的另一个实施例提供的终端的结构示意图。
具体实施方式
本申请的实施方式部分使用的术语仅用于对本申请的具体实施例进行解释，而非旨在限定本申请。
图3示出了本申请涉及的一种eMMC存储系统。如图3所示，eMMC存储系统可包括：主控制器100和eMMC 200，主控制器100通过存储接口300控制eMMC 200。其中：
eMMC 200集成了内部控制器400和存储介质500。内部控制器400可用于纠错和校验(Error Checking and Correction，ECC)、坏块管理(Bad Block Management，BBM)和损耗均衡(Wear Leveling)等。存储介质500可以是一种可擦除和再编程的存储介质，例如Nand Flash。eMMC200还实现了eMMC接口。主控制器100只需通过接口总线向eMMC200下发命令即可，不需要配置任何内存管理方面的功能，例如ECC、BMM、Wear Leveling等。
具体的，主控制器100和eMMC200之间的接口总线可包括：时钟线CLK、命令和响应传输线CMD、双向数据线Data。其中，时钟线CLK上的每个时钟周期可在命令和响应传输线CMD上传输1比特的命令或响应信号，或者在双向数据线Data上传输1比特的数据(单数据速率模式下)或2比特的数据(双数据速率模式下)。
eMMC协议支持多种数据速率模式，图4A和图4B分别示出了HS200和HS400这两种数据速率模式的eMMC的输入时序。
图4A示出了eMMC工作在数据速率模式HS200下的时序。如图4A所示，HS200是一种单数据速率模式，eMMC芯片仅在时钟信号的上升沿进行一次读/写操作，即HS200在一个时钟周期内采样一次。HS200的带宽最高可达200MB/s。为了保证采样点附近的数据是稳定的，eMMC协议对HS200模式下的采样点前后的稳态时间规定如下：
tISU≥1.4ns,tIH≥0.8ns
其中，tISU表示输入建立时间，tIH表示输入保持时间。输入建立时间是指在时钟上升沿到来之前输入数据必须保持稳定的时间。输入保持时间是指在时钟上升沿到来以后输入数据必须保持稳定的时间。由此可以看出，HS200模式下的最短输入建立时间为1.4ns，最短输入保持时间为0.8ns。
图4B示出了eMMC工作在数据速率模式HS400下的时序。如图4B所示，HS400是一种双数据速率模式，eMMC芯片在时钟信号的上升沿、下降沿分别进行一次读操作和一次写操作，即HS400在一个时钟周期内采样两次。HS400的带宽最高可达400MB/s。为了保 证采样点附近的数据是稳定的，eMMC协议对HS400模式下的采样点前后的稳态时间规定如下：
tISU≥0.4ns,tIH≥0.4ns
其中，tISU表示输入建立时间，tIH表示输入保持时间。由此可以看出，HS400模式下的最短输入建立时间和最短输入保持时间均为0.4ns。
由于eMMC协议规定eMMC不能直接工作在HS400模式。因此，主控制器100需要和eMMC200先协商工作在HS200数据速率模式，然后通过配置eMMC200的相应寄存器才能切换到HS400数据速率模式。
可以理解的，如果主控制器100通过存储接口300输出的时钟信号和数据信号在时序上既能满足HS200模式下的最短输入建立时间和最短输入保持时间，也能满足HS400模式下的最短输入建立时间和最短输入保持时间，那么主控制器100可以控制eMMC芯片200在HS200和HS400这两种数据速率模式之间切换。
本申请中，存储接口300可以集成在主控制器100中，也可以独立在主控制器100外，不作限制。
本申请提供了一种存储接口，所述存储接口连接在主控制器和存储设备之间，可简单有效的实现存储接口在不同数据速率模式下输出给存储设备的数据信号均满足协议规定的输入数据建立时间和输入数据保持时间的要求。
本申请的主要发明原理可包括：
对于工作在不同数据速率模式下的存储设备，存储接口对主控制器输出给存储设备的数据信号进行延时处理，以及对主控制器输出给存储设备的时钟信号进行移相处理，使得移相后的时钟信号的上升沿/下降沿在时序上对应延时后的所述数据信号的中间位置，从而满足所述不同数据速率模式下的最短输入建立时间和最短输入保持时间的要求。
可以理解的，所述时钟信号的上升沿/下降沿可用于采样输出数据，如果所述时钟信号的上升沿/下降沿对应输出的数据信号的中间位置，则可以确保采样时刻前后的输出数据稳定，即满足所述存储设备要求的最短输入建立时间和最短输入保持时间。
例如，在eMMC的HS200数据速率模式下，参考图4A，所述中间位置可以是指图中矩形阴影区指示的位置，即数据信号对应的采样时刻可以在一定范围内波动，满足下述条件即可：tISU≥tISU-min，tIH≥tIH-min，其中，tISU-min表示最短输入建立时间(HS200模式下，tIH-min＝0.8ns)，tIH-nim表示最短输入保持时间。具体的，协议规定在(HS200模式下，tISU-min＝1.4ns)。
需要说明的，图3所示的eMMC存储系统仅仅示出了本申请适用的一种存储系统，对于其他需要在多种数据传输速率之间进行切换的存储系统，本申请同样适用。
参考图5，图5是本申请的一个实施例提供的存储接口的结构示意图。存储接口10连接在主控制器和存储设备之间，存储接口10可集成在所述主控制器中，也可以独立在所述主控制器外。本申请中，所述存储设备可以工作在多种数据速率模式下。如图5所示，存储接口10可包括：第一可编程输入输出单元103和第二可编程输入输出单元105。其中：
第一可编程输入输出单元103可用于对所述主控制器输出的时钟信号(tx_clk)进行相 位反转，并输出所述反相后的时钟信号给所述存储设备，用于采样所述主控制器输出给所述存储设备的数据信号。所述反相后的时钟信号的周期可表示成TCLK。
具体的，第一可编程输入输出单元103与所述主控制器中的时钟电路101相连。时钟电路101可用于产生时钟信号。具体实现中，时钟电路101可以是锁相环PLL电路，也可以是其他类型的时钟电路，这里不作限制。
第二可编程输入输出单元105可用于对所述主控制器输出的数据信号进行延时处理，并输出延时后的所述数据信号给所述存储设备。延时后的所述数据信号在时序上比所述主控制器输出的时钟信号延后了时间△T，且TCLK/2-△T≥TISU且△T≥TIH。其中，TCLK表示所述时钟信号的周期，TISU表示不同数据速率模式下所述存储设备要求的最短输入建立时间，TIH表示不同数据速率模式下所述存储设备要求的最短输入保持时间。
本申请中，所述存储设备可包括：存储介质和设备控制器，其中，所述设备控制器可用于根据存储接口10输出的所述写时钟信号和延时后的所述数据信号，对所述存储介质执行写操作。
在一些实施例中，所述存储设备对应的多种数据速率模式可以表现为：单数据速率模式和双数据速率模式。在这两种数据速率模式下，存储接口10输出的时钟信号和数据信号满足：TCLK/2-△T≥TISU-SDR且△T≥TIH-SDR，TCLK/2-△T≥TISU-DDR且△T≥TIH-DDR，其中，TISU-SDR、TISU-DDR分别表示所述存储设备在单数据速率模式、双数据速率模式下要求的最短输入建立时间，TIH-HS200、TIH-HS400分别表示所述存储设备在单数据速率模式、双数据速率模式下要求的最短输入保持时间。这样，存储接口10可支持所述存储设备在单数据速率模式和双数据速率模式之间动态切换。
应理解的，如果所述存储设备工作在单数据速率模式下，即仅在时钟信号的上升沿/下降沿采样数据信号，则所述主控制器向所述存储设备输出数据信号的时钟周期TData与TCLK一致。如果所述存储设备工作在双数据速率模式下，即在时钟信号的上升沿和下降沿均采样数据信号，则所述主控制器向所述存储设备输出数据信号的时钟周期TData是TCLK的1/2。
可以理解的，在所述主控器向所述存储设备写入数据时，通过对所述主控制器输出的数据信号进行延时处理，并且对所述主控制器输出的时钟信号进行移相处理，可实现所述存储设备在不同数据速率模式下，根据移相后的所述时钟信号对延时后的所述数据信号进行采样，都能满足最短输入建立时间和最短输入保持时间的要求。也即是说，存储接口10可支持所述存储设备在多种数据速率模式之间动态切换。
下面以所述存储设备是嵌入式多媒体卡eMCC为例，详细说明本申请提供的技术方案。
应理解的，eMCC可以工作在单数据速率模式HS200，或者双数据速率模式HS400下。在单数据速率模式下，eMCC仅在时钟信号的上升沿执行数据信号的读/写操作。在双数据速率模式下，eMCC分别在时钟信号的上升沿、下降沿各执行一次写操作、读操作。
具体的，存储接口10输出给eMMC的时钟信号和数据信号可满足：TCLK/2-△T≥TISU-HS200且△T≥TIH-HS200，TCLK/2-△T≥TISU-HS400且△T≥TIH-HS400，其中，TISU-HS200、TISU-HS400分别表示eMMC在HS200、HS400这两种数据速率模式下要求的最短输入建立时间，TIH-HS200、TIH-HS400分别表示eMMC在HS200、HS400这两种数据速率模式下要求的最短输入 保持时间。这样，存储接口10可支持eMMC在HS200、HS400这两种数据速率模式之间动态切换。
如图6所示，tx_clk表示存储接口10输出给eMMC的时钟信号。HS200速率模式下存储接口10输出数据信号HS200_DATA的周期与tx_clk的周期一致，HS400速率模式下存储接口10输出数据信号HS400_DATA的周期是tx_clk的周期的1/2。存储接口10对时钟信号tx_clk进行了相位反转，对数据信号进行了延时处理，延迟了△T。
从图6可以看出，在HS200速率模式下，移相处理前的时钟信号tx_clk的上升沿未对应数据信号HS200_DATA的中间位置，不满足HS200下eMMC要求的最短输入建立时间和最短输入保持时间，不能执行数据采样。在HS400速率模式下，移相处理前的时钟信号tx_clk的上升沿和下降沿都未对应数据信号HS400_DATA的中间位置，均不满足HS400下eMMC要求的最短输入建立时间和最短输入保持时间，不能执行数据采样。
从图6可以看出，在HS200速率模式下，相位反转后的tx_clk的上升沿对应数据信号HS200_DATA的中间位置，满足HS200下eMMC要求的最短输入建立时间和最短输入保持时间，可用于执行数据采样。在HS400速率模式下，相位反转后的tx_clk的上升沿、下降沿均对应数据信号HS400_DATA的中间位置，均满足HS400下eMMC要求的最短输入建立时间和最短输入保持时间，均可用于执行数据采样。
可以理解的，由于eMMC协议对HS200模式下的采样点前后的稳态时间规定如下：tISU≥1.4ns,tIH≥0.8ns，并且，eMMC协议对HS400模式下的采样点前后的稳态时间规定如下：tISU≥0.4ns,tIH≥0.4ns。
从图6可以看出，HS200模式下，反相后的时钟信号tx_clk的上升沿之前的输入建立时间tISU＝TCLK/2-△T，反相后的时钟信号tx_clk的上升沿之后的输入保持时间tIH＝TCLK/2+△T。这里，eMMC的存储接口10的频率为200MHz，TCLK＝5ns。因此，HS200模式下eMMC要求的最短输入保持时间一定可以满足，只需要满足tISU＝TCLK/2-△T≥1.4ns即可。
从图6可以看出，HS400模式下，反相后的时钟信号tx_clk的上升沿之前的输入建立时间tISU＝TCLK/2-△T，反相后的时钟信号tx_clk的上升沿之后的输入保持时间tIH＝△T。同样的，反相后的时钟信号tx_clk的下升沿之前的输入建立时间tISU＝TCLK/2-△T，反相后的时钟信号tx_clk的下升沿之后的输入保持时间tIH＝△T。HS400模式下，需要满足tISU＝TCLK/2-△T≥0.4ns，tIH＝△T≥0.4ns。
可以计算的，TCLK/2-△T≥1.4ns，△T≥0.4ns，即可满足HS200和HS400这两种速率模式各自要求的最短输入建立时间和最短输入保持时间。也即是说，对于eMMC来说，通过存储接口10将所述主控制器的输出的时钟信号进行相位反转，并将所述主控制器输出的数据信号延时△T(△T∈[0.4ns,1.1ns])，存储接口10可支持eMMC在HS200和HS400这两种速率模式之间动态切换。
实际应用中，可以选择时延参数满足△T∈[0.4ns,1.1ns]这一时延要求的可编程逻辑器件作为所述第二可编程输入输出单元105。
可以理解的，在所述主控器向eMMC写入数据时，通过存储接口10对所述主控制器输出的数据信号进行延时处理，并且对所述主控制器输出的时钟信号进行反相处理，可支持eMMC在不同数据速率模式之间切换。不需要为HS200和HS400这两种数据速率模式分别 产生两种相位不同的时钟信号，也不需要对这两种相位不同的时钟信号之间的时延差进行严格的控制，实现起来很简单。另外，不同批次的可编程逻辑器件和可编程逻辑器件在不同温度、电压下的时延差异对存储接口的发送时序影响很小。
可以理解的，由于所述第一可编程输入输出单元103和所述第二可编程输入输出单元105均是逻辑可编程器件实现的，存储接口10对所述主控制器输出的数据信号可以进行不同程度的延时处理，因此，本申请提供的存储接口10可适用不同的存储设备。所述不同的存储设备各自支持动态切换的数据速率模式可以不同。
在一些可选的实施例中，所述第一可编程输入输出单元103和所述第二可编程输入输出单元105可以是两个分别独立的可编程逻辑器件，也可以集成在同一个可编程逻辑器件中。
在一些可选的实施例中，如图7所示，为了同时支持多种存储设备，存储接口10可包括分别对应多种存储设备的多组所述第一可编程输入输出单元103和所述第二可编程输入输出单元105，其中，每一组对应一种存储设备。所述多种存储设备支持的数据速率模式不同。例如，存储设备1-3支持的数据速率模式相同，在不同速率模式下要求的最短输入建立时间和最短输入保持时间也相同。存储设备4-6支持的数据速率模式相同，在不同速率模式下要求的最短输入建立时间和最短输入保持时间也相同。但是，存储设备1-3和存储设备4-6支持的数据速率模式不同。即，存储设备1-3是一种存储设备，存储设备4-6是另一种存储设备，分别支持的数据速率模式不同，需要通过存储接口10对所述主控制器输出的数据信号进行不同的延时处理。需要说明的，图7仅仅用于解释本发明实施例，不应构成限定。
可选的，为了同时支持多种存储设备，也可以采用多个图5所示的存储接口10和所述主控制器相连，其中，一个存储接口10对应一种存储设备。
基于图5实施例描述的存储接口10，本申请还提供了一种存储接口的时序控制方法，通过可编程输入输出单元对主控制器输出的时钟信号进行相位反转，以及对所述主控制器输出的数据信号进行延时处理，然后将反相后的时钟信号和延时后的数据信号输出给存储设备，可支持所述存储设备在不同数据速率模式之间动态切换。下面展开描述：
S101，终端通过第一可编程输入输出单元将主控制器输出给存储设备的时钟信号进行相位反转。
S103，所述终端通过第二可编程输入输出单元将所述主控制器输出给所述存储设备的数据信号延迟时间△T。
这里，所述时钟信号可用于采样所述数据信号；TCLK/2-△T≥TISU且△T≥TIH；TCLK表示所述时钟信号的周期，TISU表示不同数据速率模式下所述存储设备要求的最短输入建立时间，TIH表示不同数据速率模式下所述存储设备要求的最短输入保持时间。
本申请中，所述终端可包括所述第一可编程输入输出单元和所述第二可编程输入输出单元。具体的，所述终端可以向所述存储设备提供存储接口，所述存储接口可包括所述第一可编程输入输出单元和所述第二可编程输入输出单元。所述存储设备可以集成在所述终端中，作为所述终端的内部存储。所述存储设备也可以独立在所述终端外，作为所述终端 的外部存储。关于所述存储接口的具体实现可参考前述实施例，这里不再赘述。
在一些实施例中，所述存储设备对应的多种数据速率模式可以表现为：单数据速率模式和双数据速率模式。在这两种数据速率模式下，存储接口10输出的时钟信号和数据信号满足：TCLK/2-△T≥TISU-SDR且△T≥TIH-SDR，TCLK/2-△T≥TISU-DDR且△T≥TIH-DDR，其中，TISU-SDR、TISU-DDR分别表示所述存储设备在单数据速率模式、双数据速率模式下要求的最短输入建立时间，TIH-HS200、TIH-HS400分别表示所述存储设备在单数据速率模式、双数据速率模式下要求的最短输入保持时间。这样，存储接口10可支持所述存储设备在单数据速率模式和双数据速率模式之间动态切换。
在一些实施例中，所述存储设备可以是嵌入式多媒体卡eMCC。eMCC可以工作在单数据速率模式HS200，或者双数据速率模式HS400下。在单数据速率模式下，eMCC仅在时钟信号的上升沿执行数据信号的读/写操作。在双数据速率模式下，eMCC分别在时钟信号的上升沿、下降沿各执行一次写操作、读操作。
具体的，输出给eMMC的反相后的时钟信号和延时后的数据信号可满足：TCLK/2-△T≥TISU-HS200且△T≥TIH-HS200，TCLK/2-△T≥TISU-HS400且△T≥TIH-HS400，其中，TISU-HS200、TISU-HS400分别表示eMMC在HS200、HS400这两种数据速率模式下要求的最短输入建立时间，TIH-HS200、TIH-HS400分别表示eMMC在HS200、HS400这两种数据速率模式下要求的最短输入保持时间。这样，存储接口10可支持eMMC在HS200、HS400这两种数据速率模式之间动态切换。
可以计算的，对于eMMC来说，通过将所述主控制器的输出的时钟信号进行相位反转，并将所述主控制器输出的数据信号延时△T(△T∈[0.4ns,1.1ns])，即可支持eMMC在HS200和HS400这两种速率模式之间动态切换。关于具体计算过程，可参考图5实施例的内容，这里不再赘述。
可以理解的，在所述终端向所述存储设备写入数据时，通过对所述终端输出的数据信号进行延时处理，并且对所述终端输出的时钟信号进行移相处理，可实现所述存储设备在不同数据速率模式下，根据移相后的所述时钟信号对延时后的所述数据信号进行采样，都能满足最短输入建立时间和最短输入保持时间的要求。也即是说，所述终端可支持所述存储设备在多种数据速率模式之间动态切换。
为了便于实施本申请提供的技术方案，本申请还提供了一种终端。所述终端可用于实现图8实施例描述的时序控制方法。如图9所示，终端90可包括：第一时序控制单元和第二时序控制单元，其中：
所述第一时序控制单元可用于通过第一可编程输入输出单元将主控制器输出给存储设备的时钟信号进行相位反转。
所述第二时序控制单元可用于通过第二可编程输入输出单元将所述主控制器输出给所述存储设备的数据信号延迟时间△T。
这里，所述时钟信号可用于采样所述数据信号。TCLK/2-△T≥TISU且△T≥TIH，TCLK表示所述时钟信号的周期，TISU表示不同数据速率模式下所述存储设备要求的最短输入建立时间，TIH表示不同数据速率模式下所述存储设备要求的最短输入保持时间。
本申请中，所述终端可包括所述第一可编程输入输出单元和所述第二可编程输入输出单元。具体的，所述终端可以向所述存储设备提供存储接口，所述存储接口可包括所述第一可编程输入输出单元和所述第二可编程输入输出单元。所述存储设备可以集成在所述终端中，作为所述终端的内部存储。所述存储设备也可以独立在所述终端外，作为所述终端的外部存储。关于所述存储接口的具体实现可参考前述实施例，这里不再赘述。
可以理解的，终端90包括的各个功能单元的具体实现关可参考图8方法实施例，这里不再赘述。
为了便于实施本申请提供的技术方案，本申请还提供了一种终端。所述终端可包括图5实施例描述的存储接口10，可用于实现图8实施例描述的时序控制方法。
如图10所示，终端30可包括：处理器301、耦合于处理器301的内存302、射频模块303、输入输出系统304，以及eMMC305。这些部件可在一个或多个通信总线14上通信。
射频模块303用于接收和发送信号，主要集成了终端30的接收器和发射器。具体实现中，射频模块303可包括但不限于：Wi-Fi模块3031、电信射频模块3033。其中，Wi-Fi模块3031可用于访问互联网。电信射频模块3033可以是GSM(2G)模块、WCDMA(3G)模块或者LTE(4G)模块，可用于通过电信运营商网络和其他设备建立通话连接，也可以用于通过电信运营商网络访问互联网。需要说明的，不限于图10所示，射频模块303还可以包括蓝牙模块等。在一些实施例中，可在单独的芯片上实现射频模块303。
输入输出系统304主要用于实现终端30和用户/外部环境之间的交互功能，主要包括终端30的输入输出装置。具体实现中，输入输出系统304可包括触摸屏控制器3041、音频控制器3045以及传感器控制器3047。其中，各个控制器可与各自对应的外围设备(触摸屏3051、音频电路3055以及运动传感器3057耦合。需要说明的，输入输出系统304还可以包括其他I/O外设。
eMMC305可用于扩展终端30的内部存储空间，存储用户的图片、文档、邮件等用户资料。eMMC305可以实现成图3所示的eMMC存储系统，可独立配置有主控制器306。可选的，主控制器306也可以集成在处理器301中。本申请中，eMMC305可支持在多种不同的数据速率模式之间动态切换，具体可参考图5实施例的内容，这里不再赘述。在一些可选的实施例中，终端30还可以包括其他类型的存储器，例如SDCard，这里不作限制。
处理器301可集成包括：一个或多个CPU、时钟模块以及电源管理模块。所述时钟模块主要用于为处理器301产生数据传输和时序控制所需要的时钟。所述电源管理模块主要用于为处理器301、射频模块303以及输入输出系统304等提供稳定的、高精确度的电压。
内存302与处理器301耦合，用于存储各种软件程序和/或多组指令,运行软件、输入和输出数据、中间结果及与外存交换信息等。具体实现中，内存302可包括高速随机存取的存储器，也可包括非易失性存储器，例如一个或多个易挥发性随机存取存储器(RamdomAccessMemory，RAM)。内存302还可以用于存储操作系统，例如ANDROID，IOS，WINDOWS，或者LINUX等嵌入式操作系统。
需要说明的，图10仅仅是本发明实施例的一种实现方式，实际应用中，终端30还可以包括更多或更少的部件，这里不作限制。
另外，本申请还提供了一种存储系统，可包括：主控制器、存储设备，以及连接在所述主控制器和所述存储设备之间的存储接口，所述存储接口包括第一可编程输入输出单元和第二可编程输入输出单元。其中：所述第一可编程输入输出单元用于对所述主控制器输出的时钟信号进行相位反转，并输出所述反相后的时钟信号给所述存储设备，用于采样所述主控制器输出给所述存储设备的数据信号。所述第二可编程输入输出单元对所述主控制器输出的数据信号进行延时处理，并输出延时后的所述数据信号给所述存储设备，延时后的所述数据信号在时序上比所述主控制器输出的时钟信号延后了时间△T，且TCLK/2-△T≥TISU且△T≥TIH。这里，TCLK表示所述时钟信号的周期，TISU表示不同数据速率模式下所述存储设备要求的最短输入建立时间，TIH表示不同数据速率模式下所述存储设备要求的最短输入保持时间。
关于所述存储接口的具体实现可参考图5实施例，这里不再赘述。
综上，实施本发明实施例，在主控制器向存储设备写入数据时，通过存储接口对所述主控制器输出的数据信号进行延时处理，并且对所述主控制器输出的时钟信号进行反相处理，可支持所述存储设备在不同数据速率模式之间切换。不需要为不同的数据速率模式分别产生时钟信号，也不需要对不同的数据速率模式对应的不同的时钟信号之间的时延差进行严格的控制，实现起来很简单。另外，不同批次的可编程逻辑器件和可编程逻辑器件在不同温度、电压下的时延差异对所述存储接口的发送时序影响很小。
本领域普通技术人员可以理解实现上述实施例方法中的全部或部分流程，该流程可以由计算机程序来指令相关的硬件完成，该程序可存储于计算机可读取存储介质中，该程序在执行时，可包括如上述各方法实施例的流程。而前述的存储介质包括：ROM或随机存储记忆体RAM、磁碟或者光盘等各种可存储程序代码的介质。

Claims (11)

  1. 一种存储接口，所述存储接口连接在主控制器和存储设备之间，其特征在于，包括：第一可编程输入输出单元和第二可编程输入输出单元，其中：
    所述第一可编程输入输出单元用于对所述主控制器输出的时钟信号进行相位反转，并输出所述反相后的时钟信号给所述存储设备，用于采样所述主控制器输出给所述存储设备的数据信号；
    所述第二可编程输入输出单元对所述主控制器输出的数据信号进行延时处理，并输出延时后的所述数据信号给所述存储设备，延时后的所述数据信号在时序上比所述主控制器输出的时钟信号延后了时间△T，且TCLK/2-△T≥TISU且△T≥TIH；
    其中，TCLK表示所述时钟信号的周期，TISU表示不同数据速率模式下所述存储设备要求的最短输入建立时间，TIH表示不同数据速率模式下所述存储设备要求的最短输入保持时间。
  2. 如权利要求1所述的方法，其特征在于，所述存储设备包括：存储介质和设备控制器，所述设备控制器用于根据所述存储接口输出的所述写时钟信号和延时后的所述数据信号，对所述存储介质执行写操作。
  3. 如权利要求1或2所述的方法，其特征在于，所述数据信号对应多种数据速率模式，包括：单数据速率模式和双数据速率模式，其中：TCLK/2-△T≥TISU-SDR且△T≥TIH-SDR，TCLK/2-△T≥TISU-DDR且△T≥TIH-DDR，其中，TISU-SDR、TISU-DDR分别表示所述存储设备在单数据速率模式、双数据速率模式下要求的最短输入建立时间，TIH-HS200、TIH-HS400分别表示所述存储设备在单数据速率模式、双数据速率模式下要求的最短输入保持时间。
  4. 如权利要求1-3中任一项所述的方法，其特征在于，所述第一可编程输入输出单元和所述第二可编程输入输出单元是两个分别独立的可编程逻辑器件，或者集成在同一个可编程逻辑器件中。
  5. 如权利要求1-4中任一项所述的方法，其特征在于，所述存储接口包括分别对应多种存储设备的多组所述第一可编程输入输出单元和所述第二可编程输入输出单元，其中，一种存储设备对应一组所述第一可编程输入输出单元和所述第二可编程输入输出单元；所述多种存储设备支持的数据速率模式不同。
  6. 如权利要求1-5中任一项所述的方法，其特征在于，所述存储接口集成在所述主控制器上，或者，所述存储接口独立在所述主控制器外。
  7. 如权利要求1-6中任一项所述的方法，其特征在于，所述存储设备是嵌入式多媒体卡eMCC，所述数据信号对应的多种数据速率模式包括：HS200和HS400，其中：TCLK/2-△T≥TISU-HS200且△T≥TIH-HS200，TCLK/2-△T≥TISU-HS400且△T≥TIH-HS400，其中，TISU-HS200、 TISU-HS400分别表示eMMC在HS200、HS400这两种数据速率模式下要求的最短输入建立时间，TIH-HS200、TIH-HS400分别表示eMMC在HS200、HS400这两种数据速率模式下要求的最短输入保持时间。
  8. 一种存储系统，其特征在于，包括：主控制器、存储设备，以及连接在所述主控制器和所述存储设备之间的存储接口，所述存储接口包括第一可编程输入输出单元和第二可编程输入输出单元，其中：
    所述第一可编程输入输出单元用于对所述主控制器输出的时钟信号进行相位反转，并输出所述反相后的时钟信号给所述存储设备，用于采样所述主控制器输出给所述存储设备的数据信号；
    所述第二可编程输入输出单元用于对所述主控制器输出的数据信号进行延时处理，并输出延时后的所述数据信号给所述存储设备，延时后的所述数据信号在时序上比所述主控制器输出的时钟信号延后了时间△T，且TCLK/2-△T≥TISU且△T≥TIH；
    其中，TCLK表示所述时钟信号的周期，TISU表示不同数据速率模式下所述存储设备要求的最短输入建立时间，TIH表示不同数据速率模式下所述存储设备要求的最短输入保持时间。
  9. 一种时序控制方法，其特征在于，包括
    终端通过第一可编程输入输出单元将主控制器输出给存储设备的时钟信号进行相位反转；
    所述终端通过第二可编程输入输出单元将所述主控制器输出给所述存储设备的数据信号延迟时间△T；
    其中，所述时钟信号用于采样所述数据信号；TCLK/2-△T≥TISU且△T≥TIH；TCLK表示所述时钟信号的周期，TISU表示不同数据速率模式下所述存储设备要求的最短输入建立时间，TIH表示不同数据速率模式下所述存储设备要求的最短输入保持时间。
  10. 一种终端，其特征在于，包括：第一时序控制单元和第二时序控制单元，其中：
    所述第一时序控制单元用于通过第一可编程输入输出单元将主控制器输出给存储设备的时钟信号进行相位反转；
    所述第二时序控制单元用于通过第二可编程输入输出单元将所述主控制器输出给所述存储设备的数据信号延迟时间△T；
    其中，所述时钟信号用于采样所述数据信号；TCLK/2-△T≥TISU且△T≥TIH；TCLK表示所述时钟信号的周期，TISU表示不同数据速率模式下所述存储设备要求的最短输入建立时间，TIH表示不同数据速率模式下所述存储设备要求的最短输入保持时间。
  11. 一种终端，其特征在于，包括：处理器、内部存储器，其中，所述内部存储器包括：主控制器、存储设备，以及连接在所述主控制器和所述存储设备之间的存储接口，所述存储接口包括第一可编程输入输出单元和第二可编程输入输出单元；其中：所述第一可编程输入输出单元用于对所述主控制器输出的时钟信号进行相位反转，并输出所述反相后 的时钟信号给所述存储设备，用于采样所述主控制器输出给所述存储设备的数据信号；所述第二可编程输入输出单元用于对所述主控制器输出的数据信号进行延时处理，并输出延时后的所述数据信号给所述存储设备，延时后的所述数据信号在时序上比所述主控制器输出的时钟信号延后了时间△T，且TCLK/2-△T≥TISU且△T≥TI；其中，TCLK表示所述时钟信号的周期，TISU表示不同数据速率模式下所述存储设备要求的最短输入建立时间，TIH表示不同数据速率模式下所述存储设备要求的最短输入保持时间。
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