WO2018173125A1 - Cellule solaire et module solaire - Google Patents

Cellule solaire et module solaire Download PDF

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Publication number
WO2018173125A1
WO2018173125A1 PCT/JP2017/011256 JP2017011256W WO2018173125A1 WO 2018173125 A1 WO2018173125 A1 WO 2018173125A1 JP 2017011256 W JP2017011256 W JP 2017011256W WO 2018173125 A1 WO2018173125 A1 WO 2018173125A1
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WO
WIPO (PCT)
Prior art keywords
back surface
electrode
solar cell
semiconductor substrate
light receiving
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PCT/JP2017/011256
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English (en)
Japanese (ja)
Inventor
裕樹 長谷川
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三菱電機株式会社
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Filing date
Publication date
Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to JP2019506585A priority Critical patent/JPWO2018173125A1/ja
Priority to PCT/JP2017/011256 priority patent/WO2018173125A1/fr
Priority to CN201780087633.2A priority patent/CN110419112A/zh
Priority to TW107108438A priority patent/TWI668880B/zh
Publication of WO2018173125A1 publication Critical patent/WO2018173125A1/fr

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    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells

Definitions

  • the present invention relates to a solar battery cell and a solar battery module.
  • a passivation film has been used for the purpose of suppressing the carrier recombination rate on the surface of the silicon substrate on the light receiving surface side.
  • the passivation film has a function to directly reduce the recombination center at the interface between the silicon substrate and the passivation film by terminating the dangling bonds depending on the relationship between the passivation film and silicon, or by processing before and after the passivation film is formed. have.
  • the passivation film has a function of suppressing a recombination rate due to an electric field effect by causing an electric field barrier at the interface by including a fixed charge in the interface between the silicon substrate and the passivation film.
  • Patent Document 1 by providing a passivation film on the back surface that is the non-light-receiving surface side of the solar battery cell, and providing a PERC (Passivated Emitter and Rear Cell) structure that aims to improve characteristics on the back surface side. It has been found that further improvement in characteristics can be achieved.
  • Al 2 O 3 aluminum oxide
  • SiN film silicon nitride film
  • the electrodes of adjacent solar cells are electrically joined by a tab.
  • the tab is connected to the electrode of the solar battery cell, the residual thermal stress due to the heating of the tab connection process is applied to the solar battery cell.
  • residual thermal stress is applied to the hole portion provided on the back surface of the silicon substrate, so that a crack occurs in the silicon substrate of the solar battery cell starting from the hole portion, and the manufacturing yield at the time of manufacturing the solar cell module is increased.
  • the output of the solar cell module is reduced when an external force is applied to the solar cell module, thereby reducing the output of the solar cell module and reducing the reliability of the solar cell module.
  • the present invention has been made in view of the above, and is intended to improve the characteristics of a solar battery cell using a back surface passivation film, and to suppress the occurrence of problems due to the connection of tab wires to the solar battery cell.
  • the purpose is to obtain a cell.
  • a solar cell according to the present invention includes a first conductivity type silicon substrate, and a back surface passivation film formed on the back surface of the silicon substrate facing the light receiving surface.
  • a plurality of contact holes that penetrate the back surface passivation film and reach the surface layer of the back surface of the silicon substrate from the surface of the back surface passivation film, and are arranged side by side along the first direction on the back surface passivation film, along the first direction
  • the solar battery cell is provided with a contact hole avoiding a region adjacent to the first back electrode in the first direction.
  • the solar battery cell according to the present invention is intended to improve the characteristics of the solar battery cell by the back surface passivation film, and to obtain a solar battery cell capable of suppressing the occurrence of defects due to the connection of the tab wire to the solar battery cell. There is an effect.
  • the perspective view which looked at the solar cell module concerning embodiment of this invention from the light-receiving surface side The disassembled perspective view which looked at the solar cell module concerning embodiment of this invention from the light-receiving surface side Sectional drawing of the principal part of the solar cell module concerning embodiment of this invention.
  • the perspective view which looked at the solar cell array concerning embodiment of this invention from the back surface side The perspective view which looked at the solar cell string concerning embodiment of this invention from the light-receiving surface side
  • the perspective view which looked at the solar cell string concerning embodiment of this invention from the back surface side The top view which looked at the photovoltaic cell concerning embodiment of this invention from the light-receiving surface side
  • FIG. 9 is a cross-sectional view showing a configuration of a solar battery cell according to an embodiment of the present invention, and is a cross-sectional view of a main part taken along line IX-IX in FIG.
  • FIG. 9 is a cross-sectional view showing a configuration of a solar battery cell according to an embodiment of the present invention, and is a cross-sectional view of a main part taken along line XX in FIG.
  • the principal part enlarged view of the back surface of the photovoltaic cell concerning embodiment of this invention
  • the flowchart which shows the procedure of the manufacturing method of the photovoltaic cell concerning embodiment of this invention.
  • the conceptual diagram which shows the presence of the damage layer in the semiconductor substrate which consists of p-type silicon doped with boron in embodiment of this invention shows the state which removed the damage layer which exists in the surface of a semiconductor substrate in embodiment of this invention
  • Schematic sectional view showing a planarization step on the back side of the semiconductor substrate in the embodiment of the present invention Schematic cross-sectional view showing a step of forming a back surface passivation film and a cap film on the back surface of the semiconductor substrate in the embodiment of the present invention
  • FIG. 1 is a perspective view of a solar cell module 100 according to an embodiment of the present invention as viewed from the light receiving surface side.
  • FIG. 2 is an exploded perspective view of the solar cell module 100 according to the embodiment of the present invention as viewed from the light receiving surface side.
  • FIG. 3 is a cross-sectional view of a main part of the solar cell module 100 according to the embodiment of the present invention.
  • the solar cell module 100 according to the present embodiment has the light receiving surface side of the solar cell array 70 covered with the light receiving surface side sealing material 33 and the light receiving surface protection material 31, and the solar cell array.
  • the back surface side facing the light receiving surface in 70 is covered with the back surface side sealing material 34 and the back surface protection material 32, and the outer periphery is surrounded by a reinforcing frame 40.
  • FIG. 4 is a perspective view of the solar cell array 70 according to the embodiment of the present invention as seen from the back side.
  • FIG. 5 is a perspective view of the solar cell string 50 according to the embodiment of the present invention as viewed from the light receiving surface side.
  • FIG. 6 is a perspective view of the solar cell string 50 according to the embodiment of the present invention as seen from the back side.
  • FIG. 7 is a plan view of the solar battery cell 10 according to the embodiment of the present invention as viewed from the light receiving surface side.
  • FIG. 8 is a plan view of the solar battery cell 10 according to the embodiment of the present invention as viewed from the back surface side facing the light receiving surface side. In FIG. 8, an example of the position where the tab line 20 is joined is indicated by a broken line.
  • the solar cell array 70 is configured by a plurality of solar cell strings 50 being electrically and mechanically joined in series or in parallel by horizontal tab wires 25 and output tab wires 26.
  • the solar cell string 50 includes a plurality of solar cells 10 each having a rectangular shape arranged adjacent to each other and electrically and mechanically connected in series with tab wires 20. It is configured. As shown in FIGS. 3 to 6, the plurality of solar cells 10 are connected in series in the X direction in the drawing, which is the first direction, by tab wires 20. The first direction is a connection direction of the plurality of solar cells 10 connected by the tab wire 20.
  • the solar cell 10 has a light receiving surface of a semiconductor substrate which is a first main surface of a semiconductor substrate 11 having a quadrangular shape formed of a p-type single crystal silicon substrate in which an n-type impurity diffusion layer is formed and a pn junction is formed.
  • a semiconductor substrate 11 On the 11A side, an uneven shape is formed by texture etching in order to increase the light collection rate.
  • the outer shape of the semiconductor substrate 11 has a square shape in the surface direction of the semiconductor substrate 11.
  • the n-type impurity diffusion layer is formed on the light receiving surface 11A side of the semiconductor substrate.
  • a silicon nitride film as an antireflection film is formed on the light receiving surface 11A of the semiconductor substrate. In the drawings, the uneven shape and the antireflection film are not shown.
  • a light receiving surface electrode 12 is formed on the light receiving surface 11 ⁇ / b> A side of the semiconductor substrate, and a back electrode 13 is formed on the back surface 11 ⁇ / b> B side of the semiconductor substrate that is the second main surface of the semiconductor substrate 11.
  • a plurality of light receiving surface grid electrodes 12G which are light receiving surface current collecting electrodes for collecting electrons generated by photo-electron conversion, and tab wires 20 are provided.
  • a light receiving surface bus electrode 12B which is a light receiving surface bonding electrode to be bonded, is formed.
  • the light-receiving surface grid electrode 12G is an electrode for collecting photocurrent. In order to collect photocurrent while preventing the sunlight from reaching the inside of the solar battery cell 10, a plurality of thin linear electrodes are used. These are formed side by side in parallel.
  • the light-receiving surface bus electrodes 12B are provided in four rows in a line over almost the entire length of the solar cells 10 along the first direction which is the connecting direction of the solar cells 10 as shown in FIG. ing. That is, the light receiving surface bus electrode 12B is provided so as to be connected to all the light receiving surface grid electrodes 12G along a direction orthogonal to the light receiving surface grid electrode 12G.
  • FIGS. 1, 2, 4 and 5 show a case where the light receiving surface bus electrodes 12B are provided in two rows.
  • the light-receiving surface bus electrode 12 ⁇ / b> B is an electrode provided to be electrically connected to the tab wire 20.
  • the light-receiving surface bus electrode 12B and the light-receiving surface grid electrode 12G are formed by applying and baking a conductive paste having metal particles in a desired range.
  • the back surface collecting electrode 13 a containing aluminum (Al) and the back surface joining electrode 13 b containing silver (Ag) are formed on the back surface 10 B side of the solar battery cell, and the back surface electrode 13 is configured. is doing.
  • the back surface collecting electrode 13a is an electrode provided to form a back surface electric field layer (not shown) for improving the open circuit voltage and the short circuit current, and to collect the current on the back surface side, and is substantially the back surface 10B of the solar battery cell. Cover the whole area.
  • the back junction electrode 13b is an electrode provided for taking out the holes collected by the back collector electrode 13a to the outside and making contact with the external electrode.
  • the back surface bonding electrode 13 b is an electrode provided to be electrically bonded to the tab wire 20.
  • the back surface joining electrode 13b is provided along the 1st direction which is the connection direction of the photovoltaic cell 10, similarly to the light-receiving surface bus electrode 12B. And the back surface joining electrode 13b is arrange
  • back junction electrodes 13 b of the present embodiment are arranged in four rows in a stepping stone shape over almost the entire length of solar cells 10 along a first direction that is a connecting direction of solar cells 10. Is provided.
  • the back junction electrode 13b By forming the back junction electrode 13b in a stepping stone shape, the amount of silver used can be suppressed and the manufacturing cost can be suppressed.
  • the back surface collecting electrode 13a and the back surface bonding electrode 13b are formed by applying and baking a conductive paste having metal particles such as Al or Ag in a desired range.
  • FIG. 9 is a cross-sectional view showing the configuration of the solar battery cell 10 according to the embodiment of the present invention, and is a cross-sectional view taken along the line IX-IX in FIG.
  • FIG. 10 is a cross-sectional view showing the configuration of the solar battery cell 10 according to the embodiment of the present invention, and is a cross-sectional view of the main part along the line XX in FIG. 9 and 10, the tab wire 20 connected to the solar battery cell 10 is also shown.
  • an n-type impurity which is an impurity diffusion layer in which an n-type impurity is diffused by phosphorus diffusion on the light receiving surface side of the semiconductor substrate 1 made of p-type silicon which is the first conductivity type.
  • a diffusion layer 3 is formed, and an antireflection film 4 made of a silicon nitride film is formed.
  • a p-type single crystal or polycrystalline silicon substrate can be used.
  • the semiconductor substrate 1 is not limited to this, and an n-type silicon substrate may be used.
  • the antireflection film 4 may be a silicon oxide film.
  • minute irregularities are formed as a texture structure. The micro unevenness increases the area for absorbing light from the outside on the light receiving surface, suppresses the reflectance on the light receiving surface, and has a structure for confining light. In FIG. 9 and FIG. 10, the illustration of minute irregularities is omitted for convenience.
  • the above-described light receiving surface electrode 12 is provided so as to penetrate the antireflection film 4 and be electrically connected to the n-type impurity diffusion layer 3.
  • a plurality of elongated light receiving surface grid electrodes 12G are arranged in the in-plane direction of the light receiving surface of the semiconductor substrate 1, and a light receiving surface bus electrode 12B that is electrically connected to the light receiving surface grid electrode 12G is a semiconductor. It is provided so as to be orthogonal to the light receiving surface grid electrode 12G in the in-plane direction of the light receiving surface of the substrate 1, and is electrically connected to the n-type impurity diffusion layer 3 at the bottom.
  • the longitudinal direction of the light-receiving surface bus electrode 12B is the same direction as the first direction described above, and is the connection direction of the plurality of solar cells 10 connected by the tab wires 20.
  • the longitudinal direction of the light receiving surface bus electrode 12B is the same as the second direction orthogonal to the first direction in the plane of the semiconductor substrate 1.
  • the tab wire 20 is soldered to the light-receiving surface bus electrode 12 ⁇ / b> B of the light-receiving surface electrode 12 as shown in FIGS. 9 and 10 when the solar battery module is manufactured using the solar cells 10. 9 and 10, only the light receiving surface bus electrode 12B of the light receiving surface electrode 12 is shown.
  • a cap film 6 made of a silicon oxynitride film (SiON) and protecting the back surface passivation film 5 is provided over the entire surface.
  • the cap film 6 may be a silicon nitride film (SiN film).
  • the cap film 6 is provided with dot-like contact holes 6H penetrating in the thickness direction.
  • the back surface passivation film 5 is provided with dot-like contact holes 5 ⁇ / b> H extending in the contact holes 6 ⁇ / b> H and reaching the back surface of the semiconductor substrate 1 arranged in a lattice pattern.
  • the contact holes 5H extend to the surface layer on the back surface of the semiconductor substrate 1, and the dot-like contact holes 1H are arranged in a lattice pattern.
  • the contact holes 6H, the contact holes 5H, and the contact holes 1H constitute contact holes 7 arranged in a lattice pattern.
  • the contact hole 7 has a circular cross section along the plane of the semiconductor substrate 1.
  • the contact hole 7 is constituted by the contact hole 5H and the contact hole 1H.
  • the contact holes 7 are provided in a circle having a diameter of about 20 nm to 100 nm at intervals of 0.5 mm to 1 mm. Further, the contact hole 7 is not limited to a circular shape in cross section along the plane of the semiconductor substrate 1.
  • the back electrode 13 described above is provided on the back surface of the semiconductor substrate 1 so as to be electrically connected to the back surface of the semiconductor substrate 1.
  • a back surface collecting electrode 13 a that fills the contact hole 7 and covers the entire back surface passivation film 5 in the in-plane direction of the back surface passivation film 5 is provided.
  • a back surface bonding electrode 13 b that is surrounded by the back surface current collecting electrode 13 a and electrically connected to the back surface current collecting electrode 13 a is provided.
  • the back current collecting electrode 13a is a point contact that is electrically connected to the back surface of the semiconductor substrate 1 in a contact hole 1H.
  • the tab wire 20 is soldered to the back surface joining electrode 13b among the back surface electrodes 13 as shown in FIGS. 9 and 10 when the solar cell module 100 is manufactured.
  • the solar battery cell 10 has a thickness of 200 ⁇ m, a vertical width of 156 mm, and a horizontal width of 156 mm.
  • the light receiving surface bus electrodes 12B have a width of 1 mm and a length of 155 mm, and four light receiving surface bus electrodes 12B are arranged at 39 mm intervals on the light receiving surface side of the solar battery cell 10.
  • the light-receiving surface grid electrode 12G has a width of 50 ⁇ m to 100 ⁇ m and a length of 155 mm.
  • the direction perpendicular to the longitudinal direction of the light-receiving surface bus electrode 12B is the longitudinal direction, and 156 at equal intervals of 1 mm to 2 mm. 78 books are provided.
  • the back junction electrode 13b has a square shape with a width of 2 mm and a length of 2 mm, and is parallel to the longitudinal direction of the light receiving surface bus electrode 12B at a position corresponding to the light receiving surface bus electrode 12B on the back surface side of the solar battery cell 10. 6 to 10 pieces are arranged in four rows evenly at intervals of 26 mm to 15 mm in a row having a long direction as a long direction.
  • a back surface electric field which is a p + region in which aluminum is diffused from the back surface collecting electrode 13a to the surface layer on the surface layer at a high concentration.
  • BSF Back Surface Field
  • the BSF layer 8 is formed in a region adjacent to the contact hole 1H in the surface layer on the back surface of the semiconductor substrate 1.
  • electricity generated by the solar cells flows from the semiconductor substrate 1 through a path of the BSF layer 8, the back current collecting electrode 13 a, and the back surface joining electrode 13 b.
  • FIG. 11 is an enlarged view of a main part of the back surface of the solar battery cell 10 according to the embodiment of the present invention.
  • contact hole 7 is provided in a region other than tab line connection region 14 on the back surface of semiconductor substrate 1 as shown in FIG. 8. That is, in the solar battery cell 10, the contact hole 7 is not provided in the tab line connection region 14 on the back surface.
  • the tab line connection region 14 is a region corresponding to a predetermined region to which the tab line 20 is connected on the back surface of the semiconductor substrate 1 or a region to which the tab line 20 is likely to be connected. It is provided over the entire length.
  • the area where the tab line 20 is likely to be connected is an area where the tab line 20 is likely to be connected when the tab line 20 is connected with a displacement from a predetermined connection position.
  • four tab line connection regions 14 are provided, for example, at a width of 2 mm ⁇ a length of 156 mm at an interval of 39 mm. In FIG. 8, for convenience, the tab line connection region 14 is indicated by a broken line including a region exceeding the lateral width on the back surface of the semiconductor substrate 1.
  • the tab line connection region 14 includes a solar cell 10 when the width of the tab region 20 is W and the first region 14 a that is adjacent to the back surface bonding electrode 13 b in the first direction.
  • a second region 14b that is a region within a distance of W / 2 from a pair of sides along the first direction in a second direction orthogonal to the first direction in the surface of the back surface of .
  • the second direction is the Y direction in the figure, and is the width direction of the direct back junction electrode 13b.
  • the tab wire 20 When manufacturing the solar cell module 100 by connecting the tab wire 20 to the electrode of the solar battery cell 10, the tab wire 20 is soldered to the light-receiving surface bus electrode 12B and the back surface joining electrode 13b as shown in FIGS. Attached. And the residual stress generate
  • the thickness of the semiconductor substrate 11 is about 200 ⁇ m, which is very small compared to the arrangement interval of the back surface bonding electrodes 13 b, is not relaxed by the thickness of the semiconductor substrate 11, and is transmitted to the back surface side of the semiconductor substrate 11.
  • the light receiving surface bus electrode 12 ⁇ / b> B and the back surface bonding electrode 13 b are provided at corresponding positions in the surface of the semiconductor substrate 1. Therefore, the vicinity of the back surface bonding electrode 13b on the back surface side of the semiconductor substrate 1 is affected by the residual thermal stress generated near the back surface bonding electrode 13b when the tab wire 20 is connected, and the light receiving surface bus electrode when the tab wire 20 is connected. Under the influence of the residual thermal stress generated in the vicinity of 12B, many residual thermal stresses are applied.
  • the tab line connection region 14 including the first region 14 a and the second region 14 b described above on the back surface side of the semiconductor substrate 1 remains due to the connection of the tab wire 20 to the back surface bonding electrode 13 b on the back surface side of the semiconductor substrate 1.
  • the contact hole 7, more specifically, the contact hole 1H is provided in a region other than the tab line connection region 14 on the back surface of the semiconductor substrate 1, so that the vicinity of the light receiving surface bus electrode 12B and the back surface bonding electrode 13b.
  • the influence of the residual thermal stress generated in the vicinity on the contact hole 1H can be suppressed. That is, in the solar battery cell 10, the influence of the residual thermal stress caused by the connection of the tab wire 20 to the back surface bonding electrode 13b and the influence of the residual thermal stress caused by the connection of the tab wire 20 to the light receiving surface bus electrode 12B are affected.
  • the contact hole 1H is not provided in the tab line connection region 14 in the vicinity of the receiving back junction electrode 13b.
  • the thermal stress is applied to the contact hole 1H provided on the back surface of the semiconductor substrate 1 due to the influence of the residual thermal stress generated in the vicinity of the light-receiving surface bus electrode 12B and the back surface bonding electrode 13b.
  • Generation of cracks in the cell 10 can be suppressed.
  • the solar cell 10 can suppress the deterioration of the manufacturing yield of the solar cell 10 and the output decrease of the solar cell module 100 due to the influence of the residual thermal stress generated in the vicinity of the light receiving surface bus electrode 12B.
  • the contact hole 7 it is preferable not to provide the contact hole 7 because there is a concern that the residual thermal stress is generated just above the tab wire 20. Therefore, it is preferable not to provide the contact hole 7 in the first region 14a which is a region adjacent to the back surface bonding electrode 13b in the first direction. That is, the contact hole 7 is preferably provided so as to avoid the first region 14a that is a region adjacent to the back surface bonding electrode 13b in the first direction.
  • the tab line 20 when the tab line 20 is connected, the tab line 20 may be displaced from a predetermined connection position. It is preferable to selectively form the contact hole 7 in consideration of such a positional deviation of the tab line 20. Regarding the positional deviation of the tab wire 20, it is preferable that at least half of the tab wire 20 in the width direction is solder-bonded to the back surface bonding electrode 13 b in consideration of the current collection effect from the back surface bonding electrode 13 b.
  • the width of the tab line 20 is W
  • the non-contact hole region where the contact hole 7 is not formed is preferably in a range of W / 2 in consideration of the positional deviation of the tab line 20.
  • the contact hole 7 in the second region 14b which is a region within the distance range of / 2. That is, the contact hole 7 is preferably provided so as to avoid the second region 14b that is a region adjacent to the back surface bonding electrode 13b in the first direction.
  • the width of the light receiving surface bus electrode 12B and the width of the tab line are set to the same width, for example, 1 mm.
  • the width of the back surface bonding electrode 13b is about 1 mm wider than the width of the tab line in consideration of the manufacturing accuracy of the back surface bonding electrode 13b and the tab line, for example, about 2 mm.
  • the width of the tab wire 20 is W
  • the width of the back surface bonding electrode 13b in the second direction is 2W
  • the contact hole 7 is formed in the second direction. It is not provided within the range of a distance of 2 W from the center position C of the back junction electrode 13b.
  • FIG. 12 is a flowchart showing the procedure of the method for manufacturing the solar battery cell 10 according to the embodiment of the present invention.
  • FIG. 13 to FIG. 20, FIG. 22 and FIG. 23 are cross-sectional views showing a method for manufacturing the solar battery cell 10 according to the embodiment of the present invention.
  • FIG. 21 is a schematic plan view showing a region where a contact hole is formed on the back surface side of the semiconductor substrate in the embodiment of the present invention.
  • FIG. 13 is a conceptual diagram showing the presence of the damage layer 15 in the semiconductor substrate 1 made of p-type silicon doped with boron (B) in the embodiment of the present invention.
  • FIG. 14 is a conceptual diagram showing a state in which the damaged layer 15 existing on the surface of the semiconductor substrate 1 is removed in the embodiment of the present invention.
  • 13 and 14 show a semiconductor substrate 1 which is a p-type single crystal silicon substrate cut from a silicon ingot with a wire saw.
  • a cylindrical ingot is produced by, for example, a pulling method.
  • a cylindrical p-type silicon ingot is obtained by doping boron into silicon melted at around 1400 ° C. to generate holes in the silicon and pulling it up by a pulling method.
  • doping boron with silicon lowers the resistance inside the silicon ingot, but there is a concern that the purity of the silicon will be lowered, that is, the number of electrons that can be taken out will be reduced and the crystal quality will be lowered. Care must be taken with the amount. Such a decrease in purity is widely known to be particularly noticeable in the case of single crystal silicon with stable quality, and is often managed by the specific resistance of silicon.
  • impurities such as tungsten, titanium, iron, aluminum, and nickel in silicon forms a level at the center of the crystal defect and the band gap of silicon, which occurs inside the silicon substrate of solar cell 10. Note that the recombination of the generated carriers is accelerated and the current that can be taken out is reduced.
  • the cylindrical p-type silicon ingot is cut into ingot-sized blocks with a band saw, and then sliced into a practical semiconductor substrate 1 for a solar cell with a multi-wire saw.
  • the damage layer 15 generated by machining remains on the surface of the semiconductor substrate 1 sliced by the multi-wire saw, and the solar battery cell 10 with high photoelectric conversion efficiency cannot be produced as it is. Therefore, the damage layer 15 can be removed by etching using a caustic aqueous solution typified by sodium hydroxide or potassium hydroxide, or etching using an acid solution such as a mixed solution of hydrofluoric acid and nitric acid at room temperature. Done.
  • the damage layer 15 generally remains to a depth of about 10 ⁇ m, although it varies depending on the method of slicing the p-type silicon substrate. Then, it is necessary to vary the etching processing time depending on the remaining degree of the damaged layer 15.
  • FIG. 15 is a schematic cross-sectional view showing a texture etching process for forming a texture structure on the surface of the semiconductor substrate 1 in the embodiment of the present invention.
  • the semiconductor substrate 1 is etched to form a texture structure on the surface of the semiconductor substrate 1 with a depth of about 1 ⁇ m to 10 ⁇ m as shown in FIG. Unevenness 2 is formed.
  • Etching to form a texture structure is generally performed using a mixed solution method in which isopropyl alcohol (IPA) is mixed with an alkaline aqueous solution such as an aqueous sodium hydroxide solution, but a dry etching method is selected. You can also
  • the light incident on the surface is reflected about 35%, and the amount of light that can be taken into the semiconductor substrate 1 is reduced.
  • the texture structure on the light receiving surface side of the semiconductor substrate 1
  • light is diffusely reflected on the surface of the minute irregularities 2, multiple reflection of light is generated on the surface of the solar battery cell 10, and the reflectance is effectively increased.
  • the electric current value which can be taken out with the photovoltaic cell 10 can be improved, and photoelectric conversion efficiency can be improved.
  • FIG. 16 is a schematic cross-sectional view showing an impurity diffusion step for forming n-type impurity diffusion layer 3 in semiconductor substrate 1 in the embodiment of the present invention.
  • a PN junction that is the basic structure of the solar cell is formed in step S20.
  • phosphorus (P) is diffused from the surface by thermal diffusion to the semiconductor substrate 1 having a textured structure on the surface, and as shown in FIG. 16, the sheet resistance is 60 ⁇ / sq. To 200 ⁇ / sq.
  • n-type impurity diffusion layer 3 is formed on the surface layer of semiconductor substrate 1.
  • the vapor phase diffusion of phosphorus with respect to the semiconductor substrate 1 is generally performed in a phosphorus oxychloride (POCl 3 ) atmosphere.
  • POCl 3 phosphorus oxychloride
  • the surface of the semiconductor substrate 1 immediately after the formation of the n-type impurity diffusion layer 3 is a phosphorus glass layer 3a which is a film mainly composed of glass and containing P 2 O 5 and SiO 2. Therefore, it is removed using a treatment liquid typified by hydrofluoric acid. By removing the phosphorous glass layer 3a, it is possible to improve light transmittance and prevent recombination of carriers generated in the solar battery cell 10.
  • a re-diffusion process that is, a drive-in process is performed.
  • FIG. 17 is a schematic cross-sectional view showing a flattening step on the back surface side of the semiconductor substrate 1 in the embodiment of the present invention.
  • step S30 a planarization process is performed in which the n-type impurity diffusion layer 3 formed on the back surface side of the semiconductor substrate 1 is removed and the back surface side of the semiconductor substrate 1 is planarized. Thereby, the n-type impurity diffusion layer 3 is formed on the light receiving surface side, and the semiconductor substrate 11 having a flat back surface is obtained.
  • the semiconductor substrate 1 is immersed in a hydrofluoric acid solution, thereby removing the n-type impurity diffusion layer 3 on the end surface and the back surface side of the semiconductor substrate 1. . Then, with the light receiving surface side protected, the back surface of the semiconductor substrate 1 is flattened by etching the back surface of the semiconductor substrate 1 with a mixed acid of hydrogen fluoride aqueous solution and nitric acid or an alkaline aqueous solution.
  • the planarization process on the back surface of the semiconductor substrate 1 is a process necessary for stably producing the PERC structure.
  • n-type impurity diffusion layer 3 may not be formed in advance on the back side of the semiconductor substrate 1.
  • FIG. 18 is a schematic cross-sectional view showing a process of forming the back surface passivation film 5 and the cap film 6 on the back surface of the semiconductor substrate 1 in the embodiment of the present invention.
  • the back surface passivation film 5 made of aluminum oxide (Al 2 O 3 ) having a film thickness of about 5 nm to 20 nm, and the film thickness from 100 nm.
  • a cap film 6 made of a silicon oxynitride film (SiON) of about 150 nm is formed on the back surface of the semiconductor substrate 1 in this order.
  • a plasma CVD method can be used to form the back surface passivation film 5 and the cap film 6.
  • the back surface passivation film 5 By forming the back surface passivation film 5, the disappearance of carriers at the interface between the silicon surface on the back surface of the semiconductor substrate 1 and the back surface passivation film 5 is suppressed, and red light having a long wavelength is reflected on the back surface passivation film 5. Thus, the effect of improving the photoelectric conversion efficiency by returning to the semiconductor substrate 1 can be expected.
  • FIG. 19 is a schematic cross-sectional view showing a process of forming the antireflection film 4 on the light receiving surface side of the semiconductor substrate 11 in the embodiment of the present invention.
  • the antireflection film 4 made of a SiNHO film having a film thickness of 65 nm to 90 nm is formed on the n-type impurity diffusion layer 3. It is formed on the light receiving surface side of the semiconductor substrate 1, that is, on the n-type impurity diffusion layer 3.
  • the antireflection film 4 for example, a plasma chemical vapor deposition (CVD) method is used, and a silicon nitride film is formed as the antireflection film 4 using a mixed gas of silane, ammonia, and oxygen. Note that a silicon oxide film may be formed as the antireflection film 4.
  • CVD plasma chemical vapor deposition
  • the antireflection film 4 is formed, and at the same time, hydrogen ions and radicals generated during the formation process of the antireflection film 4 are generated on the surface of the semiconductor substrate 11 and the crystal grain boundaries. It is possible to eliminate the existing dangling bonds and obtain an effect of improving the crystal quality.
  • the dangling bond means a state in which the bonding of silicon atoms existing on the substrate surface is broken. By bonding with the hydrogen ions and radicals, the level is moved to the end of the band gap and the recombination rate is lowered. It becomes possible.
  • the interference between the light reflected by the surface of the antireflection film 4 and the surface of the semiconductor substrate 11 is used, so that their periods cancel each other and the reflected light is not detected. Is an appropriate state.
  • members such as a cover glass and a sealing material, which will be described later, and attention should be paid to the fact that the specification of the appropriate antireflection film 4 described above changes.
  • FIG. 20 is a schematic cross-sectional view showing a process of forming the contact hole 7 on the back side of the semiconductor substrate 1 in the embodiment of the present invention.
  • the contact hole 5H is formed on the entire surface of the region excluding the tab line connection region 14 on the back surface side of the semiconductor substrate 1.
  • the contact holes 6H and the contact holes 5H are formed in a lattice shape having a predetermined interval using, for example, a laser. When only the back surface passivation film 5 is formed without forming the cap film 6, only the contact hole 5H is formed.
  • a contact hole 1H having the same predetermined contact hole diameter and predetermined contact hole depth as the contact hole 5H is formed on the back surface of the semiconductor substrate 1 in a region corresponding to the lower portion of the contact hole 5H using a laser.
  • a contact hole 7 having a predetermined contact hole diameter and a predetermined contact hole depth in which the contact hole 6H, the contact hole 5H, and the contact hole 1H communicate with each other is formed on the back surface side of the semiconductor substrate 1.
  • FIG. 21 is a schematic plan view showing a region where the contact hole 7 is formed on the back surface side of the semiconductor substrate 1 in the embodiment of the present invention.
  • the contact holes 7 are uniformly arranged in a dot shape in a region other than the tab line connection region 14 on the back surface of the semiconductor substrate 1.
  • the contact holes 7 are arranged at equal intervals on the entire back surface of the semiconductor substrate 1 at intervals of about 0.5 mm to 1 mm. In FIG. 21, the interval and quantity of the adjacent contact holes 7 are schematically shown.
  • the hole machining can be substituted by using an electrode material having fire-through performance when the back electrode 13 is formed. Is also possible.
  • FIG. 22 is a schematic cross-sectional view showing a process of printing an electrode material paste for forming the light-receiving surface electrode 12 and the back electrode 13 on the front and back surfaces of the semiconductor substrate 11 in the embodiment of the present invention.
  • the back surface bonding electrode material paste 16a which is the electrode material of the back surface bonding electrode 13b and contains silver and glass is used to form the back surface by screen printing on the cap film 6 on the back surface of the semiconductor substrate 11, as shown in FIG.
  • the pattern of the bonding electrode 13b is selectively printed.
  • the back surface bonding electrode material paste 16a is printed on the cap film 6 in a lattice shape having a predetermined interval in a predetermined formation region of the tab line connection region 14 where the contact hole 7 is not formed.
  • the back surface bonding electrode material paste 16 a is printed on the back surface passivation film 5.
  • a general screen printer is used for screen printing. That is, by scanning the squeegee on the printing mask on which the electrode material paste is placed, the electrode material paste is printed on the printing surface of the semiconductor substrate 11 through the printing mask.
  • the back surface current collecting electrode material paste 16b which is the electrode material of the back surface current collecting electrode 13a and contains aluminum and glass, is applied to the back surface of the semiconductor substrate 11 by screen printing as shown in FIG.
  • the pattern of the current collecting electrode 13a is selectively printed.
  • the back surface collecting electrode material paste 16b is an electrode material paste including a diffusion source of the first conductivity type.
  • the back surface collecting electrode material paste 16 b is printed on the back surface side of the semiconductor substrate 11 by filling the contact hole 7 and covering the entire cap film 6 in the in-plane direction of the back surface of the semiconductor substrate 11. That is, the back surface collecting electrode material paste 16b is printed by connecting the adjacent contact holes 7 together.
  • the back surface collecting electrode material paste 16b is printed in a state of surrounding the back surface connection electrode material paste 16a. Thereafter, the back surface collecting electrode material paste 16b is dried.
  • step S90 on the antireflection film 4 on the light receiving surface side of the semiconductor substrate 11, a light receiving surface electrode material paste 16c containing silver and glass as the electrode material of the light receiving surface electrode 12.
  • a light receiving surface electrode material paste 16c containing silver and glass as the electrode material of the light receiving surface electrode 12.
  • the light receiving surface electrode material paste 16c is selectively printed on the pattern of the light receiving surface grid electrode 12G and the pattern of the light receiving surface bus electrode 12B.
  • FIG. 23 is a schematic cross-sectional view showing a process of forming the light-receiving surface electrode 12 and the back surface electrode 13 by simultaneously firing the electrode material paste in the embodiment of the present invention.
  • step S100 in the atmosphere or oxygen atmosphere, for example, at a temperature of 700 ° C. to 900 ° C. for a time of 2 seconds to 10 seconds, back connection electrode material paste 16a, back collector electrode material paste 16b, and light receiving surface electrode
  • the printed pattern of the material paste 16c is fired simultaneously.
  • an organic solvent or the like contained in the electrode material paste is thermally decomposed to change to a low resistance state preferable as an electrode, and an ohmic contact is ensured between the electrode and the semiconductor substrate 11.
  • the light-receiving surface electrode material paste 16c penetrates the antireflection film 4 through the fire, and the light-receiving surface electrode 12 that is electrically connected to the n-type impurity diffusion layer 3 is formed.
  • the back surface collecting electrode 13a and the back surface joining electrode 13b are formed, and the region around the back surface collecting electrode 13a in the surface layer on the back surface of the semiconductor substrate 11 is formed from the back surface collecting electrode 13a to the aluminum.
  • a BSF layer 8 which is a p + region in which is diffused at a high concentration is formed, and the BSF layer 8 and the back collector electrode 13a are electrically connected in the contact hole 7.
  • the back surface collecting electrode material paste 16b printed in the contact hole 7 and the silicon on the back surface of the semiconductor substrate 11 react with each other to form a BSF layer 8 and to be electrically connected to the BSF layer 8 A contact is formed.
  • the light receiving surface electrode 12 since it is necessary to ensure good electrical contact with the n-type impurity diffusion layer 3 existing under the antireflection film 4 through the antireflection film 4 which is an insulating film, at least In the light receiving surface grid electrode 12G, a glass material is mixed into the electrode material paste. Then, when the electrode material paste is melted during firing, the glass material evaporates together with the silicon nitride film that is the antireflection film 4 and titanium oxide, and reaches the n-type impurity diffusion layer 3 including silver that is the metal component. .
  • the electrode is fired at a temperature as short as possible.
  • the solar cell 10 is obtained by performing the above process.
  • the electrode material paste may be performed by other methods such as a sputtering method or a transfer method.
  • the tab wire 20 is connected to the solar battery cell 10. That is, the region on one end side of the tab wire 20 is arranged on the back surface joining electrode 13b formed on the back surface 10B of the solar battery cell, and the light receiving surface bus electrode 12B formed on the light receiving surface 10A of the adjacent solar battery cell. A region on the other end side of the tab line 20 is arranged. Then, the solder coated on the tab wire 20 is melted by heating, and then cooled and solidified. As a result, solder bonding is performed between the region on one end side of the tab wire 20 and the back surface bonding electrode 13b, and the region on the other end side of the tab wire 20 and the light receiving surface bus electrode 12B. 20 are connected electrically and mechanically.
  • FIG. 24 is a schematic diagram showing a tab line joining step for electrically joining the light receiving surface electrode 12 and the back electrode 13 and the tab wire 20 in the embodiment of the present invention.
  • the region on one end side of the tab wire 20 is overlaid on the back surface bonding electrode 13b of the solar battery cell 10 and the region on the other end side of the tab wire 20 is overlaid on the light receiving surface bus electrode 12B (not shown).
  • the electric bonding and mechanical bonding between the tab wire 20 and the back surface bonding electrode 13b, and the electric bonding and mechanical bonding between the tab wire 20 and the light receiving surface bus electrode 12B are performed. Bonding is obtained at the same time.
  • CF adhesive conductive film
  • the contact hole 7 is formed in a region other than the tab line connection region 14 on the back surface of the semiconductor substrate 11.
  • the manufacturing yield of the solar battery cell 10 is deteriorated due to the influence of the residual thermal stress when the tab wire 20 is connected to the light receiving surface bus electrode 12B and the back junction electrode 13b of the solar battery cell 10 and the solar cell.
  • the output reduction of the battery module 100 can be suppressed.
  • FIG. 25 is a perspective view showing the solar cell string 50 in the embodiment of the present invention.
  • the above connection process of the tab wires 20 is repeated to form a plurality of solar battery strings 50 in which a desired number of solar battery cells 10 are connected in series as shown in FIG.
  • the solar cell array 70 is formed by connecting the plurality of solar cell strings 50 obtained as described above by the horizontal tab wires 25.
  • the solar cell array 70 is formed by connecting a plurality of solar cell strings 50 arranged in parallel using a bus bar as a horizontal tab line 25 in series, and installing a bus bar as an output tab line 26 for extracting power.
  • cracks starting from the contact holes 1 ⁇ / b> H may occur in the semiconductor substrate 1 due to thermal stress applied to the solar cells 10.
  • the contact hole 7 is formed in a region other than the tab line connection region 14 on the back surface of the semiconductor substrate 1.
  • the manufacturing yield of the solar battery cell 10 is deteriorated due to the influence of the residual thermal stress when the tab wire 20 is connected to the light receiving surface bus electrode 12B and the back junction electrode 13b of the solar battery cell 10 and the solar cell.
  • the output reduction of the battery module 100 can be suppressed.
  • the light receiving surface side sealing material 33 and the light receiving surface protection material 31 are disposed on the light receiving surface side of the solar cell array 70, and the back surface side sealing is performed on the back surface side of the solar cell array 70.
  • the material 34 and the back surface protection material 32 are arranged to form a laminate.
  • laminate is mounted on a laminating apparatus, and heat treatment and laminating treatment are performed at 140 ° C. to 160 ° C. for about 30 minutes. Thereby, each member of a laminated body is integrated via the light-receiving surface side sealing material 33, the back surface side sealing material 34, and the back surface protection material 32, and the solar cell module 100 is obtained.
  • the solar cell module 100 is installed outdoors, and it is not uncommon for an external force such as snow load or wind to be applied to the front cover glass and the rear back film. At this time, stress is also generated in the packaged solar cell 10, so that a crack starting from the contact hole 1 ⁇ / b> H is generated in the semiconductor substrate 1, and there is a risk that power generation is reduced.
  • the contact hole 7 is formed in a region other than the tab line connection region 14 on the back surface of the semiconductor substrate 1.
  • the manufacturing yield of the solar battery cell 10 is deteriorated due to the influence of the residual thermal stress when the tab wire 20 is connected to the light receiving surface bus electrode 12B and the back junction electrode 13b of the solar battery cell 10 and the solar cell.
  • the output reduction of the battery module 100 can be suppressed.
  • the contact hole 7 provided on the back surface side is selectively formed in a region other than the tab line connection region 14 on the back surface of the semiconductor substrate 1. ing. Therefore, as described above, the characteristics of the solar cell 10 are improved by the passivation effect on the back surface of the semiconductor substrate 11 by the back surface passivation film 5, and the tab line 20 to the light receiving surface electrode 12 and the back surface electrode 13 of the solar cell 10. It is possible to suppress the occurrence of defects due to the connection.
  • the configuration described in the above embodiment shows an example of the contents of the present invention, and can be combined with another known technique, and can be combined with other configurations without departing from the gist of the present invention. It is also possible to omit or change the part.
  • Photovoltaic cell 10A Photosensitive surface of the solar cell, 10B Back surface of the photovoltaic cell, 11A Semiconductor substrate light receiving surface, 11B Semiconductor substrate light receiving surface, 12 Light receiving surface electrode, 12B Light receiving surface bus electrode, 12G Light receiving surface grid electrode , 13 Back electrode, 13a Back current collecting electrode, 13b Back surface bonding electrode, 13s Pair of sides, 14 Tab line connection region, 14a 1st region, 14b 2nd region, 15 Damage layer, 16a Back surface bonding electrode material paste, 16b Back surface Current collecting electrode material paste, 16c light receiving surface electrode material paste, 20 tab wire, 5 horizontal tab line, 26 output tab line, 31 light receiving surface protective material, 32 back surface protective material, 33 light receiving surface side sealing material, 34 back

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  • Photovoltaic Devices (AREA)

Abstract

La présente invention comprend : un substrat de silicium d'un premier type de conduction ; un film de passivation de surface arrière qui est formé sur la surface arrière du substrat de silicium faisant face à une surface de réception de lumière ; une pluralité de trous de contact (7) qui passent par le film de passivation de surface arrière et atteignent une couche de surface de la surface arrière du substrat de silicium à partir de la surface du film de passivation de surface arrière ; une pluralité de premières électrodes de surface arrière (13b) qui sont disposées le long d'une première direction sur le film de passivation de surface arrière et sont utilisées pour connecter des lignes de languette de type bande (20) le long de la première direction ; et une électrode de collecteur de surface arrière (13a) qui connecte le substrat de silicium à l'intérieur des trous de contact (7) et les premières électrodes de surface arrière (13b). Une cellule solaire (10) est pourvue des trous de contact (7), évitant des zones voisines des premières électrodes de surface arrière (13b) dans la première direction.
PCT/JP2017/011256 2017-03-21 2017-03-21 Cellule solaire et module solaire WO2018173125A1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2019506585A JPWO2018173125A1 (ja) 2017-03-21 2017-03-21 太陽電池セルおよび太陽電池モジュール
PCT/JP2017/011256 WO2018173125A1 (fr) 2017-03-21 2017-03-21 Cellule solaire et module solaire
CN201780087633.2A CN110419112A (zh) 2017-03-21 2017-03-21 太阳能电池单元以及太阳能电池模块
TW107108438A TWI668880B (zh) 2017-03-21 2018-03-13 Solar battery unit and solar battery module

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Citations (5)

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Publication number Priority date Publication date Assignee Title
US20100275965A1 (en) * 2009-06-18 2010-11-04 Daeyong Lee Solar cell and method of manufacturing the same
US20130025665A1 (en) * 2011-07-25 2013-01-31 Daeyong Lee Solar cell and method for manufacturing the same
WO2016047564A1 (fr) * 2014-09-22 2016-03-31 京セラ株式会社 Élément de cellule solaire
JP2016164969A (ja) * 2015-02-26 2016-09-08 京セラ株式会社 太陽電池素子およびその製造方法
JP2017045907A (ja) * 2015-08-28 2017-03-02 京セラ株式会社 太陽電池素子およびその製造方法

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Publication number Priority date Publication date Assignee Title
JP2007266262A (ja) * 2006-03-28 2007-10-11 Sharp Corp インターコネクタ付き太陽電池、太陽電池モジュールおよび太陽電池モジュールの製造方法
US20090260685A1 (en) * 2008-04-17 2009-10-22 Daeyong Lee Solar cell and method of manufacturing the same
WO2011058653A1 (fr) * 2009-11-13 2011-05-19 三菱電機株式会社 Pile solaire
TWI590473B (zh) * 2014-10-24 2017-07-01 昱晶能源科技股份有限公司 太陽能電池及其製造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100275965A1 (en) * 2009-06-18 2010-11-04 Daeyong Lee Solar cell and method of manufacturing the same
US20130025665A1 (en) * 2011-07-25 2013-01-31 Daeyong Lee Solar cell and method for manufacturing the same
WO2016047564A1 (fr) * 2014-09-22 2016-03-31 京セラ株式会社 Élément de cellule solaire
JP2016164969A (ja) * 2015-02-26 2016-09-08 京セラ株式会社 太陽電池素子およびその製造方法
JP2017045907A (ja) * 2015-08-28 2017-03-02 京セラ株式会社 太陽電池素子およびその製造方法

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