WO2018171063A1 - 一种移动终端 - Google Patents

一种移动终端 Download PDF

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Publication number
WO2018171063A1
WO2018171063A1 PCT/CN2017/089948 CN2017089948W WO2018171063A1 WO 2018171063 A1 WO2018171063 A1 WO 2018171063A1 CN 2017089948 W CN2017089948 W CN 2017089948W WO 2018171063 A1 WO2018171063 A1 WO 2018171063A1
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WO
WIPO (PCT)
Prior art keywords
clock
module
frequency
clock signal
clock generator
Prior art date
Application number
PCT/CN2017/089948
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English (en)
French (fr)
Inventor
李童杰
张君勇
刘晓松
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to CN201780065696.8A priority Critical patent/CN109863728B/zh
Priority to JP2019552191A priority patent/JP2020514925A/ja
Priority to KR1020197030455A priority patent/KR102444599B1/ko
Priority to US16/496,804 priority patent/US11429133B2/en
Priority to EP17901891.6A priority patent/EP3591917B1/en
Publication of WO2018171063A1 publication Critical patent/WO2018171063A1/zh

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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/08Clock generators with changeable or programmable clock frequency
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03BGENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/02Details
    • H03B5/04Modifications of generator to compensate for variations in physical values, e.g. power supply, load, temperature
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/06Clock generators producing several clock signals
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04Generating or distributing clock signals or signals derived directly therefrom
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03BGENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/08Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
    • H03B5/12Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03BGENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/30Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator
    • H03B5/32Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/02Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/08Modifications for reducing interference; Modifications for reducing effects due to line faults ; Receiver end arrangements for detecting or overcoming line faults
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04MTELEPHONIC COMMUNICATION
    • H04M1/00Substation equipment, e.g. for use by subscribers
    • H04M1/02Constructional features of telephone sets
    • H04M1/0202Portable telephone sets, e.g. cordless phones, mobile phones or bar type handsets
    • H04M1/026Details of the structure or mounting of specific components
    • H04M1/0264Details of the structure or mounting of specific components for a camera module assembly
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04MTELEPHONIC COMMUNICATION
    • H04M1/00Substation equipment, e.g. for use by subscribers
    • H04M1/02Constructional features of telephone sets
    • H04M1/0202Portable telephone sets, e.g. cordless phones, mobile phones or bar type handsets
    • H04M1/026Details of the structure or mounting of specific components
    • H04M1/0266Details of the structure or mounting of specific components for a display module assembly
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03BGENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B2200/00Indexing scheme relating to details of oscillators covered by H03B
    • H03B2200/0014Structural aspects of oscillators
    • H03B2200/002Structural aspects of oscillators making use of ceramic material
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03BGENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B2202/00Aspects of oscillators relating to reduction of undesired oscillations
    • H03B2202/08Reduction of undesired oscillations originated from the oscillator in circuit elements external to the oscillator by means associated with the oscillator
    • H03B2202/082Reduction of undesired oscillations originated from the oscillator in circuit elements external to the oscillator by means associated with the oscillator by avoiding coupling between these circuit elements

Definitions

  • the present application relates to the field of electronic technologies, and in particular, to a mobile terminal.
  • the clock source is a module that generates a clock pulse signal that can clock the operation of other modules.
  • the spacing of the modules is getting closer and closer.
  • the adjacent electromagnetic interference may cause problems in the operation of the module, such as the fingerprint unlocking speed is too slow, the camera There are stuck in the photo, the button is linked when dialing, and the line is broken when marking on the touch screen.
  • the prior art adopts a frequency domain control method, and different crystal oscillators are configured for each module, and clocks of different frequencies are generated by each crystal oscillator. In this way, the electromagnetic frequency interference can be reduced by different clock frequencies of the modules.
  • the clock frequencies generated by different types of crystal oscillators will shift by different magnitudes. In this way, the clock frequency or the frequency of the higher harmonics of the two modules will coincide at a specific frequency. In this way, electromagnetic interference between the modules can cause the two modules to be dysfunctional.
  • the application provides a mobile terminal with better anti-electromagnetic interference capability.
  • a first aspect of the present application provides a mobile terminal, including: a clock generator, a first frequency conversion circuit, a first module, a second frequency conversion circuit, and a second module, wherein the first frequency conversion circuit generates a clock generated by the clock generator The signal is frequency-converted to obtain a first clock signal, and the first clock signal is output to the first module; the second frequency conversion circuit converts the clock signal generated by the clock generator to obtain a second clock signal, and outputs the second clock signal to the second module. .
  • the first frequency conversion circuit is respectively connected to the clock generator and the first module, and the second frequency conversion circuit is respectively connected to the clock generator and the second module, and the first clock signal and the second clock signal are clock signals of different frequencies.
  • the first clock signal and the second clock signal are both obtained by frequency conversion of a clock signal generated by the clock generator, that is, the first clock signal and the second clock signal are homologous clocks.
  • the clock signal generated by the clock generator is temperature drifted
  • the temperature drift percentage of the first clock signal and the second clock signal are the same, and the temperature drift percentage refers to the percentage of the clock frequency offset under the action of temperature. In this way, the clock frequencies of different modules are difficult to overlap, thereby reducing electromagnetic interference.
  • a ratio of a clock frequency of the first clock signal to a clock frequency of the second clock signal is M/N, M is a positive odd number, N is a power of n to the power of n, and n is a positive integer. Since the product of M and the odd number cannot be equal to N, it is difficult for the odd harmonic frequency of the first clock signal and the subharmonic frequency of the second clock signal to coincide. Compared with the prior art, the electromagnetic interference between the first module and the second module can be effectively reduced by the above parameter configuration.
  • the first module includes a third frequency conversion circuit and a first functional unit
  • the second module includes a fourth frequency conversion circuit and a second function unit
  • the third frequency conversion circuit converts the first clock signal Obtaining a third clock signal
  • the third clock signal is output to the first functional unit
  • the fourth frequency conversion circuit converts the second clock signal to obtain a fourth clock signal, and outputs the fourth clock signal to the second functional unit.
  • the third frequency conversion circuit is respectively connected to the first frequency conversion circuit and the first function unit
  • the fourth frequency conversion circuit is respectively connected to the second frequency conversion circuit and the second function unit
  • the clock frequency of the third clock signal and the clock frequency of the fourth clock signal are
  • M/N M is a positive odd number
  • N is a power of n to the power of n
  • n is a positive integer.
  • the first module is a touch screen module, a display module, a fingerprint recognition module or a camera module
  • the second module is a touch screen module, a display module, a fingerprint recognition module or The camera module, the first module and the second module are different types of modules.
  • the clock generator is a crystal oscillator, a semiconductor oscillator, or a ceramic oscillator.
  • the mobile terminal further includes a power adapter, the ratio of the clock frequency of the first clock signal to the fundamental frequency of the power adapter is M/N, or the clock frequency of the second clock signal and the fundamental frequency of the power adapter.
  • the ratio is M/N, M is a positive odd number, N is a power of n to the power of n, and n is a positive integer.
  • the mobile terminal further includes an audio processing module and a video processing module.
  • the ratio of the fundamental frequency of the audio processing module to the fundamental frequency of the video processing module is M/N, and M is a positive odd number.
  • N is a power of n to n, and n is a positive integer.
  • the mobile terminal further includes a third module and a fourth module, the third module includes a fifth frequency conversion circuit and a third function unit, and the fourth module includes a sixth frequency conversion circuit and a fourth a functional unit; the fifth frequency conversion circuit converts the clock signal generated by the clock generator to obtain a fifth clock signal, and outputs the fifth clock signal to the third functional unit; and the sixth frequency conversion circuit converts the clock signal generated by the clock generator to obtain a sixth The clock signal outputs the sixth clock signal to the fourth functional unit.
  • the fifth frequency conversion circuit is respectively connected to the clock generator and the third function unit, and the sixth frequency conversion circuit is respectively connected to the clock generator and the fourth function unit, and the fifth clock signal and the sixth clock signal are clock signals of different frequencies.
  • the fifth clock signal and the sixth clock signal are both obtained by frequency conversion of a clock signal generated by the clock generator, and when the clock signal generated by the clock generator is temperature drifted, the fifth clock signal and the sixth clock signal are The temperature drift percentage is the same.
  • the clock frequencies of the third functional unit and the fourth functional unit are difficult to overlap, thereby reducing electromagnetic interference.
  • the ratio of the clock frequency of the fifth clock signal to the clock frequency of the sixth clock signal is M/N, M is a positive odd number, N is a power of n to the power of n, and n is a positive integer.
  • a second aspect of the present application provides a mobile terminal, where the mobile terminal includes a first module and a second module, the first module includes a first clock generator, and the second module includes a second clock generator;
  • the generator's clock frequency temperature drift trend is consistent with the second clock generator's clock frequency temperature drift trend.
  • a ratio of a clock frequency generated by the first clock generator to a clock frequency generated by the second clock generator is M/N, M is a positive odd number, N is a power of n, and n is A positive integer. Since the product of M and the odd number cannot be equal to N, it is difficult for the odd harmonic frequency of the first clock signal and the subharmonic frequency of the second clock signal to coincide. Compared with the prior art, the electromagnetic interference between the first module and the second module can be effectively reduced by the above parameter configuration.
  • the first module is a touch screen module, a display module, a fingerprint recognition module or a camera module
  • the second module is a touch screen module, a display module, a fingerprint recognition module or The camera module, the first module and the second module are different types of modules.
  • the clock frequency temperature drift trend of the first clock generator and the clock frequency temperature drift trend of the second clock generator are monotonically decreasing; or the clock frequency of the first clock generator is temperature drifted.
  • the trend and the clock frequency temperature drift trend of the second clock generator are monotonically decreasing; or, the clock frequency temperature drift trend of the first clock generator and the clock frequency temperature drift trend curve of the second clock generator are both parabolic.
  • the first clock generator and the second clock generator are both crystal oscillators.
  • the first clock generator and the second clock generator are both semiconductor oscillators.
  • the first clock generator and the second clock generator are both ceramic oscillators.
  • the mobile terminal includes a clock generator, a first frequency conversion circuit, a first module, a second frequency conversion circuit, and a second module.
  • the first frequency conversion circuit converts the clock signal generated by the clock generator to obtain a first clock signal, and outputs the first clock signal to the first module;
  • the second frequency conversion circuit converts the clock signal generated by the clock generator to obtain a second clock signal,
  • the second clock signal is output to the second module.
  • the clock of the above module is a homologous clock.
  • the temperature drift percentage of the clock frequency of each module is the same as the temperature drift percentage of the clock frequency of the clock generator. In this way, the clock frequencies of different modules are difficult to overlap, and electromagnetic interference can be minimized.
  • 1 is a schematic diagram of a configuration clock of an existing mobile terminal
  • FIG. 2 is a schematic diagram showing the spectrum distribution of an existing TP module and an LCD module under normal conditions
  • FIG. 3 is a schematic diagram of a spectral temperature drift of the existing TP module and the LCD module;
  • FIG. 4 is a schematic diagram of a mobile terminal in an embodiment of the present application.
  • FIG. 5 is a schematic diagram of a spectrum offset of a TP module and an LCD module according to an embodiment of the present application
  • FIG. 6 is another schematic diagram of a mobile terminal according to an embodiment of the present application.
  • FIG. 7 is a schematic diagram of anti-interference capability of a TP module according to an embodiment of the present application.
  • FIG. 8 is a schematic diagram showing another spectrum distribution of the TP module and the LCD module in a normal state
  • FIG. 9 is another schematic diagram of temperature drift of a TP module and an LCD module according to an embodiment of the present application.
  • FIG. 10 is another schematic diagram of a mobile terminal according to an embodiment of the present application.
  • FIG. 11 is a schematic diagram of a temperature drift trend of two clock frequencies in an embodiment of the present application.
  • FIG. 12 is another schematic diagram of a temperature drift trend of two clock frequencies in an embodiment of the present application.
  • FIG. 13 is another schematic diagram of the temperature drift trend of two clock frequencies in the embodiment of the present application.
  • a mobile terminal refers to a computer device that can be used for mobile use, such as a mobile phone, a platform computer, a vehicle-mounted computer, a wearable electronic device, a mobile point of sales terminal (POS), and the like.
  • a system-on-chip (SOC) is also installed in the mobile terminal, and is also written as a SoC.
  • FIG. 1 is a clock configuration diagram of an internal module of an existing terminal. Intention, a module is a module with independent functions in an electronic device.
  • the source clock is generated by the crystal oscillator of the SOC11, and the crystal oscillator is also called a quartz crystal oscillator, which is referred to as a crystal oscillator.
  • Each module has a clock signal, an active clock is configured in the SOC 11, the A module 12 is configured with a clock 1, the B module 13 is configured with a clock 2, and the C module 14 is configured with a clock 3.
  • the source clock can be output as a clock for other modules, such as clock 1.
  • Both clock 2 and clock 3 are independent clocks, which are generated by separate clock oscillators and have nothing to do with the source clock.
  • the module 2 is exemplified by a touch panel (TP) module
  • the module 3 is exemplified by a liquid crystal display (LCD) module.
  • 2 is a schematic diagram showing the spectrum distribution of the TP module and the LCD module in a normal state, in which the horizontal axis unit is kilohertz (kHz) and the vertical axis unit is decibel milliwatt (dBm).
  • the fundamental frequency of the LCD module is 30 kHz, and the subharmonic frequency is an integral multiple of 30 kHz.
  • the fundamental frequency of the TP module is 98 kHz, and the subharmonic frequency of the TP module is an odd multiple of 98 kHz, such as 3, 5, 7, 9, 11, and the like.
  • the frequency and temperature drift of clock 2 and clock 3 are different, and the temperature drift is simply referred to as temperature drift.
  • the temperature drift of the TP fundamental frequency is ⁇ 3% due to the ambient temperature
  • the frequency of the subharmonic of the TP module will also vary within ⁇ 3%.
  • the 3rd harmonic of the TP module and the subharmonic of the LCD module coincide at 300 kHz, forming harmonic interference.
  • the frequency of the 5th harmonic of the TP module coincides with the subharmonic of the LCD module at 480kHz, forming harmonic interference. Harmonic interference can easily lead to module failure, and subharmonics are also called noise.
  • an embodiment of the mobile terminal 400 provided by the present application includes:
  • a clock generator 401 a first frequency conversion circuit 402, a first module 403, a second frequency conversion circuit 404 and a second module 405;
  • the first frequency conversion circuit 402 is connected to the clock generator 401 and the first module 403, for converting the clock signal generated by the clock generator 401 to obtain a first clock signal, and outputting the first clock signal to the first module 403;
  • the second frequency conversion circuit 404 is connected to the clock generator 401 and the second module 405 respectively for converting the clock signal generated by the clock generator 401 to the second clock signal, and outputting the second clock signal to the second module 405.
  • a clock signal and a second clock signal are clock signals of different frequencies.
  • the clock generator 401 may be a crystal oscillator, a semiconductor oscillator or a ceramic oscillator, and the semiconductor oscillator is also called a silicon oscillator.
  • the frequency conversion circuit may be a frequency dividing circuit, a frequency multiplying circuit or a combination circuit including a frequency dividing circuit and a frequency multiplying circuit.
  • the first frequency conversion circuit 402 is a frequency dividing circuit having a ratio of an input frequency to an output frequency of n1
  • the second frequency converting circuit 404 is a frequency multiplying circuit having a ratio of an input frequency to an output frequency of n2.
  • the frequency of the clock signal generated by the clock generator 401 is 26 MHz
  • the frequency of the clock signal output from the frequency dividing circuit is 26 MHz/n1
  • the frequency of the clock signal output from the frequency multiplying circuit is n2*26 MHz.
  • the first module 403 is a touch screen module, a display module, a fingerprint recognition module or a camera module
  • the second module 405 is a touch screen module, a display module, a fingerprint recognition module or
  • the camera module, the first module 403 and the second module 405 are different types of modules.
  • the display module of the display module may be an LCD, a Light Emitting Diode (LED) or an Organic Light Emitting Diode (Organic Light Emitting Diode). OLED) and so on.
  • the mobile terminal 400 can also include other frequency conversion circuits and other modules, each of which can convert the frequency of the clock signal generated by the clock generator to the clock frequency of the corresponding module.
  • the clock of the first module 403 and the clock of the second module 405 are homologous clocks.
  • the temperature drift percentage of f0 be a%, that is, (1 ⁇ a%)*f0.
  • the temperature drift percentage of the subharmonics of each module is the same as the temperature drift percentage of f0. In this way, the clock frequencies of different modules are difficult to overlap, so that the degree of electromagnetic interference is very low.
  • the temperature drift percentage refers to the percentage of the frequency offset due to temperature and the normal frequency.
  • Figure 5 is a schematic diagram of the spectral offset of two modules.
  • the first module 403 is a TP module
  • the second module 405 is an LCD module.
  • the dotted line in the upper part of FIG. 5 is the offset TP spectrum
  • the broken line in the lower part of FIG. 5 is the shifted LCD spectrum.
  • the spectrum offsets of the first module 403 and the second module 405 are the same, the clock frequencies of the two modules are difficult to overlap, and the degree of electromagnetic interference is low.
  • the ratio of the clock frequency of the first clock signal to the clock frequency of the second clock signal is M/N, M is a positive odd number, N is a power of n to the power of n, and n is a positive integer.
  • M is a positive odd number and N is a positive integer power of 2
  • M/N cannot be an integer
  • the clock frequency of the first clock signal cannot be equal to the clock frequency of the second clock signal, and it is impossible Equal to a positive integer multiple of the clock frequency of the second clock signal.
  • the odd harmonic of the first clock signal may be a harmonic of 1, 3, 5, etc., and the product of the odd number and M/N may not be an integer, so the odd harmonic frequency of the first clock signal may not be equal to An integer multiple of the subharmonic frequency of the second clock signal. This ensures that the fundamental or subharmonic frequencies of the first module and the second module do not coincide in the normal mode.
  • the fundamental frequency of the first clock signal is F 1 (1)
  • the fundamental frequency of the second clock signal is F 2 (1)
  • ⁇ f
  • the fundamental frequency of the first clock signal is 90 kHz
  • the fundamental frequency of the second clock signal is 40 kHz
  • M/N 9/4
  • the frequency values of the 9th harmonics are 90, 270, 450, etc., respectively.
  • the frequency of the 40 kHz subharmonic is 40, 80, 120, 160, 200, 240, 280, and the like.
  • the minimum frequency difference between the two clock signals is
  • the clock frequency spacing of the two clock signals is always greater than or equal to F 2 (1)/N, and F 2 (1) is the fundamental frequency of the second module.
  • F 2 (1) is the fundamental frequency of the second module.
  • the tolerance causes the offset of the clock frequency to be less than F 2 (1)/N, the above two spectra do not overlap, thus effectively reducing the electromagnetic interference caused by the tolerance.
  • the first module 403 includes a third frequency conversion circuit 4031 and a first function unit 4032
  • the second module 405 includes a fourth frequency conversion circuit 4051 and a second function unit 4052
  • the third frequency conversion circuit 4031 is connected to the first frequency conversion circuit 402 and the first function unit 4032, respectively, for converting the first clock signal to obtain a third a clock signal, the third clock signal is output to the first function unit 4032
  • the fourth frequency conversion circuit 4051 is connected to the second frequency conversion circuit 404 and the second function unit 4052, respectively, for converting the second clock signal to obtain a fourth clock signal
  • the fourth clock signal is output to the second functional unit 4052; wherein, the ratio of the clock frequency of the third clock signal to the clock frequency of the fourth clock signal is M/N, M is a positive odd number, and N is a power of n n, n Is a positive integer.
  • M is a positive odd number and N is a positive integer power of 2
  • M/N cannot be an integer
  • the clock frequency of the third clock signal cannot be equal to the clock frequency of the fourth clock signal, and it is impossible Equal to an integer multiple of the clock frequency of the fourth clock signal.
  • the odd harmonics of the third clock signal may be 1, 3, 5 and other subharmonics, and the product of odd and M/N may not be an integer, and the odd harmonic frequency of the third clock signal may not be equal to the fourth clock.
  • An integer multiple of the subharmonic frequency of the signal This ensures that in the normal mode, the fundamental or subharmonic frequencies of the first functional unit and the second functional unit are difficult to coincide.
  • the first functional unit when the first module is a touch screen module, the first functional unit may be a touch screen circuit.
  • the second module is a liquid crystal display module, the second functional unit may be a driving circuit of the liquid crystal display.
  • the first module may further include other functional units connected to the first frequency conversion circuit, and the second module may further include other functional units connected to the second frequency conversion circuit.
  • the mobile terminal includes a third module and a fourth module, the third module includes a fifth frequency conversion circuit and a third function unit, and the fourth module includes a sixth frequency conversion circuit and a fourth function.
  • the fifth frequency conversion circuit is connected to the clock generator 401 and the third function unit respectively for converting the first clock signal to obtain the fifth clock signal, and outputting the fifth clock signal to the third functional unit;
  • the sixth frequency conversion circuit is respectively connected
  • the clock generator 401 and the fourth function unit are configured to frequency-convert the clock signal generated by the clock generator 401 to obtain a sixth clock signal, and output the sixth clock signal to the fourth functional unit; wherein the clock frequency of the fifth clock signal is
  • the ratio of the clock frequency of the sixth clock signal is M/N, M is a positive odd number, N is a power of n to the power of n, and n is a positive integer.
  • the fundamental frequencies of the third module and the fourth module are the same, and the ratio of the clock frequencies of the above two functional units (ie, the third functional unit and the fourth functional unit) is M/N. Since M is a positive odd number, N is a positive integer power of 2, so M/N cannot be an integer, and the clock frequency of the fifth clock signal cannot be equal to the clock frequency of the sixth clock signal, and may not be equal to the sixth clock signal. An integer multiple of the clock frequency.
  • the odd harmonic of the fifth clock signal may be a harmonic of 1, 3, 5, etc., and the product of the odd number and the M/N may not be an integer, and the odd harmonic frequency of the fifth clock signal may not be equal to the first An integer multiple of the subharmonic frequency of the six clock signals. This ensures that the fundamental or subharmonic frequencies of the third functional unit and the fourth functional unit do not coincide in the normal mode.
  • the SOC of the mobile terminal can be connected to a power adapter.
  • the ratio of the clock frequency of the TP circuit to the clock frequency of the power adapter is M/N.
  • the ratio of the clock frequency of the fingerprint identification circuit to the clock frequency of the power adapter is M/N, and the values of M and N are as shown in the above embodiment.
  • the mobile terminal takes a mobile phone as an example.
  • the mobile phone includes a TP module and an LCD module.
  • the base frequency F 1 (1) of the TP module is 80 kHz
  • the fundamental frequency F 2 (1) of the LCD module is 22.86 kHz.
  • Figure 7 is a schematic diagram of the anti-interference of the TP module.
  • the TP module has poor anti-interference ability at frequencies of 80 kHz, 240 kHz, 400 kHz, and 560 kHz, that is, odd-order harmonics of 1, 3, 5, and 7 with a base frequency of 80 kHz. It is easy to be disturbed, and the TP module detection is easy to malfunction.
  • the temperature drift of the fundamental frequency of the TP module is 1.6 kHz
  • the temperature drift of the third harmonic is The amplitude is 4.8 kHz
  • the temperature drift of the 7th harmonic is 11.2 kHz. It can be seen from the above that as the number of subharmonics increases, the temperature drift of the subharmonics increases. It can be seen from 11.2kHz ⁇ 11.43kHz that the temperature drift of the 7th harmonic is still smaller than the frequency spacing of the subharmonic, so the above harmonic frequencies will not coincide, as shown in Fig. 9. It can be seen that by configuring the above-mentioned fundamental frequency for different modules, harmonic interference can be effectively reduced within a certain range.
  • another embodiment of the mobile terminal 1000 of the present application includes:
  • the clock frequency temperature drift tendency of the first clock generator 10011 coincides with the clock frequency temperature drift trend of the second clock generator 10021, the clock frequency of the first clock generator and the clock of the second clock generator The frequency is different.
  • the clock frequency temperature drift trend refers to the trend of the clock frequency offset as the temperature changes.
  • the set temperature range may be a normal operating temperature interval of the first module, or a normal operating temperature interval of the second module, or a normal operating temperature interval of the mobile terminal 1000.
  • the normal operating temperature range of the mobile terminal 1000 is generally 0 to 40 °C.
  • the difference between the clock frequency offsets of the two clock generators is less than the threshold value, and it can be considered that the clock frequency fluctuation trends of the two clock generators are consistent. Since the clock frequency of different modules is consistent, and the clock frequencies of different modules are different, the clock frequencies of different modules are difficult to overlap, and the electromagnetic interference level is very low.
  • the clock frequency temperature drift trend of the first clock generator and the clock frequency temperature drift trend of the second clock generator are both monotonically decreasing.
  • the clock frequency offset of the first clock generator is f1
  • the clock frequency offset of the second clock generator is f3
  • the clock frequency offset of the first clock generator is when the temperature is t2.
  • the amount is f2, and the clock frequency offset of the second clock generator is f4.
  • the clock frequency offset of both clock generators is the largest.
  • the clock frequency offset gradually decreases.
  • the clock frequency of the two clock generators is biased.
  • the amount of shift is minimized.
  • the difference between the two clock frequency offsets is less than a preset threshold.
  • the clock frequency temperature drift tendency of the first clock generator and the clock frequency temperature drift trend of the second clock generator are both monotonically increasing.
  • the clock frequency offset of the first clock generator is f1
  • the clock frequency offset of the second clock generator is f3
  • the clock frequency offset of the first clock generator is when the temperature is t2.
  • the amount is f2, and the clock frequency offset of the second clock generator is f4.
  • the clock frequency offset of both clock generators is the smallest.
  • the clock frequency offset gradually increases.
  • the clock frequency of the two clock generators is biased.
  • the amount of shift has reached the maximum. At any one of [t1, t2], the difference between the two clock frequency offsets is less than a preset threshold.
  • the clock frequency temperature drift trend of the first clock generator and the clock frequency temperature drift trend curve of the second clock generator are both parabolic.
  • Clock frequency of the first clock generator at temperatures t1 and t3 The rate offset is f1, the clock frequency offset of the second clock generator is f3; when the temperature is t2, the clock frequency offset of the first clock generator is f2, and the clock frequency of the second clock generator is biased.
  • the shift is f4.
  • the clock frequency offset of both clock generators is the largest. In [t1, t2], as the temperature increases, the clock frequency offset gradually decreases.
  • the first module 1001 is a touch screen module, a display module, a fingerprint recognition module or a camera module
  • the second module 1002 is a touch screen module, a display module, a fingerprint recognition module or The camera module, the first module 1001 and the second module 1002 are different types of modules.
  • each module may further include other modules such as a third module and a fourth module.
  • each module also includes a functional unit.
  • the functional unit included therein may be a touch screen circuit.
  • the functional unit included therein may be a driving circuit of the liquid crystal display.
  • the ratio of the clock frequency generated by the first clock generator 10011 to the clock frequency generated by the second clock generator 10021 is M/N, M is a positive odd number, and N is a power of n n, n Is a positive integer.
  • M/N cannot be an integer
  • the clock frequency generated by the first clock generator cannot be equal to the clock frequency generated by the second clock generator. It is also impossible to be equal to an integral multiple of the clock frequency generated by the second clock generator.
  • the odd harmonics of the clock frequency generated by the first clock generator may be 1, 3, and 5th harmonics, and the product of odd and M/N may not be integers, and the odd harmonics generated by the first clock generator The frequency cannot be equal to an integer multiple of the subharmonic frequency produced by the second clock generator. This ensures that the fundamental or subharmonic frequencies of the first module and the second module do not coincide in the normal mode.
  • the difference between the clock frequencies of the two clock signals is always greater than or equal to F 2 (1)/N, and F 2 (1) is the fundamental frequency of the second module.
  • F 2 (1) is the fundamental frequency of the second module.
  • the tolerance causes the offset of the clock frequency to be less than F 2 (1)/N, the above two spectra do not overlap, thus effectively reducing the electromagnetic interference caused by the tolerance.
  • the first clock generator 10011 is a crystal oscillator and the second clock generator 10021 is a crystal oscillator.
  • the crystal shape of the two crystal oscillators and the crystal are cut in the same way, so that the temperature drift of the two clock generators is consistent, for example, the temperature drift trend is monotonically increasing, monotonically decreasing or parabolic.
  • the first clock generator 10011 is a semiconductor oscillator and the second clock generator 10021 is a semiconductor oscillator.
  • the first clock generator 10011 is a ceramic oscillator and the second clock generator 10021 is a ceramic oscillator.

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Abstract

本申请公开了一种移动终端,包括:时钟生成器、第一变频电路、第一模组、第二变频电路和第二模组,第一变频电路将时钟生成器产生的时钟信号变频得到第一时钟信号,将第一时钟信号输出给第一模组;第二变频电路将时钟生成器产生的时钟信号变频得到第二时钟信号,将第二时钟信号输出给第二模组。本申请的移动终端具有更好的抗电磁干扰能力。

Description

一种移动终端
本申请要求于2017年3月24日提交中国专利局、申请号为201710182423.3、发明名称为“一种移动终端”的中国专利申请的优先权,其全部内容通过引用结合在本申请中。
技术领域
本申请涉及电子技术领域,尤其涉及一种移动终端。
背景技术
时钟源是指产生时钟脉冲信号的模组,其可以为其他模组的运行提供时钟。随着电子设备的小型化,其中模组的间距越来越近,当模组的时钟频率相同或者基本相同时,邻近的电磁干扰会导致模组运行出现问题,例如指纹解锁速度过慢,摄像拍照有卡顿,拨号时按键联动,在触摸屏上划线时断线等。
为了解决模组间的电磁干扰,现有技术采用频域管控方法,为各模组配置不同的晶体振荡器,由各晶体振荡器产生不同频率的时钟。这样,各模组的时钟频率不同,就能够降低电磁干扰。
但是,受到环境温度影响,不同类型的晶体振荡器产生的时钟频率会发生不同幅度的偏移。这样,两个模组的时钟频率或高次谐波的频率在特定频点会重合。这样,模组间的电磁干扰会导致两个模组功能紊乱。
发明内容
本申请提供了一种移动终端,具有更好的抗电磁干扰能力。
本申请的第一方面提供了一种移动终端,包括:时钟生成器、第一变频电路、第一模组、第二变频电路和第二模组,第一变频电路将时钟生成器产生的时钟信号变频得到第一时钟信号,将第一时钟信号输出给第一模组;第二变频电路将时钟生成器产生的时钟信号变频得到第二时钟信号,将第二时钟信号输出给第二模组。其中,第一变频电路分别连接时钟生成器和第一模组,第二变频电路分别连接时钟生成器和第二模组,第一时钟信号和第二时钟信号为不同频率的时钟信号。
在上述移动终端中,第一时钟信号和第二时钟信号均由时钟生成器产生的时钟信号变频得到,即第一时钟信号和第二时钟信号为同源时钟。当时钟生成器产生的时钟信号发生温漂时,第一时钟信号和第二时钟信号的温漂百分比相同,温漂百分比是指在温度作用下时钟频率偏移百分比。这样,不同模组的时钟频率难以重合,从而降低电磁干扰。
在一种可能的实现方式中,第一时钟信号的时钟频率与第二时钟信号的时钟频率之比为M/N,M为正奇数,N为2的n次幂,n为正整数。由于M与奇数的乘积不可能等于N,因此第一时钟信号的奇次谐波频率和第二时钟信号的次谐波频率难以重合。与现有技术相比,通过上述参数配置能够有效降低第一模组和第二模组之间的电磁干扰。
在另一种可能的实现方式中,第一模组包括第三变频电路和第一功能单元,第二模组包括第四变频电路和第二功能单元;第三变频电路将第一时钟信号变频得到第三时钟信号, 将第三时钟信号输出给第一功能单元;第四变频电路将第二时钟信号变频得到第四时钟信号,将第四时钟信号输出给第二功能单元。其中,第三变频电路分别连接第一变频电路和第一功能单元,第四变频电路分别连接第二变频电路和第二功能单元,第三时钟信号的时钟频率与第四时钟信号的时钟频率之比为M/N,M为正奇数,N为2的n次幂,n为正整数。这样,由于M与奇数的乘积不可能等于N,因此第三时钟信号的奇次谐波频率和第四时钟信号的次谐波频率难以重合。与现有技术相比,通过上述参数配置能够有效降低第一功能单元和第二功能单元之间的电磁干扰。
在另一种可能的实现方式中,第一模组为触摸屏模组、显示器模组、指纹识别模组或摄像头模组,第二模组为触摸屏模组、显示器模组、指纹识别模组或摄像头模组,第一模组与第二模组为不同类型的模组。
在另一种可能的实现方式中,时钟生成器为晶体振荡器、半导体振荡器或陶瓷振荡器。
在另一种可能的方式中,移动终端还包括电源适配器,第一时钟信号的时钟频率和电源适配器的基频之比为M/N,或第二时钟信号的时钟频率和电源适配器的基频之比为M/N,M为正奇数,N为2的n次幂,n为正整数。
在另一种可能的方式中,移动终端还包括音频处理模组和视频处理模组,音频处理模组的基频和视频处理模组的基频之比为M/N,M为正奇数,N为2的n次幂,n为正整数。
在另一种可能的方式中,移动终端还包括第三模组和第四模组,第三模组包括第五变频电路和第三功能单元,第四模组包括第六变频电路和第四功能单元;第五变频电路将时钟生成器产生的时钟信号变频得到第五时钟信号,将第五时钟信号输出给第三功能单元;第六变频电路将时钟生成器产生的时钟信号变频得到第六时钟信号,将第六时钟信号输出给第四功能单元。其中,第五变频电路分别连接时钟生成器和第三功能单元,第六变频电路分别连接时钟生成器和第四功能单元,第五时钟信号和第六时钟信号为不同频率的时钟信号。在该移动终端中,第五时钟信号和第六时钟信号均由时钟生成器产生的时钟信号变频得到,当时钟生成器产生的时钟信号发生温漂时,第五时钟信号和第六时钟信号的温漂百分比相同。这样,第三功能单元和第四功能单元的时钟频率难以重合,从而降低电磁干扰。
在另一种可能的方式中,第五时钟信号的时钟频率与第六时钟信号的时钟频率之比为M/N,M为正奇数,N为2的n次幂,n为正整数。
本申请的第二方面提供一种移动终端,移动终端包括第一模组和第二模组,第一模组包括第一时钟生成器,第二模组包括第二时钟生成器;第一时钟生成器的时钟频率温漂趋势和第二时钟生成器的时钟频率温漂趋势一致。这样,由于不同模组的时钟频率温漂趋势一致,且不同模组的时钟频率不同,这样,不同模组的时钟频率难以重合。与现有技术相比,能够有效降低第一模组和第二模组的电磁干扰。
在一种可能的实现方式中,第一时钟生成器产生的时钟频率与第二时钟生成器产生的时钟频率之比为M/N,M为正奇数,N为2的n次幂,n为正整数。由于M与奇数的乘积不可能等于N,因此第一时钟信号的奇次谐波频率和第二时钟信号的次谐波频率难以重合。与现有技术相比,通过上述参数配置能够有效降低第一模组和第二模组之间的电磁干扰。
在另一种可能的实现方式中,第一模组为触摸屏模组、显示器模组、指纹识别模组或摄像头模组,第二模组为触摸屏模组、显示器模组、指纹识别模组或摄像头模组,第一模组与第二模组为不同类型的模组。
在另一种可能的实现方式中,第一时钟生成器的时钟频率温漂趋势和第二时钟生成器的时钟频率温漂趋势均为单调递减;或,第一时钟生成器的时钟频率温漂趋势和第二时钟生成器的时钟频率温漂趋势均为单调递减;或,第一时钟生成器的时钟频率温漂趋势和第二时钟生成器的时钟频率温漂趋势曲线均为抛物线。这样,在两个模组采用以上时钟频率温漂趋势时,均能有效降低电磁干扰。
在另一种可能的实现方式中,第一时钟生成器和第二时钟生成器均为晶体振荡器。
在另一种可能的实现方式中,第一时钟生成器和第二时钟生成器均为半导体振荡器。
在另一种可能的实现方式中,第一时钟生成器和第二时钟生成器均为陶瓷振荡器。
在本申请的实施例中,移动终端包括时钟生成器、第一变频电路、第一模组、第二变频电路和第二模组。第一变频电路将时钟生成器产生的时钟信号变频得到第一时钟信号,将第一时钟信号输出给第一模组;第二变频电路将时钟生成器产生的时钟信号变频得到第二时钟信号,将第二时钟信号输出给第二模组。可见,以上模组的时钟为同源时钟。在环境温度影响时钟频率时,各模组的时钟频率的温度漂移百分比与时钟生成器的时钟频率的温度漂移百分比相同。这样,不同模组的时钟频率难以重合,能够尽量降低电磁干扰。
附图说明
图1为现有移动终端的配置时钟的一个示意图;
图2为在正常状态下现有TP模组和LCD模组的频谱分布示意图;
图3为现有TP模组和LCD模组的一个频谱温漂示意图;
图4为本申请实施例中移动终端的一个示意图;
图5为本申请实施例中TP模组和LCD模组的一个频谱偏移示意图;
图6为本申请实施例中移动终端的另一个示意图;
图7为本申请实施例中TP模组抗干扰能力的一个示意图;
图8为在正常状态下TP模组和LCD模组的另一个频谱分布示意图;
图9为本申请实施例中TP模组和LCD模组的另一个频谱温漂示意图;
图10为本申请实施例中移动终端的另一个示意图;
图11为本申请实施例中两个时钟频率的温漂趋势的一个示意图;
图12为本申请实施例中两个时钟频率的温漂趋势的另一个示意图;
图13为本申请实施例中两个时钟频率的温漂趋势的另一个示意图。
具体实施方式
移动终端是指可移动使用的计算机设备,例如手机、平台电脑、车载电脑、可穿戴式电子设备、可移动的销售终端(point of sales terminal,POS)等。在移动终端内设置有系统级芯片(System on Chip,SOC),也写作SoC。图1为现有终端内部模组的时钟配置示 意图,模组是电子设备中具有独立功能的模块。由SOC11的晶体振荡器产生源时钟,晶体振荡器也称为石英晶体振荡器,简称晶振。每个模组都有时钟信号,在SOC11配置有源时钟,A模组12配置有时钟1,B模组13配置有时钟2,C模组14配置有时钟3。源时钟可以输出作为其他模组的时钟,例如时钟1。时钟2和时钟3均为独立时钟,分别由独立的时钟振荡器产生,与源时钟并无关系。
模组2以触摸屏(touch panel,TP)模组为例,模组3以液晶显示器(liquid crystal display,LCD)模组为例。图2为在正常状态下TP模组和LCD模组的频谱分布示意图,其中,横轴单位为千赫兹(kHz),纵轴单位为分贝毫瓦(dBm)。LCD模组的基频为30kHz,次谐波频点为30kHz的整数倍。TP模组的基频为98kHz,TP模组的次谐波频点为98kHz的奇数倍,例如3、5、7、9、11等。这样,TP模组的次谐波和LCD模组的次谐波之间存在频率间隔,此时模组间的谐波干扰程度较低。
然而,由于不同晶体振荡器中晶体的几何形状或切割方式不同,时钟2和时钟3的频率温度漂移幅度不同,温度漂移简称为温漂。请参阅图3,受到环境温度影响,若TP基频的温漂百分比为±3%,则TP模组的次谐波的频率也会在±3%的范围变动。这样,TP模组的3次谐波和LCD模组的次谐波在300kHz重合,形成谐波干扰。与之相似,TP模组的5次谐波的频点和LCD模组的次谐波在480kHz重合,形成谐波干扰。谐波干扰容易导致模组失灵,次谐波也称为噪声。
为了解决不同晶体振荡器的时钟频率受到环境影响导致的频点重合,在本申请的移动终端中通过一个晶体振荡器为多个模组提供时钟。请参阅图4,本申请提供的移动终端400的一个实施例包括:
时钟生成器401、第一变频电路402、第一模组403、第二变频电路404和第二模组405;
第一变频电路402分别连接时钟生成器401和第一模组403,用于将时钟生成器401产生的时钟信号变频得到第一时钟信号,将第一时钟信号输出给第一模组403;
第二变频电路404分别连接时钟生成器401和第二模组405,用于将时钟生成器401产生的时钟信号变频得到第二时钟信号,将第二时钟信号输出给第二模组405,第一时钟信号和第二时钟信号为不同频率的时钟信号。
其中,时钟生成器401可以是晶体振荡器、半导体振荡器或陶瓷振荡器,半导体振荡器也称为硅振荡器。
其中,变频电路可以是分频电路、倍频电路或者是包括分频电路和倍频电路的组合电路。举例来说,第一变频电路402为分频电路,其输入频率和输出频率之比为n1,第二变频电路404为倍频电路,其输入频率和输出频率之比为n2。当时钟生成器401产生的时钟信号的频率为26MHz时,从分频电路输出的时钟信号的频率为26MHz/n1,从倍频电路输出的时钟信号的频率为n2*26MHz。
在一些可选实施例中,第一模组403为触摸屏模组、显示器模组、指纹识别模组或摄像头模组,第二模组405为触摸屏模组、显示器模组、指纹识别模组或摄像头模组,第一模组403与第二模组405为不同类型的模组。其中,显示器模组的显示器可以是LCD,发光二极管(Light Emitting Diode,LED)或有机发光二极管(Organic Light Emitting Diode, OLED)等。
可以理解的是,移动终端400还可以包括其他变频电路和其他模组,每个变频电路均能将时钟生成器产生的时钟信号的频率转换为相应模组的时钟频率。
本实施例中,第一模组403的时钟和第二模组405的时钟为同源时钟。在环境温度影响时钟频率时,设f0的温漂百分比为a%,即(1±a%)*f0。经变频电路输出的时钟频率也会发生同幅变化,即f1=(1±a%)*f0/n1,f2=(1±a%)*f0*n2。各模组的次谐波的温漂百分比和f0的温漂百分比相同。这样,不同模组的时钟频率难以重合,从而使电磁干扰程度很低。温漂百分比是指由于温度导致的频率偏移幅度与正常频率的百分比。
举例来说,图5为两个模组的频谱偏移示意图。第一模组403为TP模组,第二模组405为LCD模组,图5上部分的虚线为偏移后的TP频谱,图5下部分的虚线为偏移后的LCD频谱。从图5可以看出,第一模组403和第二模组405的频谱偏移幅度相同,两个模组的时钟频率难以重合,电磁干扰程度很低。
在一个可选实施例中,第一时钟信号的时钟频率与第二时钟信号的时钟频率之比为M/N,M为正奇数,N为2的n次幂,n为正整数。
本实施例中,由于M为正奇数,N为2的正整数次幂,因此M/N不可能是整数,第一时钟信号的时钟频率不可能等于第二时钟信号的时钟频率,也不可能等于第二时钟信号的时钟频率的正整数倍。另外,第一时钟信号的奇次谐波可以是1、3、5等次谐波,奇数与M/N之积也不可能是整数,因此第一时钟信号的奇次谐波频率不可能等于第二时钟信号的次谐波频率的整数倍。这样能够保证在正常模式下,第一模组和第二模组的基频或次谐波频率不会重合。
具体的,记第一时钟信号的基频为F1(1),其奇次谐波的频率为F1(n3)=F1(1)*n3,n3为奇数变量。记第二时钟信号的基频为F2(1),其次谐波的频率为F2(n4)=F2(1)*n4,n4为偶数变量。
由P(1)/F2(1)=M/N可知,F1(1)=F2(1)*M/N。
以上两个时钟信号的次谐波的频率间距Δf为:
Δf=|F1(n3)-F2(n4))|=|(n3*(M*F2(1))/N)-(n4*F2(1))|=|(n3*M-n4*N)*F2(1)/N|。
举例来说,第一时钟信号的基频为90kHz,第二时钟信号的基频为40kHz,M/N=9/4,那么9的次谐波的频率值分别为90,270,450等,40kHz的次谐波的频率值为40,80,120,160,200,240,280等。以上可见,两个时钟信号的最小频率差为|90-80|或|280-270|,即10kHz。
需要说明的是,两个时钟信号的时钟频率间距总是大于或等于F2(1)/N,F2(1)为第二模组的基频。当温漂百分比小于F2(1)/N时,上述两个时钟频率不会重叠,这样就能够有效降低温漂导致的谐波干扰,如图8所示。或者,当公差导致时钟频率的偏移幅度小于F2(1)/N时,上述两个频谱不会重叠,这样就能够有效降低公差导致的电磁干扰。
请参阅图6,在另一个可选实施例中,第一模组403包括第三变频电路4031和第一功能单元4032,第二模组405包括第四变频电路4051和第二功能单元4052;第三变频电路4031分别连接第一变频电路402和第一功能单元4032,用于将第一时钟信号变频得到第三 时钟信号,将第三时钟信号输出给第一功能单元4032;第四变频电路4051分别连接第二变频电路404和第二功能单元4052,用于将第二时钟信号变频得到第四时钟信号,将第四时钟信号输出给第二功能单元4052;其中,第三时钟信号的时钟频率与第四时钟信号的时钟频率之比为M/N,M为正奇数,N为2的n次幂,n为正整数。
本实施例中,由于M为正奇数,N为2的正整数次幂,因此M/N不可能是整数,第三时钟信号的时钟频率不可能等于第四时钟信号的时钟频率,也不可能等于第四时钟信号的时钟频率的整数倍。第三时钟信号的奇次谐波可以是1、3、5等次谐波,奇数与M/N之积也不可能是整数,第三时钟信号的奇次谐波频率不可能等于第四时钟信号的次谐波频率的整数倍。这样能够保证在正常模式下,第一功能单元和第二功能单元的基频或次谐波频率难以重合。
可以理解的是,当第一模组为触摸屏模组时,第一功能单元可以是触摸屏电路。第二模组为液晶显示器模组时,第二功能单元可以是液晶显示器的驱动电路。第一模组还可以包括与第一变频电路连接的其他功能单元,第二模组还可以包括与第二变频电路连接的其他功能单元。
在另一个可选实施例中,移动终端包括第三模组和第四模组,第三模组包括第五变频电路和第三功能单元,第四模组包括第六变频电路和第四功能单元;第五变频电路分别连接时钟生成器401和第三功能单元,用于将第一时钟信号变频得到第五时钟信号,将第五时钟信号输出给第三功能单元;第六变频电路分别连接时钟生成器401和第四功能单元,用于将时钟生成器401产生的时钟信号变频得到第六时钟信号,将第六时钟信号输出给第四功能单元;其中,第五时钟信号的时钟频率与第六时钟信号的时钟频率之比为M/N,M为正奇数,N为2的n次幂,n为正整数。
本实施例中,第三模组和第四模组的基频相同,以上两个功能单元(即第三功能单元和第四功能单元)的时钟频率之比为M/N。由于M为正奇数,N为2的正整数次幂,因此M/N不可能是整数,第五时钟信号的时钟频率不可能等于第六时钟信号的时钟频率,也不可能等于第六时钟信号的时钟频率的整数倍。另外,第五时钟信号的奇次谐波可以是1、3、5等次谐波,奇数与M/N之积也不可能是整数,第五时钟信号的奇次谐波频率不可能等于第六时钟信号的次谐波频率的整数倍。这样能够保证在正常模式下,第三功能单元和第四功能单元的基频或次谐波频率不会重合。
在一些实施例中,移动终端的SOC可以与电源适配器连接。在移动终端中,TP电路的时钟频率和电源适配器的时钟频率之比为M/N。或者,指纹识别电路的时钟频率和电源适配器的时钟频率之比为M/N,M、N的取值如上述实施例所示。
为便于理解,下面以一个具体应用场景对本申请提供的移动终端进行详细介绍:
移动终端以手机为例,手机包括TP模组和LCD模组,通过TP模组的基频F1(1)为80kHz,LCD模组的基频F2(1)为22.86kHz。图7为TP模组的抗干扰示意图,TP模组在80kHz、240kHz、400kHz和560kHz的频点上抗干扰能力差,即以80kHz为基频的1、3、5、7等奇次谐波容易被干扰,此时TP模组检测容易失灵。
当TP模组和LCD模组正常工作时,由于F1(1)/F2(1)=M/N=7/2,TP模组的奇次谐波 频点和LCD模组的次谐波频点不会发生重合,如图8所示。此时,两个模组产生次谐波的频点间距Δf=F2(1)/2=11.43kHz。
当TP模组的频谱的温漂百分比为±2%,LCD模组的频谱的温漂幅度基本不变时,TP模组的基频的温漂幅度为1.6kHz,3次谐波的温漂幅度为4.8kHz,7次谐波的温漂幅度为11.2kHz。从以上可见,随着次谐波的次数增加,次谐波的温漂幅度增大。从11.2kHz<11.43kHz可见,7次谐波的温漂幅度仍然小于次谐波的频点间距,因此以上次谐波频点均不会发生重合,如图9所示。可见,通过为不同模组配置上述基频,能够在一定范围内有效降低谐波干扰。
请参阅图10,本申请的移动终端1000的另一个实施例包括:
第一模组1001和第二模组1002,第一模组1001包括第一时钟生成器10011,第二模组1002包括第二时钟生成器10021;
在设定温度范围内,第一时钟生成器10011的时钟频率温漂趋势和第二时钟生成器10021的时钟频率温漂趋势一致,第一时钟生成器的时钟频率和第二时钟生成器的时钟频率不同。
其中,时钟频率温漂趋势是指随着温度变化的时钟频率偏移量的变化趋势。设定温度范围可以是第一模组的正常工作温度区间,或者是第二模组的正常工作温度区间,或者是移动终端1000的正常工作温度区间。移动终端1000的正常工作温度区间一般为0~40℃。
本实施例中,在设定温度范围的任意一个温度下,两个时钟生成器的时钟频率偏移量之差小于阈值,可以认为两个时钟生成器的时钟频率温漂趋势一致。由于不同模组的时钟频率温漂趋势一致,且不同模组的时钟频率不同,这样,不同模组的时钟频率难以重合,从而使电磁干扰程度很低。
请参阅图11,在一些实施例中,第一时钟生成器的时钟频率温漂趋势和第二时钟生成器的时钟频率温漂趋势均为单调递减。在温度为t1时,第一时钟生成器的时钟频率偏移量为f1,第二时钟生成器的时钟频率偏移量为f3;在温度为t2时,第一时钟生成器的时钟频率偏移量为f2,第二时钟生成器的时钟频率偏移量为f4。其中,t2>t1,f1>f2,f3>f4。在温度为t1时,两个时钟生成器的时钟频率偏移量均为最大,随着温度增加,时钟频率偏移量逐渐减小,在温度为t2时,两个时钟生成器的时钟频率偏移量均达到最小。在[t1,t2]中的任意一个温度,两个时钟频率偏移量之差小于预设阈值。
请参阅图12,在另一些实施例中,第一时钟生成器的时钟频率温漂趋势和第二时钟生成器的时钟频率温漂趋势均为单调递增。在温度为t1时,第一时钟生成器的时钟频率偏移量为f1,第二时钟生成器的时钟频率偏移量为f3;在温度为t2时,第一时钟生成器的时钟频率偏移量为f2,第二时钟生成器的时钟频率偏移量为f4。其中,t2>t1,f2>f1,f4>f3。在温度为t1时,两个时钟生成器的时钟频率偏移量均为最小,随着温度增加,时钟频率偏移量逐渐增大,在温度为t2时,两个时钟生成器的时钟频率偏移量均达到最大。在[t1,t2]中的任意一个温度,两个时钟频率偏移量之差小于预设阈值。
请参阅图13,在另一些实施例中,第一时钟生成器的时钟频率温漂趋势和第二时钟生成器的时钟频率温漂趋势曲线均为抛物线。在温度为t1和t3时,第一时钟生成器的时钟频 率偏移量为f1,第二时钟生成器的时钟频率偏移量为f3;在温度为t2时,第一时钟生成器的时钟频率偏移量为f2,第二时钟生成器的时钟频率偏移量为f4。其中,t3>t2>t1,f1>f2,f3>f4。在温度为t1时,两个时钟生成器的时钟频率偏移量均为最大,在[t1,t2]中随着温度增加,时钟频率偏移量逐渐减少,在温度为t2时,两个时钟生成器的时钟频率偏移量均达到最小,在[t2,t3]中随着温度增加,时钟频率偏移量逐渐增加。在[t1,t3]中的任意一个温度,两个时钟频率偏移量之差小于预设阈值。
在一些可选实施例中,第一模组1001为触摸屏模组、显示器模组、指纹识别模组或摄像头模组,第二模组1002为触摸屏模组、显示器模组、指纹识别模组或摄像头模组,第一模组1001与第二模组1002为不同类型的模组。
可以理解的是,移动终端1000还可以包括第三模组、第四模组等其他模组。除了时钟生成器之外,每个模组还包括功能单元。例如,当第一模组1001为触摸屏模组时,其包括的功能单元可以是触摸屏电路。第二模组1002为液晶显示器模组时,其包括的功能单元可以是液晶显示器的驱动电路。
在一个可选实施例中,第一时钟生成器10011产生的时钟频率与第二时钟生成器10021产生的时钟频率之比为M/N,M为正奇数,N为2的n次幂,n为正整数。
本实施例中,由于M为正奇数,N为2的正整数次幂,因此M/N不可能是整数,第一时钟生成器产生的时钟频率不可能等于第二时钟生成器产生的时钟频率,也不可能等于第二时钟生成器产生的时钟频率的整数倍。另外,第一时钟生成器产生的时钟频率的奇次谐波可以是1、3、5次谐波,奇数与M/N之积不可能是整数,第一时钟生成器产生的奇次谐波频率不可能等于第二时钟生成器产生的次谐波频率的整数倍。这样能够保证在正常模式下,第一模组和第二模组的基频或次谐波频率不会重合。
需要说明的是,两个时钟信号的时钟频率之差总是大于或等于F2(1)/N,F2(1)为第二模组的基频。当温漂幅度小于F2(1)/N时,上述两个时钟频率不会重叠,这样就能够有效降低温漂导致的谐波干扰。或者,当公差导致时钟频率的偏移幅度小于F2(1)/N时,上述两个频谱不会重叠,这样就能够有效降低公差导致的电磁干扰。
在另一个可选实施例中,第一时钟生成器10011为晶体振荡器,第二时钟生成器10021为晶体振荡器。两个晶体振荡器的晶体形状以及晶体切割方式相同,使得两个时钟生成器的温漂趋势一致,例如温漂趋势为单调递增、单调递减或抛物线。
在另一个可选实施例中,第一时钟生成器10011为半导体振荡器,第二时钟生成器10021为半导体振荡器。
在另一个可选实施例中,第一时钟生成器10011为陶瓷振荡器,第二时钟生成器10021为陶瓷振荡器。
以上实施例仅用以说明本申请的技术方案,而非对其限制;尽管参照前述实施例对本申请进行了详细的说明,本领域的普通技术人员应当理解:其依然可以对前述各实施例记载的技术方案进行修改,或者对其中部分技术特征进行等同替换;而这些修改或者替换,并不使相应技术方案脱离本申请各实施例记载技术方案的精神和范围。

Claims (12)

  1. 一种移动终端,其特征在于,包括:
    时钟生成器、第一变频电路、第一模组、第二变频电路和第二模组;
    所述第一变频电路分别连接所述时钟生成器和所述第一模组,用于将所述时钟生成器产生的时钟信号变频得到第一时钟信号,将所述第一时钟信号输出给所述第一模组;
    所述第二变频电路分别连接所述时钟生成器和所述第二模组,用于将所述时钟生成器产生的时钟信号变频得到第二时钟信号,将所述第二时钟信号输出给所述第二模组,所述第一时钟信号和所述第二时钟信号为不同频率的时钟信号。
  2. 根据权利要求1所述的移动终端,其特征在于,第一时钟信号的时钟频率与所述第二时钟信号的时钟频率之比为M/N,所述M为正奇数,所述N为2的n次幂,所述n为正整数。
  3. 根据权利要求1所述的移动终端,其特征在于,所述第一模组包括第三变频电路和第一功能单元,所述第二模组包括第四变频电路和第二功能单元;
    所述第三变频电路分别连接所述第一变频电路和所述第一功能单元,用于将所述第一时钟信号变频得到第三时钟信号,将所述第三时钟信号输出给所述第一功能单元;
    所述第四变频电路分别连接所述第二变频电路和所述第二功能单元,用于将所述第二时钟信号变频得到第四时钟信号,将所述第四时钟信号输出给所述第二功能单元;
    其中,所述第三时钟信号的时钟频率与所述第四时钟信号的时钟频率之比为M/N,所述M为正奇数,所述N为2的n次幂,所述n为正整数。
  4. 根据权利要求1至3中任一项所述的移动终端,其特征在于,所述第一模组为触摸屏模组、显示器模组、指纹识别模组或摄像头模组,所述第二模组为触摸屏模组、显示器模组、指纹识别模组或摄像头模组,所述第一模组与所述第二模组为不同类型的模组。
  5. 根据权利要求1至3中任一项所述的移动终端,其特征在于,所述时钟生成器为晶体振荡器、半导体振荡器或陶瓷振荡器。
  6. 一种移动终端,所述移动终端包括第一模组和第二模组,其特征在于,所述第一模组包括第一时钟生成器,所述第二模组包括第二时钟生成器;
    所述第一时钟生成器的时钟频率温漂趋势和所述第二时钟生成器的时钟频率温漂趋势一致,所述第一时钟生成器的时钟频率和所述第二时钟生成器的时钟频率不同。
  7. 根据权利要求6所述的移动终端,其特征在于,所述第一时钟生成器产生的时钟频率与所述第二时钟生成器产生的时钟频率之比为M/N,所述M为正奇数,所述N为2的n次幂,所述n为正整数。
  8. 根据权利要求6或7所述的移动终端,其特征在于,所述第一模组为触摸屏模组、显示器模组、指纹识别模组或摄像头模组,所述第二模组为触摸屏模组、显示器模组、指纹识别模组或摄像头模组,所述第一模组与所述第二模组为不同类型的模组。
  9. 根据权利要求6或7所述的移动终端,其特征在于,所述第一时钟生成器的时钟频率温漂趋势和所述第二时钟生成器的时钟频率温漂趋势均为单调递减;
    或,所述第一时钟生成器的时钟频率温漂趋势和所述第二时钟生成器的时钟频率温漂 趋势均为单调递减;
    或,所述第一时钟生成器的时钟频率温漂趋势和所述第二时钟生成器的时钟频率温漂趋势曲线均为抛物线。
  10. 根据权利要求6或7所述的移动终端,其特征在于,所述第一时钟生成器和所述第二时钟生成器均为晶体振荡器。
  11. 根据权利要求6或7所述的移动终端,其特征在于,所述第一时钟生成器和所述第二时钟生成器均为半导体振荡器。
  12. 根据权利要求6或7所述的移动终端,其特征在于,所述第一时钟生成器和所述第二时钟生成器均为陶瓷振荡器。
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Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117348686B (zh) * 2023-12-04 2024-04-30 芯海科技(深圳)股份有限公司 时钟信号温漂修正方法、电路、芯片及电子设备

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101093403A (zh) * 2006-06-22 2007-12-26 国际商业机器公司 减小时钟电路和时钟管理电路中的电磁干扰的方法
US20120072631A1 (en) * 2010-09-21 2012-03-22 Kai Chirca Multilayer Arbitration for Access to Multiple Destinations
CN102801174A (zh) * 2012-08-31 2012-11-28 长沙威胜能源产业技术有限公司 用于低压动态无功谐波综合补偿装置的主控模块
US20160357889A1 (en) * 2015-06-04 2016-12-08 Synopsys, Inc. Simulation modeling frameworks for controller designs
CN106341219A (zh) * 2015-12-24 2017-01-18 深圳艾科创新微电子有限公司 一种基于扩频技术的数据同步传输装置

Family Cites Families (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH083772B2 (ja) * 1988-03-08 1996-01-17 富士通株式会社 マイクロコンピュータシステムのクロック信号供給装置
JPH02227698A (ja) * 1989-02-28 1990-09-10 Sharp Corp 時計自動調整装置
JPH08249836A (ja) * 1995-03-08 1996-09-27 Olympus Optical Co Ltd 情報記録再生装置
US5736893A (en) * 1996-01-29 1998-04-07 Hewlett-Packard Company Digital method and apparatus for reducing EMI emissions in digitally-clocked systems
JP3144312B2 (ja) * 1996-08-28 2001-03-12 日本電気株式会社 クロック周期調節方法とその装置
JP2923882B2 (ja) * 1997-03-31 1999-07-26 日本電気株式会社 クロック供給回路を備える半導体集積回路
US6956918B2 (en) * 2001-06-27 2005-10-18 Intel Corporation Method for bi-directional data synchronization between different clock frequencies
JP2004110718A (ja) * 2002-09-20 2004-04-08 Matsushita Electric Ind Co Ltd 半導体集積回路装置のリセット方法及び半導体集積回路装置
US6954869B2 (en) 2002-09-26 2005-10-11 Analog Devices, Inc. Methods and apparatus for clock domain conversion in digital processing systems
JP4175096B2 (ja) * 2002-11-22 2008-11-05 日本電気株式会社 クロック制御方式及び方法
US7242223B1 (en) * 2003-03-10 2007-07-10 National Semiconductor Corporation Clock frequency monitor
US20040225977A1 (en) * 2003-05-08 2004-11-11 Ryan Akkerman System and method for simulating clock drift between asynchronous clock domains
KR101108397B1 (ko) 2005-06-10 2012-01-30 엘지전자 주식회사 멀티-코어 프로세서의 전원 제어 장치 및 방법
US7720108B2 (en) * 2005-09-27 2010-05-18 Rohde & Schwarz Gmbh & Co. Kg Apparatus and method for inserting synchronization headers into serial data communication streams
JP2007193658A (ja) * 2006-01-20 2007-08-02 Sharp Corp 半導体装置
JP2008017322A (ja) * 2006-07-07 2008-01-24 Sharp Corp 携帯電話機
JP2008148274A (ja) * 2006-11-14 2008-06-26 Renesas Technology Corp Rf通信用半導体集積回路
JP2010034662A (ja) * 2008-07-25 2010-02-12 Shimadzu Corp 撮像装置
WO2010050097A1 (ja) * 2008-10-29 2010-05-06 日本電気株式会社 クロック分周回路、クロック分配回路、クロック分周方法及びクロック分配方法
JP5363143B2 (ja) * 2009-03-02 2013-12-11 オリンパス株式会社 データ通信システム及び受信装置
US8706073B2 (en) 2009-06-16 2014-04-22 Blackberry Limited System and method for dynamic adjustment of clock calibration
WO2011014178A1 (en) 2009-07-31 2011-02-03 Hewlett-Packard Development Company, L.P. Providing fault-tolerant spread spectrum clock signals in a system
DE102012204084A1 (de) * 2011-12-23 2013-06-27 Rohde & Schwarz Gmbh & Co. Kg Verfahren und System zur Optimierung einer Kurzzeitstabilität eines Taktes
US9048851B2 (en) * 2013-03-15 2015-06-02 Intel Corporation Spread-spectrum apparatus for voltage regulator
US20160239649A1 (en) * 2015-02-13 2016-08-18 Qualcomm Incorporated Continuous authentication
US9639225B2 (en) * 2015-09-18 2017-05-02 Motorola Solutions, Inc. Method and apparatus for detecting a touch on a device
CN106992770B (zh) * 2016-01-21 2021-03-30 华为技术有限公司 时钟电路及其传输时钟信号的方法
JP7006435B2 (ja) * 2018-03-26 2022-01-24 株式会社デンソーウェーブ 入出力装置
US10992301B1 (en) * 2020-01-09 2021-04-27 Microsemi Semiconductor Ulc Circuit and method for generating temperature-stable clocks using ordinary oscillators

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101093403A (zh) * 2006-06-22 2007-12-26 国际商业机器公司 减小时钟电路和时钟管理电路中的电磁干扰的方法
US20120072631A1 (en) * 2010-09-21 2012-03-22 Kai Chirca Multilayer Arbitration for Access to Multiple Destinations
CN102801174A (zh) * 2012-08-31 2012-11-28 长沙威胜能源产业技术有限公司 用于低压动态无功谐波综合补偿装置的主控模块
US20160357889A1 (en) * 2015-06-04 2016-12-08 Synopsys, Inc. Simulation modeling frameworks for controller designs
CN106341219A (zh) * 2015-12-24 2017-01-18 深圳艾科创新微电子有限公司 一种基于扩频技术的数据同步传输装置

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