WO2018161397A1 - Tft阵列基板及液晶显示面板 - Google Patents

Tft阵列基板及液晶显示面板 Download PDF

Info

Publication number
WO2018161397A1
WO2018161397A1 PCT/CN2017/079702 CN2017079702W WO2018161397A1 WO 2018161397 A1 WO2018161397 A1 WO 2018161397A1 CN 2017079702 W CN2017079702 W CN 2017079702W WO 2018161397 A1 WO2018161397 A1 WO 2018161397A1
Authority
WO
WIPO (PCT)
Prior art keywords
doped region
gate
lightly doped
array substrate
polysilicon layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2017/079702
Other languages
English (en)
French (fr)
Inventor
陈成
马亮
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wuhan China Star Optoelectronics Technology Co Ltd
Original Assignee
Wuhan China Star Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wuhan China Star Optoelectronics Technology Co Ltd filed Critical Wuhan China Star Optoelectronics Technology Co Ltd
Priority to US15/535,656 priority Critical patent/US20180364503A1/en
Publication of WO2018161397A1 publication Critical patent/WO2018161397A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0314—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral top-gate TFTs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • H10D30/6715—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes characterised by the doping profiles, e.g. having lightly-doped source or drain extensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6731—Top-gate only TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6733—Multi-gate TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6745—Polycrystalline or microcrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/40—Arrangements for improving the aperture ratio
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
    • G02F2202/10—Materials and properties semiconductor
    • G02F2202/104—Materials and properties semiconductor poly-Si

Definitions

  • the present invention relates to the field of touch screen technologies, and in particular, to a TFT array substrate and a liquid crystal display panel.
  • the Thin Film Transistor (TFT) of the liquid crystal display has a leakage phenomenon in the doped region in the off state, causing a voltage difference between the pixel electrode and the common electrode to change.
  • TFT Thin Film Transistor
  • the gray scale of the pixel changes, resulting in string power, etc.
  • Adverse reactions reduce the optical quality of the LCD screen.
  • it mainly improves from the following two aspects: 1. Increase the pixel storage capacitance; 2. Reduce the leakage current of the thin film transistor. The reduction of the thin film transistor leakage current is achieved by increasing the channel region length or the number of channels of the TFT, but this reduces the pixel aperture ratio.
  • the present invention provides a TFT array substrate that reduces leakage current of a thin film transistor without affecting pixel aperture ratio.
  • the application also provides a liquid crystal display panel.
  • the TFT array substrate of the present application includes a substrate and a TFT switch formed on the substrate, the TFT switch includes a polysilicon layer, a gate, a first lightly doped region, and a heavily doped region, and the polysilicon layer includes two opposite And an extension of the body connecting the ends of the two extensions, the gate being disposed across the two extensions, the heavily doped region being formed in the body segment of the polysilicon layer and located at the gate On one side, the first lightly doped region is formed at a central portion of the heavily doped region.
  • the polysilicon layer is further provided with an auxiliary heavily doped region on the other side of the gate.
  • the first lightly doped region is formed by the second doping of the heavily doped region.
  • the TFT switch includes a second lightly doped region, and the second lightly doped region is located between the two sides of the gate and the heavily doped region and the auxiliary heavily doped region.
  • the first lightly doped region and the second lightly doped region are formed in the same process step.
  • the present invention provides a liquid crystal display panel, comprising a color filter substrate, a TFT array substrate, and a liquid crystal layer between the color filter substrate and the TFT array substrate, wherein the TFT array substrate includes a substrate and a TFT switch formed on the substrate.
  • the TFT switch includes a polysilicon layer, a gate, a first lightly doped region, and a heavily doped region, and the polysilicon layer includes two opposite extensions and a body segment connecting the ends of the two extensions, the gate is horizontal Provided across two extensions, the heavily doped region is formed on a body segment of the polysilicon layer and on a side of the gate, and the first lightly doped region is formed in a middle of the heavily doped region position.
  • the polysilicon layer is further provided with an auxiliary heavily doped region on the other side of the gate.
  • the first lightly doped region is formed by the second doping of the heavily doped region.
  • the TFT switch includes a second lightly doped region, and the second lightly doped region is located between the two sides of the gate and the heavily doped region and the auxiliary heavily doped region.
  • the first lightly doped region and the second lightly doped region are formed in the same process step.
  • the TFT switch described in the present application sets a lightly doped region in the heavily doped region without affecting the aperture ratio of the array substrate and the process process, thereby effectively reducing the leakage current of the TFT switch without affecting the aperture ratio.
  • FIG. 1 is a schematic structural view of a liquid crystal display panel of the present invention
  • FIG. 2 is a plan view of the TFT array substrate shown in FIG. 1.
  • the present invention provides a TFT array substrate and a liquid crystal display panel.
  • the liquid crystal display panel includes a color filter substrate 20, the TFT array substrate 10, and the color filter substrate 20 and the TFT array substrate 10.
  • the liquid crystal layer 30 is interposed.
  • the liquid crystal display panel includes a plurality of pixels and a TFT switch disposed on the TFT array substrate corresponding to the pixel.
  • the TFT switch 101 supplies power to the pixel corresponding to the pixel area.
  • the TFT array substrate 10 includes a substrate 11 and a plurality of TFT switches 101 formed on the substrate.
  • the TFT switch 101 includes a polysilicon layer 12, a gate electrode 13, a first lightly doped region 14, and a heavily doped region 15.
  • the polysilicon layer 12 and the gate electrode 13 are spaced apart by an insulating layer.
  • the polysilicon layer 12 includes two opposite extensions 121 and a body segment 122 connecting the ends of the two extensions 121.
  • the gate 13 is disposed across the two extensions 121.
  • the heavily doped region 15 Formed on the body segment 122 of the polysilicon layer 12 and on the side of the gate electrode 13, the first lightly doped region 14 is formed at a central portion of the heavily doped region 15.
  • the polysilicon layer 12 has a U-shaped structure.
  • the first lightly doped region 14 is subjected to a second doping formation for the heavily doped region 15.
  • the resistance of the heavily doped region 15 becomes the key to controlling the leakage current. Since the first lightly doped region 14 is disposed on the heavily doped region 15, the resistance of the TFT switch is increased. In turn, leakage current can be reduced.
  • the length of the first lightly doped region 14 can be adjusted according to the pixel switching pixel charging and leakage conditions to effectively reduce the leakage current under the premise of satisfying the charging requirement.
  • the gate 13 spans the two extensions 121 and covers a portion of the extension 121.
  • the region where the gate electrode 13 overlaps the extension portion 121 constitutes a channel region.
  • the TFT switch 101 is also provided with an auxiliary heavily doped region 16.
  • the heavily doped region 15 and the auxiliary heavily doped region 16 are located on opposite sides of the gate 13 and are spaced apart from the gate 13 .
  • the heavily doped region 15 is formed in the same process step as the auxiliary heavily doped region 16.
  • the TFT switch 101 further includes a second lightly doped region 17, the second lightly doped region 17 is located at an interval between the gate 13 and the heavily doped region 15, and the gate 13 and the auxiliary The spacing between the heavily doped regions 16 is.
  • the first lightly doped region 14 is formed in the same process step as the second lightly doped region 17.
  • the TFT switch described in the present application is heavy on the premise of not affecting the aperture ratio of the array substrate and the process of the process.
  • a lightly doped region is disposed in the doped region to effectively reduce the leakage current of the TFT switch, and at the same time meet the pixel switching pixel charging requirements.

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种TFT阵列基板（10），其包括基板（11）及形成于基板（11）上的TFT开关（101），TFT开关（101）包括多晶硅层（12）、栅极（13）、第一轻掺杂区（14）及重掺杂区（15），多晶硅层（12）包括两个相对的延伸段（121）及连接两个延伸段（121）端部的主体段（122），栅极（13）横跨两个延伸段（121）设置，重掺杂区（15）形成于多晶硅层（12）的主体段（122）并位于栅极（13）一侧，第一轻掺杂区（14）形成于重掺杂区（15）中部位置。

Description

TFT阵列基板及液晶显示面板
本发明要求2017年3月8日递交的发明名称为“TFT阵列基板及液晶显示面板”的申请号2017101368067的在先申请优先权，上述在先申请的内容以引入的方式并入本文本中。
技术领域
本发明涉及触摸屏技术领域，尤其涉及一种TFT阵列基板及液晶显示面板。
背景技术
液晶显示屏的薄膜晶体管(Thin Film Transistor，TFT)在关闭状态下掺杂区存在漏电现象，引起像素电极与公共电极之间电压差变化，漏电严重时会导致像素灰阶变化，产生串电等不良反应，使液晶屏幕的光学品质下降。目前主要从以下两方面来改善，1.增大像素储存电容；2.降低薄膜晶体管漏电流。其中降低薄膜晶体管漏电流一是通过增加TFT的沟道区长度或沟道数，但这样会降低像素开口率。
发明内容
本发明提供一种不影响像素开口率而降低薄膜晶体管开关漏电流的TFT阵列基板。
本申请还提供一种液晶显示面板。
本申请所述的TFT阵列基板包括基板及形成于基板上的TFT开关，所述TFT开关包括多晶硅层、栅极、第一轻掺杂区及重掺杂区，所述多晶硅层包括两个相对的延伸段及连接两个延伸段端部的主体段，所述栅极横跨两个所述延伸段设置，所述重掺杂区形成于所述多晶硅层的主体段并位于所述栅极一侧，所述第一轻掺杂区形成于所述重掺杂区中部位置。
其中，所述多晶硅层上位于所述栅极另一侧还设有辅助重掺杂区。
其中，所述第一轻掺杂区为所述重掺杂区进行第二次掺杂形成。
其中，所述TFT开关包括第二轻掺杂区，所述第二轻掺杂区位于所述栅极两侧与所述重掺杂区及辅助重掺杂区之间。
其中，所述第一轻掺杂区与第二轻掺杂区同一工艺步骤形成。
本申请提供一种液晶显示面板，包括彩膜基板、TFT阵列基板及位于彩膜基板与TFT阵列基板之间的液晶层，所述TFT阵列基板，包括基板即形成与基板上的TFT开关，所述TFT开关包括多晶硅层、栅极、第一轻掺杂区及重掺杂区，所述多晶硅层包括两个相对的延伸段及连接两个延伸段端部的主体段，所述栅极横跨两个所述延伸段设置，所述重掺杂区形成于所述多晶硅层的主体段并位于所述栅极一侧，所述第一轻掺杂区形成于所述重掺杂区中部位置。
其中，所述多晶硅层上位于所述栅极另一侧还设有辅助重掺杂区。
其中，所述第一轻掺杂区为所述重掺杂区进行第二次掺杂形成。
其中，所述TFT开关包括第二轻掺杂区，所述第二轻掺杂区位于所述栅极两侧与所述重掺杂区及辅助重掺杂区之间。
其中，所述第一轻掺杂区与第二轻掺杂区同一工艺步骤形成。
本申请所述的TFT开关在不影响阵列基板开口率及工艺制程的前提在重掺杂区内设置轻掺杂区，有效地降低TFT开关漏电流，且不影响开口率。
附图说明
为更清楚地阐述本发明的构造特征和功效，下面结合附图与具体实施例来对其进行详细说明。
图1是本发明液晶显示面板结构示意图；
图2是图1所示的TFT阵列基板的俯视图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述。其中，附图仅用于示例性说明，表示的仅是示意图，不能理解为对本专利的限制。
请参阅图1与图2，本发明提供一种TFT阵列基板及液晶显示面板，其中，液晶显示面板包括彩膜基板20、所述TFT阵列基板10及位于彩膜基板20与TFT阵列基板10之间的液晶层30。所述液晶显示面板包括多个像素及与像素对应的设于TFT阵列基板上的TFT开关。所述TFT开关101与像素区域对应为像素提供电能。
请参阅图2，本实施例中，所述TFT阵列基板10包括基板11及形成于基板上的数个TFT开关101。本实施例以一个TFT开关为例进行说明。所述TFT开关101包括多晶硅层12、栅极13、第一轻掺杂区14及重掺杂区15。多晶硅层12与栅极13之间通过绝缘层间隔设置。所述多晶硅层12包括两个相对的延伸段121及连接两个延伸段121端部的主体段122，所述栅极13横跨两个所述延伸段121设置，所述重掺杂区15形成于所述多晶硅层12的主体段122并位于所述栅极13一侧，所述第一轻掺杂区14形成于所述重掺杂区15中部位置。
本实施例中，所述多晶硅层12呈U型结构。所述重掺杂区15形成后，所述第一轻掺杂区14为所述重掺杂区15进行第二次掺杂形成。当所述TFT开关101关闭状态下，重掺杂区15区域的电阻成为控制漏电流的关键，由于重掺杂区15上设置有第一轻掺杂区14，增大了TFT开关的电阻，进而可以降低漏电流。而且在制造过程中，第一轻掺杂区14的长度可以根据TFT开关像素充电和漏电情况进行调整，以在满足充电要求的前提下有效降低漏电流。
所述栅极13横跨两个所述延伸段121并覆盖部分所述延伸段121。栅极13与所述延伸段121重叠区域构成沟道区。所述TFT开关101还设有辅助重掺杂区16。所述重掺杂区15与辅助重掺杂区16位于所述栅极13相对两侧，并均与所述栅极13间隔设置。所述重掺杂区15与辅助重掺杂区16在同一工艺步骤形成。
所述TFT开关101还包括第二轻掺杂区17，所述第二轻掺杂区17位于所述栅极13与所述重掺杂区15之间的间隔位置，以及栅极13与辅助重掺杂区16之间的间隔位置。所述第一轻掺杂区14与第二轻掺杂区17同一工艺步骤形成。
本申请所述的TFT开关在不影响阵列基板开口率及工艺制程的前提在重 掺杂区内设置轻掺杂区，有效地降低TFT开关漏电流，同时能够满足TFT开关像素充电要求。
以上所述是本发明的优选实施例，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也视为本发明的保护范围。

Claims (12)

  1. 一种TFT阵列基板，包括基板及形成于基板上的TFT开关，其中，所述TFT开关包括多晶硅层、栅极、第一轻掺杂区及重掺杂区，所述多晶硅层包括两个相对的延伸段及连接两个延伸段端部的主体段，所述栅极横跨两个所述延伸段设置，所述重掺杂区形成于所述多晶硅层的主体段并位于所述栅极一侧，所述第一轻掺杂区形成于所述重掺杂区中部位置。
  2. 如权利要求1所述的TFT阵列基板，其中，所述多晶硅层上位于所述栅极另一侧还设有辅助重掺杂区。
  3. 如权利要求2所述的TFT阵列基板，其中，所述第一轻掺杂区为所述重掺杂区进行第二次掺杂形成。
  4. 如权利要求3所述的TFT阵列基板，其中，所述TFT开关包括第二轻掺杂区，所述第二轻掺杂区位于所述栅极两侧与所述重掺杂区及辅助重掺杂区之间。
  5. 如权利要求4所述的TFT阵列基板，其中，所述第一轻掺杂区与第二轻掺杂区同一工艺步骤形成。
  6. 如权利要求1所述的TFT阵列基板，其中，所述栅极及多晶硅层形成于所述基板并通过绝缘层间隔。
  7. 一种液晶显示面板，包括彩膜基板、TFT阵列基板及位于彩膜基板与TFT阵列基板之间的液晶层，其中，所述TFT阵列基板，包括基板即形成与基板上的TFT开关，所述TFT开关包括多晶硅层、栅极、第一轻掺杂区及重掺杂区，所述多晶硅层包括两个相对的延伸段及连接两个延伸段端部的主体段，所述栅极横跨两个所述延伸段设置，所述重掺杂区形成于所述多晶硅层的主体段并位于所述栅极一侧，所述第一轻掺杂区形成于所述重掺杂区中部位置。
  8. 如权利要求7所述的液晶显示面板，其中，所述多晶硅层上位于所述栅极另一侧还设有辅助重掺杂区。
  9. 如权利要求8所述的液晶显示面板，其中，所述第一轻掺杂区为所述重掺杂区进行第二次掺杂形成。
  10. 如权利要求8所述的液晶显示面板，其中，所述TFT开关包括第二轻掺杂区，所述第二轻掺杂区位于所述栅极两侧与所述重掺杂区及辅助重掺杂区之间。
  11. 如权利要求10所述的液晶显示面板，其中，所述第一轻掺杂区与第二轻掺杂区同一工艺步骤形成。
  12. 如权利要求7所述的液晶显示面板，其中，所述栅极及多晶硅层形成于所述基板并通过绝缘层间隔。
PCT/CN2017/079702 2017-03-08 2017-04-07 Tft阵列基板及液晶显示面板 Ceased WO2018161397A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US15/535,656 US20180364503A1 (en) 2017-03-08 2017-04-07 Tft array substrate and liquid crystal display panel

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201710136806.7 2017-03-08
CN201710136806.7A CN106816446A (zh) 2017-03-08 2017-03-08 Tft阵列基板及液晶显示面板

Publications (1)

Publication Number Publication Date
WO2018161397A1 true WO2018161397A1 (zh) 2018-09-13

Family

ID=59115611

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/079702 Ceased WO2018161397A1 (zh) 2017-03-08 2017-04-07 Tft阵列基板及液晶显示面板

Country Status (3)

Country Link
US (1) US20180364503A1 (zh)
CN (1) CN106816446A (zh)
WO (1) WO2018161397A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109742088B (zh) * 2018-12-29 2021-03-16 武汉华星光电技术有限公司 一种tft阵列基板

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08279620A (ja) * 1995-04-07 1996-10-22 Fuji Xerox Co Ltd 薄膜トランジスタの製造方法
US20140070225A1 (en) * 2012-09-07 2014-03-13 Apple Inc. Hydrogenation and Crystallization of Polycrystalline Silicon
CN204204858U (zh) * 2014-11-14 2015-03-11 厦门天马微电子有限公司 一种阵列基板和显示面板
CN105097675A (zh) * 2015-09-22 2015-11-25 深圳市华星光电技术有限公司 阵列基板及其制备方法
CN105977307A (zh) * 2016-06-30 2016-09-28 上海中航光电子有限公司 薄膜晶体管、显示面板及显示装置
CN205657056U (zh) * 2016-04-19 2016-10-19 厦门天马微电子有限公司 阵列基板与显示装置

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101304047B (zh) * 2008-07-07 2015-03-11 友达光电股份有限公司 薄膜晶体管
US8704232B2 (en) * 2012-06-12 2014-04-22 Apple Inc. Thin film transistor with increased doping regions

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08279620A (ja) * 1995-04-07 1996-10-22 Fuji Xerox Co Ltd 薄膜トランジスタの製造方法
US20140070225A1 (en) * 2012-09-07 2014-03-13 Apple Inc. Hydrogenation and Crystallization of Polycrystalline Silicon
CN204204858U (zh) * 2014-11-14 2015-03-11 厦门天马微电子有限公司 一种阵列基板和显示面板
CN105097675A (zh) * 2015-09-22 2015-11-25 深圳市华星光电技术有限公司 阵列基板及其制备方法
CN205657056U (zh) * 2016-04-19 2016-10-19 厦门天马微电子有限公司 阵列基板与显示装置
CN105977307A (zh) * 2016-06-30 2016-09-28 上海中航光电子有限公司 薄膜晶体管、显示面板及显示装置

Also Published As

Publication number Publication date
CN106816446A (zh) 2017-06-09
US20180364503A1 (en) 2018-12-20

Similar Documents

Publication Publication Date Title
US10324348B2 (en) Array substrate, liquid crystal display panel and liquid crystal display device
US10120249B2 (en) Array substrate, liquid crystal display panel and liquid crystal display device
TWI448796B (zh) 畫素結構、主動元件陣列基板以及平面顯示面板
US20240393650A1 (en) Electronic device
US10197870B2 (en) Array substrate and display device
WO2021073253A1 (zh) 薄膜晶体管及其制作方法、阵列基板和显示装置
US7268839B2 (en) Array substrate comprising an island shaped drain electrode enclosed by the source electrode and liquid crystal display device including the same
US20210333608A1 (en) Array substrate and manufacturing method thereof, display device
US10216058B2 (en) Display devices and the display panels thereof
US20170139247A1 (en) Thin Film Transistor Array Substrate, Manufacturing for the Same, and Liquid Crystal Display Panel Having the Same
US9778523B2 (en) Array substrate, liquid crystal display panel and liquid crystal display device
JP6433169B2 (ja) 薄膜半導体装置
JP2016009719A5 (zh)
CN102338955B (zh) 薄膜晶体管像素单元
KR102129500B1 (ko) 액정표시패널
CN104122721B (zh) 像素结构
WO2018161397A1 (zh) Tft阵列基板及液晶显示面板
US6906760B2 (en) Array substrate for a liquid crystal display and method for fabricating thereof
WO2017143660A1 (zh) 阵列基板、显示面板以及液晶显示装置
KR20160116189A (ko) 색필터 표시판 및 이를 포함하는 액정 표시 장치
US6590628B2 (en) Liquid crystal display device with orientation control window
CN202167491U (zh) Tft像素单元
CN115084167A (zh) 一种显示面板

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17900132

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 17900132

Country of ref document: EP

Kind code of ref document: A1