WO2018155284A1 - 駆動回路、ｔｆｔ基板、表示装置 - Google Patents

駆動回路、ｔｆｔ基板、表示装置 Download PDF

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Publication number
WO2018155284A1
WO2018155284A1 PCT/JP2018/005097 JP2018005097W WO2018155284A1 WO 2018155284 A1 WO2018155284 A1 WO 2018155284A1 JP 2018005097 W JP2018005097 W JP 2018005097W WO 2018155284 A1 WO2018155284 A1 WO 2018155284A1
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Prior art keywords
conductive film
conductive
drive circuit
film
circuit according
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PCT/JP2018/005097
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English (en)
French (fr)
Inventor
智 堀内
芳啓 浅井
小笠原　功
冨永　真克
義仁 原
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シャープ株式会社
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Priority to CN201880013127.3A priority Critical patent/CN110326113B/zh
Priority to US16/486,840 priority patent/US11374037B2/en
Publication of WO2018155284A1 publication Critical patent/WO2018155284A1/ja

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13454—Drivers integrated on the active matrix substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
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    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
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    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
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    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
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    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
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    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
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    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors

Definitions

  • the present invention relates to a drive circuit (driver) provided in a display device.
  • Patent Document 1 in a drive circuit including a TFT (thin film transistor) formed on a substrate and a capacitor connected to the TFT, a metal of a source layer on which the source of the TFT is formed and an upper layer than the source layer.
  • TFT thin film transistor
  • a driving circuit in which a transistor including a gate electrode, a semiconductor film, and first and second conductive electrodes is formed above the substrate, the first conductive film formed below the gate electrode;
  • the driving circuit includes a second conductive film functioning as the gate electrode, and a first capacitor is formed between the first conductive film and the second conductive film.
  • the circuit scale can be reduced while maintaining the characteristics of the drive circuit.
  • FIG. 1 shows a configuration of a display device according to the present embodiment, where (a) is a schematic cross-sectional view showing an overall configuration, (b) is a schematic plan view showing the overall configuration, and (c) shows a pixel circuit of a display unit.
  • It is a circuit diagram. 2A and 2B are diagrams illustrating a gate driver according to a first embodiment, in which FIG. 1A is a circuit diagram of each stage, and FIG. FIGS. 2A and 2B show a portion in which a bootstrap circuit is configured in the gate driver of Embodiment 1;
  • FIG. 3A is a plan view and FIG. FIGS. 2A and 2B show a portion where a bootstrap circuit is formed in a gate driver of a comparative form, where FIG.
  • FIG. 2A is a plan view and FIG. 3 is a schematic diagram showing one of the merits of Embodiment 1.
  • FIG. The structure of the display apparatus concerning this embodiment is shown, (a) is a plane schematic diagram which shows the whole structure, (b) is a plane schematic diagram which shows the structural example of a non-display part.
  • FIG. 10 is a plan view showing a portion where a bootstrap circuit is configured in the gate driver of the second embodiment. 10 is a plan view showing a modification of the second embodiment.
  • FIG. 10 is a plan view showing a portion where a bootstrap circuit is configured in the gate driver of the second embodiment.
  • 10 is a plan view showing a modification of the second embodiment.
  • FIG. FIG. 12 is a plan view showing a further modification of the second embodiment.
  • 6 is a plan view showing a configuration of Embod
  • FIG. 1A and 1B show a configuration of a display device according to the present embodiment.
  • FIG. 1A is a schematic cross-sectional view showing the overall configuration
  • FIG. 1B is a schematic plan view showing the overall configuration
  • FIG. It is a circuit diagram which shows a circuit.
  • a display device 10 includes a backlight (not shown), a TFT substrate 3 including a substrate 2, a liquid crystal layer 4, a color filter substrate 5, and an optical film 6.
  • the display unit 3p of the TFT substrate 3 includes a pixel electrode 11, a transistor 12, a data signal line 15 and a scanning signal line 16.
  • the pixel electrode 11 is connected to the data signal line 15 and the data signal line 15 via the transistor 12.
  • a common electrode (not shown) may be provided on the TFT substrate 3 to adopt an FFS (Fringe-Field-Switching) method.
  • an in-cell touch sensor can also be comprised using this common electrode.
  • the non-display portion (inactive portion) 3q of the TFT substrate 3 is provided with a gate driver (drive circuit) 20 that drives the scanning signal line 16 and an IC chip 9 that includes a source driver that drives the data signal line 15. .
  • the gate driver 20 and the pixel circuit 3g are formed monolithically on the same substrate 2.
  • FIG. 2 illustrates a gate driver, where (a) is a circuit diagram of each stage, and (b) is a signal timing chart relating to each stage.
  • the n-th stage circuit 20n of the gate driver 20 includes transistors TRa to TRd, and includes a bootstrap circuit 20b including a transistor TRc and a bootstrap capacitor Cb.
  • the gate electrode and the drain electrode of the transistor TRc are connected via the bootstrap capacitor Cb, and the output terminal Po of the n-th stage circuit 20n is connected to the drain electrode of the transistor TRc.
  • the nth stage circuit 20n operates as follows. That is, in the period T1, the (n ⁇ 1) stage gate signal GL (n ⁇ 1) is input to TRa, and the internal node (netA) is precharged. At this time, TRc and TRd are turned on. However, since CKA is at the low potential (VSS), the gate line GL (n) is charged with the low potential (VSS). Next, in a period T2, the clock signal CKA is switched to a high potential (VDD) and the clock signal CKB is switched to a low potential (VSS). At this time, since TRc is on and TRd is off, the gate line GL (n) is charged with the high potential (VDD) of the clock signal CKA.
  • the internal node (netA) As GL (n) is charged, the internal node (netA) is pushed up to a higher potential via the capacitor Cb, and a high enough voltage is applied to the gate electrode of TRc to charge the gate line to the high potential (VDD). Can be applied.
  • the GL (n) signal is input to the (n + 1) stage gate driver, and its internal node is precharged.
  • the clock signal CKA is switched to a low potential (VSS), and the CKB is switched to a high potential (VDD).
  • VDD high potential
  • FIGS. 3A and 3B show a portion where the bootstrap circuit is configured in the gate driver of the first embodiment.
  • FIG. 3A is a plan view and
  • FIG. 3B is a cross-sectional view including a channel of a transistor.
  • the bootstrap circuit 20b of the gate driver includes a first conductive film 21, an extended wiring EW extending from the first conductive film 21, and an insulating film formed above the first conductive film 21 on the upper side of the substrate 2.
  • Z1 for example, an inorganic insulating film such as a silicon nitride film or a silicon oxide film
  • a second conductive film 22 formed above the insulating film Z1
  • an insulating film Z2 formed above the second conductive film 22
  • a gate insulating film for example, an inorganic insulating film such as a silicon nitride film or a silicon oxide film
  • a semiconductor film HF formed above the insulating film Z2
  • a sub-source electrode formed above the semiconductor film HF Sa / Sb sub-drain electrodes Da to Dc
  • a third conductive film 23 connected to the sub-drain electrode Dc
  • a lead-out wiring DW connected to the sub-drain electrodes Da to Dc.
  • the semiconductor film HF is, for example, an oxide semiconductor film, and may include at least one metal element of In, Ga, and Zn.
  • the semiconductor film HF of Embodiment 1 includes, for example, an In—Ga—Zn—O-based semiconductor.
  • the second conductive film 22 functioning as a gate electrode, the semiconductor film HF, the source electrode S composed of the sub-source electrodes Sa and Sb, and the drain electrode D composed of the sub-drain electrodes Da to Dc are used as a bottom gate type.
  • a transistor TRc (see FIG. 2) is configured.
  • the sub-source electrodes Sa and Sb and the sub-drain electrodes Da to Dc extend in the column direction (the extending direction of the data signal line), and the first channel (in the row direction) below the gap between the sub-source electrode Sa and the sub-drain electrode Da. Is formed, a second channel (row direction) is formed under the gap between the sub-source electrode Sa and the sub-drain electrode Db, and a third channel (row direction) is formed under the gap between the sub-source electrode Sb and the sub-drain electrode Db. And a fourth channel (in the row direction) is formed under the gap between the sub-source electrode Sb and the sub-drain electrode Dc.
  • the lead wiring DW and the extended wiring EW extend in the row direction (extending direction of the scanning signal line).
  • the first conductive film 21 and the second conductive film 22 overlap with each other via the insulating film Z1, and the first capacitor C1 is formed between the first and second conductive films 21 and 22. Further, the second conductive film 22 and the third conductive film 23 overlap with each other via the insulating film Z2, and a second capacitor C2 is formed between the second and third conductive films 22 and 23.
  • the entire first conductive film 21 overlaps with the second conductive film 22
  • the entire semiconductor film HF overlaps with the first conductive film 21, and the area of the first conductive film 21 is larger than the overlapping area with the semiconductor film HF.
  • the entire semiconductor film HF overlaps with the second conductive film 22, and the second conductive film 22 includes an extension region 22K that overlaps with the first and third conductive films 21 and 23 but does not overlap with the semiconductor film HF. It is out.
  • an output pad Po formed in the same layer (gate layer) as the second conductive film 22 is provided, and the lead-out wiring DW connected to the sub-drain electrodes Da to Dc and the output pad Po are connected via the first contact hole CHx.
  • the extended wiring EW that is connected and extends from the first conductive film 21 and the output pad Po are connected via the second contact hole CHy.
  • the first conductive film 21 and the third conductive film 23 are electrically connected. It can also be said that the first conductive film 21 and the drain electrode D are electrically connected.
  • the first conductive film 21 and the third conductive film 23 are electrically connected, they are formed between the first and second conductive films 21 and 22.
  • the capacitor C1 and the capacitor C2 are connected in parallel.
  • the areas of the second conductive film 22 and the third conductive film 23 are reduced without changing the capacitance value of the bootstrap capacitor Cb, as compared with the comparative example of FIG. 4 (a configuration in which the first conductive film 21 is not provided). Therefore, the circuit scale of the gate driver 20 can be reduced.
  • the bootstrap capacitor Cb is formed by the capacitance formed between the extended region 22K of the second conductive film 22 (the region not overlapping with the semiconductor film HF) and the first and third conductive films 21 and 23, respectively. The capacity value is increased.
  • the electric field caused by the first conductive film 21 can be shielded, and adverse effects on the channel can be prevented.
  • the characteristics of the first to fourth channels are made uniform.
  • the circuit area can be reduced as compared with the case where the contact holes are provided apart from each other. .
  • the edge of the insulating film Z1 covering the first conductive film 21 is configured not to overlap with the intermediate conductor formed in the gate layer. That is, as shown in FIGS. 3 and 5A, the output pad Po (middle layer conductor) does not overlap the edge of the insulating film Z1, and the lead-out wiring DW (upper layer conductor) of the drain electrode D is formed on the insulating film Z1.
  • the lead-out wiring DW (upper layer conductor) which is configured to straddle the edge and led out to the absent portion of the insulating film Z1, is formed in the absence region of the insulating film Z1, as shown in FIG.
  • the second conductive film 22 is connected (reconnected) to the scanning signal line 16 (corresponding to GL (n) in FIG. 2) in the same layer (gate layer) as the conductive film 22 via the contact hole CHd. Thereby, the electrical connection between the output pad Po and the scanning signal line 16 of the display unit is secured. If the output pad Po (intermediate layer conductor) is configured to straddle the edge of the insulating film Z1, for example, the output pad Po (intermediate layer conductor) is extended and connected to the scanning signal line, FIG. As shown in (b), the output pad Po may be disconnected near the edge of the insulating film Z1, and the electrical connection with the scanning signal line may be impaired.
  • the insulating film Z1 between the first and second conductive films 21 and 22 is locally formed only in the non-display region. Specifically, the area of Z1 is Since it is less than 20% of the substrate area, there is no possibility that the TFT substrate 3 is warped.
  • a lower layer conductor Fa1 is formed below the gate electrode of the transistor in the display portion, and an intermediate layer conductor Fb1 is formed in the same layer as the gate electrode of the transistor.
  • Upper layer conductors Ja, Jb, Jc, Fa2, and Fb2 and terminals Ta to Tc and terminals Ta to Tc are formed above the gate electrode, an insulating film Z1 is formed so as to cover the lower layer conductor Fa1, and the middle layer conductor Fb1 is formed.
  • An insulating film Z2 is formed so as to cover it. Terminals Ta to Tc are connected to an IC chip 9 including a source driver.
  • the upper layer conductor Ja (for example, the end of the data signal line) is connected to the lower layer conductor Fa1 (relay wiring) via the contact hole Ha1, and the lower layer conductor Fa1 is connected to the upper layer via the contact hole Ha2. It is connected to the conductor Fa2 (terminal wiring), and the upper layer conductor Fa2 is connected to the terminal Ta.
  • the upper layer conductor Jb (for example, the end of the data signal line) is connected to the middle layer conductor Fb1 (relay wiring) via the contact hole Hb1, and the middle layer conductor Fb1 is connected to the upper layer conductor Fb2 via the contact hole Hb2. It is connected to (terminal wiring), and the upper layer conductor Fb2 is connected to the terminal Tb.
  • the upper layer conductor Jc (for example, the end of the data signal line) is connected to the terminal Tc.
  • each of the lower conductor Fa1 and the middle conductor Fb1 does not overlap the edge of the insulating film Z1, and the upper conductors Ja, Jb, Jc, Fa2, and Fb2 straddle the edge of the insulating film Z1.
  • the reliability of the connection between the data signal line 15 and the IC chip 9 is improved.
  • the middle layer conductor may be disconnected at a portion over the edge.
  • FIG. 7 is a plan view showing a portion where the bootstrap circuit is configured in the gate driver of the second embodiment.
  • the bootstrap circuit 20 b of the gate driver includes a first conductive film 21, an extended wiring EW extending from the upper side of the substrate 2, and an insulating film formed above the first conductive film 21.
  • Z1 for example, an inorganic insulating film such as a silicon nitride film or a silicon oxide film
  • a second conductive film 22 formed above the insulating film Z1
  • an insulating film Z2 formed above the second conductive film 22
  • a gate insulating film for example, an inorganic insulating film such as a silicon nitride film or a silicon oxide film
  • a semiconductor film HF formed above the insulating film Z2
  • the second conductive film 22 functioning as a gate electrode, the semiconductor film HF, the source electrode S composed of the sub-source electrodes Sa and Sb, and the drain electrode D composed of the sub-drain electrodes Da to Dc are used as a bottom gate type.
  • a transistor TRc (see FIG. 2) is configured.
  • the first conductive film 21 and the second conductive film 22 overlap with each other via the insulating film Z1, and the first capacitor C1 is formed between the first and second conductive films 21 and 22.
  • the entire first conductive film 21 overlaps with the second conductive film 22
  • the entire semiconductor film HF overlaps with the first conductive film 21
  • the area of the first conductive film 21 is larger than the overlapping area with the semiconductor film HF.
  • the entire semiconductor film HF overlaps with the second conductive film 22.
  • an output pad Po formed in the same layer (gate layer) as the second conductive film 22 is provided, and the lead-out wiring DW connected to the sub-drain electrodes Da to Dc and the output pad Po are connected via the first contact hole CHx.
  • the extended wiring EW that is connected and extends from the first conductive film 21 and the output pad Po are connected via the second contact hole CHy. Thereby, the first conductive film 21 and the drain electrode D are electrically connected.
  • the circuit area can be reduced as compared with the case where the contact holes are provided apart from each other. .
  • the electric field caused by the first conductive film 21 can be shielded, and adverse effects on the channel can be prevented.
  • the characteristics of the first to fourth channels are made uniform.
  • the edge of the insulating film Z1 covering the first conductive film 21 is configured not to overlap with the intermediate conductor formed in the gate layer. That is, as shown in FIG. 7 and FIG. 5A, the output pad Po (intermediate layer conductor) does not overlap the edge of the insulating film Z1, and the lead-out wiring DW (upper layer conductor) of the drain electrode D is formed on the insulating film Z1. It is configured so as to straddle the edges, thereby ensuring electrical connection between the output pad Po and the scanning signal line of the display unit.
  • the edge of the first conductive film 21 may include a portion that is orthogonal to the channel direction (row direction) of the transistor TRc and overlaps the sub-drain electrode Dc. .
  • the configuration of the structure shown in FIG. 8 can prevent the edge of the first conductive film 21 from crossing the channel.
  • the edge of the first conductive film 21 can be overlapped with four channels.
  • the marking may be formed using the wiring of each layer.
  • the wiring 21m is covered with an insulating film Z1. In this way, it is possible to perform marking even in a small area while preventing a short circuit between the second conductive film 22 and the same wiring layer 22p and the third conductive film 23 and the same wiring layer 23p.
  • the present drive circuit is also suitable for a drive circuit of a self-luminous panel such as an OLED (organic light emitting diode) panel.
  • OLED organic light emitting diode
  • Aspect 1 is a driving circuit in which a transistor including a gate electrode, a semiconductor film, and first and second conductive electrodes is formed above the substrate, and the first circuit is formed below the gate electrode.
  • a conductive film and a second conductive film functioning as the gate electrode are provided, and a first capacitor is formed between the first conductive film and the second conductive film.
  • the first conductive film and the second conductive electrode are electrically connected.
  • the semiconductor film is formed in an upper layer than the second conductive film and in a lower layer than the first and second conductive electrodes.
  • a third conductive film is formed in the same layer as the first and second conductive electrodes and is connected to the second conductive electrode.
  • a second capacitor is formed between the second conductive film and the third conductive film.
  • the entire first conductive film overlaps the second conductive film.
  • the entire semiconductor film overlaps the first conductive film.
  • the entire semiconductor film overlaps the second conductive film.
  • the area of the first conductive film is larger than the overlapping area with the semiconductor film.
  • the second conductive film includes an extension region that overlaps with the first and third conductive films but does not overlap with the semiconductor film.
  • the edge of the first conductive film includes a portion that is orthogonal to the channel direction of the transistor and overlaps the second conductive electrode.
  • an output pad formed in the same layer as the gate electrode and electrically connected to the second conductive electrode is provided.
  • the lead-out wiring led out from the second conductive electrode and the output pad are connected through the first contact hole.
  • the extended wiring extending from the first conductive film and the output pad are connected via the second contact hole.
  • the opening of the second contact hole is formed in the opening of the first contact hole in plan view.
  • the lead-out wiring straddles the edge of the insulating film between the first and second conductive films.
  • a clock signal is supplied to the first conductive electrode.
  • the first capacitor functions as a bootstrap capacitor.
  • the semiconductor film is made of an oxide semiconductor.
  • one of the first and second conductive electrodes is composed of a plurality of parallel sub-source electrodes, and the other is composed of a plurality of parallel sub-drain electrodes.
  • the drive circuit and the pixel circuit are monolithically formed on the same substrate.
  • the scanning signal line driven by the driving circuit is provided.
  • Aspect 23 includes a marking wiring formed in the same layer as the first conductive film.
  • the insulating film between the first and second conductive films is locally formed only in the non-display region.
  • the TFT substrate of aspect 25 includes a transistor, and in a non-active portion, a lower layer conductor formed below the gate electrode of the transistor, a middle layer conductor formed in the same layer as the gate electrode, and the gate An upper layer conductor formed in an upper layer than the electrode and an insulating film covering the lower layer conductor are provided, the middle layer conductor does not overlap an edge of the insulating film, and the upper layer conductor is formed of the insulating film. It is comprised so that an edge may be straddled.
  • the display device according to aspect 26 includes the TFT substrate.
  • the present invention is not limited to the above-described embodiments, and embodiments obtained by appropriately combining technical means disclosed in different embodiments are also included in the technical scope of the present invention. Furthermore, a new technical feature can be formed by combining the technical means disclosed in each embodiment.

Abstract

駆動回路の特性を維持しつつ回路規模を小さくする。基板よりも上側に、ゲート電極と半導体膜（ＨＦ）と第１および第２導通電極（Ｓ・Ｄ）とを含むトランジスタ（ＴＲｃ）が形成されている駆動回路であって、前記ゲート電極よりも下層に形成された第１導電膜（２１）と、前記ゲート電極として機能する第２導電膜（２２）とを備え、前記第１導電膜（２１）と前記第２導電膜（２２）との間に第１容量（Ｃ１）が形成されている。

Description

駆動回路、ＴＦＴ基板、表示装置
　本発明は、表示装置に設けられる駆動回路（ドライバ）に関する。
　特許文献１には、基板上に形成されたＴＦＴ（薄膜トランジスタ）とこのＴＦＴに接続された容量とを含む駆動回路において、前記ＴＦＴのソースが形成されるソース層のメタルとこのソース層よりも上層のメタルとの間で容量を形成する構成が開示されている。
日本国再公表特許「ＷＯ２０１１／１３５８７３号公報（２０１１年１１月３日公開）」
　容量を構成する各電極が占める面積によって回路規模が大きくなるという問題がある。
　基板よりも上側に、ゲート電極と半導体膜と第１および第２導通電極とを含むトランジスタが形成されている駆動回路であって、前記ゲート電極よりも下層に形成された第１導電膜と、前記ゲート電極として機能する第２導電膜とを備え、前記第１導電膜と前記第２導電膜との間に第１容量が形成されている駆動回路とする。
　駆動回路の特性を維持しつつ回路規模を小さくすることができる。
本実施形態にかかる表示装置の構成を示すものであり、（ａ）は全体構成を示す断面模式図、（ｂ）は全体構成を示す平面模式図、（ｃ）は表示部の画素回路を示す回路図である。 実施形態１のゲートドライバを説明するものであり、（ａ）は各段の回路図、（ｂ）は各段に関する信号タイミングチャートである。 実施形態１のゲートドライバにおいてブートストラップ回路が構成される部分を示すものであり、（ａ）は平面図、（ｂ）はトランジスタのチャネルを含む断面図である。 比較形態のゲートドライバにおいてブートストラップ回路が構成される部分を示すものであり、（ａ）は平面図、（ｂ）はトランジスタのチャネルを含む断面図である。 実施形態１のメリットの１つを示す模式図である。 本実施形態にかかる表示装置の構成を示すものであり、（ａ）は全体構成を示す平面模式図、（ｂ）は非表示部の構成例を示す平面模式図である。 実施形態２のゲートドライバにおいてブートストラップ回路が構成される部分を示す平面図である。 実施形態２の変形例を示す平面図である。 実施形態２のさらなる変形例を示す平面図である。 実施形態３の構成を示す平面図である。
　以下に、図１～図１０に基づき、本発明の実施形態を説明する。ただし、これら実施形態は例示に過ぎない。
　図１は本実施形態にかかる表示装置の構成を示すものであり、（ａ）は全体構成を示す断面模式図、（ｂ）は全体構成を示す平面模式図、（ｃ）は表示部の画素回路を示す回路図である。
　図１に示すように、本実施形態にかかる表示装置１０は、バックライト（図示せず）、基板２を含むＴＦＴ基板３、液晶層４、カラーフィルタ基板５、および光学フィルム６を備える。
　ＴＦＴ基板３の表示部３ｐには、画素電極１１、トランジスタ１２、データ信号線１５および走査信号線１６が含まれ、画素回路３ｇでは、画素電極１１は、トランジスタ１２を介してデータ信号線１５および走査信号線１６に接続される。なお、共通電極（図示しない）をＴＦＴ基板３に設けてＦＦＳ（Fringe-Field Switching）方式とすることもできる。また、この共通電極を用いてインセルタッチセンサを構成することもできる。
　ＴＦＴ基板３の非表示部（非アクティブ部）３ｑには、走査信号線１６を駆動するゲートドライバ（駆動回路）２０と、データ信号線１５を駆動するソースドライバを含むＩＣチップ９とが設けられる。ゲートドライバ２０および画素回路３ｇは同一基板２にモノリシックに形成される。
　図２はゲートドライバを説明するものであり、（ａ）は各段の回路図、（ｂ）は各段に関する信号タイミングチャートである。
　図２（ａ）に示すように、ゲートドライバ２０の第ｎ段回路２０ｎは、トランジスタＴＲａ～ＴＲｄを含んで構成され、トランジスタＴＲｃおよびブートストラップ容量Ｃｂを含むブートストラップ回路２０ｂを含む。ブートストラップ回路２０ｂでは、トランジスタＴＲｃのゲート電極およびドレイン電極がブートストラップ容量Ｃｂを介して接続され、第ｎ段回路２０ｎの出力端ＰｏがトランジスタＴＲｃのドレイン電極に接続される。
　第ｎ段回路２０ｎは以下のように動作する。すなわち、期間Ｔ１において、ＴＲａに（ｎ－１）段のゲート信号ＧＬ（ｎ－１）が入力され、内部ノード（ｎｅｔＡ）がプリチャージされる。この時、ＴＲｃおよびＴＲｄはオン状態となるが、ＣＫＡがＬｏｗ電位（ＶＳＳ）であるためゲートラインＧＬ（ｎ）にはＬｏｗ電位（ＶＳＳ）が充電される。次に期間Ｔ２において、クロック信号ＣＫＡがＨｉｇｈ電位（ＶＤＤ）へ、クロック信号ＣＫＢがＬｏｗ電位（ＶＳＳ）に切り替わる。この時、ＴＲｃがオン状態、ＴＲｄがオフ状態であるためゲートラインＧＬ（ｎ）にはクロック信号ＣＫＡのＨｉｇｈ電位（ＶＤＤ）が充電される。ＧＬ（ｎ）が充電されるとともに容量Ｃｂを介して内部ノード（ｎｅｔＡ）がさらに高い電位に突き上げられ、ＴＲｃのゲート電極にはゲートラインをＨｉｇｈ電位（ＶＤＤ）に充電するための十分高い電圧を印加することができる。またこの期間に、ＧＬ（ｎ）の信号が（ｎ＋１）段のゲートドライバに入力され、その内部ノードがプリチャージされる。次に期間Ｔ３において、クロック信号ＣＫＡがＬｏｗ電位（ＶＳＳ）、ＣＫＢがＨｉｇｈ電位（ＶＤＤ）に切り替わる。これによりＴＲｄを介してゲートラインＧＬ（ｎ）はＬｏｗ電位（ＶＳＳ）に放電される。またこの時、（ｎ＋１）段のゲートラインがＨｉｇｈ電位（ＶＤＤ）に充電されるため、ＴＲｂがオン状態となり、内部ノード（ｎｅｔＡ）をＶＳＳ電位に放電することで、ｎ行目のゲートラインの動作を完了する。以降次フレームで再度操作が行われるまで、クロック信号ＣＫＢの動作に合わせ、ゲートラインＧＬ（ｎ）にＴＲｄを介してＶＳＳ電位が入力されＬｏｗ状態を維持する。
　〔実施形態１〕
　図３は、実施形態１のゲートドライバにおいてブートストラップ回路が構成される部分を示すものであり、（ａ）は平面図、（ｂ）はトランジスタのチャネルを含む断面図である。
　図３に示すように、ゲートドライバのブートストラップ回路２０ｂは、基板２の上側に、第１導電膜２１およびこれから延伸する延伸配線ＥＷと、第１導電膜２１よりも上層に形成される絶縁膜Ｚ１（例えば窒化シリコン膜、酸化シリコン膜等の無機絶縁膜）と、絶縁膜Ｚ１よりも上層に形成される第２導電膜２２と、第２導電膜２２よりも上層に形成される絶縁膜Ｚ２（ゲート絶縁膜、例えば窒化シリコン膜、酸化シリコン膜等の無機絶縁膜）と、絶縁膜Ｚ２よりも上層に形成される半導体膜ＨＦと、半導体膜ＨＦよりも上層に形成される、サブソース電極Ｓａ・Ｓｂ、サブドレイン電極Ｄａ～Ｄｃ、サブドレイン電極Ｄｃに接続する第３導電膜２３、並びにサブドレイン電極Ｄａ～Ｄｃに接続する引き出し配線ＤＷとを備える。
　半導体膜ＨＦは、例えば酸化物半導体膜であり、Ｉｎ、Ｇａ及びＺｎのうち少なくとも１種の金属元素を含んでもよい。実施形態１の半導体膜ＨＦは、例えば、Ｉｎ－Ｇａ－Ｚｎ－Ｏ系の半導体を含む。ここで、Ｉｎ－Ｇａ－Ｚｎ－Ｏ系の半導体は、Ｉｎ（インジウム）、Ｇａ（ガリウム）、Ｚｎ（亜鉛）の三元系酸化物であって、Ｉｎ、Ｇａ及びＺｎの割合（組成比）は特に限定されず、例えばＩｎ：Ｇａ：Ｚｎ＝２：２：１、Ｉｎ：Ｇａ：Ｚｎ＝１：１：１、Ｉｎ：Ｇａ：Ｚｎ＝１：１：２等を含む。
　ここでは、ゲート電極として機能する第２導電膜２２と、半導体膜ＨＦと、サブソース電極Ｓａ・Ｓｂからなるソース電極Ｓと、サブドレイン電極Ｄａ～Ｄｃからなるドレイン電極Ｄとによってボトムゲート型のトランジスタＴＲｃ（図２参照）が構成される。
　なお、サブソース電極Ｓａ・Ｓｂおよびサブドレイン電極Ｄａ～Ｄｃは列方向（データ信号線の延伸方向）に伸び、サブソース電極Ｓａおよびサブドレイン電極Ｄａ間の間隙下に第１チャネル（行方向）が形成され、サブソース電極Ｓａおよびサブドレイン電極Ｄｂ間の間隙下に第２チャネル（行方向）が形成され、サブソース電極Ｓｂおよびサブドレイン電極Ｄｂ間の間隙下に第３チャネル（行方向）が形成され、サブソース電極Ｓｂおよびサブドレイン電極Ｄｃ間の間隙下に第４チャネル（行方向）が形成される。引き出し配線ＤＷおよび延伸配線ＥＷは行方向（走査信号線の延伸方向）に伸びる。
　実施形態１では、第１導電膜２１と第２導電膜２２とが絶縁膜Ｚ１を介して重なっており、第１および第２導電膜２１・２２間に第１容量Ｃ１が形成される。また、第２導電膜２２と第３導電膜２３とが絶縁膜Ｚ２を介して重なっており、第２および第３導電膜２２・２３間に第２容量Ｃ２が形成される。
　また、第１導電膜２１の全体が第２導電膜２２と重なり、半導体膜ＨＦの全体が第１導電膜２１と重なり、第１導電膜２１は、その面積が半導体膜ＨＦとの重畳面積よりも大きく、半導体膜ＨＦの全体が第２導電膜２２と重なり、第２導電膜２２は、第１および第３導電膜２１・２３と重畳するが半導体膜ＨＦとは重畳しない拡張領域２２Ｋを含んでいる。
　また、第２導電膜２２と同層（ゲート層）に形成される出力パッドＰｏを備え、サブドレイン電極Ｄａ～Ｄｃに接続する引き出し配線ＤＷと出力パッドＰｏとが第１コンタクトホールＣＨｘを介して接続され、第１導電膜２１から延伸する延伸配線ＥＷと出力パッドＰｏとが第２コンタクトホールＣＨｙを介して接続されている。これにより、第１導電膜２１および第３導電膜２３が電気的に接続される。第１導電膜２１とドレイン電極Ｄとが電気的に接続されるともいえる。
　実施形態１では、第１導電膜２１と（ドレイン電極Ｄに接続する）第３導電膜２３とが電気的に接続されるため、（第１および第２導電膜２１・２２間に形成される）容量Ｃ１と（第２および第３導電膜２２・２３間に形成される）容量Ｃ２とが並列接続の関係となる。前記のように第２導電膜２２は図２のトランジスタＴＲｃのゲート電極として機能するため、実施形態１によれば、図２のブートストラップ容量Ｃｂを、並列接続された容量Ｃ１および容量Ｃ２で構成する（ブートストラップ容量Ｃｂの容量値＝容量Ｃ１の容量値＋容量Ｃ２の容量値とする）ことができる。これにより、図４の比較形態（第１導電膜２１を設けない構成）に対して、ブートストラップ容量Ｃｂの容量値を変えることなく第２導電膜２２および第３導電膜２３の面積を小さくすることができ、ゲートドライバ２０の回路規模の縮小が可能となる。
　実施形態１では、第２導電膜２２の拡張領域２２Ｋ（半導体膜ＨＦと重ならない領域）と、第１および第３導電膜２１・２３それぞれとの間に形成される容量によってブートストラップ容量Ｃｂの容量値が高められる。
　また、第１導電膜２１の全体が第２導電膜２２と重なっているため、第１導電膜２１による電界をシールドすることができ、チャネルへの悪影響を防ぐことができる。
　また、半導体膜ＨＦの全体が第１導電膜２１と重なるため、前記第１～第４チャネルの特性が均一化される。
　また、平面視において、第１コンタクトホールＣＨｘの開口内に第２コンタクトホールＣＨｙの開口が形成されているため、コンタクトホールを離間して設ける場合に比較して回路面積を縮小化することができる。
　また、第１導電膜２１（下層導電体）を覆う絶縁膜Ｚ１のエッジが、ゲート層に形成される中層導電体と重ならないように構成されている。すなわち、図３および図５（ａ）のように、出力パッドＰｏ（中層導電体）が絶縁膜Ｚ１のエッジと重ならず、ドレイン電極Ｄの引き出し配線ＤＷ（上層導電体）が絶縁膜Ｚ１のエッジを跨ぐように構成されており、絶縁膜Ｚ１の不在部分に引き出された引き出し配線ＤＷ（上層導電体）は、図５（ａ）に示されるように、絶縁膜Ｚ１の不在領域において、第２導電膜２２と同層（ゲート層）の走査信号線１６（図２のＧＬ（ｎ）に対応）とコンタクトホールＣＨｄを介して接続される（繋ぎ換えられる）。これによって、出力パッドＰｏと表示部の走査信号線１６との電気的接続が担保される。なお、出力パッドＰｏ（中層導電体）が絶縁膜Ｚ１のエッジを跨ぐように構成する、例えば、出力パッドＰｏ（中層導電体）を延長して走査信号線に繋げるような構成とすると、図５（ｂ）のように出力パッドＰｏが絶縁膜Ｚ１のエッジ近傍で段切れし、走査信号線との電気的接続が損なわれるおそれがある。
　なお、図６（ａ）のように、第１および第２導電膜２１・２２間の絶縁膜Ｚ１は、局所的に非表示領域にのみ形成しており、具体的には、Ｚ１の面積を基板面積の２０パーセント未満としているため、ＴＦＴ基板３に反りが生じるおそれはない。
　ＴＦＴ基板３では、図６（ｂ）に示すように、表示部のトランジスタのゲート電極よりも下層に下層導電体Ｆａ１が形成され、前記トランジスタのゲート電極と同層に中層導電体Ｆｂ１が形成され、前記ゲート電極よりも上層に、上層導電体Ｊａ・Ｊｂ・Ｊｃ・Ｆａ２・Ｆｂ２並びに端子Ｔａ～Ｔｃが形成され、下層導電体Ｆａ１を覆うように絶縁膜Ｚ１が形成され、中層導電体Ｆｂ１を覆うように絶縁膜Ｚ２が形成される。端子Ｔａ～Ｔｃはソースドライバを含むＩＣチップ９と接続する。
　具体的には、上層導電体Ｊａ（例えば、データ信号線の端部）がコンタクトホールＨａ１を介して下層導電体Ｆａ１（中継配線）に接続され、下層導電体Ｆａ１がコンタクトホールＨａ２を介して上層導電体Ｆａ２（端子配線）に接続され、上層導電体Ｆａ２が端子Ｔａに繋げられている。
　また、上層導電体Ｊｂ（例えば、データ信号線の端部）がコンタクトホールＨｂ１を介して中層導電体Ｆｂ１（中継配線）に接続され、中層導電体Ｆｂ１がコンタクトホールＨｂ２を介して上層導電体Ｆｂ２（端子配線）に接続され、上層導電体Ｆｂ２が端子Ｔｂに繋げられている。
　また、上層導電体Ｊｃ（例えば、データ信号線の端部）が端子Ｔｃに繋げられている。
　図６の構成では、下層導電体Ｆａ１および中層導電体Ｆｂ１それぞれが絶縁膜Ｚ１のエッジと重ならず、上層導電体Ｊａ・Ｊｂ・Ｊｃ・Ｆａ２・Ｆｂ２が絶縁膜Ｚ１のエッジを跨いでいるため、データ信号線１５およびＩＣチップ９間の接続の信頼性が高められる。この点、中層導電体が絶縁膜Ｚ１のエッジを跨ぐような構成ではこのエッジの乗り越え部分で中層導電体が段切れするおそれがある。
　〔実施形態２〕
　図７は、実施形態２のゲートドライバにおいてブートストラップ回路が構成される部分を示す平面図である。
　図７に示すように、ゲートドライバのブートストラップ回路２０ｂは、基板２の上側に、第１導電膜２１およびこれから延伸する延伸配線ＥＷと、第１導電膜２１よりも上層に形成される絶縁膜Ｚ１（例えば窒化シリコン膜、酸化シリコン膜等の無機絶縁膜）と、絶縁膜Ｚ１よりも上層に形成される第２導電膜２２と、第２導電膜２２よりも上層に形成される絶縁膜Ｚ２（ゲート絶縁膜、例えば窒化シリコン膜、酸化シリコン膜等の無機絶縁膜）と、絶縁膜Ｚ２よりも上層に形成される半導体膜ＨＦと、半導体膜ＨＦよりも上層に形成される、サブソース電極Ｓａ・Ｓｂ、サブドレイン電極Ｄａ～Ｄｃ、並びにサブドレイン電極Ｄａ～Ｄｃに接続する引き出し配線ＤＷとを備える。
　ここでは、ゲート電極として機能する第２導電膜２２と、半導体膜ＨＦと、サブソース電極Ｓａ・Ｓｂからなるソース電極Ｓと、サブドレイン電極Ｄａ～Ｄｃからなるドレイン電極Ｄとによってボトムゲート型のトランジスタＴＲｃ（図２参照）が構成される。
　実施形態２では、第１導電膜２１と第２導電膜２２とが絶縁膜Ｚ１を介して重なっており、第１および第２導電膜２１・２２間に第１容量Ｃ１が形成される。
　また、第１導電膜２１の全体が第２導電膜２２と重なり、半導体膜ＨＦの全体が第１導電膜２１と重なり、第１導電膜２１は、その面積が半導体膜ＨＦとの重畳面積よりも大きく、半導体膜ＨＦの全体が第２導電膜２２と重なる。
　また、第２導電膜２２と同層（ゲート層）に形成される出力パッドＰｏを備え、サブドレイン電極Ｄａ～Ｄｃに接続する引き出し配線ＤＷと出力パッドＰｏとが第１コンタクトホールＣＨｘを介して接続され、第１導電膜２１から延伸する延伸配線ＥＷと出力パッドＰｏとが第２コンタクトホールＣＨｙを介して接続されている。これにより、第１導電膜２１とドレイン電極Ｄとが電気的に接続される。
　実施形態１では、第１および第２導電膜２１・２２間に容量Ｃ１が形成される。前記のように第２導電膜２２は図２のトランジスタＴＲｃのゲート電極として機能するため、実施形態２によれば、図２のブートストラップ容量Ｃｂを、半導体膜ＨＦの裏側に形成される容量Ｃ１で構成する（ブートストラップ容量Ｃｂの容量値＝容量Ｃ１の容量値とする）ことができる。これにより、図４の比較形態（第１導電膜２１を設けない構成）に対して、ブートストラップ容量Ｃｂの容量値を変えることなく第２導電膜２２の面積を小さくすることができ、ゲートドライバ２０の回路規模の縮小が可能となる。
　また、平面視において、第１コンタクトホールＣＨｘの開口内に第２コンタクトホールＣＨｙの開口が形成されているため、コンタクトホールを離間して設ける場合に比較して回路面積を縮小化することができる。
　また、第１導電膜２１の全体が第２導電膜２２と重なっているため、第１導電膜２１による電界をシールドすることができ、チャネルへの悪影響を防ぐことができる。
　また、半導体膜ＨＦの全体が第１導電膜２１と重なるため、前記第１～第４チャネルの特性が均一化される。
　また、第１導電膜２１（下層導電体）を覆う絶縁膜Ｚ１のエッジが、ゲート層に形成される中層導電体と重ならないように構成されている。すなわち、図７および図５（ａ）のように、出力パッドＰｏ（中層導電体）が絶縁膜Ｚ１のエッジと重ならず、ドレイン電極Ｄの引き出し配線ＤＷ（上層導電体）が絶縁膜Ｚ１のエッジを跨ぐように構成されており、これによって、出力パッドＰｏと表示部の走査信号線との電気的接続が担保される。
　実施形態２では、図８のように、第１導電膜２１のエッジに、トランジスタＴＲｃのチャネル方向（行方向）と直交し、かつサブドレイン電極Ｄｃと重なる部分が含まれる構成とすることもできる。第１導電膜２１を小さくし、そのエッジを半導体膜ＨＦに重ねる場合、図８のように構成することで、第１導電膜２１のエッジがチャネルを横切らないようにすることができる。なお、図９のように、第１導電膜２１のエッジを４つのチャネルに重ねることもできる。
　〔実施形態３〕
　ＴＦＴ基板の非表示部では、各レイアの配線を用いてマーキングを形成する場合がある。この場合、図１０のように、第２導電膜２２と同層の配線２２ｐおよび第３導電膜２３と同層の配線２３ｐとは別層である、第１導電膜２１と同層の配線２１ｍでマーキングを行う（例えば数字の９を描く）こともできる。なお、配線２１ｍは絶縁膜Ｚ１で覆う。こうすれば、第２導電膜２２と同層の配線２２ｐおよび第３導電膜２３と同層の配線２３ｐとの短絡を防止しながら狭い面積でもマーキングを行うことができる。
　〔実施形態１～３について〕
　実施形態１～３では液晶表示装置について説明したが、本駆動回路は、ＯＬＥＤ（有機発光ダイオード）パネル等の自発光パネルの駆動回路にも好適である。
　〔まとめ〕
　態様１では、基板よりも上側に、ゲート電極と半導体膜と第１および第２導通電極とを含むトランジスタが形成されている駆動回路であって、前記ゲート電極よりも下層に形成された第１導電膜と、前記ゲート電極として機能する第２導電膜とを備え、前記第１導電膜と前記第２導電膜との間に第１容量が形成されている。
　態様２では、前記第１導電膜と前記第２導通電極とが電気的に接続されている。
　態様３では、前記半導体膜は、前記第２導電膜よりも上層かつ前記第１および第２導通電極よりも下層に形成されている。
　態様４では、前記第１および第２導通電極と同層に形成され、前記第２導通電極に繋がる第３導電膜を備える。
　態様５では、前記第２導電膜と前記第３導電膜との間に第２容量が形成されている。
　態様６では、前記第１導電膜の全体が前記第２導電膜と重なる。
　態様７では、前記半導体膜の全体が前記第１導電膜と重なる。
　態様８では、前記半導体膜の全体が前記第２導電膜と重なる。
　態様９では、前記第１導電膜は、その面積が前記半導体膜との重畳面積よりも大きい。
　態様１０では、前記第２導電膜は、第１および第３導電膜と重畳するが前記半導体膜とは重畳しない拡張領域を含む。
　態様１１では、前記第１導電膜のエッジに、前記トランジスタのチャネル方向と直交し、かつ前記第２導通電極と重なる部分が含まれる。
　態様１２では、前記ゲート電極と同層に形成され、前記第２導通電極と電気的に接続する出力パッドを備える。
　態様１３では、前記第２導通電極から引き出された引き出し配線と前記出力パッドとが第１コンタクトホールを介して接続されている。
　態様１４では、前記第１導電膜から延伸する延伸配線と前記出力パッドとが第２コンタクトホールを介して接続されている。
　態様１５では、平面視において、前記第１コンタクトホールの開口内に第２コンタクトホールの開口が形成されている。
　態様１６では、前記引き出し配線が、前記第１および第２導電膜間の絶縁膜のエッジを跨ぐ。
　態様１７では、前記第１導通電極にクロック信号が供給される。
　態様１８では、前記第１容量がブートストラップ容量として機能する。
　態様１９では、前記半導体膜が酸化物半導体で構成されている。
　態様２０では、前記第１および第２導通電極の一方が複数の平行なサブソース電極で構成され、他方が複数の平行なサブドレイン電極で構成されている。
　態様２１のＴＦＴ基板では、前記駆動回路と画素回路とが同一基板にモノリシックに形成されている。
　態様２２では、前記駆動回路によって駆動される走査信号線を備える。
　態様２３では、前記第１導電膜と同層に形成されたマーキング配線を備える。
　態様２４では、前記第１および第２導電膜間の絶縁膜は、局所的に非表示領域にのみ形成されている。
　態様２５のＴＦＴ基板は、トランジスタを含み、非アクティブ部に、前記トランジスタのゲート電極よりも下層に形成された下層導電体と、前記ゲート電極と同層に形成された中層導電体と、前記ゲート電極よりも上層に形成された上層導電体と、前記下層導電体を覆う絶縁膜とが設けられ、前記中層導電体が前記絶縁膜のエッジと重ならず、前記上層導電体が前記絶縁膜のエッジを跨ぐように構成されている。
　態様２６の表示装置は、前記ＴＦＴ基板を備える。
　本発明は上述した実施形態に限定されるものではなく、異なる実施形態にそれぞれ開示された技術的手段を適宜組み合わせて得られる実施形態についても本発明の技術的範囲に含まれる。さらに、各実施形態にそれぞれ開示された技術的手段を組み合わせることにより、新しい技術的特徴を形成することができる。
　２　基板
　３　ＴＦＴ基板
　１０　表示装置
　１６　走査信号線
　２１　第１導電膜（下層導電体）
　２２　第２導電膜
　２３　第３導電膜
　Ｚ１・Ｚ２　絶縁膜
　ＤＷ　引き出し配線（上層導電体）
　ＥＷ　延伸配線
　Ｃｂ　ブートストラップ容量
　Ｃ１　第１容量
　Ｃ２　第２容量
　ＴＲｃ　トランジスタ
　Ｐｏ　出力パット（中層導電体）

Claims (26)

  1. 　基板よりも上側に、ゲート電極と半導体膜と第１および第２導通電極とを含むトランジスタが形成されている駆動回路であって、
    　前記ゲート電極よりも下層に形成された第１導電膜と、前記ゲート電極として機能する第２導電膜とを備え、前記第１導電膜と前記第２導電膜との間に第１容量が形成されている駆動回路。
  2. 　前記第１導電膜と前記第２導通電極とが電気的に接続されている請求項１記載の駆動回路。
  3. 　前記半導体膜は、前記第２導電膜よりも上層かつ前記第１および第２導通電極よりも下層に形成されている請求項１または２に記載の駆動回路。
  4. 　前記第１および第２導通電極と同層に形成され、前記第２導通電極に繋がる第３導電膜を備える請求項２に記載の駆動回路。
  5. 　前記第２導電膜と前記第３導電膜との間に第２容量が形成されている請求項４に記載の駆動回路。
  6. 　前記第１導電膜の全体が前記第２導電膜と重なる請求項１～５のいずれか１項に記載の駆動回路。
  7. 　前記半導体膜の全体が前記第１導電膜と重なる請求項１～６のいずれか１項に記載の駆動回路。
  8. 　前記半導体膜の全体が前記第２導電膜と重なる請求項１～６のいずれか１項に記載の駆動回路。
  9. 　前記第１導電膜は、その面積が前記半導体膜との重畳面積よりも大きい請求項５に記載の駆動回路。
  10. 　前記第２導電膜は、第１および第３導電膜と重畳するが前記半導体膜とは重畳しない拡張領域を含む請求項５に記載の駆動回路。
  11. 　前記第１導電膜のエッジに、前記トランジスタのチャネル方向と直交し、かつ前記第２導通電極と重なる部分が含まれる請求項１～３のいずれか１項に記載の駆動回路。
  12. 　前記ゲート電極と同層に形成され、前記第２導通電極と電気的に接続する出力パッドを備える請求項２に記載の駆動回路。
  13. 　前記第２導通電極から引き出された引き出し配線と前記出力パッドとが第１コンタクトホールを介して接続されている請求項１２に記載の駆動回路。
  14. 　前記第１導電膜から延伸する延伸配線と前記出力パッドとが第２コンタクトホールを介して接続されている請求項１３に記載の駆動回路。
  15. 　平面視において、前記第１コンタクトホールの開口内に第２コンタクトホールの開口が形成されている請求項１４に記載の駆動回路。
  16. 　前記引き出し配線が、前記第１および第２導電膜間の絶縁膜のエッジを跨ぐ請求項１３に記載の駆動回路。
  17. 　前記第１導通電極にクロック信号が供給される請求項１～１６のいずれか１項に記載の駆動回路。
  18. 　前記第１容量がブートストラップ容量として機能する請求項１～１７のいずれか１項に記載の駆動回路。
  19. 　前記半導体膜が酸化物半導体で構成されている請求項１～１８のいずれか１項に記載の駆動回路。
  20. 　前記第１および第２導通電極の一方が複数の平行なサブソース電極で構成され、他方が複数の平行なサブドレイン電極で構成されている請求項１～１９のいずれか１項に記載の駆動回路。
  21. 　請求項１～２０のいずれか１項に記載の駆動回路と画素回路とが同一基板にモノリシックに形成されているＴＦＴ基板。
  22. 　前記駆動回路によって駆動される走査信号線を備える請求項２１に記載のＴＦＴ基板。
  23. 　前記第１導電膜と同層に形成されたマーキング配線を備える請求項２１または２２に記載のＴＦＴ基板。
  24. 　前記第１および第２導電膜間の絶縁膜は、局所的に非表示領域にのみ形成されている請求項２１～２３のいずれか１項に記載のＴＦＴ基板。
  25. 　トランジスタを含むＴＦＴ基板であって、
    　非アクティブ部に、前記トランジスタのゲート電極よりも下層に形成された下層導電体と、前記ゲート電極と同層に形成された中層導電体と、前記ゲート電極よりも上層に形成された上層導電体と、前記下層導電体を覆う絶縁膜とが設けられ、
    　前記中層導電体が前記絶縁膜のエッジと重ならず、前記上層導電体が前記絶縁膜のエッジを跨ぐＴＦＴ基板。
  26. 　請求項２１～２５のいずれか１項に記載のＴＦＴ基板を備える表示装置。
PCT/JP2018/005097 2017-02-21 2018-02-14 駆動回路、ｔｆｔ基板、表示装置 WO2018155284A1 (ja)

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