CN110326113B - 驱动电路、tft基板、显示装置 - Google Patents

驱动电路、tft基板、显示装置 Download PDF

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CN110326113B
CN110326113B CN201880013127.3A CN201880013127A CN110326113B CN 110326113 B CN110326113 B CN 110326113B CN 201880013127 A CN201880013127 A CN 201880013127A CN 110326113 B CN110326113 B CN 110326113B
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conductive film
electrode
film
conductive
drive circuit
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CN110326113A (zh
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堀内智
浅井芳启
小笠原功
富永真克
原义仁
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Sharp Corp
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
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    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
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Abstract

即维持驱动电路的特性，又使电路规模变小。一种驱动电路，在比基板靠上侧形成有包含栅极电极、半导体膜(HF)、以及第1导通电极(S)和第2导通电极(D)的晶体管(TRc)，具备相比于上述栅极电极形成在下层的第1导电膜(21)和作为上述栅极电极发挥功能的第2导电膜(22)，在上述第1导电膜(21)与上述第2导电膜(22)之间形成有第1电容(C1)。

Description

驱动电路、TFT基板、显示装置
技术领域
本发明涉及设置于显示装置的驱动电路(驱动器)。
背景技术
在专利文献1中公开了如下构成：在包含形成在基板上的TFT(薄膜晶体管)和连接到该TFT的电容的驱动电路中，在形成上述TFT的源极的源极层的金属与比该源极层靠上层的金属之间形成电容。
现有技术文献
专利文献
专利文献1：日本再公告特许“WO2011/135873号公报(2011年11月3日公开)”
发明内容
发明要解决的问题
存在电路规模由于构成电容的各电极所占的面积而变大这样的问题。
用于解决问题的方案
一种驱动电路，在比基板靠上侧形成有包含栅极电极、半导体膜、以及第1导通电极和第2导通电极的晶体管，其中，具备相比于上述栅极电极形成在下层的第1导电膜和作为上述栅极电极发挥功能的第2导电膜，在上述第1导电膜与上述第2导电膜之间形成有第1电容。
发明效果
既能够维持驱动电路的特性，又能够使电路规模变小。
附图说明
图1是示出本发明的若干实施方式的显示装置的构成的图，(a)是示出整体构成的截面示意图，(b)是示出整体构成的俯视示意图，(c)是示出显示部的像素电路的电路图。
图2是说明本发明的若干实施方式的栅极驱动器的图，(a)是各级的电路图，(b)是关于各级的信号时序图。
图3是示出在实施方式1的栅极驱动器中构成自举电路的部分的图，(a)是俯视图，(b)是包含晶体管的沟道的截面图。
图4是示出在比较方式的栅极驱动器中构成自举电路的部分的图，(a)是俯视图，(b)是包含晶体管的沟道的截面图。
图5是示出实施方式1的一个优点的示意图。
图6是示出实施方式1的显示装置的构成的图，(a)是示出整体构成的俯视示意图，(b)是示出非显示部的构成例的俯视示意图。
图7是示出在实施方式2的栅极驱动器中构成自举电路的部分的俯视图。
图8是示出实施方式2的变形例的俯视图。
图9是示出实施方式2的另一变形例的俯视图。
图10是示出实施方式3的构成的俯视图。
具体实施方式
下面，基于图1～图10来说明本发明的实施方式。但是，这些实施方式只是例示。
图1是示出本发明的若干实施方式的显示装置的构成的图，(a)是示出整体构成的截面示意图，(b)是示出整体构成的俯视示意图，(c)是示出显示部的像素电路的电路图。
如图1所示，本发明的若干实施方式的显示装置10具备背光源(未图示)、包含基板2的TFT基板3、液晶层4、彩色滤光片基板5以及光学膜6。
TFT基板3的显示部3p包含像素电极11、晶体管12、数据信号线15以及扫描信号线16，在像素电路3g中，像素电极11经由晶体管12连接到数据信号线15和扫描信号线16。此外，也能够将共用电极(未图示的)设置于TFT基板3而设为FFS(Fringe-Field Switching；边缘场开关)方式。另外，还能够使用该共用电极来构成内嵌式触摸传感器。
在TFT基板3的非显示部(非有源部)3q，设置有驱动扫描信号线16的栅极驱动器(驱动电路)20、以及包含驱动数据信号线15的源极驱动器的IC芯片9。栅极驱动器20和像素电路3g单片地形成于同一基板2。
图2是说明栅极驱动器20的图，(a)是各级的电路图，(b)是关于各级的信号时序图。
如图2的(a)所示，栅极驱动器20的第n级电路20n包含晶体管TRa～TRd而构成，并包含自举电路20b，自举电路20b包含晶体管TRc和自举电容Cb。在自举电路20b中，晶体管TRc的栅极电极和漏极电极经由自举电容Cb连接，第n级电路20n的输出焊盘Po连接到晶体管TRc的漏极电极。
第n级电路20n按如下方式进行动作。即，在期间T1中，晶体管TRa被输入第(n-1)行的栅极线GL(n-1)的信号，内部节点(netA)被预充电。此时，晶体管TRc和晶体管TRd变为导通状态，但由于时钟信号CKA为低电位(VSS)，因此栅极线GL(n)被充进低电位(VSS)。接着，在期间T2中，时钟信号CKA切换为高电位(VDD)，时钟信号CKB切换为低电位(VSS)。此时，晶体管TRc为导通状态，晶体管TRd为截止状态，因此，栅极线GL(n)被充进时钟信号CKA的高电位(VDD)。随着栅极线GL(n)被充电，内部节点(netA)经由电容Cb被推高到更高的电位，能够对晶体管TRc的栅极电极施加用于将栅极线GL(n)充电到高电位(VDD)的足够高的电压。另外，在该期间中，栅极线GL(n)的信号被输入到第(n+1)级电路20(n+1)，其内部节点被预充电。接着，在期间T3中，时钟信号CKA切换为低电位(VSS)，时钟信号CKB切换为高电位(VDD)。从而，栅极线GL(n)经由晶体管TRd放电至低电位(VSS)。另外，此时，第(n+1)行的栅极线GL(n+1)被充电到高电位(VDD)，因此，晶体管TRb变为导通状态，将内部节点(netA)放电至低电位(VSS)，从而结束第n行的栅极线GL(n)的动作。以后，根据时钟信号CKB的动作，低电位(VSS)经由晶体管TRd输入到栅极线GL(n)，并维持低电位状态，直到在下一帧再次进行操作为止。
〔实施方式1〕
图3是示出在实施方式1的栅极驱动器中构成自举电路的部分的图，(a)是俯视图，(b)是包含晶体管的沟道的截面图。
如图3所示，栅极驱动器的自举电路20b在基板2的上侧具备：第1导电膜21和自其延伸的延伸配线EW；相比于第1导电膜21形成在上层的绝缘膜Z1(例如氮化硅膜、氧化硅膜等无机绝缘膜)；相比于绝缘膜Z1形成在上层的第2导电膜22；相比于第2导电膜22形成在上层的绝缘膜Z2(栅极绝缘膜，例如氮化硅膜、氧化硅膜等无机绝缘膜)；相比于绝缘膜Z2形成在上层的半导体膜HF；相比于半导体膜HF形成在上层的子源极电极Sa、Sb、子漏极电极Da～Dc；连接到子漏极电极Dc的第3导电膜23；以及连接到子漏极电极Da～Dc的引出配线DW。
半导体膜HF例如是氧化物半导体膜，可以包含In、Ga以及Zn中的至少1种金属元素。实施方式1的半导体膜HF例如包含In-Ga-Zn-O系的半导体。在此，In-Ga-Zn-O系的半导体是In(铟)、Ga(镓)、Zn(锌)的三元系氧化物，In、Ga以及Zn的比例(组成比)没有特别限定，例如包含In：Ga：Zn＝2：2：1、In：Ga：Zn＝1：1：1以及In：Ga：Zn＝1：1：2等。
在此，通过作为栅极电极发挥功能的第2导电膜22、半导体膜HF、包括子源极电极Sa、Sb的源极电极S、包括子漏极电极Da～Dc的漏极电极D来构成底栅型的晶体管TRc(参照图2)。
此外，子源极电极Sa、Sb以及子漏极电极Da～Dc在列方向(数据信号线的延伸方向)上延伸，在子源极电极Sa与子漏极电极Da之间的间隙下形成第1沟道(行方向)，在子源极电极Sa与子漏极电极Db之间的间隙下形成第2沟道(行方向)，在子源极电极Sb与子漏极电极Db之间的间隙下形成第3沟道(行方向)，在子源极电极Sb与子漏极电极Dc之间的间隙下形成第4沟道(行方向)。引出配线DW和延伸配线EW在行方向(扫描信号线的延伸方向)上延伸。
在实施方式1中，第1导电膜21与第2导电膜22隔着绝缘膜Z1重叠，在第1导电膜21与第2导电膜22之间形成第1电容C1。另外，第2导电膜22与第3导电膜23隔着绝缘膜Z2重叠，在第2导电膜22与第3导电膜23之间形成第2电容C2。
另外，第1导电膜21的整体与第2导电膜22重叠，半导体膜HF的整体与第1导电膜21重叠，第1导电膜21的面积大于其与半导体膜HF的重叠面积，半导体膜HF的整体与第2导电膜22重叠，第2导电膜22包含与第1导电膜21和第3导电膜23重叠但不与半导体膜HF重叠的扩展区域22K。
另外，具备与第2导电膜22形成于同一层(栅极层)的输出焊盘Po，连接到子漏极电极Da～Dc的引出配线DW与输出焊盘Po经由第1接触孔CHx连接，从第1导电膜21延伸的延伸配线EW与输出焊盘Po经由第2接触孔CHy连接。从而，第1导电膜21与第3导电膜23电连接。也可以说第1导电膜21与漏极电极D电连接。
在实施方式1中，由于第1导电膜21与(连接到漏极电极D的)第3导电膜23电连接，因此，(形成在第1导电膜21与第2导电膜22之间的)电容C1与(形成在第2导电膜22与第3导电膜23之间的)电容C2成为并联连接的关系。如上所述，第2导电膜22作为图2的晶体管TRc的栅极电极发挥功能，因此，根据实施方式1，能够通过并联连接的电容C1与电容C2构成图2的自举电容Cb(使自举电容Cb的电容值＝电容C1的电容值+电容C2的电容值)。从而，与图4的比较方式(不设置第1导电膜21的构成)相比，不用改变自举电容Cb的电容值就能够使第2导电膜22和第3导电膜23的面积变小，能缩小栅极驱动器20的电路规模。
在实施方式1中，由于形成在第2导电膜22的扩展区域22K(不与半导体膜HF重叠的区域)与第1导电膜21之间的电容、以及形成在第2导电膜22的扩展区域22K(不与半导体膜HF重叠的区域)与第3导电膜23之间的电容，自举电容Cb的电容值得到提高。
另外，由于第1导电膜21的整体与第2导电膜22重叠，因此，能够屏蔽由于第1导电膜21而产生的电场，能够防止对沟道的不良影响。
另外，由于半导体膜HF的整体与第1导电膜21重叠，因此，上述第1沟道～上述第4沟道的特性得到均匀化。
另外，在俯视时，在第1接触孔CHx的开口内形成有第2接触孔CHy的开口，因此，与将接触孔分开设置的情况相比，能够使电路面积缩小。
另外构成为，覆盖第1导电膜21(下层导电体)的绝缘膜Z1的边缘不与形成于栅极层的中层导电体重叠。即，如图3和图5的(a)那样构成为，输出焊盘Po(中层导电体)不与绝缘膜Z1的边缘重叠，漏极电极D的引出配线DW(上层导电体)横跨绝缘膜Z1的边缘，如图5的(a)所示，引出到不存在绝缘膜Z1的部分的引出配线DW(上层导电体)在不存在绝缘膜Z1的区域中经由接触孔CHd连接(转接)到与第2导电膜22为同一层(栅极层)的扫描信号线16(对应于图2的GL(n))。从而，能确保输出焊盘Po与显示部的扫描信号线16的电连接。此外，如果构成为输出焊盘Po(中层导电体)横跨绝缘膜Z1的边缘，例如设为使输出焊盘Po(中层导电体)延长并与扫描信号线相连这样的构成，则会如图5的(b)那样，输出焊盘Po在绝缘膜Z1的边缘附近断开，有可能损害与扫描信号线的电连接。
此外，如图6的(a)那样，第1导电膜21与第2导电膜22之间的绝缘膜Z1仅局部地形成于非显示区域，具体而言，将Z1的面积设为不到基板面积的百分之二十，因此，TFT基板3不会产生翘曲。
如图6的(b)所示，在TFT基板3中，在比显示部的晶体管的栅极电极靠下层形成导电体Fa1，在与上述晶体管的栅极电极同一层中形成中层导电体Fb1，在比上述栅极电极靠上层形成上层导电体Ja、Jb、Jc、Fa2、Fb2以及端子Ta～Tc，以覆盖下层导电体Fa1的方式形成绝缘膜Z1，以覆盖中层导电体Fb1的方式形成绝缘膜Z2。端子Ta～Tc与包含源极驱动器的IC芯片9连接。
具体而言，上层导电体Ja(例如，数据信号线的端部)经由接触孔Ha1连接到下层导电体Fa1(中继配线)，下层导电体Fa1经由接触孔Ha2连接到上层导电体Fa2(端子配线)，上层导电体Fa2是与端子Ta相连的。
另外，上层导电体Jb(例如，数据信号线的端部)经由接触孔Hb1连接到中层导电体Fb1(中继配线)，中层导电体Fb1经由接触孔Hb2连接到上层导电体Fb2(端子配线)，上层导电体Fb2是与端子Tb相连的。
另外，上层导电体Jc(例如，数据信号线的端部)是与端子Tc相连的。
在图6的构成中，下层导电体Fa1和中层导电体Fb1各自不与绝缘膜Z1的边缘重叠，上层导电体Ja、Jb、Jc、Fa2、Fb2横跨绝缘膜Z1的边缘，因此，数据信号线15与IC芯片9之间的连接的可靠性得到提高。在这方面，在中层导电体横跨绝缘膜Z1的边缘这样的构成中，中层导电体可能在越过该边缘的部分处断开。
〔实施方式2〕
图7是示出在实施方式2的栅极驱动器中构成自举电路的部分的俯视图。
如图7所示，栅极驱动器的自举电路20b在基板2的上侧具备：第1导电膜21和自其延伸的延伸配线EW；相比于第1导电膜21形成在上层的绝缘膜Z1(例如氮化硅膜、氧化硅膜等无机绝缘膜)；相比于绝缘膜Z1形成在上层的第2导电膜22；相比于第2导电膜22形成在上层的绝缘膜Z2(栅极绝缘膜，例如氮化硅膜、氧化硅膜等无机绝缘膜)；相比于绝缘膜Z2形成在上层的半导体膜HF；相比于半导体膜HF形成在上层的子源极电极Sa、Sb、子漏极电极Da～Dc；以及连接到子漏极电极Da～Dc的引出配线DW。
在此，通过作为栅极电极发挥功能的第2导电膜22、半导体膜HF、包括子源极电极Sa、Sb的源极电极S、以及包括子漏极电极Da～Dc的漏极电极D来构成底栅型的晶体管TRc(参照图2)。
在实施方式2中，第1导电膜21与第2导电膜22隔着绝缘膜Z1重叠，在第1导电膜21与第2导电膜22之间形成第1电容C1。
另外，第1导电膜21的整体与第2导电膜22重叠，半导体膜HF的整体与第1导电膜21重叠，第1导电膜21的面积大于其与半导体膜HF的重叠面积，半导体膜HF的整体与第2导电膜22重叠。
另外，具备与第2导电膜22形成于同一层(栅极层)的输出焊盘Po，连接到子漏极电极Da～Dc的引出配线DW与输出焊盘Po经由第1接触孔CHx连接，从第1导电膜21延伸的延伸配线EW与输出焊盘Po经由第2接触孔CHy连接。从而，第1导电膜21与漏极电极D电连接。
在实施方式2中，在第1导电膜21与第2导电膜22之间形成电容C1。如上所述，由于第2导电膜22作为图2的晶体管TRc的栅极电极发挥功能，因此，根据实施方式2，能够通过形成在半导体膜HF的里侧的电容C1来构成图2的自举电容Cb(使自举电容Cb的电容值＝电容C1的电容值)。从而，与图4的比较方式(不设置第1导电膜21的构成)相比，不用改变自举电容Cb的电容值就能够使第2导电膜22的面积变小，能缩小栅极驱动器20的电路规模。
另外，在俯视时，在第1接触孔CHx的开口内形成有第2接触孔CHy的开口，因此，与将接触孔分开设置的情况相比，能够使电路面积缩小。
另外，由于第1导电膜21的整体与第2导电膜22重叠，因此，能够屏蔽由于第1导电膜21而产生的电场，能够防止对沟道的不良影响。
另外，由于半导体膜HF的整体与第1导电膜21重叠，因此，上述第1沟道～上述第4沟道的特性得到均匀化。
另外构成为，覆盖第1导电膜21(下层导电体)的绝缘膜Z1的边缘不与形成于栅极层的中层导电体重叠。即，如图7和图5的(a)那样构成为，输出焊盘Po(中层导电体)不与绝缘膜Z1的边缘重叠，漏极电极D的引出配线DW(上层导电体)横跨绝缘膜Z1的边缘，从而，能确保输出焊盘Po与显示部的扫描信号线的电连接。
在实施方式2中，也能够如图8那样设为如下构成：在第1导电膜21的边缘中包含与晶体管TRc的沟道方向(行方向)正交并且与子漏极电极Db重叠的部分。在使第1导电膜21变小，使其边缘与半导体膜HF重叠的情况下，通过如图8那样构成，能够使第1导电膜21的边缘不横穿沟道。此外，也能够如图9那样，使第1导电膜21的边缘与4个沟道重叠。
〔实施方式3〕
在TFT基板的非显示部中，有时使用各层的配线来形成标记。在这种情况下，也能够如图10那样，通过与配线22p和配线23p为不同层而与第1导电膜21为同一层的配线21m来进行标记(例如描绘数字9)，其中，配线22p与第2导电膜22为同一层，配线23p与第3导电膜23为同一层。此外，配线21m由绝缘膜Z1覆盖。如此，能够防止与第2导电膜22为同一层的配线22p和与第3导电膜23为同一层的配线23p的短路，并且即使是在窄的面积中也能够进行标记。
〔关于实施方式1～3〕
虽然在实施方式1～3中说明了液晶显示装置，但本驱动电路也适用于OLED(有机发光二极管)面板等自发光面板的驱动电路。
〔总结〕
方式1是一种驱动电路，在比基板靠上侧形成有包含栅极电极、半导体膜、以及第1导通电极和第2导通电极的晶体管，其中，具备相比于上述栅极电极形成在下层的第1导电膜和作为上述栅极电极发挥功能的第2导电膜，在上述第1导电膜与上述第2导电膜之间形成有第1电容。
在方式2中，上述第1导电膜与上述第2导通电极是电连接的。
在方式3中，上述半导体膜相比于上述第2导电膜形成在上层且相比于上述第1导通电极和上述第2导通电极形成在下层。
在方式4中，具备与上述第1导通电极和上述第2导通电极形成于同一层且与上述第2导通电极相连的第3导电膜。
在方式5中，在上述第2导电膜与上述第3导电膜之间形成有第2电容。
在方式6中，上述第1导电膜的整体与上述第2导电膜重叠。
在方式7中，上述半导体膜的整体与上述第1导电膜重叠。
在方式8中，上述半导体膜的整体与上述第2导电膜重叠。
在方式9中，上述第1导电膜的面积大于其与上述半导体膜的重叠面积。
在方式10中，上述第2导电膜包含与第1导电膜和第3导电膜重叠但不与上述半导体膜重叠的扩展区域。
在方式11中，在上述第1导电膜的边缘中包含与上述晶体管的沟道方向正交并且与上述第2导通电极重叠的部分。
在方式12中，具备与上述栅极电极形成于同一层且与上述第2导通电极电连接的输出焊盘。
在方式13中，从上述第2导通电极引出的引出配线与上述输出焊盘经由第1接触孔连接。
在方式14中，从上述第1导电膜延伸的延伸配线与上述输出焊盘经由第2接触孔连接。
在方式15中，在俯视时，在上述第1接触孔的开口内形成有第2接触孔的开口。
在方式16中，上述引出配线横跨上述第1导电膜与上述第2导电膜之间的绝缘膜的边缘。
在方式17中，时钟信号供应到上述第1导通电极。
在方式18中，上述第1电容作为自举电容发挥功能。
在方式19中，上述半导体膜包括氧化物半导体。
在方式20中，上述第1导通电极和上述第2导通电极中的一方包括多个平行的子源极电极，另一方包括多个平行的子漏极电极。
在方式21的TFT基板中，在同一基板上单片地形成有上述驱动电路、以及像素电路。
在方式22中，具备由上述驱动电路驱动的扫描信号线。
在方式23中，具备与上述第1导电膜形成于同一层的标记配线。
在方式24中，上述第1导电膜与第2导电膜之间的绝缘膜仅局部地形成于非显示区域。
方式25的TFT基板构成为，包含晶体管，在非有源部设置有相比于上述晶体管的栅极电极形成在下层的下层导电体、与上述栅极电极形成于同一层的中层导电体、相比于上述栅极电极形成在上层的上层导电体、以及覆盖上述下层导电体的绝缘膜，上述中层导电体不与上述绝缘膜的边缘重叠，上述上层导电体横跨上述绝缘膜的边缘。
方式26的显示装置具备上述TFT基板。
本发明不限于上述的实施方式，将分别在不同的实施方式中公开的技术手段适当地组合而得到的实施方式也包含在本发明的技术范围内。而且，通过将分别在各实施方式中公开的技术手段组合起来，能够形成新的技术特征。
附图标记说明
2 基板
3 TFT基板
10 显示装置
16 扫描信号线
21 第1导电膜(下层导电体)
22 第2导电膜
23 第3导电膜
Z1、Z2 绝缘膜
DW 引出配线(上层导电体)
EW 延伸配线
Cb 自举电容
C1 第1电容
C2 第2电容
TRc 晶体管
Po 输出焊盘(中层导电体)。

Claims (9)

1.一种驱动电路，在比基板靠上侧形成有包含栅极电极、半导体膜、以及第1导通电极和第2导通电极的底栅型的晶体管，
上述驱动电路的特征在于，
具备相比于上述栅极电极形成在下层的第1导电膜和作为上述栅极电极发挥功能的第2导电膜，在上述第1导电膜与上述第2导电膜之间形成有第1电容，
具备与上述栅极电极形成于同一层且将上述第1导电膜与上述第2导通电极电连接的输出焊盘，
具备与上述第1导通电极和上述第2导通电极形成于同一层且与上述第2导通电极相连的第3导电膜，
上述第2导电膜包含与上述第1导电膜和上述第3导电膜重叠但不与上述半导体膜重叠的扩展区域，
在上述第2导电膜的上述扩展区域与上述第3导电膜之间形成有第2电容，
上述第1电容与上述第2电容并联连接。
2.根据权利要求1所述的驱动电路，
从上述第2导通电极引出的引出配线与上述输出焊盘经由第1接触孔连接。
3.根据权利要求2所述的驱动电路，
从上述第1导电膜延伸的延伸配线与上述输出焊盘经由第2接触孔连接。
4.根据权利要求3所述的驱动电路，
在俯视时，在上述第1接触孔的开口内形成有第2接触孔的开口。
5.根据权利要求2所述的驱动电路，
上述引出配线横跨上述第1导电膜与上述第2导电膜之间的绝缘膜的边缘。
6.根据权利要求1至5中的任意一项所述的驱动电路，
上述半导体膜包括氧化物半导体。
7.根据权利要求1至5中的任意一项所述的驱动电路，
时钟信号供应到上述第1导通电极。
8.根据权利要求1至5中的任意一项所述的驱动电路，
上述第1电容作为自举电容发挥功能。
9.根据权利要求1至5中的任意一项所述的驱动电路，
上述第1导通电极和上述第2导通电极中的一方包括多个平行的子源极电极，另一方包括多个平行的子漏极电极。
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