CN111463220B - 阵列基板及显示装置 - Google Patents

阵列基板及显示装置 Download PDF

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CN111463220B
CN111463220B CN202010272733.6A CN202010272733A CN111463220B CN 111463220 B CN111463220 B CN 111463220B CN 202010272733 A CN202010272733 A CN 202010272733A CN 111463220 B CN111463220 B CN 111463220B
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array substrate
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CN111463220A (zh
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何孝金
董成才
金一坤
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Priority to PCT/CN2020/085980 priority patent/WO2021203482A1/zh
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Abstract

本申请提供一种阵列基板及显示装置，阵列基板具有一绑定区，阵列基板包括第一导电层、第二导电层以及设置于第一导电层和第二导电层之间的绝缘层，第一导电层包括位于绑定区的至少两个并排设置的第一导电构件；第二导电层包括位于绑定区的至少两个第二导电构件，每个第二导电构件与每个第一导电构件对应设置且电性连接，至少两个第二导电构件与至少两个第一导电构件通过绝缘层上的同一个导通孔电连接。相对于传统技术，本申请去除相邻两个第二导电构件之间的绝缘层，使得每个第一导电构件与第二导电构件有效接触的面积更大，降低阻抗，且第二导电构件不会形成在相邻两个第二导电构件之间的绝缘层的侧壁上，避免第二导电构件出现断裂等风险。

Description

阵列基板及显示装置
技术领域
本申请涉及显示技术领域，尤其涉及一种阵列基板及显示装置。
背景技术
对于高解析度显示装置，例如解析度为7680×4320的显示装置，显示装置用于输入栅极驱动电路(Gate On Array，GOA)的时钟信号CK(Clock)的绑定引脚(bonding lead)的导通能力需求大。
如图1所示，其为传统用于输入时钟信号CK的绑定引脚的平面示意图，每个绑定引脚包括一个矩形金属图案11和与一个矩形金属图案11对应设置且电连接的四个透明条状(slit)导电图案12，每个透明条状导电图案12与矩形金属图案11通过一个条状过孔10a电连接，相邻两个矩形金属图案11之间具有绝缘层，相邻两个透明条状导电图案12之间具有绝缘层，用于输入时钟信号CK的绑定引脚由于每个透明导电图案12与矩形金属图案11的有效接触面积(等于条状过孔10a的面积)较小，导致绑定引脚导通电阻较大，无法满足高解析度显示装置的驱动需求。
因此，有必要提出一种技术方案以解决传统用于输入时钟信号CK的绑定引脚存在导通阻抗较大的问题。
发明内容
本申请的目的在于提供一种阵列基板及显示装置，以解决传统用于输入时钟信号CK的绑定引脚存在导通阻抗较大的问题。
为实现上述目的，本申请提供一种阵列基板，所述阵列基板具有一绑定区，所述阵列基板包括第一导电层、第二导电层以及设置于所述第一导电层和所述第二导电层之间的绝缘层，
所述第一导电层包括位于所述绑定区的至少两个并排设置的第一导电构件；
所述第二导电层包括位于所述绑定区的至少两个第二导电构件，每个所述第二导电构件与每个所述第一导电构件对应设置且电性连接，至少两个相邻的所述第二导电构件与至少两个相邻的所述第一导电构件通过所述绝缘层上的同一个导通孔电连接。
在上述阵列基板上，每个所述第二导电构件在所述阵列基板上的正投影位于所述导通孔在所述阵列基板的正投影内。
在上述阵列基板上，所述导通孔沿所述第一导电构件的长度方向的尺寸小于或等于所述第一导电构件的长度。
在上述阵列基板上，所述第一导电构件的宽度等于与所述第一导电构件对应且电连接的所述第二导电构件的宽度。
在上述阵列基板上，所述阵列基板包括多个引脚，每个所述引脚包括一个所述第一导电构件和与所述第一导电构件电连接的一个所述第二导电构件，
多个所述引脚包括用于输入时钟信号的第一引脚以及用于输入低频信号的第二引脚，所述第二引脚设置于所述第一引脚的相对两侧，或/和，
多个所述引脚包括用于输入数据信号的第三引脚。
在上述阵列基板上，所述第一导电层的制备材料选自钼、铝、钛、铜中的至少一种，所述第二导电层的制备材料为氧化铟锡或氧化铟锌。
在上述阵列基板上，所述绝缘层的厚度为1000埃-6000埃，所述绝缘层的制备材料选自氮化硅以及氧化硅中的至少一种。
在上述阵列基板上，所述阵列基板还包括绑定件，所述绑定件绑定于所述绑定区，所述绑定件包括多个导电端子，每个所述导电端子与一个所述第二导电构件电连接。
在上述阵列基板上，相邻两个所述第二导电构件之间的间隙宽度为6微米-12微米，每个所述第二导电构件的宽度为50微米-150微米，每个所述第二导电构件的长度为400微米-800微米。
一种显示装置，所述显示装置包括上述阵列基板。
有益效果：本申请提供一种阵列基板及显示装置，阵列基板具有一绑定区，阵列基板包括第一导电层、第二导电层以及设置于第一导电层和第二导电层之间的绝缘层，第一导电层包括位于绑定区的至少两个并排设置的第一导电构件；第二导电层包括位于绑定区的至少两个第二导电构件，每个第二导电构件与每个第一导电构件对应设置且电性连接，至少两个相邻的第二导电构件与至少两个相邻的第一导电构件通过绝缘层上的同一个导通孔电连接。相对于传统技术，本申请去除相邻两个第二导电构件之间的绝缘层，使得每个第一导电构件与第二导电构件有效接触的面积更大，降低阻抗，且第二导电构件不会形成在相邻两个第二导电构件之间的绝缘层的侧壁上，避免第二导电构件出现断裂等风险。
附图说明
图1为传统用于输入时钟信号CK的绑定引脚的平面示意图；
图2为本申请实施例显示装置的示意图；
图3为图2所示显示面板的阵列基板的平面示意图；
图4为显示面板绑定区的局部放大示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
请参阅图2，其为本申请实施例显示装置的示意图。显示装置100包括显示面板101以及背光模组20，显示面板101为液晶显示面板。显示面板101包括阵列基板1011、与阵列基板1011相对设置的彩膜基板1012以及设置于阵列基板1011和彩膜基板1012之间的液晶层。可以理解的是，显示装置100也可以为有机发光二极管显示面板。显示装置100也可以为无机发光二极管显示面板。
请参阅图3，其为图2所示显示面板的阵列基板的平面示意图。阵列基1011具有显示区1011a以及位于显示区1011a外的绑定区1011b。
阵列基板1011的显示区1011a设置有多个平行的扫描线S、多个平行设置的数据线D以及多个像素电路P，每个像素电路P包括至少一个薄膜晶体管。
阵列基板1011的绑定区1011b包括多个引脚。多个引脚用于与绑定件进行绑定，以实现信号的传输。绑定区1011b包括第一绑定区1011b1以及第二绑定区1011b2，两个第一绑定区1011b1设置于第二绑定区1011b2的相对两侧。多个引脚包括用于输入时钟信号CK的第一引脚10111以及用于输入低频信号(例如VSS信号)的第二引脚10112，第二引脚10112设置于第一引脚10111的相对两侧，第一引脚10111和第二引脚10112并排设置于第一绑定区1011b1，第一引脚10111与时钟信号线CK连接，第二引脚10112与低频信号线连接。多个引脚包括用于传输数据信号的第三引脚10113，第三引脚10113并排设置于第二绑定区1011b2，第三引脚10113与数据线D电性连接。
阵列基板1011还包括绑定件，绑定件绑定于绑定区1011b，绑定件包括多个导电端子，每个导电端子与一个引脚对应，通过各向异性导电胶连接，每个导电端子与一个第二导电构件电连接。绑定件包括第一绑定件10131以及第二绑定件10132。第一绑定件10131为柔性印刷电路板，第一绑定件10131绑定于第一绑定区1011b1。第二绑定件10132为覆晶薄膜或源极驱动芯片，第二绑定件10132绑定于第二绑定区1011b2。
阵列基板1011包括第一导电层、第二导电层以及设置于第一导电层和第二导电层之间的绝缘层104。
结合图2、图3和图4所示，图4为显示面板绑定区的局部放大示意图。第一导电层包括位于绑定区1011b的至少两个并排设置的第一导电构件1021，第一导电层还包括位于显示区100a的扫描线S以及栅极1022。第一导电层的制备材料选自钼、铝、钛、铜的至少一种。第一导电层的厚度为2500埃-3500埃。相邻两个第一导电构件1021之间的间隙宽度为8微米-12微米，例如相邻两个第一导电构件1021之间的间隙宽度为8微米。每个第一导电构件1021的长度为500微米-800微米，例如为500微米、550微米、650微米、680微米以及750微米等。每个第一导电构件1021的宽度为50微米-150微米，例如为60微米、80微米、90微米、130微米以及150微米。多个第一导电构件1021沿第一导电构件1021的宽度方向并排设置。
在本实施例中，第二导电层包括位于绑定区1011b的至少两个第二导电构件1031，第二导电层还包括位于显示区1011a的像素电极1032。至少两个第二导电构件1031并排设置。每个第二导电构件1031与每个第一导电构件1021对应设置且电性连接。第二导电层的制备材料为氧化铟锡或氧化铟锌。第二导电层的厚度为600埃-1000埃。相邻两个第二导电构件1031之间的间隙宽度为6微米-12微米，每个第二导电构件1031的宽度为50微米-150微米，例如为60微米、80微米、100微米、120微米以及140微米，每个第二导电构件1031的长度为400微米-800微米，例如为450微米、500微米、600微米以及680微米。
在本实施例中，第一导电构件1021的宽度等于与第一导电构件1021对应且电连接第二导电构件1031的宽度，以使得第一导电构件1021和第二导电构件1031在宽度方向上的接触面积最大，减小两者的导通电阻。
在本实施例中，至少两个相邻的第二导电构件1031与至少两个相邻的第一导电构件1021通过绝缘层104上的同一个导通孔104a电连接，导通孔104a的形状为矩形。绝缘层104为栅极绝缘层，绝缘层104的厚度为1000埃-6000埃，绝缘层104的制备材料选自氮化硅以及氧化硅的至少一种。具体地，至少两个第二导电构件与至少两个第一导电构件通过绝缘层104上的同一个导通孔104a电连接。
至少两个相邻的第二导电构件1031与至少两个相邻的第一导电构件1021通过绝缘层104上的同一个导通孔104a电连接，使得相邻两个第二导电构件1031之间没有绝缘层，相对于图1所示绑定引脚的透明条状导电图案与矩形金属图案的有效接触面积取决于条状孔的面积，本申请使得第一导电构件1021与第二导电构件1031之间的有效接触面积增大，第一导电构件1021和第二导电构件1031之间的导通阻抗减小，导通能力提升，提升传输电信号的能力，满足1G1D架构8K显示装置对引脚的要求。另外，相对于传统技术，相邻两个第二导电构件1031之间的绝缘层104去除，使得第二导电构件1031不用形成于围合成绝缘层104的过孔的内壁上，避免内壁坡度大于90度时导致第二导电构件1031出现断裂等问题而影响电信号传输。其中，1G1D是指显示面板的显示区同一行子像素与同一条扫描线电连接，同一列子像素与同一条数据线连接。
在本实施例中，每个第二导电构件1031在阵列基板1011上的正投影位于导通孔104a在阵列基板1011的正投影内，以避免第二导电构件1031形成在围合成导通孔104a的内壁上，防止内壁坡脚大于90度时导致第二导电构件1031出现断裂，影响绑定件与第二导电构件1031之间的电信号传输。
在本实施例中，导通孔104a沿第一导电构件1021长度方向的尺寸小于或等于第一导电构件1021的长度，以使得第一导电构件1021与后续形成的第二导电构件1031的有效接触面积取决于第二导电构件1031的面积，有利于提高第二导电构件1031和第一导电构件1021之间接触面积的均匀性以及制程稳定性。
在本实施例中，每个引脚包括一个第一导电构件1021和与第一导电构件1021电连接的一个第二导电构件1031。每个第一引脚10111、每个第二引脚10112以及每个第三引脚10113均由一个第一导电构件1021以及与第一导电构件1021电连接的一个第二导电构件1031组成，其中，组成第三引脚10113的第一导电构件1021与显示区1011a的数据线D通过绝缘层104上的过孔连接。
在本实施例中，背光模组20包括阵列基板，阵列基板包括阵列排布的薄膜晶体管201以及阵列排布的亚毫米发光二极管202(Mini-LED)，薄膜晶体管201用于控制亚毫米发光二极管202的开关状态以及驱动电流大小。如图2所示，背光模组20还包括第三绑定区1011b3，第三绑定区1011b3设置有多个第四引脚203，多个第四引脚203与驱动芯片(未示出)电连接，驱动芯片将驱动信号通过第四引脚203传输至薄膜晶体管，以控制亚毫米发光二极管202的驱动电流值。每个第四引脚203包括一个第一导电构件1021以及与第一导电构件1021电连接的一个第二导电构件1031，多个第四引脚203的第一导电构件1021与第二导电构件1031通过同一个导通孔电连接，使得第一导电构件1021与第二导电构件1031之间的有效接触面积增大，使得第四引脚203的导通能力提升，提升背光模组20的发光效果。
以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (10)

1.一种阵列基板，其特征在于，所述阵列基板具有一绑定区，所述阵列基板包括第一导电层、第二导电层以及设置于所述第一导电层和所述第二导电层之间的绝缘层，
所述第一导电层包括位于所述绑定区的至少两个并排设置的第一导电构件；
所述第二导电层包括位于所述绑定区的至少两个第二导电构件，每个所述第二导电构件与每个所述第一导电构件对应设置且电性连接，每个所述第二导电构件与对应的所述第一导电构件接触，至少两个相邻的所述第二导电构件与至少两个相邻的所述第一导电构件通过所述绝缘层上的同一个导通孔电连接。
2.根据权利要求1所述的阵列基板，其特征在于，每个所述第二导电构件在所述阵列基板上的正投影位于所述导通孔在所述阵列基板的正投影内。
3.根据权利要求1所述的阵列基板，其特征在于，所述导通孔沿所述第一导电构件的长度方向的尺寸小于或等于所述第一导电构件的长度。
4.根据权利要求1所述的阵列基板，其特征在于，所述第一导电构件的宽度等于与所述第一导电构件对应且电连接的所述第二导电构件的宽度。
5.根据权利要求1所述的阵列基板，其特征在于，所述阵列基板包括多个引脚，每个所述引脚包括一个所述第一导电构件和与所述第一导电构件电连接的一个所述第二导电构件，
多个所述引脚包括用于输入时钟信号的第一引脚以及用于输入低频信号的第二引脚，所述第二引脚设置于所述第一引脚的相对两侧，或/和，
多个所述引脚包括用于输入数据信号的第三引脚。
6.根据权利要求1所述的阵列基板，其特征在于，所述第一导电层的制备材料选自钼、铝、钛、铜中的至少一种，所述第二导电层的制备材料为氧化铟锡或氧化铟锌。
7.根据权利要求1所述的阵列基板，其特征在于，所述绝缘层的厚度为1000埃-6000埃，所述绝缘层的制备材料选自氮化硅以及氧化硅中的至少一种。
8.根据权利要求1所述的阵列基板，其特征在于，所述阵列基板还包括绑定件，所述绑定件绑定于所述绑定区，所述绑定件包括多个导电端子，每个所述导电端子与一个所述第二导电构件电连接。
9.根据权利要求1所述的阵列基板，其特征在于，相邻两个所述第二导电构件之间的间隙宽度为6微米-12微米，每个所述第二导电构件的宽度为50微米-150微米，每个所述第二导电构件的长度为400微米-800微米。
10.一种显示装置，其特征在于，所述显示装置包括权利要求1-9任一项所述的阵列基板。
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