WO2018149122A1 - 像素电路及其驱动方法、显示装置 - Google Patents

像素电路及其驱动方法、显示装置 Download PDF

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Publication number
WO2018149122A1
WO2018149122A1 PCT/CN2017/101702 CN2017101702W WO2018149122A1 WO 2018149122 A1 WO2018149122 A1 WO 2018149122A1 CN 2017101702 W CN2017101702 W CN 2017101702W WO 2018149122 A1 WO2018149122 A1 WO 2018149122A1
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Prior art keywords
node
potential
signal
circuit
transistor
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PCT/CN2017/101702
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English (en)
French (fr)
Inventor
张锴
张毅
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BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
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Priority to US15/763,615 priority Critical patent/US10431156B2/en
Publication of WO2018149122A1 publication Critical patent/WO2018149122A1/zh
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
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    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0814—Several active elements per pixel in active matrix panels used for selection purposes, e.g. logical AND for partial update
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    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
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    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
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    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
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    • G09G2320/00—Control of display operating conditions
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    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a pixel circuit, a driving method thereof, and a display device.
  • a pixel circuit is a circuit structure that controls a current flowing through an organic light emitting diode (English: Organic Light Emitting Diode; OLED) by a driving transistor.
  • OLED Organic Light Emitting Diode
  • an OLED pixel circuit generally includes an OLED and a plurality of driving transistors and a capacitor.
  • the plurality of driving transistors are capable of converting a data signal of the data signal end into a driving current for driving the OLED under the control of the scanning signal terminal.
  • a part of the driving transistor in the OLED pixel circuit is further connected to the light emitting control end, and the display brightness of the OLED display device can be adjusted by adjusting the pulse width of the light emitting control signal output by the light emitting control terminal.
  • the voltage of some nodes in the pixel circuit may be unstable, which affects the uniformity of display brightness of the OLED display device.
  • the present disclosure provides a pixel circuit, a driving method thereof, and a display device.
  • the technical solution is as follows:
  • a pixel circuit in a first aspect, includes: an input sub-circuit, a driving sub-circuit, an illumination control sub-circuit, an illumination sub-circuit, and a voltage regulator sub-circuit; and the input sub-circuit is respectively connected to the scan signal end, a data signal end, a first node, a second node, and a third node are connected, for outputting a data signal from the data signal end to the second node under control of a scan signal from the scan signal end, and
  • the third node is connected to the first node;
  • the driving sub-circuit is respectively connected to the first power signal end, the first node, the second node, and the third node, and is configured to be third in the input sub-circuit
  • the node is connected to the first node, the level of the first node is adjusted according to the level of the second node and the first power signal output by the first power signal terminal; the third node and the third node are not in the input sub-circuit
  • the pixel circuit further includes: a reset sub-circuit connected to the reset signal terminal, the initialization signal terminal, and the first node, respectively, for resetting signals from the reset signal terminal Controlling, the initialization signal from the initialization signal terminal is output to the first node.
  • the regulated signal terminal is any one of the first power signal terminal, the second power signal terminal, the reference signal terminal, and the initialization signal terminal.
  • the voltage regulator sub-circuit includes: a first capacitor; one end of the first capacitor is connected to the second node, and the other end is connected to the voltage stabilizing signal end.
  • the input sub-circuit includes: a second transistor and a fourth transistor; a gate of the second transistor is connected to the scan signal end, and a first pole is connected to the third node, a diode is connected to the first node; a gate of the fourth transistor is connected to the scan signal end, a first pole is connected to the data signal end, and a second pole is connected to the second node.
  • the driving sub-circuit includes: a third transistor and a second capacitor; a gate of the third transistor is connected to the first node, and a first pole is connected to the first power signal end a second pole is connected to the third node; one end of the second capacitor is connected to the first node, and the other end is connected to the second node.
  • the illumination control sub-circuit includes: a fifth transistor and a sixth transistor; a gate of the fifth transistor is connected to the illumination control signal end, and the first pole is connected to the reference signal end a second pole is connected to the second node; a gate of the sixth transistor is connected to the light emitting control signal end, a first pole is connected to the third node, and a second pole is connected to the light emitting subcircuit Connected at one end.
  • the illuminating sub-circuit includes: an OLED; one end of the OLED The light-emitting control sub-circuit is connected, and the other end is connected to the second power signal end.
  • the transistors are all P-type transistors.
  • the reset sub-circuit includes: a first transistor; a gate of the first transistor is connected to the reset signal end, a first pole is connected to the initialization signal end, and a second pole is The first node is connected.
  • a method for driving a pixel circuit comprising: a data voltage writing phase, and a scan signal output by the scan signal terminal is first a potential, the input sub-circuit outputs a data signal from the data signal end to the second node, and causes the first node N1 and the third node N3 to be connected, and the driving sub-circuit outputs the first according to the first power signal end a power signal and the data signal, adjusting a potential of the first node; in the light emitting phase, the light emission control signal outputted by the light emission control signal end is a first potential, and the light emission control sub circuit is based on a potential of the reference signal output by the reference signal end Adjusting the potential of the second node; the driving sub-circuit adjusts the potential of the first node according to the potential of the second node, and outputs a driving current to the third node under the control of the first node;
  • the first retention phase and the second retention phase are alternately performed during a transition of the potential of the illumination control signal to the first potential and the second potential.
  • the voltage regulator sub-circuit includes: a first capacitor; the input sub-circuit includes: a second transistor and a fourth transistor; the driver sub-circuit includes: a third transistor and a second capacitor; The light emission control sub-circuit includes: a fifth transistor and a sixth transistor; and the light-emitting sub-circuit includes: an organic electroluminescent diode OLED.
  • the scan signal is a first potential
  • the second transistor and the fourth transistor are turned on, and the data signal end outputs the data signal to the second node
  • the third transistor is turned on, and according to the first a potential of the power signal to adjust a potential of the first node
  • the light emission control signal is a first potential
  • the fifth transistor and the sixth transistor are turned on, and the reference signal end
  • the second node outputs the reference signal
  • the second capacitor adjusts a potential of the first node according to a potential of the second node
  • the third transistor is turned on to output a driving current to the OLED.
  • the OLED emits light; in the first holding phase, the light emission control signal is a second potential, and the first capacitor keeps the potential of the second node unchanged under the control of the voltage stabilization signal; In the second holding phase, the light emission control signal potential is a first potential, the fifth transistor and the sixth transistor are turned on, and the reference signal end outputs the reference signal to the second node, The second capacitor adjusts a potential of the first node according to a potential of the second node, the third transistor is turned on, and outputs a driving current to the OLED, and the OLED emits light.
  • the pixel circuit further includes: a reset sub-circuit connected to the reset signal terminal, the initialization signal terminal, and the first node, respectively, for resetting signals from the reset signal terminal Controlling, the initialization signal from the initialization signal terminal is output to the first node.
  • the method further includes a reset phase, before the data voltage writing phase, the reset signal output by the reset signal terminal is a first potential, and the reset sub-circuit outputs an initialization signal from the initialization signal terminal to the first node.
  • the initialization signal is the first potential.
  • the reset sub-circuit includes: a first transistor; in the reset phase, the reset signal is a first potential, the first transistor is turned on, and the initialization signal is turned to the first The node outputs the initialization signal.
  • the method before the resetting phase, further includes: a preparation phase; in the preparation phase, the reset signal and the scan signal are both a second potential, and the illumination control signal is The first potential jumps to a second potential, the first transistor, the second transistor, and the fourth transistor to the sixth transistor are both turned off, and the first capacitor is under the control of the voltage stabilization signal , keeping the potential of the second node unchanged.
  • the method further comprises: a first transition phase; before the illuminating phase, the method further comprises: a second transition phase; In the first transition phase, the reset signal is jumped from a first potential to a second potential, and the signals output by the scan signal end and the light-emitting control signal end are both at a second potential, and the first transistor is The sixth transistor is turned off; in the second transition phase, the reset signal maintains a second potential, the scan signal is transitioned from a first potential to a second potential, and the second capacitor causes the first The potential of one node and the second node remains unchanged.
  • the transistors are all P-type transistors, and the first potential is low relative to the second potential.
  • a display device comprising: the pixel circuit according to the first aspect.
  • the technical solution provided by the present disclosure has the beneficial effects that the present disclosure provides a pixel circuit, a driving method thereof, and a display device.
  • the pixel circuit further includes a voltage regulator circuit, and one end of the voltage regulator circuit is regulated. The signal end is connected, and the other end is connected to the second node. Since the potential of the voltage stabilizing signal outputted by the voltage stabilizing signal terminal is a fixed potential, the voltage regulator sub-circuit can enable the second node in the process of driving the pixel circuit. The potential remains stable, and the influence of the potential change of the illumination control signal on the potential of the second node is avoided, thereby preventing the brightness unevenness of the display device.
  • FIG. 1 is a schematic block diagram of a pixel circuit according to an embodiment of the present disclosure
  • FIG. 2 is a schematic circuit diagram of the pixel circuit shown in FIG. 1 according to an embodiment of the present disclosure
  • FIG. 3 is another schematic circuit diagram of the pixel circuit shown in FIG. 1 according to an embodiment of the present disclosure
  • FIG. 4 is another schematic circuit diagram of the pixel circuit shown in FIG. 1 according to an embodiment of the present disclosure
  • FIG. 5 is a flowchart of a method for driving a pixel circuit according to an embodiment of the present disclosure
  • FIG. 6 is a timing diagram of a driving process of a pixel circuit according to an embodiment of the present disclosure
  • FIG. 7 is a schematic diagram of potentials of respective signal terminals, potentials of respective nodes, and magnitudes of driving currents during driving of a pixel circuit according to an embodiment of the present disclosure.
  • the transistors employed in all embodiments of the present disclosure may each be a thin film transistor or a field effect transistor or
  • the transistor used in the embodiment of the present disclosure is mainly a switching transistor. Since the source and drain of the switching transistor used here are symmetrical, the source and the drain are interchangeable. In the embodiments of the present disclosure, the source is referred to as a first stage and the drain is referred to as a second stage. According to the form in the drawing, the middle end of the transistor is the gate, the signal input end is the source, and the signal output end is the drain.
  • the switching transistor employed in the embodiments of the present disclosure may include any one of a P-type switching transistor and an N-type switching transistor, wherein the P-type switching transistor is turned on when the gate is at a low level, and is turned off when the gate is at a high level.
  • the N-type switching transistor is turned on when the gate is at a high level and turned off when the gate is at a low level.
  • the plurality of signals in various embodiments of the present disclosure correspond to a first potential and a second potential. The first potential and the second potential only represent two state quantities of the potential of the signal, and do not mean that the first potential or the second potential has a specific value in the whole text.
  • FIG. 1 is a schematic structural diagram of a pixel circuit according to an embodiment of the present disclosure.
  • the pixel circuit may include: an input sub-circuit 10 , a driving sub-circuit 20 , an emission control sub-circuit 30 , an illuminating sub-circuit 40 , and Voltage regulator sub-circuit 50.
  • the input sub-circuit 10 is respectively connected to the scan signal terminal GATE, the data signal terminal DATA, the first node N1, the second node N2, and the third node N3 for controlling the scan signal from the scan signal terminal GATE.
  • the second node N2 outputs a data signal from the data signal terminal DATA, and connects the third node N3 with the first node N1.
  • the driving sub-circuit 20 is respectively connected to the first power signal terminal VDD, the first node N1, the second node N2, and the third node N3 for connecting the third node N3 to the first node N1 at the input sub-circuit 10.
  • the level of the first node N1 is adjusted according to the level of the second node N2 and the first power signal outputted by the first power signal terminal VDD; the third node N3 is not connected to the first node N1 at the input sub-circuit 10.
  • the driving current is output to the third node N3 according to the first power signal outputted by the first power signal terminal VDD.
  • the illumination control sub-circuit 30 is respectively connected to the illumination control signal terminal EM, the reference signal terminal Vref, the second node N2, the third node N3, and one end of the illumination sub-circuit 40 for receiving the illumination control signal terminal EM. Controlling the potential of the second node N2 according to the reference signal from the reference signal terminal Vref under the control of the illumination control signal; and outputting the drive current under the control of the illumination control signal from the illumination control signal terminal EM To the illuminating sub-circuit 40.
  • the other end of the illuminating sub-circuit 40 is connected to the second power supply signal terminal VSS for emitting light under the driving of the driving current.
  • the voltage stabilizing sub-circuit 50 is respectively connected to the second node N2 and the voltage stabilizing signal terminal for The potential of the second node N2 is stabilized under the control of the regulated signal at the regulated signal terminal, and the potential of the regulated signal remains unchanged during the driving process of the pixel circuit.
  • the regulated signal terminal is the first power signal terminal VDD.
  • the potential of the first power signal outputted by the first power signal terminal VDD is always the second potential.
  • the pixel circuit shown in FIG. 1 may further include: a reset sub-circuit 60.
  • the reset sub-circuit 60 is respectively connected to the reset signal terminal RST, the initialization signal terminal Vin, and the first node N1, and is configured to output the signal from the first node N1 under the control of the reset signal from the reset signal terminal RST.
  • the initialization signal of the initialization signal terminal Vin is respectively connected to the reset signal terminal RST, the initialization signal terminal Vin, and the first node N1, and is configured to output the signal from the first node N1 under the control of the reset signal from the reset signal terminal RST.
  • the initialization signal of the initialization signal terminal Vin may further include: a reset sub-circuit 60.
  • the reset sub-circuit 60 is respectively connected to the reset signal terminal RST, the initialization signal terminal Vin, and the first node N1, and is configured to output the signal from the first node N1 under the control of the reset signal from the reset signal terminal RST.
  • the initialization signal of the initialization signal terminal Vin
  • the embodiment of the present disclosure provides a pixel circuit, where the pixel circuit includes a voltage regulator circuit, one end of the voltage regulator circuit is connected to the voltage stabilization signal end, and the other end is connected to the second node.
  • the potential of the regulated signal outputted by the regulated signal terminal is a fixed potential, so the voltage regulator sub-circuit can keep the potential of the second node stable during the driving process of the pixel circuit, and avoid the potential change of the light-emitting control signal to the second The influence of the node potential, thereby avoiding the uneven brightness of the display device.
  • the The voltage stabilizing signal terminal connected to the voltage stabilizing sub-circuit may be any one of the first power signal terminal VDD, the second power signal terminal VSS, the reference signal terminal Vref, and the initialization signal terminal Vin.
  • FIG. 2 to FIG. 4 are schematic circuit diagrams of a pixel circuit according to an embodiment of the present disclosure.
  • the regulated signal terminal may be the first power signal terminal VDD, and the potential of the first power signal outputted by the first power signal terminal VDD continues to be the second potential; or, as shown in FIG.
  • the voltage signal terminal may be the reference signal terminal Vref, and the potential of the reference signal outputted by the reference signal terminal Vref continues to be the second potential; or, as shown in FIG. 4, the voltage regulation signal terminal may be the initialization signal terminal Vin, The potential of the initialization signal output from the initialization signal terminal Vin continues to be the first potential.
  • the input sub-circuit 10 may include a second transistor M2 and a fourth transistor M4. Specifically, the gate of the second transistor M2 is connected to the scan signal terminal GATE, the first pole is connected to the third node N3, the second pole is connected to the first node N1, and the gate of the fourth transistor M4 is The scan signal terminal GATE is connected, the first pole is connected to the data signal terminal DATA, and the second pole is connected to the second node N2.
  • the input sub-circuit 10 is configured to output the number from the second node N2 under the control of the scan signal from the scan signal terminal GATE According to the data signal of the signal terminal DATA, the third node N3 is connected to the first node N1.
  • the driving sub-circuit 20 may include a third transistor M3 and a second capacitor C2. Specifically, the gate of the third transistor M3 is connected to the first node N1, the first pole is connected to the first power signal terminal VDD, the second pole is connected to the third node N3, and one end of the second capacitor C2 The first node N1 is connected, and the other end is connected to the second node N2.
  • the driving sub-circuit 20 is configured to adjust according to the level of the second node N2 and the first power signal output by the first power signal terminal VDD in the case where the input sub-circuit 10 connects the third node N3 with the first node N1.
  • the light emission control sub-circuit 30 may include a fifth transistor M5 and a sixth transistor M6. Specifically, the gate of the fifth transistor M5 is connected to the light emission control signal terminal EM, the first pole is connected to the reference signal terminal Vref, and the second pole is connected to the second node N2; the gate of the sixth transistor M6 The light-emitting control signal terminal EM is connected, the first pole is connected to the third node N3, and the second pole is connected to one end of the light-emitting sub-circuit 40.
  • the illumination control sub-circuit 30 is configured to control the potential of the second node N2 according to a reference signal from the reference signal terminal Vref under the control of the illumination control signal from the illumination control signal terminal EM; and from the illumination control The drive current is output to the illuminating sub-circuit 40 under the control of the illuminating control signal of the signal terminal EM.
  • the illuminator circuit 40 can include an OLED. One end of the OLED is connected to the light emission control sub-circuit 30, and the other end is connected to the second power signal terminal VSS.
  • the illuminating sub-circuit 40 is for illuminating under the driving of the driving current.
  • the voltage regulator sub-circuit 50 can include a first capacitor C1. One end of the first capacitor C1 is connected to the second node N2, and the other end is connected to the voltage stabilizing signal end.
  • the voltage regulator circuit 50 is configured to stabilize the potential of the second node N2 under the control of the voltage stabilization signal from the voltage regulation signal terminal.
  • the pixel circuit may further include: a reset sub-circuit 60.
  • the reset subcircuit 60 can include a first transistor M1. Specifically, the gate of the first transistor M1 is connected to the reset signal terminal RST, the first pole is connected to the initialization signal terminal Vin, and the second pole is connected to the first node N1.
  • the reset sub-circuit 60 is configured to output an initialization signal from the initialization signal terminal Vin to the first node N1 under the control of a reset signal from the reset signal terminal RST.
  • the embodiment of the present disclosure provides a pixel circuit, where the pixel circuit includes a voltage regulator circuit, one end of the voltage regulator circuit is connected to the voltage stabilization signal end, and the other end is connected to the second node. Since the potential of the regulated signal outputted by the regulated signal terminal is a fixed potential, the voltage regulator sub-circuit can stabilize the potential of the second node during the driving of the pixel circuit, and avoid the potential change of the light-emitting control signal. The influence of the potential of the second node, thereby avoiding the phenomenon of uneven brightness of the display device.
  • FIG. 5 is a flowchart of a driving method of a pixel circuit according to an embodiment of the present disclosure. The method is used to drive a pixel circuit as shown in any one of FIG. 1 to FIG. 4 . Referring to FIG. 5 , the method may include:
  • Step 102 In the data voltage writing phase, the scan signal outputted by the scan signal terminal GATE is the first potential, and the input sub-circuit 10 outputs the data signal from the data signal terminal DATA to the second node N2, and makes the first node N1 and the first node The three nodes N3 are connected, and the driving sub-circuit 20 adjusts the potential of the first node N1 according to the first power signal outputted by the first power signal terminal VDD and the data signal.
  • Step 103 The illuminating phase, the illuminating control signal outputted by the illuminating control signal terminal EM is a first potential, and the illuminating control sub-circuit 30 adjusts the potential of the second node N2 according to the potential of the reference signal outputted by the reference signal terminal Vref;
  • the sub-circuit 20 adjusts the potential of the first node N1 according to the potential of the second node N2, and outputs a driving current to the third node N3 under the control of the first node N1;
  • the illumination control sub-circuit 30 The drive current is output to the illuminating sub-circuit 40, and the illuminating sub-circuit 40 emits light.
  • Step 104 The first holding phase, the potential of the illumination control signal outputted by the illumination control signal terminal EM is changed from the first potential to the second potential, and the voltage stabilization signal outputted by the voltage regulator sub-circuit 50 at the voltage stabilization signal terminal is controlled. Next, the potential of the second node N2 is kept unchanged.
  • Step 105 The second holding phase, the potential of the illumination control signal outputted by the illumination control signal terminal EM is changed from the second potential to the first potential, and the potential of the reference signal output by the illumination control sub-circuit 30 according to the reference signal terminal Vref, Adjusting the potential of the second node N2; the driving sub-circuit 20 adjusts the potential of the first node N1 according to the potential of the second node N2, and under the control of the first node N1, to the third node N3 outputs a drive current; the illumination control sub-circuit 30 outputs the drive current to the illuminating sub-circuit 40, and the illuminating sub-circuit 40 emits light.
  • the method may further include a step 101, a reset phase, before the data voltage writing phase, the reset signal outputted by the reset signal terminal RST is a first potential, and the reset sub-circuit 60 outputs the initialization signal terminal Vin to the first node N1.
  • the initialization signal is the first potential.
  • the embodiment of the present disclosure provides a driving method of a pixel circuit, where the driving method further includes a holding phase in which a potential of the light emission control signal is jumped by the first potential Up to the second potential, the voltage regulator circuit in the pixel circuit can avoid the influence of the potential change of the light-emitting control signal on the potential of the second node, so that the potential of the second node remains unchanged during the holding phase, thereby preventing the display device from appearing Uneven brightness.
  • the potential of the illuminating control signal is hopped multiple times between the first potential and the second potential, so that the pixel circuit alternately performs the first holding phase and the second holding phase.
  • the voltage regulator circuit can alternate the potential of the second node in the first holding phase and the second holding phase under the control of the voltage stabilizing signal. It has always remained stable.
  • FIG. 6 is a timing diagram of a driving process of a pixel circuit according to an embodiment of the present disclosure.
  • the driving process includes eight stages, which are: preparation stage T1, reset stage T2, first transition stage T3, data voltage writing stage T4, second transition stage T5, lighting stage T6, and first holding stage. T7 and second hold phase T8.
  • T2 is not essential, and the lengths of the stages shown in FIG. 6 are merely illustrative and not limiting of the disclosure.
  • the technical solution of the present disclosure aims to solve the problem that variations in lighting control signals may cause voltages of certain nodes in a pixel circuit to be unstable.
  • the potential of the light emission control signal is jumped from the first potential to the second potential, and the voltage regulator circuit in the pixel circuit can avoid the influence of the potential change of the light emission control signal on the potential of the second node, so that The potential of the second node remains unchanged during the first holding phase, thereby preventing the display device from exhibiting uneven brightness.
  • the preparation phase T1 is further included.
  • the reset signal outputted by the reset signal terminal RST and the scan signal outputted by the scan signal terminal GATE are both the second potential, and the illumination control of the output of the illumination control signal terminal EM is performed.
  • the signal transitions from a first potential to a second potential.
  • the first transistor M1, the second transistor M2, and the fourth transistor M4 are turned off, and the fifth transistor M5 and the sixth transistor M6 are switched from the on state to the off state, and the first capacitor C1 can be in the voltage stabilization signal (for example, Under the control of a first power signal outputted by a power signal terminal VDD, the potential of the second node N2 is kept constant, ready for writing signals.
  • the reset signal outputted by the reset signal terminal RST is changed from the second potential to the first potential, the first transistor M1 is turned on, and the initialization signal terminal Vin outputs the initialization signal to the first node N1.
  • the potential of the first node N1 is initialized.
  • the potential of the second node N2 is a certain stable potential Vx, and the magnitude of the potential Vx is the potential of the data signal of the previous stage.
  • Vref is the potential of the reference signal
  • Vin is the potential of the initialization signal
  • C1 and C2 are the capacitance values of the first capacitor and the second capacitor, respectively. Since the potential of the scan signal is maintained at the second potential at this time, the second transistor M2 and the fourth transistor M4 continue to remain in the off state, the potential of the light emission control signal is also maintained at the second potential, and the fifth transistor M5 and the sixth transistor M6 remain turned off. status.
  • the method further includes: a first transition phase T3.
  • the reset signal is jumped from the first potential to the second potential, and the scan signal terminal GATE and the signal output by the illumination control signal terminal EM are both at the second potential, and the first transistor M1 is The sixth transistor M6 is turned off to prepare for writing of the data signal.
  • the scan signal is jumped from the second potential to the first potential, the second transistor M2 and the fourth transistor M4 are turned on, and the data signal terminal DATA outputs the current to the second node N2.
  • the data signal at this time, the potential of the second node N2 is the potential Vdata of the data signal. Due to the conduction of the second transistor M2, the gate and the drain of the third transistor M3 are connected, and at this time, the third transistor M3 is in a diode conduction state.
  • the potential of the gate of the third transistor M3 (ie, the first node N1) is the potential Vin of the initialization signal
  • the potential of the source of the third transistor M3 is the potential Vdd of the first power signal (the potential of the first power signal) Vdd is at a high potential with respect to the potential Vin of the initialization signal, so the first power supply signal terminal VDD can charge the first node N1.
  • the threshold voltage of the third transistor M3 is Vth, when the first power supply signal terminal VDD pulls the potential of the first node N1 high to Vdd+Vth, the third transistor M3 is turned off.
  • the reset signal maintains a second potential
  • the scan signal transitions from the first potential to the second potential
  • the second capacitor C2 maintains the potentials of the first node N1 and the second node N2 unchanged. That is, the potential of the first node N1 is maintained at Vdd+Vth, and the potential of the second node N2 is maintained at Vdata.
  • the first transition phase T3 and the second transition phase T5 described above may leave a certain gap between the reset signal and the scan signal, and between the scan signal and the illumination control signal. Since the two signals are turned on at the same time (that is, at the same time at the first potential), unnecessary current loops are formed in the pixel circuit, which affects the driving effect of the pixel circuit. Therefore, the two transition phases can effectively prevent the two signals from being simultaneously turned on. The situation ensures the normal operation of the pixel circuit.
  • the light emission control signal is jumped from the second potential to the first potential, the fifth The transistor M5 and the sixth transistor M6 are turned on, and the reference signal terminal Vref outputs the reference signal to the second node N2.
  • the potential of the second node N2 becomes Vref, and the potential variation of the second node N2 is Vref. -Vdata.
  • the second capacitor C2 can adjust the potential of the first node N1 according to the potential of the second node N2, and the potential of the first node N1 becomes Vdd+Vth+(Vref-Vdata).
  • the third transistor M3 outputs a driving current to the OLED to drive the OLED to emit light.
  • the magnitude of the driving current Id output by the third transistor M3 can be expressed as:
  • ⁇ is the carrier mobility of the third transistor M3
  • C is the capacitance of the gate insulating layer of the third transistor M3
  • W/L is the aspect ratio of the third transistor M3.
  • the light emission control signal is jumped from the first potential to the second potential, and the first capacitor C1 can be controlled by the voltage stabilization signal (eg, the first power signal)
  • the voltage stabilization signal eg, the first power signal
  • the display brightness of the display device can be adjusted by using pulse width modulation (English: Pulse Width Modulation; PWM). That is, the display brightness of the display device is changed by adjusting the number of times of the potential jump of the light-emission control signal within one frame and the duration of each potential.
  • the adjustment of the pulse width of the illumination control signal affects the number of times the illumination phase T6 and the first retention phase T7 alternately appear in FIG. 6, and the duration of each phase.
  • the fourth transistor M4 and the fifth transistor M5 are both in an off state.
  • the potentials of the second node N2 and the first node N1 are not controlled by any other signal terminals, that is, they are all in a floating state, and the potential of the node in the floating state is easily interfered by the coupling of the external signal, and the transistor leakage current in the pixel circuit.
  • the influence of the data voltage written in the pixel circuit is affected, which is likely to cause uneven brightness of the display device and affect the display effect.
  • the voltage regulator circuit 50 can be in the illumination control signal. After the potential of the number jumps to the second potential, the potential of the second node N2 remains unchanged by the voltage stabilization signal at the voltage stabilizing signal terminal. Further, the second capacitor C2 in the driving sub-circuit 20 can be under the action of the second node N2 such that the potential of the first node N1 remains unchanged. Therefore, the pixel circuit provided by the embodiment of the present disclosure can effectively prevent voltage drift of the two nodes and achieve stable display of the display device.
  • FIG. 7 is a schematic diagram of potentials of respective signal terminals, potentials of respective nodes, and magnitudes of driving currents during driving of a pixel circuit according to an embodiment of the present disclosure. It should be understood that the lengths of the various segments of the signals shown in FIG. 7 are merely illustrative and are not limiting of the disclosure.
  • the solid line is the timing when the voltage regulator sub-circuit is not provided in the related art, and the broken line is the voltage sub-circuit provided in the embodiment of the present disclosure. Timing. It can be seen from FIG.
  • the potentials of the first node N1 and the second node N2 and the magnitude of the driving current Id are greatly affected by the illumination control signal.
  • the driving current Id and the potentials of the two nodes also fluctuate, and the driving force increases with the number of times of the potential jump of the light emission control signal.
  • the current Id is also decreasing.
  • the potentials of the first node N1 and the second node N2 and the magnitude of the driving current Id are less affected by the illumination control signal.
  • the potentials of the two nodes are relatively stable, and the fluctuation of the driving current Id is relatively small, that is, the stability of the driving current Id is high, thereby ensuring adoption.
  • the PWM method adjusts the brightness of the display device, the uniformity of display brightness of the display device is not affected.
  • the embodiment of the present disclosure provides a driving method of a pixel circuit, where the driving method further includes a holding phase in which a potential of the light emission control signal jumps from a first potential to a second potential.
  • the voltage regulator circuit in the pixel circuit can avoid the influence of the potential change of the light-emitting control signal on the potential of the second node, so that the potential of the second node remains unchanged during the holding phase, thereby preventing the brightness unevenness of the display device.
  • the first transistor to the sixth transistor are P-type transistors, and the first potential is described as an example of a low potential with respect to the second potential.
  • the first to sixth transistors may further adopt an N-type transistor.
  • the first potential may be a high potential with respect to the second potential, and the respective signals
  • the potential change at the end can be opposite to the potential change shown in Figures 6 and 7 (i.e., the phase difference between the two is 180 degrees).
  • the embodiment of the present disclosure further provides a display device, which may include a pixel circuit as shown in any of FIGS. 1 to 4.
  • the display device may be: electronic paper, OLED panel, AMOLED panel, mobile phone, tablet computer, television, display, notebook computer, digital photo frame, navigator, etc., any product or component having display function.

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Abstract

一种像素电路及其驱动方法、显示装置，属于显示技术领域。像素电路包括：输入子电路（10）、驱动子电路（20）、发光控制子电路（30）、发光子电路（40）和稳压子电路（50）；稳压子电路（50）分别与像素电路中的第二节点（N2）和稳压信号端连接，用于在来自稳压信号端的稳压信号的控制下，稳定第二节点（N2）的电位，稳压信号的电位在像素电路的驱动过程中保持不变。由于稳压子电路（50）能够在像素电路驱动的过程中，使得第二节点（N2）的电位保持稳定，因此可以避免发光控制信号电位变化对第二节点（N2）电位的影响，进而避免显示装置出现亮度不均的现象。

Description

像素电路及其驱动方法、显示装置 技术领域
本公开涉及显示技术领域，特别涉及一种像素电路及其驱动方法、显示装置。
背景技术
像素电路是一种通过驱动晶体管来控制流过有机发光二极管(英文：Organic Light Emitting Diode；简称：OLED)的电流的电路结构。
相关技术中，OLED像素电路一般包括OLED和多个驱动晶体管以及电容器。该多个驱动晶体管能够在扫描信号端的控制下，将数据信号端的数据信号转化为用于驱动OLED的驱动电流。OLED像素电路中的部分驱动晶体管还与发光控制端连接，可以通过调整该发光控制端输出的发光控制信号的脉冲宽度，对OLED显示装置的显示亮度进行调整。
但是，在对发光控制信号的脉冲宽度进行调整的过程中，可能使得像素电路中某些节点的电压不稳定，影响OLED显示装置显示亮度的均匀性。
发明内容
为了解决相关技术中的像素电路中某些节点的电压不稳定，影响OLED显示装置显示亮度的均匀性的问题，本公开提供了一种像素电路及其驱动方法、显示装置。所述技术方案如下：
第一方面，提供了一种像素电路，所述像素电路包括：输入子电路、驱动子电路、发光控制子电路、发光子电路和稳压子电路；所述输入子电路分别与扫描信号端、数据信号端、第一节点、第二节点和第三节点连接，用于在来自所述扫描信号端的扫描信号的控制下，向所述第二节点输出来自所述数据信号端的数据信号，并且将所述第三节点与所述第一节点连接；所述驱动子电路分别与第一电源信号端、第一节点、第二节点和第三节点连接，用于在所述输入子电路将第三节点与第一节点连接的情况下，根据第二节点的电平和第一电源信号端输出的第一电源信号，调整所述第一节点的电平；在输入子电路未将第三节点与第一节点连接的情况下，在第一节点的控制下，根据第一电源信号端输出的第一电源信号，向所述第三节点输出驱动电流； 所述发光控制子电路分别与发光控制信号端、参考信号端、所述第二节点、所述第三节点以及所述发光子电路的一端连接，用于在来自所述发光控制信号端的发光控制信号的控制下，根据来自所述参考信号端的参考信号，控制所述第二节点的电位，以及在来自所述发光控制信号端的发光控制信号的控制下，将所述驱动电流输出至所述发光子电路；所述发光子电路的另一端与第二电源信号端连接，用于在所述驱动电流的驱动下发光；所述稳压子电路分别与所述第二节点和稳压信号端连接，用于在来自所述稳压信号端的稳压信号的控制下，稳定所述第二节点的电位，所述稳压信号的电位在所述像素电路的驱动过程中保持不变。
在一个实施例中，所述像素电路还包括：复位子电路，所述复位子电路分别与复位信号端、初始化信号端和所述第一节点连接，用于在来自所述复位信号端的复位信号的控制下，向所述第一节点输出来自所述初始化信号端的初始化信号。
在一个实施例中，所述稳压信号端为所述第一电源信号端、所述第二电源信号端、所述参考信号端和所述初始化信号端中的任一信号端。
在一个实施例中，所述稳压子电路，包括：第一电容器；所述第一电容器的一端与所述第二节点连接，另一端与所述稳压信号端连接。
在一个实施例中，所述输入子电路，包括：第二晶体管和第四晶体管；所述第二晶体管的栅极与所述扫描信号端连接，第一极与所述第三节点连接，第二极与所述第一节点连接；所述第四晶体管的栅极与所述扫描信号端连接，第一极与所述数据信号端连接，第二极与所述第二节点连接。
在一个实施例中，所述驱动子电路，包括：第三晶体管和第二电容器；所述第三晶体管的栅极与所述第一节点连接，第一极与所述第一电源信号端连接，第二极与所述第三节点连接；所述第二电容器的一端与所述第一节点连接，另一端与所述第二节点连接。
在一个实施例中，所述发光控制子电路，包括：第五晶体管和第六晶体管；所述第五晶体管的栅极与所述发光控制信号端连接，第一极与所述参考信号端连接，第二极与所述第二节点连接；所述第六晶体管的栅极与所述发光控制信号端连接，第一极与所述第三节点连接，第二极与所述发光子电路的一端连接。
在一个实施例中，所述发光子电路，包括：OLED；所述OLED的一端 与所述发光控制子电路连接，另一端与所述第二电源信号端连接。
在一个实施例中，所述晶体管均为P型晶体管。
在一个实施例中，所述复位子电路，包括：第一晶体管；所述第一晶体管的栅极与所述复位信号端连接，第一极与所述初始化信号端连接，第二极与所述第一节点连接。
第二方面，提供一种像素电路的驱动方法，所述方法用于驱动如第一方面所述的像素电路，所述方法包括：数据电压写入阶段，扫描信号端输出的扫描信号为第一电位，所述输入子电路向第二节点输出来自所述数据信号端的数据信号，并且使得第一节点N1和第三节点N3连接，并且所述驱动子电路根据第一电源信号端输出的第一电源信号以及所述数据信号，调整所述第一节点的电位；发光阶段，发光控制信号端输出的发光控制信号为第一电位，所述发光控制子电路根据参考信号端输出的参考信号的电位，调整第二节点的电位；所述驱动子电路根据第二节点的电位，对第一节点的电位进行调整，并且在所述第一节点的控制下，向第三节点输出驱动电流；所述发光控制子电路将所述驱动电流输出至发光子电路，所述发光子电路发光；第一保持阶段，所述发光控制信号端输出的发光控制信号的电位由第一电位跳变至第二电位，稳压子电路在稳压信号端输出的稳压信号的控制下，使第二节点的电位保持不变；第二保持阶段，所述发光控制信号端输出的发光控制信号的电位由第二电位跳变至第一电位，所述发光控制子电路根据参考信号端输出的参考信号的电位，调整第二节点的电位；所述驱动子电路根据第二节点的电位，对第一节点的电位进行调整，并且在所述第一节点的控制下，向第三节点输出驱动电流；所述发光控制子电路将所述驱动电流输出至发光子电路，所述发光子电路发光。
在一个实施例中，所述第一保持阶段和第二保持阶段在所述发光控制信号的电位跳变于第一电位和第二电位的过程中被交替执行。
在一个实施例中，所述稳压子电路包括：第一电容器；所述输入子电路包括：第二晶体管和第四晶体管；所述驱动子电路包括：第三晶体管和第二电容器；所述发光控制子电路包括：第五晶体管和第六晶体管；所述发光子电路，包括：有机电致发光二极管OLED。所述数据写入阶段中，所述扫描信号为第一电位，所述第二晶体管和所述第四晶体管导通，所述数据信号端向所述第二节点输出所述数据信号，所述第三晶体管导通，并根据所述第一 电源信号的电位，调整所述第一节点的电位；所述发光阶段中，所述发光控制信号为第一电位，所述第五晶体管和所述第六晶体管导通，所述参考信号端向所述第二节点输出所述参考信号，所述第二电容器根据所述第二节点的电位调整所述第一节点的电位，所述第三晶体管导通，向所述OLED输出驱动电流，所述OLED发光；所述第一保持阶段中，所述发光控制信号为第二电位，所述第一电容器在所述稳压信号的控制下，使所述第二节点的电位保持不变；在所述第二保持阶段中，所述发光控制信号电位为第一电位，所述第五晶体管和所述第六晶体管导通，所述参考信号端向所述第二节点输出所述参考信号，所述第二电容器根据所述第二节点的电位调整所述第一节点的电位，所述第三晶体管导通，向所述OLED输出驱动电流，所述OLED发光。
在一个实施例中，所述像素电路还包括：复位子电路，所述复位子电路分别与复位信号端、初始化信号端和所述第一节点连接，用于在来自所述复位信号端的复位信号的控制下，向所述第一节点输出来自所述初始化信号端的初始化信号。所述方法还包括：复位阶段，其在所述数据电压写入阶段之前，复位信号端输出的复位信号为第一电位，所述复位子电路向第一节点输出来自初始化信号端的初始化信号，所述初始化信号为第一电位。
在一个实施例中，所述复位子电路包括：第一晶体管；所述复位阶段中，所述复位信号为第一电位，所述第一晶体管导通，所述初始化信号端向所述第一节点输出所述初始化信号。
在一个实施例中，在所述复位阶段之前，所述方法还包括：准备阶段；在所述准备阶段中，所述复位信号和所述扫描信号均为第二电位，所述发光控制信号由第一电位跳变至第二电位，所述第一晶体管、所述第二晶体管以及所述第四晶体管至所述第六晶体管均截止，所述第一电容器在所述稳压信号的控制下，使所述第二节点的电位保持不变。
在一个实施例中，在所述复位信号之后、在数据写入阶段之前，所述方法还包括：第一过渡阶段；在所述发光阶段之前，所述方法还包括：第二过渡阶段；在所述第一过渡阶段中，所述复位信号由第一电位跳变至第二电位，所述扫描信号端和所述发光控制信号端输出的信号均处于第二电位，所述第一晶体管至所述第六晶体管均截止；在所述第二过渡阶段中，所述复位信号保持第二电位，所述扫描信号由第一电位跳变至第二电位，所述第二电容器使所述第一节点和所述第二节点的电位保持不变。
在一个实施例中，所述晶体管均为P型晶体管，所述第一电位相对于所述第二电位为低电位。
第三方面，提供了一种显示装置，所述显示装置，包括：如第一方面所述的像素电路。
本公开提供的技术方案带来的有益效果是：本公开提供了一种像素电路及其驱动方法、显示装置，该像素电路中还包括稳压子电路，该稳压子电路的一端与稳压信号端连接，另一端与第二节点连接，由于该稳压信号端输出的稳压信号的电位为固定电位，因此该稳压子电路能够在像素电路驱动的过程中，使得该第二节点的电位保持稳定，避免发光控制信号电位变化对该第二节点电位的影响，进而避免显示装置出现亮度不均的现象。
附图说明
为了更清楚地说明本公开实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1是本公开实施例提供的一种像素电路的示意性框图；
图2是本公开实施例提供的图1所示的像素电路的示意性电路图；
图3是本公开实施例提供的图1所示的像素电路的另一示意性电路图；
图4是本公开实施例提供的图1所示的像素电路的另一示意性电路图；
图5是本公开实施例提供的一种像素电路的驱动方法流程图；
图6是本公开实施例提供的一种像素电路的驱动过程的时序图；
图7是本公开实施例提供的一种像素电路的驱动过程中各信号端电位、各节点电位以及驱动电流大小的示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开所有实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其 他特性相同的器件，根据在电路中的作用，本公开的实施例所采用的晶体管主要为开关晶体管。由于这里采用的开关晶体管的源极、漏极是对称的，所以其源极、漏极是可以互换的。在本公开实施例中，将其中源极称为第一级，漏极称为第二级。按附图中的形态规定晶体管的中间端为栅极、信号输入端为源极、信号输出端为漏极。此外，本公开实施例所采用的开关晶体管可以包括P型开关晶体管和N型开关晶体管中的任一种，其中，P型开关晶体管在栅极为低电平时导通，在栅极为高电平时截止，N型开关晶体管在栅极为高电平时导通，在栅极为低电平时截止。此外，本公开各个实施例中的多个信号都对应有第一电位和第二电位。第一电位和第二电位仅代表该信号的电位有2个状态量，不代表全文中第一电位或第二电位具有特定的数值。
图1是本公开实施例提供的一种像素电路的结构示意图，如图1所示，该像素电路可以包括：输入子电路10、驱动子电路20、发光控制子电路30、发光子电路40和稳压子电路50。
输入子电路10分别与扫描信号端GATE、数据信号端DATA、第一节点N1、第二节点N2和第三节点N3连接，用于在来自该扫描信号端GATE的扫描信号的控制下，向该第二节点N2输出来自该数据信号端DATA的数据信号，并且将第三节点N3与第一节点N1连接。
驱动子电路20分别与第一电源信号端VDD、第一节点N1、第二节点N2和第三节点N3连接，用于：在输入子电路10将第三节点N3与第一节点N1连接的情况下，根据第二节点N2的电平和第一电源信号端VDD输出的第一电源信号，调整该第一节点N1的电平；在输入子电路10未将第三节点N3与第一节点N1连接的情况下，在第一节点N1的控制下，根据第一电源信号端VDD输出的第一电源信号，向该第三节点N3输出驱动电流。
该发光控制子电路30分别与发光控制信号端EM、参考信号端Vref、该第二节点N2、该第三节点N3以及该发光子电路40的一端连接，用于在来自该发光控制信号端EM的发光控制信号的控制下，根据来自该参考信号端Vref的参考信号，控制该第二节点N2的电位；并且在来自该发光控制信号端EM的发光控制信号的控制下，将该驱动电流输出至该发光子电路40。
该发光子电路40的另一端与第二电源信号端VSS连接，用于在该驱动电流的驱动下发光。
该稳压子电路50分别与该第二节点N2和稳压信号端连接，用于在来自 该稳压信号端的稳压信号的控制下，稳定该第二节点N2的电位，该稳压信号的电位在该像素电路的驱动过程中保持不变。例如图1中，该稳压信号端为该第一电源信号端VDD，在该像素电路的驱动过程中，该第一电源信号端VDD输出的第一电源信号的电位一直为第二电位。
如图1所示的像素电路，还可以包括：复位子电路60。其中，该复位子电路60分别与复位信号端RST、初始化信号端Vin和该第一节点N1连接，用于在来自该复位信号端RST的复位信号的控制下，向该第一节点N1输出来自该初始化信号端Vin的初始化信号。
综上所述，本公开实施例提供了一种像素电路，该像素电路中包括稳压子电路，该稳压子电路的一端与稳压信号端连接，另一端与第二节点连接，由于该稳压信号端输出的稳压信号的电位为固定电位，因此该稳压子电路能够在像素电路驱动的过程中，使得该第二节点的电位保持稳定，避免发光控制信号电位变化对该第二节点电位的影响，进而避免显示装置出现亮度不均的现象。
在本公开实施例中，由于像素电路中第一电源信号端VDD、第二电源信号端VSS、参考信号端Vref和初始化信号端Vin输出的信号的电位在驱动过程中一直保持不变，因此该稳压子电路所连接的稳压信号端可以为该第一电源信号端VDD、该第二电源信号端VSS、该参考信号端Vref和该初始化信号端Vin中的任一信号端。
图2至图4是本公开实施例提供的一种像素电路的示意性电路图。参考图2，该稳压信号端可以为该第一电源信号端VDD，该第一电源信号端VDD输出的第一电源信号的电位持续为第二电位；或者，如图3所示，该稳压信号端可以为该参考信号端Vref，该参考信号端Vref输出的参考信号的电位持续为第二电位；又或者，如图4所示，该稳压信号端可以为该初始化信号端Vin，该初始化信号端Vin输出的初始化信号的电位持续为第一电位。
在一些实施例中，参考图2至图4，输入子电路10可以包括：第二晶体管M2和第四晶体管M4。具体地，该第二晶体管M2的栅极与该扫描信号端GATE连接，第一极与该第三节点N3连接，第二极与该第一节点N1连接；该第四晶体管M4的栅极与该扫描信号端GATE连接，第一极与该数据信号端DATA连接，第二极与该第二节点N2连接。该输入子电路10用于在来自该扫描信号端GATE的扫描信号的控制下，向该第二节点N2输出来自该数 据信号端DATA的数据信号，并且将第三节点N3与第一节点N1连接。
驱动子电路20可以包括：第三晶体管M3和第二电容器C2。具体地，该第三晶体管M3的栅极与该第一节点N1连接，第一极与该第一电源信号端VDD连接，第二极与该第三节点N3连接；该第二电容器C2的一端与该第一节点N1连接，另一端与该第二节点N2连接。该驱动子电路20用于：在输入子电路10将第三节点N3与第一节点N1连接的情况下，根据第二节点N2的电平和第一电源信号端VDD输出的第一电源信号，调整该第一节点N1的电平；在输入子电路10未将第三节点N3与第一节点N1连接的情况下，在第一节点N1的控制下，根据第一电源信号端VDD，向该第三节点N3输出驱动电流。
发光控制子电路30可以包括：第五晶体管M5和第六晶体管M6。具体地，该第五晶体管M5的栅极与该发光控制信号端EM连接，第一极与该参考信号端Vref连接，第二极与该第二节点N2连接；该第六晶体管M6的栅极与该发光控制信号端EM连接，第一极与该第三节点N3连接，第二极与该发光子电路40的一端连接。该发光控制子电路30用于在来自该发光控制信号端EM的发光控制信号的控制下，根据来自该参考信号端Vref的参考信号，控制该第二节点N2的电位；并且在来自该发光控制信号端EM的发光控制信号的控制下，将该驱动电流输出至该发光子电路40。
发光子电路40可以包括OLED。该OLED的一端与该发光控制子电路30连接，另一端与该第二电源信号端VSS连接。该发光子电路40用于在该驱动电流的驱动下发光。
稳压子电路50可以包括：第一电容器C1。该第一电容器C1的一端与该第二节点N2连接，另一端与该稳压信号端连接。该稳压子电路50用于在来自该稳压信号端的稳压信号的控制下，稳定该第二节点N2的电位。
在一个实施例中，该像素电路还可以包括：复位子电路60。该复位子电路60可以包括第一晶体管M1。具体地，该第一晶体管M1的栅极与该复位信号端RST连接，第一极与该初始化信号端Vin连接，第二极与该第一节点N1连接。该复位子电路60用于在来自该复位信号端RST的复位信号的控制下，向该第一节点N1输出来自该初始化信号端Vin的初始化信号。
综上所述，本公开实施例提供了一种像素电路，该像素电路中包括稳压子电路，该稳压子电路的一端与稳压信号端连接，另一端与第二节点连接， 由于该稳压信号端输出的稳压信号的电位为固定电位，因此该稳压子电路能够在像素电路驱动的过程中，使得该第二节点的电位保持稳定，避免发光控制信号电位变化对该第二节点电位的影响，进而避免显示装置出现亮度不均的现象。
图5是本公开实施例提供的一种像素电路的驱动方法的流程图，该方法用于驱动如图1至图4任一所示的像素电路，参考图5，该方法可以包括：
步骤102、数据电压写入阶段，扫描信号端GATE输出的扫描信号为第一电位，该输入子电路10向第二节点N2输出来自数据信号端DATA的数据信号，并且使得第一节点N1和第三节点N3连接，并且该驱动子电路20根据第一电源信号端VDD输出的第一电源信号以及所述数据信号，调整该第一节点N1的电位。
步骤103、发光阶段，发光控制信号端EM输出的发光控制信号为第一电位，该发光控制子电路30根据参考信号端Vref输出的参考信号的电位，调整该第二节点N2的电位；该驱动子电路20根据该第二节点N2的电位，对该第一节点N1的电位进行调整，并且在该第一节点N1的控制下，向该第三节点N3输出驱动电流；该发光控制子电路30将该驱动电流输出至该发光子电路40，该发光子电路40发光。
步骤104、第一保持阶段，该发光控制信号端EM输出的发光控制信号的电位由第一电位跳变至第二电位，该稳压子电路50在稳压信号端输出的稳压信号的控制下，使该第二节点N2的电位保持不变。
步骤105、第二保持阶段，该发光控制信号端EM输出的发光控制信号的电位由第二电位跳变至第一电位，该发光控制子电路30根据参考信号端Vref输出的参考信号的电位，调整该第二节点N2的电位；该驱动子电路20根据该第二节点N2的电位，对该第一节点N1的电位进行调整，并且在该第一节点N1的控制下，向该第三节点N3输出驱动电流；该发光控制子电路30将该驱动电流输出至该发光子电路40，该发光子电路40发光。
该方法还可以包括，步骤101、复位阶段，其在数据电压写入阶段之前，复位信号端RST输出的复位信号为第一电位，该复位子电路60向第一节点N1输出来自初始化信号端Vin的初始化信号，该初始化信号为第一电位。
综上所述，本公开实施例提供了一种像素电路的驱动方法，该驱动方法中还包括保持阶段，在该保持阶段中，发光控制信号的电位由第一电位跳变 至第二电位，该像素电路中的稳压子电路可以避免发光控制信号电位变化对该第二节点电位的影响，使得该第二节点的电位在该保持阶段保持不变，进而避免显示装置出现亮度不均的现象。
需要说明的是，在该发光阶段之后，该发光控制信号的电位会多次在第一电位和第二电位之间跳变，使得像素电路交替执行该第一保持阶段和该第二保持阶段。但由于该稳压信号的电位始终保持不变，因此该稳压子电路能够在该稳压信号的控制下，使第二节点的电位在该第一保持阶段和该第二保持阶段交替的过程中始终保持稳定。
进一步的，以图2所示的像素电路为例，对本公开实施例提供的驱动方法进行详细说明。图6是本公开实施例提供的一种像素电路的驱动过程的时序图。
参考图6，该驱动过程包括8个阶段，依次为：准备阶段T1、复位阶段T2、第一过渡阶段T3、数据电压写入阶段T4、第二过渡阶段T5、发光阶段T6、第一保持阶段T7和第二保持阶段T8。应了解，对于本公开的技术方案而言，T2不是必需的，并且图6所示各阶段的长度只是示意性的，而非对本公开的限制。本公开的技术方案旨在解决发光控制信号的变化可能使得像素电路中某些节点的电压不稳定的问题。在该第一保持阶段中，发光控制信号的电位由第一电位跳变至第二电位，该像素电路中的稳压子电路可以避免发光控制信号电位变化对该第二节点电位的影响，使得该第二节点的电位在该第一保持阶段保持不变，进而避免显示装置出现亮度不均的现象。
在复位阶段T2之前还包括准备阶段T1，在该准备阶段T1中，复位信号端RST输出的复位信号和扫描信号端GATE输出的扫描信号均为第二电位，发光控制信号端EM输出的发光控制信号由第一电位跳变至第二电位。此时，第一晶体管M1、第二晶体管M2以及第四晶体管M4截止，第五晶体管M5和第六晶体管M6由导通状态切换为截止状态，该第一电容器C1可以在稳压信号(例如第一电源信号端VDD输出的第一电源信号)的控制下，使第二节点N2的电位保持不变，为写入信号做好准备。
在复位阶段T2中，该复位信号端RST输出的复位信号由第二电位跳变至第一电位，第一晶体管M1导通，该初始化信号端Vin向该第一节点N1输出该初始化信号，对该第一节点N1的电位进行初始化。此时第二节点N2的电位为某个稳定电位Vx，该电位Vx的大小与前一阶段数据信号的电位 Vdata0有关，具体的，该电位Vx＝Vref-(Vdd+Vth+Vref-Vdata0-Vin)×C1/(C1+C2)，其中Vth为第三晶体管M3的阈值电压，Vdd为第一电源信号的电位，Vref为参考信号的电位，Vin为初始化信号的电位，C1和C2分别为第一电容器和第二电容器的电容值。由于此时扫描信号的电位维持在第二电位，第二晶体管M2和第四晶体管M4继续保持截止状态，发光控制信号的电位也维持在第二电位，第五晶体管M5和第六晶体管M6保持截止状态。
参考图6，在该复位阶段T2之后、在该数据写入阶段T4之前，该方法还包括：第一过渡阶段T3。在该第一过渡阶段T3中，该复位信号由第一电位跳变至第二电位，该扫描信号端GATE和该发光控制信号端EM输出的信号均处于第二电位，该第一晶体管M1至该第六晶体管M6均截止，为数据信号的写入做准备。
在该数据写入阶段T4中，该扫描信号由第二电位跳变至第一电位，该第二晶体管M2和该第四晶体管M4导通，该数据信号端DATA向该第二节点N2输出该数据信号，此时第二节点N2的电位为该数据信号的电位Vdata。由于第二晶体管M2的导通，使得该第三晶体管M3的栅极和漏极相连，此时该第三晶体管M3处于二极管导通状态。由于第三晶体管M3的栅极(即第一节点N1)的电位为初始化信号的电位Vin，该第三晶体管M3的源极的电位为第一电源信号的电位Vdd(该第一电源信号的电位Vdd相对于该初始化信号的电位Vin为高电位)，因此第一电源信号端VDD可以对第一节点N1进行充电。又由于该第三晶体管M3的阈值电压为Vth，因此当第一电源信号端VDD将第一节点N1的电位拉高至Vdd+Vth时，该第三晶体管M3截止。
在第二过渡阶段T5中，该复位信号保持第二电位，该扫描信号由第一电位跳变至第二电位，第二电容器C2使第一节点N1和第二节点N2的电位保持不变。也即是，该第一节点N1的电位保持为Vdd+Vth，第二节点N2的电位保持为Vdata。
上述第一过渡阶段T3和第二过渡阶段T5，可以使得复位信号和扫描信号之间，以及扫描信号和发光控制信号之间留有一定的空隙。由于两个信号同时开启(即同时处于第一电位)会在像素电路中形成一些不必要的电流回路，影响像素电路的驱动效果，因此通过该两个过渡阶段可以有效避免出现两个信号同时开启的情况，保证像素电路的正常工作。
在发光阶段T6中，该发光控制信号由第二电位跳变至第一电位，该第五 晶体管M5和该第六晶体管M6导通，该参考信号端Vref向该第二节点N2输出该参考信号，此时第二节点N2的电位变为Vref，该第二节点N2的电位变化量为Vref-Vdata。相应的，该第二电容器C2可以根据该第二节点N2的电位调整该第一节点N1的电位，此时该第一节点N1的电位变为Vdd+Vth+(Vref-Vdata)。此时第三晶体管M3导通，该第三晶体管M3的栅源电压Vgs为栅极电位(即第一节点N1的电位)与源极电位(即第一电源信号的电位Vdd)之差，即Vgs＝Vref+Vth-Vdata。此时，该第三晶体管M3向可以该OLED输出驱动电流，以驱动该OLED发光。其中，第三晶体管M3输出的驱动电流Id的大小可以表示为：
Id＝K×(Vgs-Vth)2＝K×(Vref-Vdata)2    公式(1)；
其中，
Figure PCTCN2017101702-appb-000001
具体的，μ为该第三晶体管M3的载流子迁移率，C为该第三晶体管M3的栅极绝缘层的电容，W/L为第三晶体管M3的宽长比。从该公式(1)中可以看出，该驱动电流Id的大小与第三晶体管M3的阈值电压Vth无关，因此避免了该驱动晶体管阈值电压偏移对发光效果的影响，提高了OLED显示面板显示亮度的均匀性，改善了OLED显示面板的显示效果。
进一步的，在第一保持阶段T7中，该发光控制信号由第一电位跳变至第二电位，该第一电容器C1可以在该稳压信号(例如第一电源信号)的控制下，使该第二节点N2的电位保持不变。
在实际应用中，可以采用脉冲宽度调制(英文：Pulse Width Modulation；简称：PWM)的方法对显示装置的显示亮度进行调整。也即是，通过调整发光控制信号在一帧之内的电位跳变次数以及每个电位的持续时长来改变显示装置的显示亮度。对发光控制信号脉冲宽度的调整，会影响图6中发光阶段T6和第一保持阶段T7交替出现的次数，以及每个阶段的持续时长。在相关技术中，像素电路从发光阶段T6切换至第一保持阶段T7后，第四晶体管M4和第五晶体管M5均处于截止状态。此时第二节点N2和第一节点N1的电位不受其他任何信号端的控制，即都处于悬空状态，该处于悬空状态的节点的电位容易受到外部信号的耦合干扰，以及像素电路中晶体管漏电流的影响，使得像素电路中写入的数据电压被影响，容易造成显示装置亮度不均，影响显示效果。
而在本公开实施例提供的像素电路中，稳压子电路50可以在发光控制信 号的电位跳变至第二电位后，通过稳压信号端的稳压信号，使得该第二节点N2的电位保持不变。进一步的，驱动子电路20中的第二电容器C2可以在第二节点N2的作用下，使得该第一节点N1的电位保持不变。因此本公开实施例提供的像素电路可以有效防止该两个节点的电压漂移，实现显示装置的稳定显示。
图7是本公开实施例提供的一种像素电路的驱动过程中各信号端电位、各节点电位以及驱动电流大小的示意图。应了解，图7中所示的各段信号的长度只是示意性的，而非对本公开的限制。图7中第一节点N1、第二节点N2以及驱动电流Id的时序中，实线为相关技术中未设置稳压子电路时的时序，虚线为本公开实施例中设置有稳压子电路后的时序。从图7中可以看出，相关技术中未设置稳压子电路的像素电路中，第一节点N1和第二节点N2的电位，以及驱动电流Id的大小受发光控制信号的影响较大，当发光控制信号端EM输出的发光控制信号的电位跳变至第二电位后，该驱动电流Id以及该两个节点的电位也出现波动，并且随着发光控制信号电位跳变次数的增加，该驱动电流Id也不断减小。而在本公开实施例提供的像素电路中，第一节点N1和第二节点N2的电位，以及驱动电流Id的大小受发光控制信号的影响较小。在发光控制信号的电位跳变至第二电位后，该两个节点的电位较为稳定，该驱动电流Id的波动也相对较小，即该驱动电流Id的稳定性较高，从而可以保证在采用PWM方法调整显示装置的亮度时，显示装置显示亮度的均匀性不受影响。
综上所述，本公开实施例提供了一种像素电路的驱动方法，该驱动方法中还包括保持阶段，在该保持阶段中，发光控制信号的电位由第一电位跳变至第二电位，该像素电路中的稳压子电路可以避免发光控制信号电位变化对该第二节点电位的影响，使得该第二节点的电位在该保持阶段保持不变，进而避免显示装置出现亮度不均的现象。
需要说明的是，在上述实施例中，均是以第一晶体管至第六晶体管为P型晶体管，且第一电位为相对于该第二电位低电位为例进行的说明。当然，该第一晶体管至第六晶体管还可以采用N型晶体管，当该第一至第六晶体管采用N型晶体管时，该第一电位相对于该第二电位可以为高电位，且该各个信号端的电位变化可以与图6和图7所示的电位变化相反(即二者的相位差为180度)。
本公开实施例还提供了一种显示装置，该显示装置可以包括如图1至图4任一所示的像素电路。该显示装置可以为：电子纸、OLED面板、AMOLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的像素电路及各子电路的具体工作过程，可以参考前述驱动方法实施例中的对应过程，在此不再赘述。
以上所述仅为本公开的较佳实施例，并不用以限制本公开，凡在本公开的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。
本申请要求2017年2月17日提交的申请号为201710086986.2且发明名称为“像素电路及其驱动方法、显示装置”的中国申请的优先权，通过引用将其全部内容并入于此。

Claims (19)

  1. 一种像素电路，其特征在于，所述像素电路包括：输入子电路、驱动子电路、发光控制子电路、发光子电路和稳压子电路；
    所述输入子电路分别与扫描信号端、数据信号端、第一节点、第二节点和第三节点连接，用于在来自所述扫描信号端的扫描信号的控制下，向所述第二节点输出来自所述数据信号端的数据信号，并且将所述第三节点与所述第一节点连接；
    所述驱动子电路分别与第一电源信号端、第一节点、第二节点和第三节点连接，用于在所述输入子电路将第三节点与第一节点连接的情况下，根据第二节点的电平和第一电源信号端输出的第一电源信号，调整所述第一节点的电平；在输入子电路未将第三节点与第一节点连接的情况下，在第一节点的控制下，根据第一电源信号端输出的第一电源信号，向所述第三节点输出驱动电流；
    所述发光控制子电路分别与发光控制信号端、参考信号端、所述第二节点、所述第三节点以及所述发光子电路的一端连接，用于在来自所述发光控制信号端的发光控制信号的控制下，根据来自所述参考信号端的参考信号，控制所述第二节点的电位，以及在来自所述发光控制信号端的发光控制信号的控制下，将所述驱动电流输出至所述发光子电路；
    所述发光子电路的另一端与第二电源信号端连接，用于在所述驱动电流的驱动下发光；
    所述稳压子电路分别与所述第二节点和稳压信号端连接，用于在来自所述稳压信号端的稳压信号的控制下，稳定所述第二节点的电位，所述稳压信号的电位在所述像素电路的驱动过程中保持不变。
  2. 根据权利要求1所述的像素电路，其特征在于，还包括复位子电路，所述复位子电路分别与复位信号端、初始化信号端和所述第一节点连接，用于在来自所述复位信号端的复位信号的控制下，向所述第一节点输出来自所述初始化信号端的初始化信号。
  3. 根据权利要求2所述的像素电路，其特征在于，所述稳压信号端为所述第一电源信号端、所述第二电源信号端、所述参考信号端和所述初始化信号端中的任一信号端。
  4. 根据权利要求1所述的像素电路，其特征在于，所述稳压子电路，包括：
    第一电容器；
    所述第一电容器的一端与所述第二节点连接，另一端与所述稳压信号端连接。
  5. 根据权利要求1所述的像素电路，其特征在于，所述输入子电路，包括：
    第二晶体管和第四晶体管；
    所述第二晶体管的栅极与所述扫描信号端连接，第一极与所述第三节点连接，第二极与所述第一节点连接；
    所述第四晶体管的栅极与所述扫描信号端连接，第一极与所述数据信号端连接，第二极与所述第二节点连接。
  6. 根据权利要求1所述的像素电路，其特征在于，所述驱动子电路，包括：
    第三晶体管和第二电容器；
    所述第三晶体管的栅极与所述第一节点连接，第一极与所述第一电源信号端连接，第二极与所述第三节点连接；
    所述第二电容器的一端与所述第一节点连接，另一端与所述第二节点连接。
  7. 根据权利要求1所述的像素电路，其特征在于，所述发光控制子电路，包括：第五晶体管和第六晶体管；
    所述第五晶体管的栅极与所述发光控制信号端连接，第一极与所述参考信号端连接，第二极与所述第二节点连接；
    所述第六晶体管的栅极与所述发光控制信号端连接，第一极与所述第三节点连接，第二极与所述发光子电路的一端连接。
  8. 根据权利要求1至7任一所述的像素电路，其特征在于，所述发光子电路，包括：有机电致发光二极管OLED；
    所述OLED的一端与所述发光控制子电路连接，另一端与所述第二电源信号端连接。
  9. 根据权利要求5至7任一所述的像素电路，其特征在于，
    所述晶体管均为P型晶体管。
  10. 根据权利要求2所述的像素电路，其特征在于，所述复位子电路，包括：
    第一晶体管；
    所述第一晶体管的栅极与所述复位信号端连接，第一极与所述初始化信号端连接，第二极与所述第一节点连接。
  11. 一种像素电路的驱动方法，其特征在于，用于驱动如权利要求1至10任一所述的像素电路，所述方法包括：
    数据电压写入阶段，扫描信号端输出的扫描信号为第一电位，所述输入子电路向第二节点输出来自所述数据信号端的数据信号，并且使得第一节点N1和第三节点N3连接，并且所述驱动子电路根据第一电源信号端输出的第一电源信号以及所述数据信号，调整所述第一节点的电位；
    发光阶段，发光控制信号端输出的发光控制信号为第一电位，所述发光控制子电路根据参考信号端输出的参考信号的电位，调整第二节点的电位；所述驱动子电路根据第二节点的电位，对第一节点的电位进行调整，并且在所述第一节点的控制下，向第三节点输出驱动电流；所述发光控制子电路将所述驱动电流输出至发光子电路，所述发光子电路发光；
    第一保持阶段，所述发光控制信号端输出的发光控制信号的电位由第一电位跳变至第二电位，稳压子电路在稳压信号端输出的稳压信号的控制下，使第二节点的电位保持不变；
    第二保持阶段，所述发光控制信号端输出的发光控制信号的电位由第二电位跳变至第一电位，所述发光控制子电路根据参考信号端输出的参考信号的电位，调整第二节点的电位；所述驱动子电路根据第二节点的电位，对第一节点的电位进行调整，并且在所述第一节点的控制下，向第三节点输出驱动电流；所述发光控制子电路将所述驱动电流输出至发光子电路，所述发光子电路发光。
  12. 根据权利要求11所述的驱动方法，其特征在于，所述第一保持阶段和第二保持阶段在所述发光控制信号的电位跳变于第一电位和第二电位的过程中被交替执行。
  13. 根据权利要求11所述的驱动方法，其特征在于，所述稳压子电路包括：第一电容器；所述输入子电路包括：第二晶体管和第四晶体管；所述驱动子电路包括：第三晶体管和第二电容器；所述发光控制子电路包括：第五 晶体管和第六晶体管；所述发光子电路，包括：有机电致发光二极管OLED；
    所述数据写入阶段中，所述扫描信号为第一电位，所述第二晶体管和所述第四晶体管导通，所述数据信号端向所述第二节点输出所述数据信号，所述第三晶体管导通，并根据所述第一电源信号的电位，调整所述第一节点的电位；
    所述发光阶段中，所述发光控制信号为第一电位，所述第五晶体管和所述第六晶体管导通，所述参考信号端向所述第二节点输出所述参考信号，所述第二电容器根据所述第二节点的电位调整所述第一节点的电位，所述第三晶体管导通，向所述OLED输出驱动电流，所述OLED发光；
    所述第一保持阶段中，所述发光控制信号为第二电位，所述第一电容器在所述稳压信号的控制下，使所述第二节点的电位保持不变；
    在所述第二保持阶段中，所述发光控制信号电位为第一电位，所述第五晶体管和所述第六晶体管导通，所述参考信号端向所述第二节点输出所述参考信号，所述第二电容器根据所述第二节点的电位调整所述第一节点的电位，所述第三晶体管导通，向所述OLED输出驱动电流，所述OLED发光。
  14. 根据权利要求11所述的方法，其特征在于，所述像素电路还包括复位子电路，所述复位子电路分别与复位信号端、初始化信号端和所述第一节点连接，用于在来自所述复位信号端的复位信号的控制下，向所述第一节点输出来自所述初始化信号端的初始化信号，
    所述方法还包括：复位阶段，其在所述数据写入阶段之前，复位信号端输出的复位信号为第一电位，所述复位子电路向第一节点输出来自初始化信号端的初始化信号，所述初始化信号为第一电位。
  15. 根据权利要求14所述的方法，其特征在于，所述复位子电路包括：第一晶体管；
    所述复位阶段中，所述复位信号为第一电位，所述第一晶体管导通，所述初始化信号端向所述第一节点输出所述初始化信号。
  16. 根据权利要求15所述的方法，其特征在于，在所述复位阶段之前，所述方法还包括：准备阶段；
    在所述准备阶段中，所述复位信号和所述扫描信号均为第二电位，所述发光控制信号由第一电位跳变至第二电位，所述第一晶体管、所述第二晶体管以及所述第四晶体管至所述第六晶体管均截止，所述第一电容器在所述稳 压信号的控制下，使所述第二节点的电位保持不变。
  17. 根据权利要求16所述的方法，其特征在于，在所述复位阶段之后、在所述数据写入阶段之前，所述方法还包括：第一过渡阶段；在所述数据写入阶段之后、在所述发光阶段之前，所述方法还包括：第二过渡阶段；
    在所述第一过渡阶段中，所述复位信号由第一电位跳变至第二电位，所述扫描信号端和所述发光控制信号端输出的信号均处于第二电位，所述第一晶体管至所述第六晶体管均截止；
    在所述第二过渡阶段中，所述复位信号保持第二电位，所述扫描信号由第一电位跳变至第二电位，所述第二电容器使所述第一节点和所述第二节点的电位保持不变。
  18. 根据权利要求13至17中任一所述的方法，其特征在于，所述晶体管均为P型晶体管，所述第一电位相对于所述第二电位为低电位。
  19. 一种显示装置，其特征在于，所述显示装置，包括：如权利要求1至10任一所述的像素电路。
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